drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96
  97 /*
  98  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  99  * symbol;
 100  */
 101 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 102 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 104 #define RADEON_IB_POOL_SIZE             16
 105 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 106 #define RADEONFB_CONN_LIMIT             4
 107 #define RADEON_BIOS_NUM_SCRATCH         8
 108
 109 /*
 110  * Errata workarounds.
 111  */
 112 enum radeon_pll_errata {
 113         CHIP_ERRATA_R300_CG             = 0x00000001,
 114         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 115         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 116 };
 117
 118
 119 struct radeon_device;
 120
 121
 122 /*
 123  * BIOS.
 124  */
 125 #define ATRM_BIOS_PAGE 4096
 126
 127 #if defined(CONFIG_VGA_SWITCHEROO)
 128 bool radeon_atrm_supported(struct pci_dev *pdev);
 129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 130 #else
 131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 132 {
 133         return false;
 134 }
 135
 136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 137         return -EINVAL;
 138 }
 139 #endif
 140 bool radeon_get_bios(struct radeon_device *rdev);
 141
 142
 143 /*
 144  * Dummy page
 145  */
 146 struct radeon_dummy_page {
 147         struct page     *page;
 148         dma_addr_t      addr;
 149 };
 150 int radeon_dummy_page_init(struct radeon_device *rdev);
 151 void radeon_dummy_page_fini(struct radeon_device *rdev);
 152
 153
 154 /*
 155  * Clocks
 156  */
 157 struct radeon_clock {
 158         struct radeon_pll p1pll;
 159         struct radeon_pll p2pll;
 160         struct radeon_pll dcpll;
 161         struct radeon_pll spll;
 162         struct radeon_pll mpll;
 163         /* 10 Khz units */
 164         uint32_t default_mclk;
 165         uint32_t default_sclk;
 166         uint32_t default_dispclk;
 167         uint32_t dp_extclk;
 168         uint32_t max_pixel_clock;
 169 };
 170
 171 /*
 172  * Power management
 173  */
 174 int radeon_pm_init(struct radeon_device *rdev);
 175 void radeon_pm_fini(struct radeon_device *rdev);
 176 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 177 void radeon_pm_suspend(struct radeon_device *rdev);
 178 void radeon_pm_resume(struct radeon_device *rdev);
 179 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 180 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 181 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 182 void rs690_pm_info(struct radeon_device *rdev);
 183 extern int rv6xx_get_temp(struct radeon_device *rdev);
 184 extern int rv770_get_temp(struct radeon_device *rdev);
 185 extern int evergreen_get_temp(struct radeon_device *rdev);
 186 extern int sumo_get_temp(struct radeon_device *rdev);
 187
 188 /*
 189  * Fences.
 190  */
 191 struct radeon_fence_driver {
 192         uint32_t                        scratch_reg;
 193         atomic_t                        seq;
 194         uint32_t                        last_seq;
 195         unsigned long                   last_jiffies;
 196         unsigned long                   last_timeout;
 197         wait_queue_head_t               queue;
 198         rwlock_t                        lock;
 199         struct list_head                created;
 200         struct list_head                emited;
 201         struct list_head                signaled;
 202         bool                            initialized;
 203 };
 204
 205 struct radeon_fence {
 206         struct radeon_device            *rdev;
 207         struct kref                     kref;
 208         struct list_head                list;
 209         /* protected by radeon_fence.lock */
 210         uint32_t                        seq;
 211         bool                            emited;
 212         bool                            signaled;
 213 };
 214
 215 int radeon_fence_driver_init(struct radeon_device *rdev);
 216 void radeon_fence_driver_fini(struct radeon_device *rdev);
 217 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 218 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 219 void radeon_fence_process(struct radeon_device *rdev);
 220 bool radeon_fence_signaled(struct radeon_fence *fence);
 221 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 222 int radeon_fence_wait_next(struct radeon_device *rdev);
 223 int radeon_fence_wait_last(struct radeon_device *rdev);
 224 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 225 void radeon_fence_unref(struct radeon_fence **fence);
 226
 227 /*
 228  * Tiling registers
 229  */
 230 struct radeon_surface_reg {
 231         struct radeon_bo *bo;
 232 };
 233
 234 #define RADEON_GEM_MAX_SURFACES 8
 235
 236 /*
 237  * TTM.
 238  */
 239 struct radeon_mman {
 240         struct ttm_bo_global_ref        bo_global_ref;
 241         struct drm_global_reference     mem_global_ref;
 242         struct ttm_bo_device            bdev;
 243         bool                            mem_global_referenced;
 244         bool                            initialized;
 245 };
 246
 247 struct radeon_bo {
 248         /* Protected by gem.mutex */
 249         struct list_head                list;
 250         /* Protected by tbo.reserved */
 251         u32                             placements[3];
 252         struct ttm_placement            placement;
 253         struct ttm_buffer_object        tbo;
 254         struct ttm_bo_kmap_obj          kmap;
 255         unsigned                        pin_count;
 256         void                            *kptr;
 257         u32                             tiling_flags;
 258         u32                             pitch;
 259         int                             surface_reg;
 260         /* Constant after initialization */
 261         struct radeon_device            *rdev;
 262         struct drm_gem_object           gem_base;
 263 };
 264 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 265
 266 struct radeon_bo_list {
 267         struct ttm_validate_buffer tv;
 268         struct radeon_bo        *bo;
 269         uint64_t                gpu_offset;
 270         unsigned                rdomain;
 271         unsigned                wdomain;
 272         u32                     tiling_flags;
 273 };
 274
 275 /*
 276  * GEM objects.
 277  */
 278 struct radeon_gem {
 279         struct mutex            mutex;
 280         struct list_head        objects;
 281 };
 282
 283 int radeon_gem_init(struct radeon_device *rdev);
 284 void radeon_gem_fini(struct radeon_device *rdev);
 285 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 286                                 int alignment, int initial_domain,
 287                                 bool discardable, bool kernel,
 288                                 struct drm_gem_object **obj);
 289 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 290                           uint64_t *gpu_addr);
 291 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 292
 293 int radeon_mode_dumb_create(struct drm_file *file_priv,
 294                             struct drm_device *dev,
 295                             struct drm_mode_create_dumb *args);
 296 int radeon_mode_dumb_mmap(struct drm_file *filp,
 297                           struct drm_device *dev,
 298                           uint32_t handle, uint64_t *offset_p);
 299 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 300                              struct drm_device *dev,
 301                              uint32_t handle);
 302
 303 /*
 304  * GART structures, functions & helpers
 305  */
 306 struct radeon_mc;
 307
 308 struct radeon_gart_table_ram {
 309         volatile uint32_t               *ptr;
 310 };
 311
 312 struct radeon_gart_table_vram {
 313         struct radeon_bo                *robj;
 314         volatile uint32_t               *ptr;
 315 };
 316
 317 union radeon_gart_table {
 318         struct radeon_gart_table_ram    ram;
 319         struct radeon_gart_table_vram   vram;
 320 };
 321
 322 #define RADEON_GPU_PAGE_SIZE 4096
 323 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 324
 325 struct radeon_gart {
 326         dma_addr_t                      table_addr;
 327         unsigned                        num_gpu_pages;
 328         unsigned                        num_cpu_pages;
 329         unsigned                        table_size;
 330         union radeon_gart_table         table;
 331         struct page                     **pages;
 332         dma_addr_t                      *pages_addr;
 333         bool                            *ttm_alloced;
 334         bool                            ready;
 335 };
 336
 337 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 338 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 339 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 340 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 341 int radeon_gart_init(struct radeon_device *rdev);
 342 void radeon_gart_fini(struct radeon_device *rdev);
 343 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 344                         int pages);
 345 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 346                      int pages, struct page **pagelist,
 347                      dma_addr_t *dma_addr);
 348
 349
 350 /*
 351  * GPU MC structures, functions & helpers
 352  */
 353 struct radeon_mc {
 354         resource_size_t         aper_size;
 355         resource_size_t         aper_base;
 356         resource_size_t         agp_base;
 357         /* for some chips with <= 32MB we need to lie
 358          * about vram size near mc fb location */
 359         u64                     mc_vram_size;
 360         u64                     visible_vram_size;
 361         u64                     gtt_size;
 362         u64                     gtt_start;
 363         u64                     gtt_end;
 364         u64                     vram_start;
 365         u64                     vram_end;
 366         unsigned                vram_width;
 367         u64                     real_vram_size;
 368         int                     vram_mtrr;
 369         bool                    vram_is_ddr;
 370         bool                    igp_sideport_enabled;
 371         u64                     gtt_base_align;
 372 };
 373
 374 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 375 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 376
 377 /*
 378  * GPU scratch registers structures, functions & helpers
 379  */
 380 struct radeon_scratch {
 381         unsigned                num_reg;
 382         uint32_t                reg_base;
 383         bool                    free[32];
 384         uint32_t                reg[32];
 385 };
 386
 387 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 388 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 389
 390
 391 /*
 392  * IRQS.
 393  */
 394
 395 struct radeon_unpin_work {
 396         struct work_struct work;
 397         struct radeon_device *rdev;
 398         int crtc_id;
 399         struct radeon_fence *fence;
 400         struct drm_pending_vblank_event *event;
 401         struct radeon_bo *old_rbo;
 402         u64 new_crtc_base;
 403 };
 404
 405 struct r500_irq_stat_regs {
 406         u32 disp_int;
 407 };
 408
 409 struct r600_irq_stat_regs {
 410         u32 disp_int;
 411         u32 disp_int_cont;
 412         u32 disp_int_cont2;
 413         u32 d1grph_int;
 414         u32 d2grph_int;
 415 };
 416
 417 struct evergreen_irq_stat_regs {
 418         u32 disp_int;
 419         u32 disp_int_cont;
 420         u32 disp_int_cont2;
 421         u32 disp_int_cont3;
 422         u32 disp_int_cont4;
 423         u32 disp_int_cont5;
 424         u32 d1grph_int;
 425         u32 d2grph_int;
 426         u32 d3grph_int;
 427         u32 d4grph_int;
 428         u32 d5grph_int;
 429         u32 d6grph_int;
 430 };
 431
 432 union radeon_irq_stat_regs {
 433         struct r500_irq_stat_regs r500;
 434         struct r600_irq_stat_regs r600;
 435         struct evergreen_irq_stat_regs evergreen;
 436 };
 437
 438 struct radeon_irq {
 439         bool            installed;
 440         bool            sw_int;
 441         /* FIXME: use a define max crtc rather than hardcode it */
 442         bool            crtc_vblank_int[6];
 443         bool            pflip[6];
 444         wait_queue_head_t       vblank_queue;
 445         /* FIXME: use defines for max hpd/dacs */
 446         bool            hpd[6];
 447         bool            gui_idle;
 448         bool            gui_idle_acked;
 449         wait_queue_head_t       idle_queue;
 450         /* FIXME: use defines for max HDMI blocks */
 451         bool            hdmi[2];
 452         spinlock_t sw_lock;
 453         int sw_refcount;
 454         union radeon_irq_stat_regs stat_regs;
 455         spinlock_t pflip_lock[6];
 456         int pflip_refcount[6];
 457 };
 458
 459 int radeon_irq_kms_init(struct radeon_device *rdev);
 460 void radeon_irq_kms_fini(struct radeon_device *rdev);
 461 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 462 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 463 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 464 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 465
 466 /*
 467  * CP & ring.
 468  */
 469 struct radeon_ib {
 470         struct list_head        list;
 471         unsigned                idx;
 472         uint64_t                gpu_addr;
 473         struct radeon_fence     *fence;
 474         uint32_t                *ptr;
 475         uint32_t                length_dw;
 476         bool                    free;
 477 };
 478
 479 /*
 480  * locking -
 481  * mutex protects scheduled_ibs, ready, alloc_bm
 482  */
 483 struct radeon_ib_pool {
 484         struct mutex            mutex;
 485         struct radeon_bo        *robj;
 486         struct list_head        bogus_ib;
 487         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 488         bool                    ready;
 489         unsigned                head_id;
 490 };
 491
 492 struct radeon_cp {
 493         struct radeon_bo        *ring_obj;
 494         volatile uint32_t       *ring;
 495         unsigned                rptr;
 496         unsigned                wptr;
 497         unsigned                wptr_old;
 498         unsigned                ring_size;
 499         unsigned                ring_free_dw;
 500         int                     count_dw;
 501         uint64_t                gpu_addr;
 502         uint32_t                align_mask;
 503         uint32_t                ptr_mask;
 504         struct mutex            mutex;
 505         bool                    ready;
 506 };
 507
 508 /*
 509  * R6xx+ IH ring
 510  */
 511 struct r600_ih {
 512         struct radeon_bo        *ring_obj;
 513         volatile uint32_t       *ring;
 514         unsigned                rptr;
 515         unsigned                wptr;
 516         unsigned                wptr_old;
 517         unsigned                ring_size;
 518         uint64_t                gpu_addr;
 519         uint32_t                ptr_mask;
 520         spinlock_t              lock;
 521         bool                    enabled;
 522 };
 523
 524 struct r600_blit {
 525         struct mutex            mutex;
 526         struct radeon_bo        *shader_obj;
 527         u64 shader_gpu_addr;
 528         u32 vs_offset, ps_offset;
 529         u32 state_offset;
 530         u32 state_len;
 531         u32 vb_used, vb_total;
 532         struct radeon_ib *vb_ib;
 533 };
 534
 535 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 536 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 537 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 538 int radeon_ib_pool_init(struct radeon_device *rdev);
 539 void radeon_ib_pool_fini(struct radeon_device *rdev);
 540 int radeon_ib_test(struct radeon_device *rdev);
 541 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 542 /* Ring access between begin & end cannot sleep */
 543 void radeon_ring_free_size(struct radeon_device *rdev);
 544 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
 545 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 546 void radeon_ring_commit(struct radeon_device *rdev);
 547 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 548 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 549 int radeon_ring_test(struct radeon_device *rdev);
 550 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 551 void radeon_ring_fini(struct radeon_device *rdev);
 552
 553
 554 /*
 555  * CS.
 556  */
 557 struct radeon_cs_reloc {
 558         struct drm_gem_object           *gobj;
 559         struct radeon_bo                *robj;
 560         struct radeon_bo_list           lobj;
 561         uint32_t                        handle;
 562         uint32_t                        flags;
 563 };
 564
 565 struct radeon_cs_chunk {
 566         uint32_t                chunk_id;
 567         uint32_t                length_dw;
 568         int kpage_idx[2];
 569         uint32_t                *kpage[2];
 570         uint32_t                *kdata;
 571         void __user *user_ptr;
 572         int last_copied_page;
 573         int last_page_index;
 574 };
 575
 576 struct radeon_cs_parser {
 577         struct device           *dev;
 578         struct radeon_device    *rdev;
 579         struct drm_file         *filp;
 580         /* chunks */
 581         unsigned                nchunks;
 582         struct radeon_cs_chunk  *chunks;
 583         uint64_t                *chunks_array;
 584         /* IB */
 585         unsigned                idx;
 586         /* relocations */
 587         unsigned                nrelocs;
 588         struct radeon_cs_reloc  *relocs;
 589         struct radeon_cs_reloc  **relocs_ptr;
 590         struct list_head        validated;
 591         /* indices of various chunks */
 592         int                     chunk_ib_idx;
 593         int                     chunk_relocs_idx;
 594         struct radeon_ib        *ib;
 595         void                    *track;
 596         unsigned                family;
 597         int parser_error;
 598 };
 599
 600 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 601 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 602
 603
 604 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 605 {
 606         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 607         u32 pg_idx, pg_offset;
 608         u32 idx_value = 0;
 609         int new_page;
 610
 611         pg_idx = (idx * 4) / PAGE_SIZE;
 612         pg_offset = (idx * 4) % PAGE_SIZE;
 613
 614         if (ibc->kpage_idx[0] == pg_idx)
 615                 return ibc->kpage[0][pg_offset/4];
 616         if (ibc->kpage_idx[1] == pg_idx)
 617                 return ibc->kpage[1][pg_offset/4];
 618
 619         new_page = radeon_cs_update_pages(p, pg_idx);
 620         if (new_page < 0) {
 621                 p->parser_error = new_page;
 622                 return 0;
 623         }
 624
 625         idx_value = ibc->kpage[new_page][pg_offset/4];
 626         return idx_value;
 627 }
 628
 629 struct radeon_cs_packet {
 630         unsigned        idx;
 631         unsigned        type;
 632         unsigned        reg;
 633         unsigned        opcode;
 634         int             count;
 635         unsigned        one_reg_wr;
 636 };
 637
 638 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 639                                       struct radeon_cs_packet *pkt,
 640                                       unsigned idx, unsigned reg);
 641 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 642                                       struct radeon_cs_packet *pkt);
 643
 644
 645 /*
 646  * AGP
 647  */
 648 int radeon_agp_init(struct radeon_device *rdev);
 649 void radeon_agp_resume(struct radeon_device *rdev);
 650 void radeon_agp_suspend(struct radeon_device *rdev);
 651 void radeon_agp_fini(struct radeon_device *rdev);
 652
 653
 654 /*
 655  * Writeback
 656  */
 657 struct radeon_wb {
 658         struct radeon_bo        *wb_obj;
 659         volatile uint32_t       *wb;
 660         uint64_t                gpu_addr;
 661         bool                    enabled;
 662         bool                    use_event;
 663 };
 664
 665 #define RADEON_WB_SCRATCH_OFFSET 0
 666 #define RADEON_WB_CP_RPTR_OFFSET 1024
 667 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 668 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 669 #define R600_WB_IH_WPTR_OFFSET   2048
 670 #define R600_WB_EVENT_OFFSET     3072
 671
 672 /**
 673  * struct radeon_pm - power management datas
 674  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 675  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 676  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 677  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 678  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 679  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 680  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 681  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 682  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 683  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 684  * @needed_bandwidth:   current bandwidth needs
 685  *
 686  * It keeps track of various data needed to take powermanagement decision.
 687  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 688  * Equation between gpu/memory clock and available bandwidth is hw dependent
 689  * (type of memory, bus size, efficiency, ...)
 690  */
 691
 692 enum radeon_pm_method {
 693         PM_METHOD_PROFILE,
 694         PM_METHOD_DYNPM,
 695 };
 696
 697 enum radeon_dynpm_state {
 698         DYNPM_STATE_DISABLED,
 699         DYNPM_STATE_MINIMUM,
 700         DYNPM_STATE_PAUSED,
 701         DYNPM_STATE_ACTIVE,
 702         DYNPM_STATE_SUSPENDED,
 703 };
 704 enum radeon_dynpm_action {
 705         DYNPM_ACTION_NONE,
 706         DYNPM_ACTION_MINIMUM,
 707         DYNPM_ACTION_DOWNCLOCK,
 708         DYNPM_ACTION_UPCLOCK,
 709         DYNPM_ACTION_DEFAULT
 710 };
 711
 712 enum radeon_voltage_type {
 713         VOLTAGE_NONE = 0,
 714         VOLTAGE_GPIO,
 715         VOLTAGE_VDDC,
 716         VOLTAGE_SW
 717 };
 718
 719 enum radeon_pm_state_type {
 720         POWER_STATE_TYPE_DEFAULT,
 721         POWER_STATE_TYPE_POWERSAVE,
 722         POWER_STATE_TYPE_BATTERY,
 723         POWER_STATE_TYPE_BALANCED,
 724         POWER_STATE_TYPE_PERFORMANCE,
 725 };
 726
 727 enum radeon_pm_profile_type {
 728         PM_PROFILE_DEFAULT,
 729         PM_PROFILE_AUTO,
 730         PM_PROFILE_LOW,
 731         PM_PROFILE_MID,
 732         PM_PROFILE_HIGH,
 733 };
 734
 735 #define PM_PROFILE_DEFAULT_IDX 0
 736 #define PM_PROFILE_LOW_SH_IDX  1
 737 #define PM_PROFILE_MID_SH_IDX  2
 738 #define PM_PROFILE_HIGH_SH_IDX 3
 739 #define PM_PROFILE_LOW_MH_IDX  4
 740 #define PM_PROFILE_MID_MH_IDX  5
 741 #define PM_PROFILE_HIGH_MH_IDX 6
 742 #define PM_PROFILE_MAX         7
 743
 744 struct radeon_pm_profile {
 745         int dpms_off_ps_idx;
 746         int dpms_on_ps_idx;
 747         int dpms_off_cm_idx;
 748         int dpms_on_cm_idx;
 749 };
 750
 751 enum radeon_int_thermal_type {
 752         THERMAL_TYPE_NONE,
 753         THERMAL_TYPE_RV6XX,
 754         THERMAL_TYPE_RV770,
 755         THERMAL_TYPE_EVERGREEN,
 756         THERMAL_TYPE_SUMO,
 757         THERMAL_TYPE_NI,
 758 };
 759
 760 struct radeon_voltage {
 761         enum radeon_voltage_type type;
 762         /* gpio voltage */
 763         struct radeon_gpio_rec gpio;
 764         u32 delay; /* delay in usec from voltage drop to sclk change */
 765         bool active_high; /* voltage drop is active when bit is high */
 766         /* VDDC voltage */
 767         u8 vddc_id; /* index into vddc voltage table */
 768         u8 vddci_id; /* index into vddci voltage table */
 769         bool vddci_enabled;
 770         /* r6xx+ sw */
 771         u16 voltage;
 772         /* evergreen+ vddci */
 773         u16 vddci;
 774 };
 775
 776 /* clock mode flags */
 777 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 778
 779 struct radeon_pm_clock_info {
 780         /* memory clock */
 781         u32 mclk;
 782         /* engine clock */
 783         u32 sclk;
 784         /* voltage info */
 785         struct radeon_voltage voltage;
 786         /* standardized clock flags */
 787         u32 flags;
 788 };
 789
 790 /* state flags */
 791 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 792
 793 struct radeon_power_state {
 794         enum radeon_pm_state_type type;
 795         /* XXX: use a define for num clock modes */
 796         struct radeon_pm_clock_info clock_info[8];
 797         /* number of valid clock modes in this power state */
 798         int num_clock_modes;
 799         struct radeon_pm_clock_info *default_clock_mode;
 800         /* standardized state flags */
 801         u32 flags;
 802         u32 misc; /* vbios specific flags */
 803         u32 misc2; /* vbios specific flags */
 804         int pcie_lanes; /* pcie lanes */
 805 };
 806
 807 /*
 808  * Some modes are overclocked by very low value, accept them
 809  */
 810 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 811
 812 struct radeon_pm {
 813         struct mutex            mutex;
 814         u32                     active_crtcs;
 815         int                     active_crtc_count;
 816         int                     req_vblank;
 817         bool                    vblank_sync;
 818         bool                    gui_idle;
 819         fixed20_12              max_bandwidth;
 820         fixed20_12              igp_sideport_mclk;
 821         fixed20_12              igp_system_mclk;
 822         fixed20_12              igp_ht_link_clk;
 823         fixed20_12              igp_ht_link_width;
 824         fixed20_12              k8_bandwidth;
 825         fixed20_12              sideport_bandwidth;
 826         fixed20_12              ht_bandwidth;
 827         fixed20_12              core_bandwidth;
 828         fixed20_12              sclk;
 829         fixed20_12              mclk;
 830         fixed20_12              needed_bandwidth;
 831         struct radeon_power_state *power_state;
 832         /* number of valid power states */
 833         int                     num_power_states;
 834         int                     current_power_state_index;
 835         int                     current_clock_mode_index;
 836         int                     requested_power_state_index;
 837         int                     requested_clock_mode_index;
 838         int                     default_power_state_index;
 839         u32                     current_sclk;
 840         u32                     current_mclk;
 841         u16                     current_vddc;
 842         u16                     current_vddci;
 843         u32                     default_sclk;
 844         u32                     default_mclk;
 845         u16                     default_vddc;
 846         u16                     default_vddci;
 847         struct radeon_i2c_chan *i2c_bus;
 848         /* selected pm method */
 849         enum radeon_pm_method     pm_method;
 850         /* dynpm power management */
 851         struct delayed_work     dynpm_idle_work;
 852         enum radeon_dynpm_state dynpm_state;
 853         enum radeon_dynpm_action        dynpm_planned_action;
 854         unsigned long           dynpm_action_timeout;
 855         bool                    dynpm_can_upclock;
 856         bool                    dynpm_can_downclock;
 857         /* profile-based power management */
 858         enum radeon_pm_profile_type profile;
 859         int                     profile_index;
 860         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
 861         /* internal thermal controller on rv6xx+ */
 862         enum radeon_int_thermal_type int_thermal_type;
 863         struct device           *int_hwmon_dev;
 864 };
 865
 866
 867 /*
 868  * Benchmarking
 869  */
 870 void radeon_benchmark(struct radeon_device *rdev);
 871
 872
 873 /*
 874  * Testing
 875  */
 876 void radeon_test_moves(struct radeon_device *rdev);
 877
 878
 879 /*
 880  * Debugfs
 881  */
 882 int radeon_debugfs_add_files(struct radeon_device *rdev,
 883                              struct drm_info_list *files,
 884                              unsigned nfiles);
 885 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 886
 887
 888 /*
 889  * ASIC specific functions.
 890  */
 891 struct radeon_asic {
 892         int (*init)(struct radeon_device *rdev);
 893         void (*fini)(struct radeon_device *rdev);
 894         int (*resume)(struct radeon_device *rdev);
 895         int (*suspend)(struct radeon_device *rdev);
 896         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 897         bool (*gpu_is_lockup)(struct radeon_device *rdev);
 898         int (*asic_reset)(struct radeon_device *rdev);
 899         void (*gart_tlb_flush)(struct radeon_device *rdev);
 900         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 901         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 902         void (*cp_fini)(struct radeon_device *rdev);
 903         void (*cp_disable)(struct radeon_device *rdev);
 904         void (*cp_commit)(struct radeon_device *rdev);
 905         void (*ring_start)(struct radeon_device *rdev);
 906         int (*ring_test)(struct radeon_device *rdev);
 907         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 908         int (*irq_set)(struct radeon_device *rdev);
 909         int (*irq_process)(struct radeon_device *rdev);
 910         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 911         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 912         int (*cs_parse)(struct radeon_cs_parser *p);
 913         int (*copy_blit)(struct radeon_device *rdev,
 914                          uint64_t src_offset,
 915                          uint64_t dst_offset,
 916                          unsigned num_pages,
 917                          struct radeon_fence *fence);
 918         int (*copy_dma)(struct radeon_device *rdev,
 919                         uint64_t src_offset,
 920                         uint64_t dst_offset,
 921                         unsigned num_pages,
 922                         struct radeon_fence *fence);
 923         int (*copy)(struct radeon_device *rdev,
 924                     uint64_t src_offset,
 925                     uint64_t dst_offset,
 926                     unsigned num_pages,
 927                     struct radeon_fence *fence);
 928         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 929         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 930         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 931         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 932         int (*get_pcie_lanes)(struct radeon_device *rdev);
 933         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 934         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 935         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 936                                uint32_t tiling_flags, uint32_t pitch,
 937                                uint32_t offset, uint32_t obj_size);
 938         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 939         void (*bandwidth_update)(struct radeon_device *rdev);
 940         void (*hpd_init)(struct radeon_device *rdev);
 941         void (*hpd_fini)(struct radeon_device *rdev);
 942         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 943         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 944         /* ioctl hw specific callback. Some hw might want to perform special
 945          * operation on specific ioctl. For instance on wait idle some hw
 946          * might want to perform and HDP flush through MMIO as it seems that
 947          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 948          * through ring.
 949          */
 950         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 951         bool (*gui_idle)(struct radeon_device *rdev);
 952         /* power management */
 953         void (*pm_misc)(struct radeon_device *rdev);
 954         void (*pm_prepare)(struct radeon_device *rdev);
 955         void (*pm_finish)(struct radeon_device *rdev);
 956         void (*pm_init_profile)(struct radeon_device *rdev);
 957         void (*pm_get_dynpm_state)(struct radeon_device *rdev);
 958         /* pageflipping */
 959         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
 960         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
 961         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
 962 };
 963
 964 /*
 965  * Asic structures
 966  */
 967 struct r100_gpu_lockup {
 968         unsigned long   last_jiffies;
 969         u32             last_cp_rptr;
 970 };
 971
 972 struct r100_asic {
 973         const unsigned          *reg_safe_bm;
 974         unsigned                reg_safe_bm_size;
 975         u32                     hdp_cntl;
 976         struct r100_gpu_lockup  lockup;
 977 };
 978
 979 struct r300_asic {
 980         const unsigned          *reg_safe_bm;
 981         unsigned                reg_safe_bm_size;
 982         u32                     resync_scratch;
 983         u32                     hdp_cntl;
 984         struct r100_gpu_lockup  lockup;
 985 };
 986
 987 struct r600_asic {
 988         unsigned                max_pipes;
 989         unsigned                max_tile_pipes;
 990         unsigned                max_simds;
 991         unsigned                max_backends;
 992         unsigned                max_gprs;
 993         unsigned                max_threads;
 994         unsigned                max_stack_entries;
 995         unsigned                max_hw_contexts;
 996         unsigned                max_gs_threads;
 997         unsigned                sx_max_export_size;
 998         unsigned                sx_max_export_pos_size;
 999         unsigned                sx_max_export_smx_size;
1000         unsigned                sq_num_cf_insts;
1001         unsigned                tiling_nbanks;
1002         unsigned                tiling_npipes;
1003         unsigned                tiling_group_size;
1004         unsigned                tile_config;
1005         struct r100_gpu_lockup  lockup;
1006 };
1007
1008 struct rv770_asic {
1009         unsigned                max_pipes;
1010         unsigned                max_tile_pipes;
1011         unsigned                max_simds;
1012         unsigned                max_backends;
1013         unsigned                max_gprs;
1014         unsigned                max_threads;
1015         unsigned                max_stack_entries;
1016         unsigned                max_hw_contexts;
1017         unsigned                max_gs_threads;
1018         unsigned                sx_max_export_size;
1019         unsigned                sx_max_export_pos_size;
1020         unsigned                sx_max_export_smx_size;
1021         unsigned                sq_num_cf_insts;
1022         unsigned                sx_num_of_sets;
1023         unsigned                sc_prim_fifo_size;
1024         unsigned                sc_hiz_tile_fifo_size;
1025         unsigned                sc_earlyz_tile_fifo_fize;
1026         unsigned                tiling_nbanks;
1027         unsigned                tiling_npipes;
1028         unsigned                tiling_group_size;
1029         unsigned                tile_config;
1030         struct r100_gpu_lockup  lockup;
1031 };
1032
1033 struct evergreen_asic {
1034         unsigned num_ses;
1035         unsigned max_pipes;
1036         unsigned max_tile_pipes;
1037         unsigned max_simds;
1038         unsigned max_backends;
1039         unsigned max_gprs;
1040         unsigned max_threads;
1041         unsigned max_stack_entries;
1042         unsigned max_hw_contexts;
1043         unsigned max_gs_threads;
1044         unsigned sx_max_export_size;
1045         unsigned sx_max_export_pos_size;
1046         unsigned sx_max_export_smx_size;
1047         unsigned sq_num_cf_insts;
1048         unsigned sx_num_of_sets;
1049         unsigned sc_prim_fifo_size;
1050         unsigned sc_hiz_tile_fifo_size;
1051         unsigned sc_earlyz_tile_fifo_size;
1052         unsigned tiling_nbanks;
1053         unsigned tiling_npipes;
1054         unsigned tiling_group_size;
1055         unsigned tile_config;
1056         struct r100_gpu_lockup  lockup;
1057 };
1058
1059 struct cayman_asic {
1060         unsigned max_shader_engines;
1061         unsigned max_pipes_per_simd;
1062         unsigned max_tile_pipes;
1063         unsigned max_simds_per_se;
1064         unsigned max_backends_per_se;
1065         unsigned max_texture_channel_caches;
1066         unsigned max_gprs;
1067         unsigned max_threads;
1068         unsigned max_gs_threads;
1069         unsigned max_stack_entries;
1070         unsigned sx_num_of_sets;
1071         unsigned sx_max_export_size;
1072         unsigned sx_max_export_pos_size;
1073         unsigned sx_max_export_smx_size;
1074         unsigned max_hw_contexts;
1075         unsigned sq_num_cf_insts;
1076         unsigned sc_prim_fifo_size;
1077         unsigned sc_hiz_tile_fifo_size;
1078         unsigned sc_earlyz_tile_fifo_size;
1079
1080         unsigned num_shader_engines;
1081         unsigned num_shader_pipes_per_simd;
1082         unsigned num_tile_pipes;
1083         unsigned num_simds_per_se;
1084         unsigned num_backends_per_se;
1085         unsigned backend_disable_mask_per_asic;
1086         unsigned backend_map;
1087         unsigned num_texture_channel_caches;
1088         unsigned mem_max_burst_length_bytes;
1089         unsigned mem_row_size_in_kb;
1090         unsigned shader_engine_tile_size;
1091         unsigned num_gpus;
1092         unsigned multi_gpu_tile_size;
1093
1094         unsigned tile_config;
1095         struct r100_gpu_lockup  lockup;
1096 };
1097
1098 union radeon_asic_config {
1099         struct r300_asic        r300;
1100         struct r100_asic        r100;
1101         struct r600_asic        r600;
1102         struct rv770_asic       rv770;
1103         struct evergreen_asic   evergreen;
1104         struct cayman_asic      cayman;
1105 };
1106
1107 /*
1108  * asic initizalization from radeon_asic.c
1109  */
1110 void radeon_agp_disable(struct radeon_device *rdev);
1111 int radeon_asic_init(struct radeon_device *rdev);
1112
1113
1114 /*
1115  * IOCTL.
1116  */
1117 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1118                           struct drm_file *filp);
1119 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1120                             struct drm_file *filp);
1121 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1122                          struct drm_file *file_priv);
1123 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1124                            struct drm_file *file_priv);
1125 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1126                             struct drm_file *file_priv);
1127 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1128                            struct drm_file *file_priv);
1129 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1130                                 struct drm_file *filp);
1131 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1132                           struct drm_file *filp);
1133 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1134                           struct drm_file *filp);
1135 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1136                               struct drm_file *filp);
1137 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1138 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1139                                 struct drm_file *filp);
1140 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1141                                 struct drm_file *filp);
1142
1143 /* VRAM scratch page for HDP bug */
1144 struct r700_vram_scratch {
1145         struct radeon_bo                *robj;
1146         volatile uint32_t               *ptr;
1147 };
1148
1149 /*
1150  * Core structure, functions and helpers.
1151  */
1152 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1153 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1154
1155 struct radeon_device {
1156         struct device                   *dev;
1157         struct drm_device               *ddev;
1158         struct pci_dev                  *pdev;
1159         /* ASIC */
1160         union radeon_asic_config        config;
1161         enum radeon_family              family;
1162         unsigned long                   flags;
1163         int                             usec_timeout;
1164         enum radeon_pll_errata          pll_errata;
1165         int                             num_gb_pipes;
1166         int                             num_z_pipes;
1167         int                             disp_priority;
1168         /* BIOS */
1169         uint8_t                         *bios;
1170         bool                            is_atom_bios;
1171         uint16_t                        bios_header_start;
1172         struct radeon_bo                *stollen_vga_memory;
1173         /* Register mmio */
1174         resource_size_t                 rmmio_base;
1175         resource_size_t                 rmmio_size;
1176         void                            *rmmio;
1177         radeon_rreg_t                   mc_rreg;
1178         radeon_wreg_t                   mc_wreg;
1179         radeon_rreg_t                   pll_rreg;
1180         radeon_wreg_t                   pll_wreg;
1181         uint32_t                        pcie_reg_mask;
1182         radeon_rreg_t                   pciep_rreg;
1183         radeon_wreg_t                   pciep_wreg;
1184         /* io port */
1185         void __iomem                    *rio_mem;
1186         resource_size_t                 rio_mem_size;
1187         struct radeon_clock             clock;
1188         struct radeon_mc                mc;
1189         struct radeon_gart              gart;
1190         struct radeon_mode_info         mode_info;
1191         struct radeon_scratch           scratch;
1192         struct radeon_mman              mman;
1193         struct radeon_fence_driver      fence_drv;
1194         struct radeon_cp                cp;
1195         /* cayman compute rings */
1196         struct radeon_cp                cp1;
1197         struct radeon_cp                cp2;
1198         struct radeon_ib_pool           ib_pool;
1199         struct radeon_irq               irq;
1200         struct radeon_asic              *asic;
1201         struct radeon_gem               gem;
1202         struct radeon_pm                pm;
1203         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1204         struct mutex                    cs_mutex;
1205         struct radeon_wb                wb;
1206         struct radeon_dummy_page        dummy_page;
1207         bool                            gpu_lockup;
1208         bool                            shutdown;
1209         bool                            suspend;
1210         bool                            need_dma32;
1211         bool                            accel_working;
1212         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1213         const struct firmware *me_fw;   /* all family ME firmware */
1214         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1215         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1216         const struct firmware *mc_fw;   /* NI MC firmware */
1217         struct r600_blit r600_blit;
1218         struct r700_vram_scratch vram_scratch;
1219         int msi_enabled; /* msi enabled */
1220         struct r600_ih ih; /* r6/700 interrupt ring */
1221         struct work_struct hotplug_work;
1222         int num_crtc; /* number of crtcs */
1223         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1224         struct mutex vram_mutex;
1225
1226         /* audio stuff */
1227         bool                    audio_enabled;
1228         struct timer_list       audio_timer;
1229         int                     audio_channels;
1230         int                     audio_rate;
1231         int                     audio_bits_per_sample;
1232         uint8_t                 audio_status_bits;
1233         uint8_t                 audio_category_code;
1234
1235         struct notifier_block acpi_nb;
1236         /* only one userspace can use Hyperz features or CMASK at a time */
1237         struct drm_file *hyperz_filp;
1238         struct drm_file *cmask_filp;
1239         /* i2c buses */
1240         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1241 };
1242
1243 int radeon_device_init(struct radeon_device *rdev,
1244                        struct drm_device *ddev,
1245                        struct pci_dev *pdev,
1246                        uint32_t flags);
1247 void radeon_device_fini(struct radeon_device *rdev);
1248 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1249
1250 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1251 {
1252         if (reg < rdev->rmmio_size)
1253                 return readl(((void __iomem *)rdev->rmmio) + reg);
1254         else {
1255                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1256                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1257         }
1258 }
1259
1260 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1261 {
1262         if (reg < rdev->rmmio_size)
1263                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1264         else {
1265                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1266                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1267         }
1268 }
1269
1270 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1271 {
1272         if (reg < rdev->rio_mem_size)
1273                 return ioread32(rdev->rio_mem + reg);
1274         else {
1275                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1276                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1277         }
1278 }
1279
1280 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1281 {
1282         if (reg < rdev->rio_mem_size)
1283                 iowrite32(v, rdev->rio_mem + reg);
1284         else {
1285                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1286                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1287         }
1288 }
1289
1290 /*
1291  * Cast helper
1292  */
1293 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1294
1295 /*
1296  * Registers read & write functions.
1297  */
1298 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1299 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1300 #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1301 #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1302 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1303 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1304 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1305 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1306 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1307 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1308 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1309 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1310 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1311 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1312 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1313 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1314 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1315 #define WREG32_P(reg, val, mask)                                \
1316         do {                                                    \
1317                 uint32_t tmp_ = RREG32(reg);                    \
1318                 tmp_ &= (mask);                                 \
1319                 tmp_ |= ((val) & ~(mask));                      \
1320                 WREG32(reg, tmp_);                              \
1321         } while (0)
1322 #define WREG32_PLL_P(reg, val, mask)                            \
1323         do {                                                    \
1324                 uint32_t tmp_ = RREG32_PLL(reg);                \
1325                 tmp_ &= (mask);                                 \
1326                 tmp_ |= ((val) & ~(mask));                      \
1327                 WREG32_PLL(reg, tmp_);                          \
1328         } while (0)
1329 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1330 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1331 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1332
1333 /*
1334  * Indirect registers accessor
1335  */
1336 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1337 {
1338         uint32_t r;
1339
1340         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1341         r = RREG32(RADEON_PCIE_DATA);
1342         return r;
1343 }
1344
1345 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1346 {
1347         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1348         WREG32(RADEON_PCIE_DATA, (v));
1349 }
1350
1351 void r100_pll_errata_after_index(struct radeon_device *rdev);
1352
1353
1354 /*
1355  * ASICs helpers.
1356  */
1357 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1358                             (rdev->pdev->device == 0x5969))
1359 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1360                 (rdev->family == CHIP_RV200) || \
1361                 (rdev->family == CHIP_RS100) || \
1362                 (rdev->family == CHIP_RS200) || \
1363                 (rdev->family == CHIP_RV250) || \
1364                 (rdev->family == CHIP_RV280) || \
1365                 (rdev->family == CHIP_RS300))
1366 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1367                 (rdev->family == CHIP_RV350) ||                 \
1368                 (rdev->family == CHIP_R350)  ||                 \
1369                 (rdev->family == CHIP_RV380) ||                 \
1370                 (rdev->family == CHIP_R420)  ||                 \
1371                 (rdev->family == CHIP_R423)  ||                 \
1372                 (rdev->family == CHIP_RV410) ||                 \
1373                 (rdev->family == CHIP_RS400) ||                 \
1374                 (rdev->family == CHIP_RS480))
1375 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1376                 (rdev->ddev->pdev->device == 0x9443) || \
1377                 (rdev->ddev->pdev->device == 0x944B) || \
1378                 (rdev->ddev->pdev->device == 0x9506) || \
1379                 (rdev->ddev->pdev->device == 0x9509) || \
1380                 (rdev->ddev->pdev->device == 0x950F) || \
1381                 (rdev->ddev->pdev->device == 0x689C) || \
1382                 (rdev->ddev->pdev->device == 0x689D))
1383 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1384 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1385                             (rdev->family == CHIP_RS690)  ||    \
1386                             (rdev->family == CHIP_RS740)  ||    \
1387                             (rdev->family >= CHIP_R600))
1388 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1389 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1390 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1391 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1392                              (rdev->flags & RADEON_IS_IGP))
1393 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1394
1395 /*
1396  * BIOS helpers.
1397  */
1398 #define RBIOS8(i) (rdev->bios[i])
1399 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1400 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1401
1402 int radeon_combios_init(struct radeon_device *rdev);
1403 void radeon_combios_fini(struct radeon_device *rdev);
1404 int radeon_atombios_init(struct radeon_device *rdev);
1405 void radeon_atombios_fini(struct radeon_device *rdev);
1406
1407
1408 /*
1409  * RING helpers.
1410  */
1411 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1412 {
1413 #if DRM_DEBUG_CODE
1414         if (rdev->cp.count_dw <= 0) {
1415                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1416         }
1417 #endif
1418         rdev->cp.ring[rdev->cp.wptr++] = v;
1419         rdev->cp.wptr &= rdev->cp.ptr_mask;
1420         rdev->cp.count_dw--;
1421         rdev->cp.ring_free_dw--;
1422 }
1423
1424
1425 /*
1426  * ASICs macro.
1427  */
1428 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1429 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1430 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1431 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1432 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1433 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1434 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1435 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1436 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1437 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1438 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1439 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1440 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1441 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1442 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1443 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1444 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1445 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1446 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1447 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1448 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1449 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1450 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1451 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1452 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1453 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1454 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1455 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1456 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1457 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1458 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1459 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1460 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1461 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1462 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1463 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1464 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1465 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1466 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1467 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1468 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1469 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1470 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1471 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1472
1473 /* Common functions */
1474 /* AGP */
1475 extern int radeon_gpu_reset(struct radeon_device *rdev);
1476 extern void radeon_agp_disable(struct radeon_device *rdev);
1477 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1478 extern void radeon_gart_restore(struct radeon_device *rdev);
1479 extern int radeon_modeset_init(struct radeon_device *rdev);
1480 extern void radeon_modeset_fini(struct radeon_device *rdev);
1481 extern bool radeon_card_posted(struct radeon_device *rdev);
1482 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1483 extern void radeon_update_display_priority(struct radeon_device *rdev);
1484 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1485 extern void radeon_scratch_init(struct radeon_device *rdev);
1486 extern void radeon_wb_fini(struct radeon_device *rdev);
1487 extern int radeon_wb_init(struct radeon_device *rdev);
1488 extern void radeon_wb_disable(struct radeon_device *rdev);
1489 extern void radeon_surface_init(struct radeon_device *rdev);
1490 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1491 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1492 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1493 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1494 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1495 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1496 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1497 extern int radeon_resume_kms(struct drm_device *dev);
1498 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1499 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1500
1501 /*
1502  * r600 functions used by radeon_encoder.c
1503  */
1504 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1505 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1506 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1507
1508 extern int ni_init_microcode(struct radeon_device *rdev);
1509 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1510
1511 /* radeon_acpi.c */
1512 #if defined(CONFIG_ACPI)
1513 extern int radeon_acpi_init(struct radeon_device *rdev);
1514 #else
1515 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1516 #endif
1517
1518 #include "radeon_object.h"
1519
1520 #endif