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ath5k: remove Atheros 11n devices from supported list
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath5k / base.c
blob2028866f59951068ebb799ee3209ef22d9ff13c6
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
46 #include <linux/hardirq.h>
47 #include <linux/if.h>
48 #include <linux/io.h>
49 #include <linux/netdevice.h>
50 #include <linux/cache.h>
51 #include <linux/pci.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54
55 #include <net/ieee80211_radiotap.h>
56
57 #include <asm/unaligned.h>
58
59 #include "base.h"
60 #include "reg.h"
61 #include "debug.h"
62
63 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
64
65
66 /******************\
67 * Internal defines *
68 \******************/
69
70 /* Module info */
71 MODULE_AUTHOR("Jiri Slaby");
72 MODULE_AUTHOR("Nick Kossifidis");
73 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
74 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
75 MODULE_LICENSE("Dual BSD/GPL");
76 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
77
78
79 /* Known PCI ids */
80 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
81 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
82 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
83 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
84 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
85 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
86 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
87 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
89 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
96 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
97 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
98 { 0 }
99 };
100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102 /* Known SREVs */
103 static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
105 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
106 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
107 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
108 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
109 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
110 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
111 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
112 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
113 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
114 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
115 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
116 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
117 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
118 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
119 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
120 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
121 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
127 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
128 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
134 };
135
136 /*
137 * Prototypes - PCI stack related functions
138 */
139 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
140 const struct pci_device_id *id);
141 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
142 #ifdef CONFIG_PM
143 static int ath5k_pci_suspend(struct pci_dev *pdev,
144 pm_message_t state);
145 static int ath5k_pci_resume(struct pci_dev *pdev);
146 #else
147 #define ath5k_pci_suspend NULL
148 #define ath5k_pci_resume NULL
149 #endif /* CONFIG_PM */
150
151 static struct pci_driver ath5k_pci_driver = {
152 .name = "ath5k_pci",
153 .id_table = ath5k_pci_id_table,
154 .probe = ath5k_pci_probe,
155 .remove = __devexit_p(ath5k_pci_remove),
156 .suspend = ath5k_pci_suspend,
157 .resume = ath5k_pci_resume,
158 };
159
160
161
162 /*
163 * Prototypes - MAC 802.11 stack related functions
164 */
165 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
166 static int ath5k_reset(struct ieee80211_hw *hw);
167 static int ath5k_start(struct ieee80211_hw *hw);
168 static void ath5k_stop(struct ieee80211_hw *hw);
169 static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171 static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173 static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
175 static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
177 struct ieee80211_if_conf *conf);
178 static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182 static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186 static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192 static int ath5k_beacon_update(struct ieee80211_hw *hw,
193 struct sk_buff *skb);
194
195 static struct ieee80211_ops ath5k_hw_ops = {
196 .tx = ath5k_tx,
197 .start = ath5k_start,
198 .stop = ath5k_stop,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
206 .conf_tx = NULL,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
210 };
211
212 /*
213 * Prototypes - Internal functions
214 */
215 /* Attach detach */
216 static int ath5k_attach(struct pci_dev *pdev,
217 struct ieee80211_hw *hw);
218 static void ath5k_detach(struct pci_dev *pdev,
219 struct ieee80211_hw *hw);
220 /* Channel/mode setup */
221 static inline short ath5k_ieee2mhz(short chan);
222 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
223 const struct ath5k_rate_table *rt,
224 unsigned int max);
225 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
226 struct ieee80211_channel *channels,
227 unsigned int mode,
228 unsigned int max);
229 static int ath5k_getchannels(struct ieee80211_hw *hw);
230 static int ath5k_chan_set(struct ath5k_softc *sc,
231 struct ieee80211_channel *chan);
232 static void ath5k_setcurmode(struct ath5k_softc *sc,
233 unsigned int mode);
234 static void ath5k_mode_setup(struct ath5k_softc *sc);
235 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
236
237 /* Descriptor setup */
238 static int ath5k_desc_alloc(struct ath5k_softc *sc,
239 struct pci_dev *pdev);
240 static void ath5k_desc_free(struct ath5k_softc *sc,
241 struct pci_dev *pdev);
242 /* Buffers setup */
243 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
244 struct ath5k_buf *bf);
245 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
246 struct ath5k_buf *bf);
247 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
248 struct ath5k_buf *bf)
249 {
250 BUG_ON(!bf);
251 if (!bf->skb)
252 return;
253 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
254 PCI_DMA_TODEVICE);
255 dev_kfree_skb(bf->skb);
256 bf->skb = NULL;
257 }
258
259 /* Queues setup */
260 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
261 int qtype, int subtype);
262 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
263 static int ath5k_beaconq_config(struct ath5k_softc *sc);
264 static void ath5k_txq_drainq(struct ath5k_softc *sc,
265 struct ath5k_txq *txq);
266 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
267 static void ath5k_txq_release(struct ath5k_softc *sc);
268 /* Rx handling */
269 static int ath5k_rx_start(struct ath5k_softc *sc);
270 static void ath5k_rx_stop(struct ath5k_softc *sc);
271 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
272 struct ath5k_desc *ds,
273 struct sk_buff *skb,
274 struct ath5k_rx_status *rs);
275 static void ath5k_tasklet_rx(unsigned long data);
276 /* Tx handling */
277 static void ath5k_tx_processq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279 static void ath5k_tasklet_tx(unsigned long data);
280 /* Beacon handling */
281 static int ath5k_beacon_setup(struct ath5k_softc *sc,
282 struct ath5k_buf *bf);
283 static void ath5k_beacon_send(struct ath5k_softc *sc);
284 static void ath5k_beacon_config(struct ath5k_softc *sc);
285 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
286
287 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
288 {
289 u64 tsf = ath5k_hw_get_tsf64(ah);
290
291 if ((tsf & 0x7fff) < rstamp)
292 tsf -= 0x8000;
293
294 return (tsf & ~0x7fff) | rstamp;
295 }
296
297 /* Interrupt handling */
298 static int ath5k_init(struct ath5k_softc *sc);
299 static int ath5k_stop_locked(struct ath5k_softc *sc);
300 static int ath5k_stop_hw(struct ath5k_softc *sc);
301 static irqreturn_t ath5k_intr(int irq, void *dev_id);
302 static void ath5k_tasklet_reset(unsigned long data);
303
304 static void ath5k_calibrate(unsigned long data);
305 /* LED functions */
306 static int ath5k_init_leds(struct ath5k_softc *sc);
307 static void ath5k_led_enable(struct ath5k_softc *sc);
308 static void ath5k_led_off(struct ath5k_softc *sc);
309 static void ath5k_unregister_leds(struct ath5k_softc *sc);
310
311 /*
312 * Module init/exit functions
313 */
314 static int __init
315 init_ath5k_pci(void)
316 {
317 int ret;
318
319 ath5k_debug_init();
320
321 ret = pci_register_driver(&ath5k_pci_driver);
322 if (ret) {
323 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
324 return ret;
325 }
326
327 return 0;
328 }
329
330 static void __exit
331 exit_ath5k_pci(void)
332 {
333 pci_unregister_driver(&ath5k_pci_driver);
334
335 ath5k_debug_finish();
336 }
337
338 module_init(init_ath5k_pci);
339 module_exit(exit_ath5k_pci);
340
341
342 /********************\
343 * PCI Initialization *
344 \********************/
345
346 static const char *
347 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
348 {
349 const char *name = "xxxxx";
350 unsigned int i;
351
352 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
353 if (srev_names[i].sr_type != type)
354 continue;
355 if ((val & 0xff) < srev_names[i + 1].sr_val) {
356 name = srev_names[i].sr_name;
357 break;
358 }
359 }
360
361 return name;
362 }
363
364 static int __devinit
365 ath5k_pci_probe(struct pci_dev *pdev,
366 const struct pci_device_id *id)
367 {
368 void __iomem *mem;
369 struct ath5k_softc *sc;
370 struct ieee80211_hw *hw;
371 int ret;
372 u8 csz;
373
374 ret = pci_enable_device(pdev);
375 if (ret) {
376 dev_err(&pdev->dev, "can't enable device\n");
377 goto err;
378 }
379
380 /* XXX 32-bit addressing only */
381 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
382 if (ret) {
383 dev_err(&pdev->dev, "32-bit DMA not available\n");
384 goto err_dis;
385 }
386
387 /*
388 * Cache line size is used to size and align various
389 * structures used to communicate with the hardware.
390 */
391 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
392 if (csz == 0) {
393 /*
394 * Linux 2.4.18 (at least) writes the cache line size
395 * register as a 16-bit wide register which is wrong.
396 * We must have this setup properly for rx buffer
397 * DMA to work so force a reasonable value here if it
398 * comes up zero.
399 */
400 csz = L1_CACHE_BYTES / sizeof(u32);
401 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
402 }
403 /*
404 * The default setting of latency timer yields poor results,
405 * set it to the value used by other systems. It may be worth
406 * tweaking this setting more.
407 */
408 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
409
410 /* Enable bus mastering */
411 pci_set_master(pdev);
412
413 /*
414 * Disable the RETRY_TIMEOUT register (0x41) to keep
415 * PCI Tx retries from interfering with C3 CPU state.
416 */
417 pci_write_config_byte(pdev, 0x41, 0);
418
419 ret = pci_request_region(pdev, 0, "ath5k");
420 if (ret) {
421 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
422 goto err_dis;
423 }
424
425 mem = pci_iomap(pdev, 0, 0);
426 if (!mem) {
427 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
428 ret = -EIO;
429 goto err_reg;
430 }
431
432 /*
433 * Allocate hw (mac80211 main struct)
434 * and hw->priv (driver private data)
435 */
436 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
437 if (hw == NULL) {
438 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
439 ret = -ENOMEM;
440 goto err_map;
441 }
442
443 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
444
445 /* Initialize driver private data */
446 SET_IEEE80211_DEV(hw, &pdev->dev);
447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
448 IEEE80211_HW_SIGNAL_DBM |
449 IEEE80211_HW_NOISE_DBM;
450 hw->extra_tx_headroom = 2;
451 hw->channel_change_time = 5000;
452 sc = hw->priv;
453 sc->hw = hw;
454 sc->pdev = pdev;
455
456 ath5k_debug_init_device(sc);
457
458 /*
459 * Mark the device as detached to avoid processing
460 * interrupts until setup is complete.
461 */
462 __set_bit(ATH_STAT_INVALID, sc->status);
463
464 sc->iobase = mem; /* So we can unmap it on detach */
465 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
466 sc->opmode = IEEE80211_IF_TYPE_STA;
467 mutex_init(&sc->lock);
468 spin_lock_init(&sc->rxbuflock);
469 spin_lock_init(&sc->txbuflock);
470
471 /* Set private data */
472 pci_set_drvdata(pdev, hw);
473
474 /* Setup interrupt handler */
475 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
476 if (ret) {
477 ATH5K_ERR(sc, "request_irq failed\n");
478 goto err_free;
479 }
480
481 /* Initialize device */
482 sc->ah = ath5k_hw_attach(sc, id->driver_data);
483 if (IS_ERR(sc->ah)) {
484 ret = PTR_ERR(sc->ah);
485 goto err_irq;
486 }
487
488 /* Finish private driver data initialization */
489 ret = ath5k_attach(pdev, hw);
490 if (ret)
491 goto err_ah;
492
493 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
494 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
495 sc->ah->ah_mac_srev,
496 sc->ah->ah_phy_revision);
497
498 if (!sc->ah->ah_single_chip) {
499 /* Single chip radio (!RF5111) */
500 if (sc->ah->ah_radio_5ghz_revision &&
501 !sc->ah->ah_radio_2ghz_revision) {
502 /* No 5GHz support -> report 2GHz radio */
503 if (!test_bit(AR5K_MODE_11A,
504 sc->ah->ah_capabilities.cap_mode)) {
505 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
506 ath5k_chip_name(AR5K_VERSION_RAD,
507 sc->ah->ah_radio_5ghz_revision),
508 sc->ah->ah_radio_5ghz_revision);
509 /* No 2GHz support (5110 and some
510 * 5Ghz only cards) -> report 5Ghz radio */
511 } else if (!test_bit(AR5K_MODE_11B,
512 sc->ah->ah_capabilities.cap_mode)) {
513 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
514 ath5k_chip_name(AR5K_VERSION_RAD,
515 sc->ah->ah_radio_5ghz_revision),
516 sc->ah->ah_radio_5ghz_revision);
517 /* Multiband radio */
518 } else {
519 ATH5K_INFO(sc, "RF%s multiband radio found"
520 " (0x%x)\n",
521 ath5k_chip_name(AR5K_VERSION_RAD,
522 sc->ah->ah_radio_5ghz_revision),
523 sc->ah->ah_radio_5ghz_revision);
524 }
525 }
526 /* Multi chip radio (RF5111 - RF2111) ->
527 * report both 2GHz/5GHz radios */
528 else if (sc->ah->ah_radio_5ghz_revision &&
529 sc->ah->ah_radio_2ghz_revision){
530 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
531 ath5k_chip_name(AR5K_VERSION_RAD,
532 sc->ah->ah_radio_5ghz_revision),
533 sc->ah->ah_radio_5ghz_revision);
534 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_2ghz_revision),
537 sc->ah->ah_radio_2ghz_revision);
538 }
539 }
540
541
542 /* ready to process interrupts */
543 __clear_bit(ATH_STAT_INVALID, sc->status);
544
545 return 0;
546 err_ah:
547 ath5k_hw_detach(sc->ah);
548 err_irq:
549 free_irq(pdev->irq, sc);
550 err_free:
551 ieee80211_free_hw(hw);
552 err_map:
553 pci_iounmap(pdev, mem);
554 err_reg:
555 pci_release_region(pdev, 0);
556 err_dis:
557 pci_disable_device(pdev);
558 err:
559 return ret;
560 }
561
562 static void __devexit
563 ath5k_pci_remove(struct pci_dev *pdev)
564 {
565 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
566 struct ath5k_softc *sc = hw->priv;
567
568 ath5k_debug_finish_device(sc);
569 ath5k_detach(pdev, hw);
570 ath5k_hw_detach(sc->ah);
571 free_irq(pdev->irq, sc);
572 pci_iounmap(pdev, sc->iobase);
573 pci_release_region(pdev, 0);
574 pci_disable_device(pdev);
575 ieee80211_free_hw(hw);
576 }
577
578 #ifdef CONFIG_PM
579 static int
580 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
581 {
582 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
583 struct ath5k_softc *sc = hw->priv;
584
585 ath5k_led_off(sc);
586
587 ath5k_stop_hw(sc);
588
589 free_irq(pdev->irq, sc);
590 pci_disable_msi(pdev);
591 pci_save_state(pdev);
592 pci_disable_device(pdev);
593 pci_set_power_state(pdev, PCI_D3hot);
594
595 return 0;
596 }
597
598 static int
599 ath5k_pci_resume(struct pci_dev *pdev)
600 {
601 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
602 struct ath5k_softc *sc = hw->priv;
603 struct ath5k_hw *ah = sc->ah;
604 int i, err;
605
606 pci_restore_state(pdev);
607
608 err = pci_enable_device(pdev);
609 if (err)
610 return err;
611
612 /*
613 * Suspend/Resume resets the PCI configuration space, so we have to
614 * re-disable the RETRY_TIMEOUT register (0x41) to keep
615 * PCI Tx retries from interfering with C3 CPU state
616 */
617 pci_write_config_byte(pdev, 0x41, 0);
618
619 pci_enable_msi(pdev);
620
621 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
622 if (err) {
623 ATH5K_ERR(sc, "request_irq failed\n");
624 goto err_msi;
625 }
626
627 err = ath5k_init(sc);
628 if (err)
629 goto err_irq;
630 ath5k_led_enable(sc);
631
632 /*
633 * Reset the key cache since some parts do not
634 * reset the contents on initial power up or resume.
635 *
636 * FIXME: This may need to be revisited when mac80211 becomes
637 * aware of suspend/resume.
638 */
639 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
640 ath5k_hw_reset_key(ah, i);
641
642 return 0;
643 err_irq:
644 free_irq(pdev->irq, sc);
645 err_msi:
646 pci_disable_msi(pdev);
647 pci_disable_device(pdev);
648 return err;
649 }
650 #endif /* CONFIG_PM */
651
652
653
654 /***********************\
655 * Driver Initialization *
656 \***********************/
657
658 static int
659 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
660 {
661 struct ath5k_softc *sc = hw->priv;
662 struct ath5k_hw *ah = sc->ah;
663 u8 mac[ETH_ALEN];
664 unsigned int i;
665 int ret;
666
667 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
668
669 /*
670 * Check if the MAC has multi-rate retry support.
671 * We do this by trying to setup a fake extended
672 * descriptor. MAC's that don't have support will
673 * return false w/o doing anything. MAC's that do
674 * support it will return true w/o doing anything.
675 */
676 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
677 if (ret < 0)
678 goto err;
679 if (ret > 0)
680 __set_bit(ATH_STAT_MRRETRY, sc->status);
681
682 /*
683 * Reset the key cache since some parts do not
684 * reset the contents on initial power up.
685 */
686 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
687 ath5k_hw_reset_key(ah, i);
688
689 /*
690 * Collect the channel list. The 802.11 layer
691 * is resposible for filtering this list based
692 * on settings like the phy mode and regulatory
693 * domain restrictions.
694 */
695 ret = ath5k_getchannels(hw);
696 if (ret) {
697 ATH5K_ERR(sc, "can't get channels\n");
698 goto err;
699 }
700
701 /* Set *_rates so we can map hw rate index */
702 ath5k_set_total_hw_rates(sc);
703
704 /* NB: setup here so ath5k_rate_update is happy */
705 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
706 ath5k_setcurmode(sc, AR5K_MODE_11A);
707 else
708 ath5k_setcurmode(sc, AR5K_MODE_11B);
709
710 /*
711 * Allocate tx+rx descriptors and populate the lists.
712 */
713 ret = ath5k_desc_alloc(sc, pdev);
714 if (ret) {
715 ATH5K_ERR(sc, "can't allocate descriptors\n");
716 goto err;
717 }
718
719 /*
720 * Allocate hardware transmit queues: one queue for
721 * beacon frames and one data queue for each QoS
722 * priority. Note that hw functions handle reseting
723 * these queues at the needed time.
724 */
725 ret = ath5k_beaconq_setup(ah);
726 if (ret < 0) {
727 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
728 goto err_desc;
729 }
730 sc->bhalq = ret;
731
732 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
733 if (IS_ERR(sc->txq)) {
734 ATH5K_ERR(sc, "can't setup xmit queue\n");
735 ret = PTR_ERR(sc->txq);
736 goto err_bhal;
737 }
738
739 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
740 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
741 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
742 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
743
744 ath5k_hw_get_lladdr(ah, mac);
745 SET_IEEE80211_PERM_ADDR(hw, mac);
746 /* All MAC address bits matter for ACKs */
747 memset(sc->bssidmask, 0xff, ETH_ALEN);
748 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
749
750 ret = ieee80211_register_hw(hw);
751 if (ret) {
752 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
753 goto err_queues;
754 }
755
756 ath5k_init_leds(sc);
757
758 return 0;
759 err_queues:
760 ath5k_txq_release(sc);
761 err_bhal:
762 ath5k_hw_release_tx_queue(ah, sc->bhalq);
763 err_desc:
764 ath5k_desc_free(sc, pdev);
765 err:
766 return ret;
767 }
768
769 static void
770 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
771 {
772 struct ath5k_softc *sc = hw->priv;
773
774 /*
775 * NB: the order of these is important:
776 * o call the 802.11 layer before detaching ath5k_hw to
777 * insure callbacks into the driver to delete global
778 * key cache entries can be handled
779 * o reclaim the tx queue data structures after calling
780 * the 802.11 layer as we'll get called back to reclaim
781 * node state and potentially want to use them
782 * o to cleanup the tx queues the hal is called, so detach
783 * it last
784 * XXX: ??? detach ath5k_hw ???
785 * Other than that, it's straightforward...
786 */
787 ieee80211_unregister_hw(hw);
788 ath5k_desc_free(sc, pdev);
789 ath5k_txq_release(sc);
790 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
791 ath5k_unregister_leds(sc);
792
793 /*
794 * NB: can't reclaim these until after ieee80211_ifdetach
795 * returns because we'll get called back to reclaim node
796 * state and potentially want to use them.
797 */
798 }
799
800
801
802
803 /********************\
804 * Channel/mode setup *
805 \********************/
806
807 /*
808 * Convert IEEE channel number to MHz frequency.
809 */
810 static inline short
811 ath5k_ieee2mhz(short chan)
812 {
813 if (chan <= 14 || chan >= 27)
814 return ieee80211chan2mhz(chan);
815 else
816 return 2212 + chan * 20;
817 }
818
819 static unsigned int
820 ath5k_copy_rates(struct ieee80211_rate *rates,
821 const struct ath5k_rate_table *rt,
822 unsigned int max)
823 {
824 unsigned int i, count;
825
826 if (rt == NULL)
827 return 0;
828
829 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
830 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
831 rates[count].hw_value = rt->rates[i].rate_code;
832 rates[count].flags = rt->rates[i].modulation;
833 count++;
834 max--;
835 }
836
837 return count;
838 }
839
840 static unsigned int
841 ath5k_copy_channels(struct ath5k_hw *ah,
842 struct ieee80211_channel *channels,
843 unsigned int mode,
844 unsigned int max)
845 {
846 unsigned int i, count, size, chfreq, freq, ch;
847
848 if (!test_bit(mode, ah->ah_modes))
849 return 0;
850
851 switch (mode) {
852 case AR5K_MODE_11A:
853 case AR5K_MODE_11A_TURBO:
854 /* 1..220, but 2GHz frequencies are filtered by check_channel */
855 size = 220 ;
856 chfreq = CHANNEL_5GHZ;
857 break;
858 case AR5K_MODE_11B:
859 case AR5K_MODE_11G:
860 case AR5K_MODE_11G_TURBO:
861 size = 26;
862 chfreq = CHANNEL_2GHZ;
863 break;
864 default:
865 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
866 return 0;
867 }
868
869 for (i = 0, count = 0; i < size && max > 0; i++) {
870 ch = i + 1 ;
871 freq = ath5k_ieee2mhz(ch);
872
873 /* Check if channel is supported by the chipset */
874 if (!ath5k_channel_ok(ah, freq, chfreq))
875 continue;
876
877 /* Write channel info and increment counter */
878 channels[count].center_freq = freq;
879 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
880 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
881 switch (mode) {
882 case AR5K_MODE_11A:
883 case AR5K_MODE_11G:
884 channels[count].hw_value = chfreq | CHANNEL_OFDM;
885 break;
886 case AR5K_MODE_11A_TURBO:
887 case AR5K_MODE_11G_TURBO:
888 channels[count].hw_value = chfreq |
889 CHANNEL_OFDM | CHANNEL_TURBO;
890 break;
891 case AR5K_MODE_11B:
892 channels[count].hw_value = CHANNEL_B;
893 }
894
895 count++;
896 max--;
897 }
898
899 return count;
900 }
901
902 static int
903 ath5k_getchannels(struct ieee80211_hw *hw)
904 {
905 struct ath5k_softc *sc = hw->priv;
906 struct ath5k_hw *ah = sc->ah;
907 struct ieee80211_supported_band *sbands = sc->sbands;
908 const struct ath5k_rate_table *hw_rates;
909 unsigned int max_r, max_c, count_r, count_c;
910 int mode2g = AR5K_MODE_11G;
911
912 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
913
914 max_r = ARRAY_SIZE(sc->rates);
915 max_c = ARRAY_SIZE(sc->channels);
916 count_r = count_c = 0;
917
918 /* 2GHz band */
919 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
920 mode2g = AR5K_MODE_11B;
921 if (!test_bit(AR5K_MODE_11B,
922 sc->ah->ah_capabilities.cap_mode))
923 mode2g = -1;
924 }
925
926 if (mode2g > 0) {
927 struct ieee80211_supported_band *sband =
928 &sbands[IEEE80211_BAND_2GHZ];
929
930 sband->bitrates = sc->rates;
931 sband->channels = sc->channels;
932
933 sband->band = IEEE80211_BAND_2GHZ;
934 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
935 mode2g, max_c);
936
937 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
938 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
939 hw_rates, max_r);
940
941 count_c = sband->n_channels;
942 count_r = sband->n_bitrates;
943
944 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
945
946 max_r -= count_r;
947 max_c -= count_c;
948
949 }
950
951 /* 5GHz band */
952
953 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
954 struct ieee80211_supported_band *sband =
955 &sbands[IEEE80211_BAND_5GHZ];
956
957 sband->bitrates = &sc->rates[count_r];
958 sband->channels = &sc->channels[count_c];
959
960 sband->band = IEEE80211_BAND_5GHZ;
961 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
962 AR5K_MODE_11A, max_c);
963
964 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
965 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
966 hw_rates, max_r);
967
968 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
969 }
970
971 ath5k_debug_dump_bands(sc);
972
973 return 0;
974 }
975
976 /*
977 * Set/change channels. If the channel is really being changed,
978 * it's done by reseting the chip. To accomplish this we must
979 * first cleanup any pending DMA, then restart stuff after a la
980 * ath5k_init.
981 */
982 static int
983 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
984 {
985 struct ath5k_hw *ah = sc->ah;
986 int ret;
987
988 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
989 sc->curchan->center_freq, chan->center_freq);
990
991 if (chan->center_freq != sc->curchan->center_freq ||
992 chan->hw_value != sc->curchan->hw_value) {
993
994 sc->curchan = chan;
995 sc->curband = &sc->sbands[chan->band];
996
997 /*
998 * To switch channels clear any pending DMA operations;
999 * wait long enough for the RX fifo to drain, reset the
1000 * hardware at the new frequency, and then re-enable
1001 * the relevant bits of the h/w.
1002 */
1003 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1004 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1005 ath5k_rx_stop(sc); /* turn off frame recv */
1006 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
1007 if (ret) {
1008 ATH5K_ERR(sc, "%s: unable to reset channel "
1009 "(%u Mhz)\n", __func__, chan->center_freq);
1010 return ret;
1011 }
1012
1013 ath5k_hw_set_txpower_limit(sc->ah, 0);
1014
1015 /*
1016 * Re-enable rx framework.
1017 */
1018 ret = ath5k_rx_start(sc);
1019 if (ret) {
1020 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1021 __func__);
1022 return ret;
1023 }
1024
1025 /*
1026 * Change channels and update the h/w rate map
1027 * if we're switching; e.g. 11a to 11b/g.
1028 *
1029 * XXX needed?
1030 */
1031 /* ath5k_chan_change(sc, chan); */
1032
1033 ath5k_beacon_config(sc);
1034 /*
1035 * Re-enable interrupts.
1036 */
1037 ath5k_hw_set_intr(ah, sc->imask);
1038 }
1039
1040 return 0;
1041 }
1042
1043 static void
1044 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1045 {
1046 sc->curmode = mode;
1047
1048 if (mode == AR5K_MODE_11A) {
1049 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1050 } else {
1051 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1052 }
1053 }
1054
1055 static void
1056 ath5k_mode_setup(struct ath5k_softc *sc)
1057 {
1058 struct ath5k_hw *ah = sc->ah;
1059 u32 rfilt;
1060
1061 /* configure rx filter */
1062 rfilt = sc->filter_flags;
1063 ath5k_hw_set_rx_filter(ah, rfilt);
1064
1065 if (ath5k_hw_hasbssidmask(ah))
1066 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1067
1068 /* configure operational mode */
1069 ath5k_hw_set_opmode(ah);
1070
1071 ath5k_hw_set_mcast_filter(ah, 0, 0);
1072 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1073 }
1074
1075 /*
1076 * Match the hw provided rate index (through descriptors)
1077 * to an index for sc->curband->bitrates, so it can be used
1078 * by the stack.
1079 *
1080 * This one is a little bit tricky but i think i'm right
1081 * about this...
1082 *
1083 * We have 4 rate tables in the following order:
1084 * XR (4 rates)
1085 * 802.11a (8 rates)
1086 * 802.11b (4 rates)
1087 * 802.11g (12 rates)
1088 * that make the hw rate table.
1089 *
1090 * Lets take a 5211 for example that supports a and b modes only.
1091 * First comes the 802.11a table and then 802.11b (total 12 rates).
1092 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1093 * if it returns 2 it points to the second 802.11a rate etc.
1094 *
1095 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1096 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1097 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1098 */
1099 static void
1100 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1101
1102 struct ath5k_hw *ah = sc->ah;
1103
1104 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1105 sc->a_rates = 8;
1106
1107 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1108 sc->b_rates = 4;
1109
1110 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1111 sc->g_rates = 12;
1112
1113 /* XXX: Need to see what what happens when
1114 xr disable bits in eeprom are set */
1115 if (ah->ah_version >= AR5K_AR5212)
1116 sc->xr_rates = 4;
1117
1118 }
1119
1120 static inline int
1121 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1122
1123 int mac80211_rix;
1124
1125 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1126 /* We setup a g ratetable for both b/g modes */
1127 mac80211_rix =
1128 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1129 } else {
1130 mac80211_rix = hw_rix - sc->xr_rates;
1131 }
1132
1133 /* Something went wrong, fallback to basic rate for this band */
1134 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1135 (mac80211_rix <= 0 ))
1136 mac80211_rix = 1;
1137
1138 return mac80211_rix;
1139 }
1140
1141
1142
1143
1144 /***************\
1145 * Buffers setup *
1146 \***************/
1147
1148 static int
1149 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1150 {
1151 struct ath5k_hw *ah = sc->ah;
1152 struct sk_buff *skb = bf->skb;
1153 struct ath5k_desc *ds;
1154
1155 if (likely(skb == NULL)) {
1156 unsigned int off;
1157
1158 /*
1159 * Allocate buffer with headroom_needed space for the
1160 * fake physical layer header at the start.
1161 */
1162 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1163 if (unlikely(skb == NULL)) {
1164 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1165 sc->rxbufsize + sc->cachelsz - 1);
1166 return -ENOMEM;
1167 }
1168 /*
1169 * Cache-line-align. This is important (for the
1170 * 5210 at least) as not doing so causes bogus data
1171 * in rx'd frames.
1172 */
1173 off = ((unsigned long)skb->data) % sc->cachelsz;
1174 if (off != 0)
1175 skb_reserve(skb, sc->cachelsz - off);
1176
1177 bf->skb = skb;
1178 bf->skbaddr = pci_map_single(sc->pdev,
1179 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1180 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1181 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1182 dev_kfree_skb(skb);
1183 bf->skb = NULL;
1184 return -ENOMEM;
1185 }
1186 }
1187
1188 /*
1189 * Setup descriptors. For receive we always terminate
1190 * the descriptor list with a self-linked entry so we'll
1191 * not get overrun under high load (as can happen with a
1192 * 5212 when ANI processing enables PHY error frames).
1193 *
1194 * To insure the last descriptor is self-linked we create
1195 * each descriptor as self-linked and add it to the end. As
1196 * each additional descriptor is added the previous self-linked
1197 * entry is ``fixed'' naturally. This should be safe even
1198 * if DMA is happening. When processing RX interrupts we
1199 * never remove/process the last, self-linked, entry on the
1200 * descriptor list. This insures the hardware always has
1201 * someplace to write a new frame.
1202 */
1203 ds = bf->desc;
1204 ds->ds_link = bf->daddr; /* link to self */
1205 ds->ds_data = bf->skbaddr;
1206 ath5k_hw_setup_rx_desc(ah, ds,
1207 skb_tailroom(skb), /* buffer size */
1208 0);
1209
1210 if (sc->rxlink != NULL)
1211 *sc->rxlink = bf->daddr;
1212 sc->rxlink = &ds->ds_link;
1213 return 0;
1214 }
1215
1216 static int
1217 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1218 {
1219 struct ath5k_hw *ah = sc->ah;
1220 struct ath5k_txq *txq = sc->txq;
1221 struct ath5k_desc *ds = bf->desc;
1222 struct sk_buff *skb = bf->skb;
1223 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1224 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1225 int ret;
1226
1227 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1228
1229 /* XXX endianness */
1230 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1231 PCI_DMA_TODEVICE);
1232
1233 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1234 flags |= AR5K_TXDESC_NOACK;
1235
1236 pktlen = skb->len;
1237
1238 if (info->control.hw_key) {
1239 keyidx = info->control.hw_key->hw_key_idx;
1240 pktlen += info->control.icv_len;
1241 }
1242 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1243 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1244 (sc->power_level * 2),
1245 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1246 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1247 if (ret)
1248 goto err_unmap;
1249
1250 ds->ds_link = 0;
1251 ds->ds_data = bf->skbaddr;
1252
1253 spin_lock_bh(&txq->lock);
1254 list_add_tail(&bf->list, &txq->q);
1255 sc->tx_stats[txq->qnum].len++;
1256 if (txq->link == NULL) /* is this first packet? */
1257 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1258 else /* no, so only link it */
1259 *txq->link = bf->daddr;
1260
1261 txq->link = &ds->ds_link;
1262 ath5k_hw_tx_start(ah, txq->qnum);
1263 mmiowb();
1264 spin_unlock_bh(&txq->lock);
1265
1266 return 0;
1267 err_unmap:
1268 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1269 return ret;
1270 }
1271
1272 /*******************\
1273 * Descriptors setup *
1274 \*******************/
1275
1276 static int
1277 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1278 {
1279 struct ath5k_desc *ds;
1280 struct ath5k_buf *bf;
1281 dma_addr_t da;
1282 unsigned int i;
1283 int ret;
1284
1285 /* allocate descriptors */
1286 sc->desc_len = sizeof(struct ath5k_desc) *
1287 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1288 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1289 if (sc->desc == NULL) {
1290 ATH5K_ERR(sc, "can't allocate descriptors\n");
1291 ret = -ENOMEM;
1292 goto err;
1293 }
1294 ds = sc->desc;
1295 da = sc->desc_daddr;
1296 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1297 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1298
1299 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1300 sizeof(struct ath5k_buf), GFP_KERNEL);
1301 if (bf == NULL) {
1302 ATH5K_ERR(sc, "can't allocate bufptr\n");
1303 ret = -ENOMEM;
1304 goto err_free;
1305 }
1306 sc->bufptr = bf;
1307
1308 INIT_LIST_HEAD(&sc->rxbuf);
1309 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1310 bf->desc = ds;
1311 bf->daddr = da;
1312 list_add_tail(&bf->list, &sc->rxbuf);
1313 }
1314
1315 INIT_LIST_HEAD(&sc->txbuf);
1316 sc->txbuf_len = ATH_TXBUF;
1317 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1318 da += sizeof(*ds)) {
1319 bf->desc = ds;
1320 bf->daddr = da;
1321 list_add_tail(&bf->list, &sc->txbuf);
1322 }
1323
1324 /* beacon buffer */
1325 bf->desc = ds;
1326 bf->daddr = da;
1327 sc->bbuf = bf;
1328
1329 return 0;
1330 err_free:
1331 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1332 err:
1333 sc->desc = NULL;
1334 return ret;
1335 }
1336
1337 static void
1338 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1339 {
1340 struct ath5k_buf *bf;
1341
1342 ath5k_txbuf_free(sc, sc->bbuf);
1343 list_for_each_entry(bf, &sc->txbuf, list)
1344 ath5k_txbuf_free(sc, bf);
1345 list_for_each_entry(bf, &sc->rxbuf, list)
1346 ath5k_txbuf_free(sc, bf);
1347
1348 /* Free memory associated with all descriptors */
1349 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1350
1351 kfree(sc->bufptr);
1352 sc->bufptr = NULL;
1353 }
1354
1355
1356
1357
1358
1359 /**************\
1360 * Queues setup *
1361 \**************/
1362
1363 static struct ath5k_txq *
1364 ath5k_txq_setup(struct ath5k_softc *sc,
1365 int qtype, int subtype)
1366 {
1367 struct ath5k_hw *ah = sc->ah;
1368 struct ath5k_txq *txq;
1369 struct ath5k_txq_info qi = {
1370 .tqi_subtype = subtype,
1371 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1372 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1373 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1374 };
1375 int qnum;
1376
1377 /*
1378 * Enable interrupts only for EOL and DESC conditions.
1379 * We mark tx descriptors to receive a DESC interrupt
1380 * when a tx queue gets deep; otherwise waiting for the
1381 * EOL to reap descriptors. Note that this is done to
1382 * reduce interrupt load and this only defers reaping
1383 * descriptors, never transmitting frames. Aside from
1384 * reducing interrupts this also permits more concurrency.
1385 * The only potential downside is if the tx queue backs
1386 * up in which case the top half of the kernel may backup
1387 * due to a lack of tx descriptors.
1388 */
1389 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1390 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1391 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1392 if (qnum < 0) {
1393 /*
1394 * NB: don't print a message, this happens
1395 * normally on parts with too few tx queues
1396 */
1397 return ERR_PTR(qnum);
1398 }
1399 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1400 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1401 qnum, ARRAY_SIZE(sc->txqs));
1402 ath5k_hw_release_tx_queue(ah, qnum);
1403 return ERR_PTR(-EINVAL);
1404 }
1405 txq = &sc->txqs[qnum];
1406 if (!txq->setup) {
1407 txq->qnum = qnum;
1408 txq->link = NULL;
1409 INIT_LIST_HEAD(&txq->q);
1410 spin_lock_init(&txq->lock);
1411 txq->setup = true;
1412 }
1413 return &sc->txqs[qnum];
1414 }
1415
1416 static int
1417 ath5k_beaconq_setup(struct ath5k_hw *ah)
1418 {
1419 struct ath5k_txq_info qi = {
1420 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1421 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1422 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1423 /* NB: for dynamic turbo, don't enable any other interrupts */
1424 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1425 };
1426
1427 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1428 }
1429
1430 static int
1431 ath5k_beaconq_config(struct ath5k_softc *sc)
1432 {
1433 struct ath5k_hw *ah = sc->ah;
1434 struct ath5k_txq_info qi;
1435 int ret;
1436
1437 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1438 if (ret)
1439 return ret;
1440 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1441 /*
1442 * Always burst out beacon and CAB traffic
1443 * (aifs = cwmin = cwmax = 0)
1444 */
1445 qi.tqi_aifs = 0;
1446 qi.tqi_cw_min = 0;
1447 qi.tqi_cw_max = 0;
1448 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1449 /*
1450 * Adhoc mode; backoff between 0 and (2 * cw_min).
1451 */
1452 qi.tqi_aifs = 0;
1453 qi.tqi_cw_min = 0;
1454 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1455 }
1456
1457 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1458 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1459 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1460
1461 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1462 if (ret) {
1463 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1464 "hardware queue!\n", __func__);
1465 return ret;
1466 }
1467
1468 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1469 }
1470
1471 static void
1472 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1473 {
1474 struct ath5k_buf *bf, *bf0;
1475
1476 /*
1477 * NB: this assumes output has been stopped and
1478 * we do not need to block ath5k_tx_tasklet
1479 */
1480 spin_lock_bh(&txq->lock);
1481 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1482 ath5k_debug_printtxbuf(sc, bf);
1483
1484 ath5k_txbuf_free(sc, bf);
1485
1486 spin_lock_bh(&sc->txbuflock);
1487 sc->tx_stats[txq->qnum].len--;
1488 list_move_tail(&bf->list, &sc->txbuf);
1489 sc->txbuf_len++;
1490 spin_unlock_bh(&sc->txbuflock);
1491 }
1492 txq->link = NULL;
1493 spin_unlock_bh(&txq->lock);
1494 }
1495
1496 /*
1497 * Drain the transmit queues and reclaim resources.
1498 */
1499 static void
1500 ath5k_txq_cleanup(struct ath5k_softc *sc)
1501 {
1502 struct ath5k_hw *ah = sc->ah;
1503 unsigned int i;
1504
1505 /* XXX return value */
1506 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1507 /* don't touch the hardware if marked invalid */
1508 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1509 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1510 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1511 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1512 if (sc->txqs[i].setup) {
1513 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1514 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1515 "link %p\n",
1516 sc->txqs[i].qnum,
1517 ath5k_hw_get_tx_buf(ah,
1518 sc->txqs[i].qnum),
1519 sc->txqs[i].link);
1520 }
1521 }
1522 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1523
1524 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1525 if (sc->txqs[i].setup)
1526 ath5k_txq_drainq(sc, &sc->txqs[i]);
1527 }
1528
1529 static void
1530 ath5k_txq_release(struct ath5k_softc *sc)
1531 {
1532 struct ath5k_txq *txq = sc->txqs;
1533 unsigned int i;
1534
1535 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1536 if (txq->setup) {
1537 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1538 txq->setup = false;
1539 }
1540 }
1541
1542
1543
1544
1545 /*************\
1546 * RX Handling *
1547 \*************/
1548
1549 /*
1550 * Enable the receive h/w following a reset.
1551 */
1552 static int
1553 ath5k_rx_start(struct ath5k_softc *sc)
1554 {
1555 struct ath5k_hw *ah = sc->ah;
1556 struct ath5k_buf *bf;
1557 int ret;
1558
1559 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1560
1561 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1562 sc->cachelsz, sc->rxbufsize);
1563
1564 sc->rxlink = NULL;
1565
1566 spin_lock_bh(&sc->rxbuflock);
1567 list_for_each_entry(bf, &sc->rxbuf, list) {
1568 ret = ath5k_rxbuf_setup(sc, bf);
1569 if (ret != 0) {
1570 spin_unlock_bh(&sc->rxbuflock);
1571 goto err;
1572 }
1573 }
1574 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1575 spin_unlock_bh(&sc->rxbuflock);
1576
1577 ath5k_hw_put_rx_buf(ah, bf->daddr);
1578 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1579 ath5k_mode_setup(sc); /* set filters, etc. */
1580 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1581
1582 return 0;
1583 err:
1584 return ret;
1585 }
1586
1587 /*
1588 * Disable the receive h/w in preparation for a reset.
1589 */
1590 static void
1591 ath5k_rx_stop(struct ath5k_softc *sc)
1592 {
1593 struct ath5k_hw *ah = sc->ah;
1594
1595 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1596 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1597 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1598
1599 ath5k_debug_printrxbuffs(sc, ah);
1600
1601 sc->rxlink = NULL; /* just in case */
1602 }
1603
1604 static unsigned int
1605 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1606 struct sk_buff *skb, struct ath5k_rx_status *rs)
1607 {
1608 struct ieee80211_hdr *hdr = (void *)skb->data;
1609 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1610
1611 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1612 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1613 return RX_FLAG_DECRYPTED;
1614
1615 /* Apparently when a default key is used to decrypt the packet
1616 the hw does not set the index used to decrypt. In such cases
1617 get the index from the packet. */
1618 if (ieee80211_has_protected(hdr->frame_control) &&
1619 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1620 skb->len >= hlen + 4) {
1621 keyix = skb->data[hlen + 3] >> 6;
1622
1623 if (test_bit(keyix, sc->keymap))
1624 return RX_FLAG_DECRYPTED;
1625 }
1626
1627 return 0;
1628 }
1629
1630
1631 static void
1632 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1633 struct ieee80211_rx_status *rxs)
1634 {
1635 u64 tsf, bc_tstamp;
1636 u32 hw_tu;
1637 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1638
1639 if (ieee80211_is_beacon(mgmt->frame_control) &&
1640 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1641 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1642 /*
1643 * Received an IBSS beacon with the same BSSID. Hardware *must*
1644 * have updated the local TSF. We have to work around various
1645 * hardware bugs, though...
1646 */
1647 tsf = ath5k_hw_get_tsf64(sc->ah);
1648 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1649 hw_tu = TSF_TO_TU(tsf);
1650
1651 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1652 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1653 (unsigned long long)bc_tstamp,
1654 (unsigned long long)rxs->mactime,
1655 (unsigned long long)(rxs->mactime - bc_tstamp),
1656 (unsigned long long)tsf);
1657
1658 /*
1659 * Sometimes the HW will give us a wrong tstamp in the rx
1660 * status, causing the timestamp extension to go wrong.
1661 * (This seems to happen especially with beacon frames bigger
1662 * than 78 byte (incl. FCS))
1663 * But we know that the receive timestamp must be later than the
1664 * timestamp of the beacon since HW must have synced to that.
1665 *
1666 * NOTE: here we assume mactime to be after the frame was
1667 * received, not like mac80211 which defines it at the start.
1668 */
1669 if (bc_tstamp > rxs->mactime) {
1670 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1671 "fixing mactime from %llx to %llx\n",
1672 (unsigned long long)rxs->mactime,
1673 (unsigned long long)tsf);
1674 rxs->mactime = tsf;
1675 }
1676
1677 /*
1678 * Local TSF might have moved higher than our beacon timers,
1679 * in that case we have to update them to continue sending
1680 * beacons. This also takes care of synchronizing beacon sending
1681 * times with other stations.
1682 */
1683 if (hw_tu >= sc->nexttbtt)
1684 ath5k_beacon_update_timers(sc, bc_tstamp);
1685 }
1686 }
1687
1688
1689 static void
1690 ath5k_tasklet_rx(unsigned long data)
1691 {
1692 struct ieee80211_rx_status rxs = {};
1693 struct ath5k_rx_status rs = {};
1694 struct sk_buff *skb;
1695 struct ath5k_softc *sc = (void *)data;
1696 struct ath5k_buf *bf, *bf_last;
1697 struct ath5k_desc *ds;
1698 int ret;
1699 int hdrlen;
1700 int pad;
1701
1702 spin_lock(&sc->rxbuflock);
1703 if (list_empty(&sc->rxbuf)) {
1704 ATH5K_WARN(sc, "empty rx buf pool\n");
1705 goto unlock;
1706 }
1707 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1708 do {
1709 rxs.flag = 0;
1710
1711 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1712 BUG_ON(bf->skb == NULL);
1713 skb = bf->skb;
1714 ds = bf->desc;
1715
1716 /*
1717 * last buffer must not be freed to ensure proper hardware
1718 * function. When the hardware finishes also a packet next to
1719 * it, we are sure, it doesn't use it anymore and we can go on.
1720 */
1721 if (bf_last == bf)
1722 bf->flags |= 1;
1723 if (bf->flags) {
1724 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1725 struct ath5k_buf, list);
1726 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1727 &rs);
1728 if (ret)
1729 break;
1730 bf->flags &= ~1;
1731 /* skip the overwritten one (even status is martian) */
1732 goto next;
1733 }
1734
1735 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1736 if (unlikely(ret == -EINPROGRESS))
1737 break;
1738 else if (unlikely(ret)) {
1739 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1740 spin_unlock(&sc->rxbuflock);
1741 return;
1742 }
1743
1744 if (unlikely(rs.rs_more)) {
1745 ATH5K_WARN(sc, "unsupported jumbo\n");
1746 goto next;
1747 }
1748
1749 if (unlikely(rs.rs_status)) {
1750 if (rs.rs_status & AR5K_RXERR_PHY)
1751 goto next;
1752 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1753 /*
1754 * Decrypt error. If the error occurred
1755 * because there was no hardware key, then
1756 * let the frame through so the upper layers
1757 * can process it. This is necessary for 5210
1758 * parts which have no way to setup a ``clear''
1759 * key cache entry.
1760 *
1761 * XXX do key cache faulting
1762 */
1763 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1764 !(rs.rs_status & AR5K_RXERR_CRC))
1765 goto accept;
1766 }
1767 if (rs.rs_status & AR5K_RXERR_MIC) {
1768 rxs.flag |= RX_FLAG_MMIC_ERROR;
1769 goto accept;
1770 }
1771
1772 /* let crypto-error packets fall through in MNTR */
1773 if ((rs.rs_status &
1774 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1775 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1776 goto next;
1777 }
1778 accept:
1779 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1780 PCI_DMA_FROMDEVICE);
1781 bf->skb = NULL;
1782
1783 skb_put(skb, rs.rs_datalen);
1784
1785 /*
1786 * the hardware adds a padding to 4 byte boundaries between
1787 * the header and the payload data if the header length is
1788 * not multiples of 4 - remove it
1789 */
1790 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1791 if (hdrlen & 3) {
1792 pad = hdrlen % 4;
1793 memmove(skb->data + pad, skb->data, hdrlen);
1794 skb_pull(skb, pad);
1795 }
1796
1797 /*
1798 * always extend the mac timestamp, since this information is
1799 * also needed for proper IBSS merging.
1800 *
1801 * XXX: it might be too late to do it here, since rs_tstamp is
1802 * 15bit only. that means TSF extension has to be done within
1803 * 32768usec (about 32ms). it might be necessary to move this to
1804 * the interrupt handler, like it is done in madwifi.
1805 *
1806 * Unfortunately we don't know when the hardware takes the rx
1807 * timestamp (beginning of phy frame, data frame, end of rx?).
1808 * The only thing we know is that it is hardware specific...
1809 * On AR5213 it seems the rx timestamp is at the end of the
1810 * frame, but i'm not sure.
1811 *
1812 * NOTE: mac80211 defines mactime at the beginning of the first
1813 * data symbol. Since we don't have any time references it's
1814 * impossible to comply to that. This affects IBSS merge only
1815 * right now, so it's not too bad...
1816 */
1817 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1818 rxs.flag |= RX_FLAG_TSFT;
1819
1820 rxs.freq = sc->curchan->center_freq;
1821 rxs.band = sc->curband->band;
1822
1823 rxs.noise = sc->ah->ah_noise_floor;
1824 rxs.signal = rxs.noise + rs.rs_rssi;
1825 rxs.qual = rs.rs_rssi * 100 / 64;
1826
1827 rxs.antenna = rs.rs_antenna;
1828 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1829 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1830
1831 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1832
1833 /* check beacons in IBSS mode */
1834 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1835 ath5k_check_ibss_tsf(sc, skb, &rxs);
1836
1837 __ieee80211_rx(sc->hw, skb, &rxs);
1838 next:
1839 list_move_tail(&bf->list, &sc->rxbuf);
1840 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1841 unlock:
1842 spin_unlock(&sc->rxbuflock);
1843 }
1844
1845
1846
1847
1848 /*************\
1849 * TX Handling *
1850 \*************/
1851
1852 static void
1853 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1854 {
1855 struct ath5k_tx_status ts = {};
1856 struct ath5k_buf *bf, *bf0;
1857 struct ath5k_desc *ds;
1858 struct sk_buff *skb;
1859 struct ieee80211_tx_info *info;
1860 int ret;
1861
1862 spin_lock(&txq->lock);
1863 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1864 ds = bf->desc;
1865
1866 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1867 if (unlikely(ret == -EINPROGRESS))
1868 break;
1869 else if (unlikely(ret)) {
1870 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1871 ret, txq->qnum);
1872 break;
1873 }
1874
1875 skb = bf->skb;
1876 info = IEEE80211_SKB_CB(skb);
1877 bf->skb = NULL;
1878
1879 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1880 PCI_DMA_TODEVICE);
1881
1882 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1883 if (unlikely(ts.ts_status)) {
1884 sc->ll_stats.dot11ACKFailureCount++;
1885 if (ts.ts_status & AR5K_TXERR_XRETRY)
1886 info->status.excessive_retries = 1;
1887 else if (ts.ts_status & AR5K_TXERR_FILT)
1888 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1889 } else {
1890 info->flags |= IEEE80211_TX_STAT_ACK;
1891 info->status.ack_signal = ts.ts_rssi;
1892 }
1893
1894 ieee80211_tx_status(sc->hw, skb);
1895 sc->tx_stats[txq->qnum].count++;
1896
1897 spin_lock(&sc->txbuflock);
1898 sc->tx_stats[txq->qnum].len--;
1899 list_move_tail(&bf->list, &sc->txbuf);
1900 sc->txbuf_len++;
1901 spin_unlock(&sc->txbuflock);
1902 }
1903 if (likely(list_empty(&txq->q)))
1904 txq->link = NULL;
1905 spin_unlock(&txq->lock);
1906 if (sc->txbuf_len > ATH_TXBUF / 5)
1907 ieee80211_wake_queues(sc->hw);
1908 }
1909
1910 static void
1911 ath5k_tasklet_tx(unsigned long data)
1912 {
1913 struct ath5k_softc *sc = (void *)data;
1914
1915 ath5k_tx_processq(sc, sc->txq);
1916 }
1917
1918
1919 /*****************\
1920 * Beacon handling *
1921 \*****************/
1922
1923 /*
1924 * Setup the beacon frame for transmit.
1925 */
1926 static int
1927 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1928 {
1929 struct sk_buff *skb = bf->skb;
1930 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1931 struct ath5k_hw *ah = sc->ah;
1932 struct ath5k_desc *ds;
1933 int ret, antenna = 0;
1934 u32 flags;
1935
1936 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1937 PCI_DMA_TODEVICE);
1938 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1939 "skbaddr %llx\n", skb, skb->data, skb->len,
1940 (unsigned long long)bf->skbaddr);
1941 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1942 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1943 return -EIO;
1944 }
1945
1946 ds = bf->desc;
1947
1948 flags = AR5K_TXDESC_NOACK;
1949 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1950 ds->ds_link = bf->daddr; /* self-linked */
1951 flags |= AR5K_TXDESC_VEOL;
1952 /*
1953 * Let hardware handle antenna switching if txantenna is not set
1954 */
1955 } else {
1956 ds->ds_link = 0;
1957 /*
1958 * Switch antenna every 4 beacons if txantenna is not set
1959 * XXX assumes two antennas
1960 */
1961 if (antenna == 0)
1962 antenna = sc->bsent & 4 ? 2 : 1;
1963 }
1964
1965 ds->ds_data = bf->skbaddr;
1966 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1967 ieee80211_get_hdrlen_from_skb(skb),
1968 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1969 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1970 1, AR5K_TXKEYIX_INVALID,
1971 antenna, flags, 0, 0);
1972 if (ret)
1973 goto err_unmap;
1974
1975 return 0;
1976 err_unmap:
1977 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1978 return ret;
1979 }
1980
1981 /*
1982 * Transmit a beacon frame at SWBA. Dynamic updates to the
1983 * frame contents are done as needed and the slot time is
1984 * also adjusted based on current state.
1985 *
1986 * this is usually called from interrupt context (ath5k_intr())
1987 * but also from ath5k_beacon_config() in IBSS mode which in turn
1988 * can be called from a tasklet and user context
1989 */
1990 static void
1991 ath5k_beacon_send(struct ath5k_softc *sc)
1992 {
1993 struct ath5k_buf *bf = sc->bbuf;
1994 struct ath5k_hw *ah = sc->ah;
1995
1996 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1997
1998 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1999 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
2000 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2001 return;
2002 }
2003 /*
2004 * Check if the previous beacon has gone out. If
2005 * not don't don't try to post another, skip this
2006 * period and wait for the next. Missed beacons
2007 * indicate a problem and should not occur. If we
2008 * miss too many consecutive beacons reset the device.
2009 */
2010 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2011 sc->bmisscount++;
2012 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2013 "missed %u consecutive beacons\n", sc->bmisscount);
2014 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2015 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2016 "stuck beacon time (%u missed)\n",
2017 sc->bmisscount);
2018 tasklet_schedule(&sc->restq);
2019 }
2020 return;
2021 }
2022 if (unlikely(sc->bmisscount != 0)) {
2023 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2024 "resume beacon xmit after %u misses\n",
2025 sc->bmisscount);
2026 sc->bmisscount = 0;
2027 }
2028
2029 /*
2030 * Stop any current dma and put the new frame on the queue.
2031 * This should never fail since we check above that no frames
2032 * are still pending on the queue.
2033 */
2034 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2035 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2036 /* NB: hw still stops DMA, so proceed */
2037 }
2038
2039 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2040 ath5k_hw_tx_start(ah, sc->bhalq);
2041 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2042 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2043
2044 sc->bsent++;
2045 }
2046
2047
2048 /**
2049 * ath5k_beacon_update_timers - update beacon timers
2050 *
2051 * @sc: struct ath5k_softc pointer we are operating on
2052 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2053 * beacon timer update based on the current HW TSF.
2054 *
2055 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2056 * of a received beacon or the current local hardware TSF and write it to the
2057 * beacon timer registers.
2058 *
2059 * This is called in a variety of situations, e.g. when a beacon is received,
2060 * when a TSF update has been detected, but also when an new IBSS is created or
2061 * when we otherwise know we have to update the timers, but we keep it in this
2062 * function to have it all together in one place.
2063 */
2064 static void
2065 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2066 {
2067 struct ath5k_hw *ah = sc->ah;
2068 u32 nexttbtt, intval, hw_tu, bc_tu;
2069 u64 hw_tsf;
2070
2071 intval = sc->bintval & AR5K_BEACON_PERIOD;
2072 if (WARN_ON(!intval))
2073 return;
2074
2075 /* beacon TSF converted to TU */
2076 bc_tu = TSF_TO_TU(bc_tsf);
2077
2078 /* current TSF converted to TU */
2079 hw_tsf = ath5k_hw_get_tsf64(ah);
2080 hw_tu = TSF_TO_TU(hw_tsf);
2081
2082 #define FUDGE 3
2083 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2084 if (bc_tsf == -1) {
2085 /*
2086 * no beacons received, called internally.
2087 * just need to refresh timers based on HW TSF.
2088 */
2089 nexttbtt = roundup(hw_tu + FUDGE, intval);
2090 } else if (bc_tsf == 0) {
2091 /*
2092 * no beacon received, probably called by ath5k_reset_tsf().
2093 * reset TSF to start with 0.
2094 */
2095 nexttbtt = intval;
2096 intval |= AR5K_BEACON_RESET_TSF;
2097 } else if (bc_tsf > hw_tsf) {
2098 /*
2099 * beacon received, SW merge happend but HW TSF not yet updated.
2100 * not possible to reconfigure timers yet, but next time we
2101 * receive a beacon with the same BSSID, the hardware will
2102 * automatically update the TSF and then we need to reconfigure
2103 * the timers.
2104 */
2105 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2106 "need to wait for HW TSF sync\n");
2107 return;
2108 } else {
2109 /*
2110 * most important case for beacon synchronization between STA.
2111 *
2112 * beacon received and HW TSF has been already updated by HW.
2113 * update next TBTT based on the TSF of the beacon, but make
2114 * sure it is ahead of our local TSF timer.
2115 */
2116 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2117 }
2118 #undef FUDGE
2119
2120 sc->nexttbtt = nexttbtt;
2121
2122 intval |= AR5K_BEACON_ENA;
2123 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2124
2125 /*
2126 * debugging output last in order to preserve the time critical aspect
2127 * of this function
2128 */
2129 if (bc_tsf == -1)
2130 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2131 "reconfigured timers based on HW TSF\n");
2132 else if (bc_tsf == 0)
2133 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2134 "reset HW TSF and timers\n");
2135 else
2136 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2137 "updated timers based on beacon TSF\n");
2138
2139 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2140 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2141 (unsigned long long) bc_tsf,
2142 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2143 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2144 intval & AR5K_BEACON_PERIOD,
2145 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2146 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2147 }
2148
2149
2150 /**
2151 * ath5k_beacon_config - Configure the beacon queues and interrupts
2152 *
2153 * @sc: struct ath5k_softc pointer we are operating on
2154 *
2155 * When operating in station mode we want to receive a BMISS interrupt when we
2156 * stop seeing beacons from the AP we've associated with so we can look for
2157 * another AP to associate with.
2158 *
2159 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2160 * interrupts to detect TSF updates only.
2161 *
2162 * AP mode is missing.
2163 */
2164 static void
2165 ath5k_beacon_config(struct ath5k_softc *sc)
2166 {
2167 struct ath5k_hw *ah = sc->ah;
2168
2169 ath5k_hw_set_intr(ah, 0);
2170 sc->bmisscount = 0;
2171 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2172
2173 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2174 sc->imask |= AR5K_INT_BMISS;
2175 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2176 /*
2177 * In IBSS mode we use a self-linked tx descriptor and let the
2178 * hardware send the beacons automatically. We have to load it
2179 * only once here.
2180 * We use the SWBA interrupt only to keep track of the beacon
2181 * timers in order to detect automatic TSF updates.
2182 */
2183 ath5k_beaconq_config(sc);
2184
2185 sc->imask |= AR5K_INT_SWBA;
2186
2187 if (ath5k_hw_hasveol(ah))
2188 ath5k_beacon_send(sc);
2189 }
2190 /* TODO else AP */
2191
2192 ath5k_hw_set_intr(ah, sc->imask);
2193 }
2194
2195
2196 /********************\
2197 * Interrupt handling *
2198 \********************/
2199
2200 static int
2201 ath5k_init(struct ath5k_softc *sc)
2202 {
2203 int ret;
2204
2205 mutex_lock(&sc->lock);
2206
2207 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2208
2209 /*
2210 * Stop anything previously setup. This is safe
2211 * no matter this is the first time through or not.
2212 */
2213 ath5k_stop_locked(sc);
2214
2215 /*
2216 * The basic interface to setting the hardware in a good
2217 * state is ``reset''. On return the hardware is known to
2218 * be powered up and with interrupts disabled. This must
2219 * be followed by initialization of the appropriate bits
2220 * and then setup of the interrupt mask.
2221 */
2222 sc->curchan = sc->hw->conf.channel;
2223 sc->curband = &sc->sbands[sc->curchan->band];
2224 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2225 if (ret) {
2226 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2227 goto done;
2228 }
2229 /*
2230 * This is needed only to setup initial state
2231 * but it's best done after a reset.
2232 */
2233 ath5k_hw_set_txpower_limit(sc->ah, 0);
2234
2235 /*
2236 * Setup the hardware after reset: the key cache
2237 * is filled as needed and the receive engine is
2238 * set going. Frame transmit is handled entirely
2239 * in the frame output path; there's nothing to do
2240 * here except setup the interrupt mask.
2241 */
2242 ret = ath5k_rx_start(sc);
2243 if (ret)
2244 goto done;
2245
2246 /*
2247 * Enable interrupts.
2248 */
2249 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2250 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2251 AR5K_INT_MIB;
2252
2253 ath5k_hw_set_intr(sc->ah, sc->imask);
2254 /* Set ack to be sent at low bit-rates */
2255 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2256
2257 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2258 msecs_to_jiffies(ath5k_calinterval * 1000)));
2259
2260 ret = 0;
2261 done:
2262 mmiowb();
2263 mutex_unlock(&sc->lock);
2264 return ret;
2265 }
2266
2267 static int
2268 ath5k_stop_locked(struct ath5k_softc *sc)
2269 {
2270 struct ath5k_hw *ah = sc->ah;
2271
2272 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2273 test_bit(ATH_STAT_INVALID, sc->status));
2274
2275 /*
2276 * Shutdown the hardware and driver:
2277 * stop output from above
2278 * disable interrupts
2279 * turn off timers
2280 * turn off the radio
2281 * clear transmit machinery
2282 * clear receive machinery
2283 * drain and release tx queues
2284 * reclaim beacon resources
2285 * power down hardware
2286 *
2287 * Note that some of this work is not possible if the
2288 * hardware is gone (invalid).
2289 */
2290 ieee80211_stop_queues(sc->hw);
2291
2292 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2293 ath5k_led_off(sc);
2294 ath5k_hw_set_intr(ah, 0);
2295 synchronize_irq(sc->pdev->irq);
2296 }
2297 ath5k_txq_cleanup(sc);
2298 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2299 ath5k_rx_stop(sc);
2300 ath5k_hw_phy_disable(ah);
2301 } else
2302 sc->rxlink = NULL;
2303
2304 return 0;
2305 }
2306
2307 /*
2308 * Stop the device, grabbing the top-level lock to protect
2309 * against concurrent entry through ath5k_init (which can happen
2310 * if another thread does a system call and the thread doing the
2311 * stop is preempted).
2312 */
2313 static int
2314 ath5k_stop_hw(struct ath5k_softc *sc)
2315 {
2316 int ret;
2317
2318 mutex_lock(&sc->lock);
2319 ret = ath5k_stop_locked(sc);
2320 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2321 /*
2322 * Set the chip in full sleep mode. Note that we are
2323 * careful to do this only when bringing the interface
2324 * completely to a stop. When the chip is in this state
2325 * it must be carefully woken up or references to
2326 * registers in the PCI clock domain may freeze the bus
2327 * (and system). This varies by chip and is mostly an
2328 * issue with newer parts that go to sleep more quickly.
2329 */
2330 if (sc->ah->ah_mac_srev >= 0x78) {
2331 /*
2332 * XXX
2333 * don't put newer MAC revisions > 7.8 to sleep because
2334 * of the above mentioned problems
2335 */
2336 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2337 "not putting device to sleep\n");
2338 } else {
2339 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2340 "putting device to full sleep\n");
2341 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2342 }
2343 }
2344 ath5k_txbuf_free(sc, sc->bbuf);
2345 mmiowb();
2346 mutex_unlock(&sc->lock);
2347
2348 del_timer_sync(&sc->calib_tim);
2349 tasklet_kill(&sc->rxtq);
2350 tasklet_kill(&sc->txtq);
2351 tasklet_kill(&sc->restq);
2352
2353 return ret;
2354 }
2355
2356 static irqreturn_t
2357 ath5k_intr(int irq, void *dev_id)
2358 {
2359 struct ath5k_softc *sc = dev_id;
2360 struct ath5k_hw *ah = sc->ah;
2361 enum ath5k_int status;
2362 unsigned int counter = 1000;
2363
2364 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2365 !ath5k_hw_is_intr_pending(ah)))
2366 return IRQ_NONE;
2367
2368 do {
2369 /*
2370 * Figure out the reason(s) for the interrupt. Note
2371 * that get_isr returns a pseudo-ISR that may include
2372 * bits we haven't explicitly enabled so we mask the
2373 * value to insure we only process bits we requested.
2374 */
2375 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2376 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2377 status, sc->imask);
2378 status &= sc->imask; /* discard unasked for bits */
2379 if (unlikely(status & AR5K_INT_FATAL)) {
2380 /*
2381 * Fatal errors are unrecoverable.
2382 * Typically these are caused by DMA errors.
2383 */
2384 tasklet_schedule(&sc->restq);
2385 } else if (unlikely(status & AR5K_INT_RXORN)) {
2386 tasklet_schedule(&sc->restq);
2387 } else {
2388 if (status & AR5K_INT_SWBA) {
2389 /*
2390 * Software beacon alert--time to send a beacon.
2391 * Handle beacon transmission directly; deferring
2392 * this is too slow to meet timing constraints
2393 * under load.
2394 *
2395 * In IBSS mode we use this interrupt just to
2396 * keep track of the next TBTT (target beacon
2397 * transmission time) in order to detect wether
2398 * automatic TSF updates happened.
2399 */
2400 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2401 /* XXX: only if VEOL suppported */
2402 u64 tsf = ath5k_hw_get_tsf64(ah);
2403 sc->nexttbtt += sc->bintval;
2404 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2405 "SWBA nexttbtt: %x hw_tu: %x "
2406 "TSF: %llx\n",
2407 sc->nexttbtt,
2408 TSF_TO_TU(tsf),
2409 (unsigned long long) tsf);
2410 } else {
2411 ath5k_beacon_send(sc);
2412 }
2413 }
2414 if (status & AR5K_INT_RXEOL) {
2415 /*
2416 * NB: the hardware should re-read the link when
2417 * RXE bit is written, but it doesn't work at
2418 * least on older hardware revs.
2419 */
2420 sc->rxlink = NULL;
2421 }
2422 if (status & AR5K_INT_TXURN) {
2423 /* bump tx trigger level */
2424 ath5k_hw_update_tx_triglevel(ah, true);
2425 }
2426 if (status & AR5K_INT_RX)
2427 tasklet_schedule(&sc->rxtq);
2428 if (status & AR5K_INT_TX)
2429 tasklet_schedule(&sc->txtq);
2430 if (status & AR5K_INT_BMISS) {
2431 }
2432 if (status & AR5K_INT_MIB) {
2433 /*
2434 * These stats are also used for ANI i think
2435 * so how about updating them more often ?
2436 */
2437 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2438 }
2439 }
2440 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2441
2442 if (unlikely(!counter))
2443 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2444
2445 return IRQ_HANDLED;
2446 }
2447
2448 static void
2449 ath5k_tasklet_reset(unsigned long data)
2450 {
2451 struct ath5k_softc *sc = (void *)data;
2452
2453 ath5k_reset(sc->hw);
2454 }
2455
2456 /*
2457 * Periodically recalibrate the PHY to account
2458 * for temperature/environment changes.
2459 */
2460 static void
2461 ath5k_calibrate(unsigned long data)
2462 {
2463 struct ath5k_softc *sc = (void *)data;
2464 struct ath5k_hw *ah = sc->ah;
2465
2466 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2467 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2468 sc->curchan->hw_value);
2469
2470 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2471 /*
2472 * Rfgain is out of bounds, reset the chip
2473 * to load new gain values.
2474 */
2475 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2476 ath5k_reset(sc->hw);
2477 }
2478 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2479 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2480 ieee80211_frequency_to_channel(
2481 sc->curchan->center_freq));
2482
2483 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2484 msecs_to_jiffies(ath5k_calinterval * 1000)));
2485 }
2486
2487
2488
2489 /***************\
2490 * LED functions *
2491 \***************/
2492
2493 static void
2494 ath5k_led_enable(struct ath5k_softc *sc)
2495 {
2496 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2497 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2498 ath5k_led_off(sc);
2499 }
2500 }
2501
2502 static void
2503 ath5k_led_on(struct ath5k_softc *sc)
2504 {
2505 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2506 return;
2507 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2508 }
2509
2510 static void
2511 ath5k_led_off(struct ath5k_softc *sc)
2512 {
2513 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2514 return;
2515 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2516 }
2517
2518 static void
2519 ath5k_led_brightness_set(struct led_classdev *led_dev,
2520 enum led_brightness brightness)
2521 {
2522 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2523 led_dev);
2524
2525 if (brightness == LED_OFF)
2526 ath5k_led_off(led->sc);
2527 else
2528 ath5k_led_on(led->sc);
2529 }
2530
2531 static int
2532 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2533 const char *name, char *trigger)
2534 {
2535 int err;
2536
2537 led->sc = sc;
2538 strncpy(led->name, name, sizeof(led->name));
2539 led->led_dev.name = led->name;
2540 led->led_dev.default_trigger = trigger;
2541 led->led_dev.brightness_set = ath5k_led_brightness_set;
2542
2543 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2544 if (err)
2545 {
2546 ATH5K_WARN(sc, "could not register LED %s\n", name);
2547 led->sc = NULL;
2548 }
2549 return err;
2550 }
2551
2552 static void
2553 ath5k_unregister_led(struct ath5k_led *led)
2554 {
2555 if (!led->sc)
2556 return;
2557 led_classdev_unregister(&led->led_dev);
2558 ath5k_led_off(led->sc);
2559 led->sc = NULL;
2560 }
2561
2562 static void
2563 ath5k_unregister_leds(struct ath5k_softc *sc)
2564 {
2565 ath5k_unregister_led(&sc->rx_led);
2566 ath5k_unregister_led(&sc->tx_led);
2567 }
2568
2569
2570 static int
2571 ath5k_init_leds(struct ath5k_softc *sc)
2572 {
2573 int ret = 0;
2574 struct ieee80211_hw *hw = sc->hw;
2575 struct pci_dev *pdev = sc->pdev;
2576 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2577
2578 /*
2579 * Auto-enable soft led processing for IBM cards and for
2580 * 5211 minipci cards.
2581 */
2582 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2583 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2584 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2585 sc->led_pin = 0;
2586 sc->led_on = 0; /* active low */
2587 }
2588 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2589 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2590 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2591 sc->led_pin = 1;
2592 sc->led_on = 1; /* active high */
2593 }
2594 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2595 goto out;
2596
2597 ath5k_led_enable(sc);
2598
2599 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2600 ret = ath5k_register_led(sc, &sc->rx_led, name,
2601 ieee80211_get_rx_led_name(hw));
2602 if (ret)
2603 goto out;
2604
2605 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2606 ret = ath5k_register_led(sc, &sc->tx_led, name,
2607 ieee80211_get_tx_led_name(hw));
2608 out:
2609 return ret;
2610 }
2611
2612
2613 /********************\
2614 * Mac80211 functions *
2615 \********************/
2616
2617 static int
2618 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2619 {
2620 struct ath5k_softc *sc = hw->priv;
2621 struct ath5k_buf *bf;
2622 unsigned long flags;
2623 int hdrlen;
2624 int pad;
2625
2626 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2627
2628 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2629 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2630
2631 /*
2632 * the hardware expects the header padded to 4 byte boundaries
2633 * if this is not the case we add the padding after the header
2634 */
2635 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2636 if (hdrlen & 3) {
2637 pad = hdrlen % 4;
2638 if (skb_headroom(skb) < pad) {
2639 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2640 " headroom to pad %d\n", hdrlen, pad);
2641 return -1;
2642 }
2643 skb_push(skb, pad);
2644 memmove(skb->data, skb->data+pad, hdrlen);
2645 }
2646
2647 spin_lock_irqsave(&sc->txbuflock, flags);
2648 if (list_empty(&sc->txbuf)) {
2649 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2650 spin_unlock_irqrestore(&sc->txbuflock, flags);
2651 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2652 return -1;
2653 }
2654 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2655 list_del(&bf->list);
2656 sc->txbuf_len--;
2657 if (list_empty(&sc->txbuf))
2658 ieee80211_stop_queues(hw);
2659 spin_unlock_irqrestore(&sc->txbuflock, flags);
2660
2661 bf->skb = skb;
2662
2663 if (ath5k_txbuf_setup(sc, bf)) {
2664 bf->skb = NULL;
2665 spin_lock_irqsave(&sc->txbuflock, flags);
2666 list_add_tail(&bf->list, &sc->txbuf);
2667 sc->txbuf_len++;
2668 spin_unlock_irqrestore(&sc->txbuflock, flags);
2669 dev_kfree_skb_any(skb);
2670 return 0;
2671 }
2672
2673 return 0;
2674 }
2675
2676 static int
2677 ath5k_reset(struct ieee80211_hw *hw)
2678 {
2679 struct ath5k_softc *sc = hw->priv;
2680 struct ath5k_hw *ah = sc->ah;
2681 int ret;
2682
2683 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2684
2685 ath5k_hw_set_intr(ah, 0);
2686 ath5k_txq_cleanup(sc);
2687 ath5k_rx_stop(sc);
2688
2689 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2690 if (unlikely(ret)) {
2691 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2692 goto err;
2693 }
2694 ath5k_hw_set_txpower_limit(sc->ah, 0);
2695
2696 ret = ath5k_rx_start(sc);
2697 if (unlikely(ret)) {
2698 ATH5K_ERR(sc, "can't start recv logic\n");
2699 goto err;
2700 }
2701 /*
2702 * We may be doing a reset in response to an ioctl
2703 * that changes the channel so update any state that
2704 * might change as a result.
2705 *
2706 * XXX needed?
2707 */
2708 /* ath5k_chan_change(sc, c); */
2709 ath5k_beacon_config(sc);
2710 /* intrs are started by ath5k_beacon_config */
2711
2712 ieee80211_wake_queues(hw);
2713
2714 return 0;
2715 err:
2716 return ret;
2717 }
2718
2719 static int ath5k_start(struct ieee80211_hw *hw)
2720 {
2721 return ath5k_init(hw->priv);
2722 }
2723
2724 static void ath5k_stop(struct ieee80211_hw *hw)
2725 {
2726 ath5k_stop_hw(hw->priv);
2727 }
2728
2729 static int ath5k_add_interface(struct ieee80211_hw *hw,
2730 struct ieee80211_if_init_conf *conf)
2731 {
2732 struct ath5k_softc *sc = hw->priv;
2733 int ret;
2734
2735 mutex_lock(&sc->lock);
2736 if (sc->vif) {
2737 ret = 0;
2738 goto end;
2739 }
2740
2741 sc->vif = conf->vif;
2742
2743 switch (conf->type) {
2744 case IEEE80211_IF_TYPE_STA:
2745 case IEEE80211_IF_TYPE_IBSS:
2746 case IEEE80211_IF_TYPE_MNTR:
2747 sc->opmode = conf->type;
2748 break;
2749 default:
2750 ret = -EOPNOTSUPP;
2751 goto end;
2752 }
2753 ret = 0;
2754 end:
2755 mutex_unlock(&sc->lock);
2756 return ret;
2757 }
2758
2759 static void
2760 ath5k_remove_interface(struct ieee80211_hw *hw,
2761 struct ieee80211_if_init_conf *conf)
2762 {
2763 struct ath5k_softc *sc = hw->priv;
2764
2765 mutex_lock(&sc->lock);
2766 if (sc->vif != conf->vif)
2767 goto end;
2768
2769 sc->vif = NULL;
2770 end:
2771 mutex_unlock(&sc->lock);
2772 }
2773
2774 /*
2775 * TODO: Phy disable/diversity etc
2776 */
2777 static int
2778 ath5k_config(struct ieee80211_hw *hw,
2779 struct ieee80211_conf *conf)
2780 {
2781 struct ath5k_softc *sc = hw->priv;
2782
2783 sc->bintval = conf->beacon_int;
2784 sc->power_level = conf->power_level;
2785
2786 return ath5k_chan_set(sc, conf->channel);
2787 }
2788
2789 static int
2790 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2791 struct ieee80211_if_conf *conf)
2792 {
2793 struct ath5k_softc *sc = hw->priv;
2794 struct ath5k_hw *ah = sc->ah;
2795 int ret;
2796
2797 /* Set to a reasonable value. Note that this will
2798 * be set to mac80211's value at ath5k_config(). */
2799 sc->bintval = 1000;
2800 mutex_lock(&sc->lock);
2801 if (sc->vif != vif) {
2802 ret = -EIO;
2803 goto unlock;
2804 }
2805 if (conf->bssid) {
2806 /* Cache for later use during resets */
2807 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2808 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2809 * a clean way of letting us retrieve this yet. */
2810 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2811 mmiowb();
2812 }
2813
2814 if (conf->changed & IEEE80211_IFCC_BEACON &&
2815 vif->type == IEEE80211_IF_TYPE_IBSS) {
2816 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2817 if (!beacon) {
2818 ret = -ENOMEM;
2819 goto unlock;
2820 }
2821 /* call old handler for now */
2822 ath5k_beacon_update(hw, beacon);
2823 }
2824
2825 mutex_unlock(&sc->lock);
2826
2827 return ath5k_reset(hw);
2828 unlock:
2829 mutex_unlock(&sc->lock);
2830 return ret;
2831 }
2832
2833 #define SUPPORTED_FIF_FLAGS \
2834 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2835 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2836 FIF_BCN_PRBRESP_PROMISC
2837 /*
2838 * o always accept unicast, broadcast, and multicast traffic
2839 * o multicast traffic for all BSSIDs will be enabled if mac80211
2840 * says it should be
2841 * o maintain current state of phy ofdm or phy cck error reception.
2842 * If the hardware detects any of these type of errors then
2843 * ath5k_hw_get_rx_filter() will pass to us the respective
2844 * hardware filters to be able to receive these type of frames.
2845 * o probe request frames are accepted only when operating in
2846 * hostap, adhoc, or monitor modes
2847 * o enable promiscuous mode according to the interface state
2848 * o accept beacons:
2849 * - when operating in adhoc mode so the 802.11 layer creates
2850 * node table entries for peers,
2851 * - when operating in station mode for collecting rssi data when
2852 * the station is otherwise quiet, or
2853 * - when scanning
2854 */
2855 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2856 unsigned int changed_flags,
2857 unsigned int *new_flags,
2858 int mc_count, struct dev_mc_list *mclist)
2859 {
2860 struct ath5k_softc *sc = hw->priv;
2861 struct ath5k_hw *ah = sc->ah;
2862 u32 mfilt[2], val, rfilt;
2863 u8 pos;
2864 int i;
2865
2866 mfilt[0] = 0;
2867 mfilt[1] = 0;
2868
2869 /* Only deal with supported flags */
2870 changed_flags &= SUPPORTED_FIF_FLAGS;
2871 *new_flags &= SUPPORTED_FIF_FLAGS;
2872
2873 /* If HW detects any phy or radar errors, leave those filters on.
2874 * Also, always enable Unicast, Broadcasts and Multicast
2875 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2876 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2877 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2878 AR5K_RX_FILTER_MCAST);
2879
2880 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2881 if (*new_flags & FIF_PROMISC_IN_BSS) {
2882 rfilt |= AR5K_RX_FILTER_PROM;
2883 __set_bit(ATH_STAT_PROMISC, sc->status);
2884 }
2885 else
2886 __clear_bit(ATH_STAT_PROMISC, sc->status);
2887 }
2888
2889 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2890 if (*new_flags & FIF_ALLMULTI) {
2891 mfilt[0] = ~0;
2892 mfilt[1] = ~0;
2893 } else {
2894 for (i = 0; i < mc_count; i++) {
2895 if (!mclist)
2896 break;
2897 /* calculate XOR of eight 6-bit values */
2898 val = get_unaligned_le32(mclist->dmi_addr + 0);
2899 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2900 val = get_unaligned_le32(mclist->dmi_addr + 3);
2901 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2902 pos &= 0x3f;
2903 mfilt[pos / 32] |= (1 << (pos % 32));
2904 /* XXX: we might be able to just do this instead,
2905 * but not sure, needs testing, if we do use this we'd
2906 * neet to inform below to not reset the mcast */
2907 /* ath5k_hw_set_mcast_filterindex(ah,
2908 * mclist->dmi_addr[5]); */
2909 mclist = mclist->next;
2910 }
2911 }
2912
2913 /* This is the best we can do */
2914 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2915 rfilt |= AR5K_RX_FILTER_PHYERR;
2916
2917 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2918 * and probes for any BSSID, this needs testing */
2919 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2920 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2921
2922 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2923 * set we should only pass on control frames for this
2924 * station. This needs testing. I believe right now this
2925 * enables *all* control frames, which is OK.. but
2926 * but we should see if we can improve on granularity */
2927 if (*new_flags & FIF_CONTROL)
2928 rfilt |= AR5K_RX_FILTER_CONTROL;
2929
2930 /* Additional settings per mode -- this is per ath5k */
2931
2932 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2933
2934 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2935 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2936 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2937 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2938 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2939 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2940 test_bit(ATH_STAT_PROMISC, sc->status))
2941 rfilt |= AR5K_RX_FILTER_PROM;
2942 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2943 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2944 rfilt |= AR5K_RX_FILTER_BEACON;
2945 }
2946
2947 /* Set filters */
2948 ath5k_hw_set_rx_filter(ah,rfilt);
2949
2950 /* Set multicast bits */
2951 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2952 /* Set the cached hw filter flags, this will alter actually
2953 * be set in HW */
2954 sc->filter_flags = rfilt;
2955 }
2956
2957 static int
2958 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2959 const u8 *local_addr, const u8 *addr,
2960 struct ieee80211_key_conf *key)
2961 {
2962 struct ath5k_softc *sc = hw->priv;
2963 int ret = 0;
2964
2965 switch(key->alg) {
2966 case ALG_WEP:
2967 /* XXX: fix hardware encryption, its not working. For now
2968 * allow software encryption */
2969 /* break; */
2970 case ALG_TKIP:
2971 case ALG_CCMP:
2972 return -EOPNOTSUPP;
2973 default:
2974 WARN_ON(1);
2975 return -EINVAL;
2976 }
2977
2978 mutex_lock(&sc->lock);
2979
2980 switch (cmd) {
2981 case SET_KEY:
2982 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2983 if (ret) {
2984 ATH5K_ERR(sc, "can't set the key\n");
2985 goto unlock;
2986 }
2987 __set_bit(key->keyidx, sc->keymap);
2988 key->hw_key_idx = key->keyidx;
2989 break;
2990 case DISABLE_KEY:
2991 ath5k_hw_reset_key(sc->ah, key->keyidx);
2992 __clear_bit(key->keyidx, sc->keymap);
2993 break;
2994 default:
2995 ret = -EINVAL;
2996 goto unlock;
2997 }
2998
2999 unlock:
3000 mmiowb();
3001 mutex_unlock(&sc->lock);
3002 return ret;
3003 }
3004
3005 static int
3006 ath5k_get_stats(struct ieee80211_hw *hw,
3007 struct ieee80211_low_level_stats *stats)
3008 {
3009 struct ath5k_softc *sc = hw->priv;
3010 struct ath5k_hw *ah = sc->ah;
3011
3012 /* Force update */
3013 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3014
3015 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3016
3017 return 0;
3018 }
3019
3020 static int
3021 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3022 struct ieee80211_tx_queue_stats *stats)
3023 {
3024 struct ath5k_softc *sc = hw->priv;
3025
3026 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3027
3028 return 0;
3029 }
3030
3031 static u64
3032 ath5k_get_tsf(struct ieee80211_hw *hw)
3033 {
3034 struct ath5k_softc *sc = hw->priv;
3035
3036 return ath5k_hw_get_tsf64(sc->ah);
3037 }
3038
3039 static void
3040 ath5k_reset_tsf(struct ieee80211_hw *hw)
3041 {
3042 struct ath5k_softc *sc = hw->priv;
3043
3044 /*
3045 * in IBSS mode we need to update the beacon timers too.
3046 * this will also reset the TSF if we call it with 0
3047 */
3048 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3049 ath5k_beacon_update_timers(sc, 0);
3050 else
3051 ath5k_hw_reset_tsf(sc->ah);
3052 }
3053
3054 static int
3055 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3056 {
3057 struct ath5k_softc *sc = hw->priv;
3058 int ret;
3059
3060 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3061
3062 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3063 ret = -EIO;
3064 goto end;
3065 }
3066
3067 ath5k_txbuf_free(sc, sc->bbuf);
3068 sc->bbuf->skb = skb;
3069 ret = ath5k_beacon_setup(sc, sc->bbuf);
3070 if (ret)
3071 sc->bbuf->skb = NULL;
3072 else {
3073 ath5k_beacon_config(sc);
3074 mmiowb();
3075 }
3076
3077 end:
3078 return ret;
3079 }
3080
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree