2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac7"
99 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
100 ICH5_PMR
= 0x90, /* port mapping register */
101 ICH5_PCS
= 0x92, /* port control and status */
102 PIIX_SCC
= 0x0A, /* sub-class code register */
104 PIIX_FLAG_SCR
= (1 << 26), /* SCR available */
105 PIIX_FLAG_AHCI
= (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
109 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
114 PIIX_PORT_ENABLED
= (1 << 0),
115 PIIX_PORT_PRESENT
= (1 << 4),
117 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
118 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
121 piix_pata_33
= 0, /* PIIX3 or 4 at 33Mhz */
122 ich_pata_33
= 1, /* ICH up to UDMA 33 only */
123 ich_pata_66
= 2, /* ICH up to 66 Mhz */
124 ich_pata_100
= 3, /* ICH up to UDMA 100 */
125 ich_pata_133
= 4, /* ICH up to UDMA 133 */
132 /* constants for mapping table */
138 NA
= -2, /* not avaliable */
139 RV
= -3, /* reserved */
141 PIIX_AHCI_DEVICE
= 6,
146 const u16 port_enable
;
150 struct piix_host_priv
{
154 static int piix_init_one (struct pci_dev
*pdev
,
155 const struct pci_device_id
*ent
);
156 static void piix_host_stop(struct ata_host
*host
);
157 static void piix_pata_error_handler(struct ata_port
*ap
);
158 static void ich_pata_error_handler(struct ata_port
*ap
);
159 static void piix_sata_error_handler(struct ata_port
*ap
);
160 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
);
161 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
);
162 static void ich_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
);
164 static unsigned int in_module_init
= 1;
166 static const struct pci_device_id piix_pci_tbl
[] = {
167 #ifdef ATA_ENABLE_PATA
168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
171 { 0x8086, 0x24db, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
172 { 0x8086, 0x25a2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
174 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
176 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
178 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
179 /* Intel ICH (i810, i815, i840) UDMA 66*/
180 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
181 /* Intel ICH0 : UDMA 33*/
182 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
184 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
185 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
186 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
188 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
189 /* Intel ICH3 (E7500/1) UDMA 100 */
190 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
191 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
192 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
193 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
195 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
196 /* ICH6 (and 6) (i915) UDMA 100 */
197 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
198 /* ICH7/7-R (i945, i975) UDMA 100*/
199 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_133
},
200 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
203 /* NOTE: The following PCI ids must be kept in sync with the
204 * list in drivers/pci/quirks.c.
208 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
210 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
211 /* 6300ESB (ICH5 variant with broken PCS present bits) */
212 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
213 /* 6300ESB pretending RAID */
214 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
215 /* 82801FB/FW (ICH6/ICH6W) */
216 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
217 /* 82801FR/FRW (ICH6R/ICH6RW) */
218 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
219 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
220 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
221 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
222 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
223 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
224 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
225 /* Enterprise Southbridge 2 (631xESB/632xESB) */
226 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
227 /* SATA Controller 1 IDE (ICH8) */
228 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
229 /* SATA Controller 2 IDE (ICH8) */
230 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
231 /* Mobile SATA Controller IDE (ICH8M) */
232 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
233 /* SATA Controller IDE (ICH9) */
234 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
235 /* SATA Controller IDE (ICH9) */
236 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
237 /* SATA Controller IDE (ICH9) */
238 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
239 /* SATA Controller IDE (ICH9M) */
240 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
241 /* SATA Controller IDE (ICH9M) */
242 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
243 /* SATA Controller IDE (ICH9M) */
244 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
246 { } /* terminate list */
249 static struct pci_driver piix_pci_driver
= {
251 .id_table
= piix_pci_tbl
,
252 .probe
= piix_init_one
,
253 .remove
= ata_pci_remove_one
,
254 .suspend
= ata_pci_device_suspend
,
255 .resume
= ata_pci_device_resume
,
258 static struct scsi_host_template piix_sht
= {
259 .module
= THIS_MODULE
,
261 .ioctl
= ata_scsi_ioctl
,
262 .queuecommand
= ata_scsi_queuecmd
,
263 .can_queue
= ATA_DEF_QUEUE
,
264 .this_id
= ATA_SHT_THIS_ID
,
265 .sg_tablesize
= LIBATA_MAX_PRD
,
266 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
267 .emulated
= ATA_SHT_EMULATED
,
268 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
269 .proc_name
= DRV_NAME
,
270 .dma_boundary
= ATA_DMA_BOUNDARY
,
271 .slave_configure
= ata_scsi_slave_config
,
272 .slave_destroy
= ata_scsi_slave_destroy
,
273 .bios_param
= ata_std_bios_param
,
274 .resume
= ata_scsi_device_resume
,
275 .suspend
= ata_scsi_device_suspend
,
278 static const struct ata_port_operations piix_pata_ops
= {
279 .port_disable
= ata_port_disable
,
280 .set_piomode
= piix_set_piomode
,
281 .set_dmamode
= piix_set_dmamode
,
282 .mode_filter
= ata_pci_default_filter
,
284 .tf_load
= ata_tf_load
,
285 .tf_read
= ata_tf_read
,
286 .check_status
= ata_check_status
,
287 .exec_command
= ata_exec_command
,
288 .dev_select
= ata_std_dev_select
,
290 .bmdma_setup
= ata_bmdma_setup
,
291 .bmdma_start
= ata_bmdma_start
,
292 .bmdma_stop
= ata_bmdma_stop
,
293 .bmdma_status
= ata_bmdma_status
,
294 .qc_prep
= ata_qc_prep
,
295 .qc_issue
= ata_qc_issue_prot
,
296 .data_xfer
= ata_pio_data_xfer
,
298 .freeze
= ata_bmdma_freeze
,
299 .thaw
= ata_bmdma_thaw
,
300 .error_handler
= piix_pata_error_handler
,
301 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
303 .irq_handler
= ata_interrupt
,
304 .irq_clear
= ata_bmdma_irq_clear
,
306 .port_start
= ata_port_start
,
307 .port_stop
= ata_port_stop
,
308 .host_stop
= piix_host_stop
,
311 static const struct ata_port_operations ich_pata_ops
= {
312 .port_disable
= ata_port_disable
,
313 .set_piomode
= piix_set_piomode
,
314 .set_dmamode
= ich_set_dmamode
,
315 .mode_filter
= ata_pci_default_filter
,
317 .tf_load
= ata_tf_load
,
318 .tf_read
= ata_tf_read
,
319 .check_status
= ata_check_status
,
320 .exec_command
= ata_exec_command
,
321 .dev_select
= ata_std_dev_select
,
323 .bmdma_setup
= ata_bmdma_setup
,
324 .bmdma_start
= ata_bmdma_start
,
325 .bmdma_stop
= ata_bmdma_stop
,
326 .bmdma_status
= ata_bmdma_status
,
327 .qc_prep
= ata_qc_prep
,
328 .qc_issue
= ata_qc_issue_prot
,
329 .data_xfer
= ata_pio_data_xfer
,
331 .freeze
= ata_bmdma_freeze
,
332 .thaw
= ata_bmdma_thaw
,
333 .error_handler
= ich_pata_error_handler
,
334 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
336 .irq_handler
= ata_interrupt
,
337 .irq_clear
= ata_bmdma_irq_clear
,
339 .port_start
= ata_port_start
,
340 .port_stop
= ata_port_stop
,
341 .host_stop
= piix_host_stop
,
344 static const struct ata_port_operations piix_sata_ops
= {
345 .port_disable
= ata_port_disable
,
347 .tf_load
= ata_tf_load
,
348 .tf_read
= ata_tf_read
,
349 .check_status
= ata_check_status
,
350 .exec_command
= ata_exec_command
,
351 .dev_select
= ata_std_dev_select
,
353 .bmdma_setup
= ata_bmdma_setup
,
354 .bmdma_start
= ata_bmdma_start
,
355 .bmdma_stop
= ata_bmdma_stop
,
356 .bmdma_status
= ata_bmdma_status
,
357 .qc_prep
= ata_qc_prep
,
358 .qc_issue
= ata_qc_issue_prot
,
359 .data_xfer
= ata_pio_data_xfer
,
361 .freeze
= ata_bmdma_freeze
,
362 .thaw
= ata_bmdma_thaw
,
363 .error_handler
= piix_sata_error_handler
,
364 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
366 .irq_handler
= ata_interrupt
,
367 .irq_clear
= ata_bmdma_irq_clear
,
369 .port_start
= ata_port_start
,
370 .port_stop
= ata_port_stop
,
371 .host_stop
= piix_host_stop
,
374 static const struct piix_map_db ich5_map_db
= {
378 /* PM PS SM SS MAP */
379 { P0
, NA
, P1
, NA
}, /* 000b */
380 { P1
, NA
, P0
, NA
}, /* 001b */
383 { P0
, P1
, IDE
, IDE
}, /* 100b */
384 { P1
, P0
, IDE
, IDE
}, /* 101b */
385 { IDE
, IDE
, P0
, P1
}, /* 110b */
386 { IDE
, IDE
, P1
, P0
}, /* 111b */
390 static const struct piix_map_db ich6_map_db
= {
394 /* PM PS SM SS MAP */
395 { P0
, P2
, P1
, P3
}, /* 00b */
396 { IDE
, IDE
, P1
, P3
}, /* 01b */
397 { P0
, P2
, IDE
, IDE
}, /* 10b */
402 static const struct piix_map_db ich6m_map_db
= {
406 /* Map 01b isn't specified in the doc but some notebooks use
407 * it anyway. MAP 01b have been spotted on both ICH6M and
411 /* PM PS SM SS MAP */
412 { P0
, P2
, RV
, RV
}, /* 00b */
413 { IDE
, IDE
, P1
, P3
}, /* 01b */
414 { P0
, P2
, IDE
, IDE
}, /* 10b */
419 static const struct piix_map_db ich8_map_db
= {
423 /* PM PS SM SS MAP */
424 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
426 { IDE
, IDE
, NA
, NA
}, /* 10b (IDE mode) */
431 static const struct piix_map_db
*piix_map_db_table
[] = {
432 [ich5_sata
] = &ich5_map_db
,
433 [ich6_sata
] = &ich6_map_db
,
434 [ich6_sata_ahci
] = &ich6_map_db
,
435 [ich6m_sata_ahci
] = &ich6m_map_db
,
436 [ich8_sata_ahci
] = &ich8_map_db
,
439 static struct ata_port_info piix_port_info
[] = {
440 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
443 .flags
= PIIX_PATA_FLAGS
,
444 .pio_mask
= 0x1f, /* pio0-4 */
445 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
446 .udma_mask
= ATA_UDMA_MASK_40C
,
447 .port_ops
= &piix_pata_ops
,
450 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
453 .flags
= PIIX_PATA_FLAGS
,
454 .pio_mask
= 0x1f, /* pio 0-4 */
455 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
456 .udma_mask
= ATA_UDMA2
, /* UDMA33 */
457 .port_ops
= &ich_pata_ops
,
459 /* ich_pata_66: 2 ICH controllers up to 66MHz */
462 .flags
= PIIX_PATA_FLAGS
,
463 .pio_mask
= 0x1f, /* pio 0-4 */
464 .mwdma_mask
= 0x06, /* MWDMA0 is broken on chip */
465 .udma_mask
= ATA_UDMA4
,
466 .port_ops
= &ich_pata_ops
,
469 /* ich_pata_100: 3 */
472 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
473 .pio_mask
= 0x1f, /* pio0-4 */
474 .mwdma_mask
= 0x06, /* mwdma1-2 */
475 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
476 .port_ops
= &ich_pata_ops
,
479 /* ich_pata_133: 4 ICH with full UDMA6 */
482 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
483 .pio_mask
= 0x1f, /* pio 0-4 */
484 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
485 .udma_mask
= ATA_UDMA6
, /* UDMA133 */
486 .port_ops
= &ich_pata_ops
,
492 .flags
= PIIX_SATA_FLAGS
,
493 .pio_mask
= 0x1f, /* pio0-4 */
494 .mwdma_mask
= 0x07, /* mwdma0-2 */
495 .udma_mask
= 0x7f, /* udma0-6 */
496 .port_ops
= &piix_sata_ops
,
502 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
,
503 .pio_mask
= 0x1f, /* pio0-4 */
504 .mwdma_mask
= 0x07, /* mwdma0-2 */
505 .udma_mask
= 0x7f, /* udma0-6 */
506 .port_ops
= &piix_sata_ops
,
509 /* ich6_sata_ahci: 7 */
512 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
514 .pio_mask
= 0x1f, /* pio0-4 */
515 .mwdma_mask
= 0x07, /* mwdma0-2 */
516 .udma_mask
= 0x7f, /* udma0-6 */
517 .port_ops
= &piix_sata_ops
,
520 /* ich6m_sata_ahci: 8 */
523 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
525 .pio_mask
= 0x1f, /* pio0-4 */
526 .mwdma_mask
= 0x07, /* mwdma0-2 */
527 .udma_mask
= 0x7f, /* udma0-6 */
528 .port_ops
= &piix_sata_ops
,
531 /* ich8_sata_ahci: 9 */
534 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SCR
|
536 .pio_mask
= 0x1f, /* pio0-4 */
537 .mwdma_mask
= 0x07, /* mwdma0-2 */
538 .udma_mask
= 0x7f, /* udma0-6 */
539 .port_ops
= &piix_sata_ops
,
544 static struct pci_bits piix_enable_bits
[] = {
545 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
546 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
549 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
550 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
551 MODULE_LICENSE("GPL");
552 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
553 MODULE_VERSION(DRV_VERSION
);
562 * List of laptops that use short cables rather than 80 wire
565 static const struct ich_laptop ich_laptop
[] = {
566 /* devid, subvendor, subdev */
567 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
573 * piix_pata_cbl_detect - Probe host controller cable detect info
574 * @ap: Port for which cable detect info is desired
576 * Read 80c cable indicator from ATA PCI device's PCI config
577 * register. This register is normally set by firmware (BIOS).
580 * None (inherited from caller).
583 static void ich_pata_cbl_detect(struct ata_port
*ap
)
585 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
586 const struct ich_laptop
*lap
= &ich_laptop
[0];
589 /* no 80c support in host controller? */
590 if ((ap
->udma_mask
& ~ATA_UDMA_MASK_40C
) == 0)
593 /* Check for specials - Acer Aspire 5602WLMi */
594 while (lap
->device
) {
595 if (lap
->device
== pdev
->device
&&
596 lap
->subvendor
== pdev
->subsystem_vendor
&&
597 lap
->subdevice
== pdev
->subsystem_device
) {
598 ap
->cbl
= ATA_CBL_PATA40_SHORT
;
604 /* check BIOS cable detect results */
605 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
606 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
607 if ((tmp
& mask
) == 0)
610 ap
->cbl
= ATA_CBL_PATA80
;
614 ap
->cbl
= ATA_CBL_PATA40
;
618 * piix_pata_prereset - prereset for PATA host controller
623 * None (inherited from caller).
625 static int piix_pata_prereset(struct ata_port
*ap
)
627 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
629 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
632 ap
->cbl
= ATA_CBL_PATA40
;
633 return ata_std_prereset(ap
);
636 static void piix_pata_error_handler(struct ata_port
*ap
)
638 ata_bmdma_drive_eh(ap
, piix_pata_prereset
, ata_std_softreset
, NULL
,
644 * ich_pata_prereset - prereset for PATA host controller
649 * None (inherited from caller).
651 static int ich_pata_prereset(struct ata_port
*ap
)
653 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
655 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
])) {
656 ata_port_printk(ap
, KERN_INFO
, "port disabled. ignoring.\n");
657 ap
->eh_context
.i
.action
&= ~ATA_EH_RESET_MASK
;
661 ich_pata_cbl_detect(ap
);
663 return ata_std_prereset(ap
);
666 static void ich_pata_error_handler(struct ata_port
*ap
)
668 ata_bmdma_drive_eh(ap
, ich_pata_prereset
, ata_std_softreset
, NULL
,
672 static void piix_sata_error_handler(struct ata_port
*ap
)
674 ata_bmdma_drive_eh(ap
, ata_std_prereset
, ata_std_softreset
, NULL
,
679 * piix_set_piomode - Initialize host controller PATA PIO timings
680 * @ap: Port whose timings we are configuring
683 * Set PIO mode for device, in host controller PCI config space.
686 * None (inherited from caller).
689 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
691 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
692 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
693 unsigned int is_slave
= (adev
->devno
!= 0);
694 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
695 unsigned int slave_port
= 0x44;
702 * See Intel Document 298600-004 for the timing programing rules
703 * for ICH controllers.
706 static const /* ISP RTC */
707 u8 timings
[][2] = { { 0, 0 },
714 control
|= 1; /* TIME1 enable */
715 if (ata_pio_need_iordy(adev
))
716 control
|= 2; /* IE enable */
718 /* Intel specifies that the PPE functionality is for disk only */
719 if (adev
->class == ATA_DEV_ATA
)
720 control
|= 4; /* PPE enable */
722 pci_read_config_word(dev
, master_port
, &master_data
);
724 /* Enable SITRE (seperate slave timing register) */
725 master_data
|= 0x4000;
726 /* enable PPE1, IE1 and TIME1 as needed */
727 master_data
|= (control
<< 4);
728 pci_read_config_byte(dev
, slave_port
, &slave_data
);
729 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
730 /* Load the timing nibble for this slave */
731 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
733 /* Master keeps the bits in a different format */
734 master_data
&= 0xccf8;
735 /* Enable PPE, IE and TIME as appropriate */
736 master_data
|= control
;
738 (timings
[pio
][0] << 12) |
739 (timings
[pio
][1] << 8);
741 pci_write_config_word(dev
, master_port
, master_data
);
743 pci_write_config_byte(dev
, slave_port
, slave_data
);
745 /* Ensure the UDMA bit is off - it will be turned back on if
749 pci_read_config_byte(dev
, 0x48, &udma_enable
);
750 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
751 pci_write_config_byte(dev
, 0x48, udma_enable
);
756 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
757 * @ap: Port whose timings we are configuring
758 * @adev: Drive in question
759 * @udma: udma mode, 0 - 6
760 * @isich: set if the chip is an ICH device
762 * Set UDMA mode for device, in host controller PCI config space.
765 * None (inherited from caller).
768 static void do_pata_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
770 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
771 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
773 u8 speed
= adev
->dma_mode
;
774 int devid
= adev
->devno
+ 2 * ap
->port_no
;
777 static const /* ISP RTC */
778 u8 timings
[][2] = { { 0, 0 },
784 pci_read_config_word(dev
, master_port
, &master_data
);
785 pci_read_config_byte(dev
, 0x48, &udma_enable
);
787 if (speed
>= XFER_UDMA_0
) {
788 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
791 int u_clock
, u_speed
;
794 * UDMA is handled by a combination of clock switching and
795 * selection of dividers
797 * Handy rule: Odd modes are UDMATIMx 01, even are 02
798 * except UDMA0 which is 00
800 u_speed
= min(2 - (udma
& 1), udma
);
802 u_clock
= 0x1000; /* 100Mhz */
804 u_clock
= 1; /* 66Mhz */
806 u_clock
= 0; /* 33Mhz */
808 udma_enable
|= (1 << devid
);
810 /* Load the CT/RP selection */
811 pci_read_config_word(dev
, 0x4A, &udma_timing
);
812 udma_timing
&= ~(3 << (4 * devid
));
813 udma_timing
|= u_speed
<< (4 * devid
);
814 pci_write_config_word(dev
, 0x4A, udma_timing
);
817 /* Select a 33/66/100Mhz clock */
818 pci_read_config_word(dev
, 0x54, &ideconf
);
819 ideconf
&= ~(0x1001 << devid
);
820 ideconf
|= u_clock
<< devid
;
821 /* For ICH or later we should set bit 10 for better
822 performance (WR_PingPong_En) */
823 pci_write_config_word(dev
, 0x54, ideconf
);
827 * MWDMA is driven by the PIO timings. We must also enable
828 * IORDY unconditionally along with TIME1. PPE has already
829 * been set when the PIO timing was set.
831 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
832 unsigned int control
;
834 const unsigned int needed_pio
[3] = {
835 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
837 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
839 control
= 3; /* IORDY|TIME1 */
841 /* If the drive MWDMA is faster than it can do PIO then
842 we must force PIO into PIO0 */
844 if (adev
->pio_mode
< needed_pio
[mwdma
])
845 /* Enable DMA timing only */
846 control
|= 8; /* PIO cycles in PIO0 */
848 if (adev
->devno
) { /* Slave */
849 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
850 master_data
|= control
<< 4;
851 pci_read_config_byte(dev
, 0x44, &slave_data
);
852 slave_data
&= (0x0F + 0xE1 * ap
->port_no
);
853 /* Load the matching timing */
854 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
855 pci_write_config_byte(dev
, 0x44, slave_data
);
856 } else { /* Master */
857 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
858 and master timing bits */
859 master_data
|= control
;
861 (timings
[pio
][0] << 12) |
862 (timings
[pio
][1] << 8);
864 udma_enable
&= ~(1 << devid
);
865 pci_write_config_word(dev
, master_port
, master_data
);
867 /* Don't scribble on 0x48 if the controller does not support UDMA */
869 pci_write_config_byte(dev
, 0x48, udma_enable
);
873 * piix_set_dmamode - Initialize host controller PATA DMA timings
874 * @ap: Port whose timings we are configuring
877 * Set MW/UDMA mode for device, in host controller PCI config space.
880 * None (inherited from caller).
883 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
885 do_pata_set_dmamode(ap
, adev
, 0);
889 * ich_set_dmamode - Initialize host controller PATA DMA timings
890 * @ap: Port whose timings we are configuring
893 * Set MW/UDMA mode for device, in host controller PCI config space.
896 * None (inherited from caller).
899 static void ich_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
901 do_pata_set_dmamode(ap
, adev
, 1);
904 #define AHCI_PCI_BAR 5
905 #define AHCI_GLOBAL_CTL 0x04
906 #define AHCI_ENABLE (1 << 31)
907 static int piix_disable_ahci(struct pci_dev
*pdev
)
913 /* BUG: pci_enable_device has not yet been called. This
914 * works because this device is usually set up by BIOS.
917 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
918 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
921 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
925 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
926 if (tmp
& AHCI_ENABLE
) {
928 writel(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
930 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
931 if (tmp
& AHCI_ENABLE
)
935 pci_iounmap(pdev
, mmio
);
940 * piix_check_450nx_errata - Check for problem 450NX setup
941 * @ata_dev: the PCI device to check
943 * Check for the present of 450NX errata #19 and errata #25. If
944 * they are found return an error code so we can turn off DMA
947 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
949 struct pci_dev
*pdev
= NULL
;
954 while((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
)
956 /* Look for 450NX PXB. Check for problem configurations
957 A PCI quirk checks bit 6 already */
958 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
959 pci_read_config_word(pdev
, 0x41, &cfg
);
960 /* Only on the original revision: IDE DMA can hang */
963 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
964 else if (cfg
& (1<<14) && rev
< 5)
968 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
969 if (no_piix_dma
== 2)
970 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
974 static void __devinit
piix_init_pcs(struct pci_dev
*pdev
,
975 struct ata_port_info
*pinfo
,
976 const struct piix_map_db
*map_db
)
980 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
982 new_pcs
= pcs
| map_db
->port_enable
;
984 if (new_pcs
!= pcs
) {
985 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
986 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
991 static void __devinit
piix_init_sata_map(struct pci_dev
*pdev
,
992 struct ata_port_info
*pinfo
,
993 const struct piix_map_db
*map_db
)
995 struct piix_host_priv
*hpriv
= pinfo
[0].private_data
;
996 const unsigned int *map
;
997 int i
, invalid_map
= 0;
1000 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1002 map
= map_db
->map
[map_value
& map_db
->mask
];
1004 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1005 for (i
= 0; i
< 4; i
++) {
1017 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1018 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1019 pinfo
[i
/ 2].private_data
= hpriv
;
1025 printk(" P%d", map
[i
]);
1027 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1034 dev_printk(KERN_ERR
, &pdev
->dev
,
1035 "invalid MAP value %u\n", map_value
);
1041 * piix_init_one - Register PIIX ATA PCI device with kernel services
1042 * @pdev: PCI device to register
1043 * @ent: Entry in piix_pci_tbl matching with @pdev
1045 * Called from kernel PCI layer. We probe for combined mode (sigh),
1046 * and then hand over control to libata, for it to do the rest.
1049 * Inherited from PCI layer (may sleep).
1052 * Zero on success, or -ERRNO value.
1055 static int piix_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1057 static int printed_version
;
1058 struct ata_port_info port_info
[2];
1059 struct ata_port_info
*ppinfo
[2] = { &port_info
[0], &port_info
[1] };
1060 struct piix_host_priv
*hpriv
;
1061 unsigned long port_flags
;
1063 if (!printed_version
++)
1064 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1065 "version " DRV_VERSION
"\n");
1067 /* no hotplugging support (FIXME) */
1068 if (!in_module_init
)
1071 hpriv
= kzalloc(sizeof(*hpriv
), GFP_KERNEL
);
1075 port_info
[0] = piix_port_info
[ent
->driver_data
];
1076 port_info
[1] = piix_port_info
[ent
->driver_data
];
1077 port_info
[0].private_data
= hpriv
;
1078 port_info
[1].private_data
= hpriv
;
1080 port_flags
= port_info
[0].flags
;
1082 if (port_flags
& PIIX_FLAG_AHCI
) {
1084 pci_read_config_byte(pdev
, PIIX_SCC
, &tmp
);
1085 if (tmp
== PIIX_AHCI_DEVICE
) {
1086 int rc
= piix_disable_ahci(pdev
);
1092 /* Initialize SATA map */
1093 if (port_flags
& ATA_FLAG_SATA
) {
1094 piix_init_sata_map(pdev
, port_info
,
1095 piix_map_db_table
[ent
->driver_data
]);
1096 piix_init_pcs(pdev
, port_info
,
1097 piix_map_db_table
[ent
->driver_data
]);
1100 /* On ICH5, some BIOSen disable the interrupt using the
1101 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1102 * On ICH6, this bit has the same effect, but only when
1103 * MSI is disabled (and it is disabled, as we don't use
1104 * message-signalled interrupts currently).
1106 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1109 if (piix_check_450nx_errata(pdev
)) {
1110 /* This writes into the master table but it does not
1111 really matter for this errata as we will apply it to
1112 all the PIIX devices on the board */
1113 port_info
[0].mwdma_mask
= 0;
1114 port_info
[0].udma_mask
= 0;
1115 port_info
[1].mwdma_mask
= 0;
1116 port_info
[1].udma_mask
= 0;
1118 return ata_pci_init_one(pdev
, ppinfo
, 2);
1121 static void piix_host_stop(struct ata_host
*host
)
1123 struct piix_host_priv
*hpriv
= host
->private_data
;
1125 ata_host_stop(host
);
1130 static int __init
piix_init(void)
1134 DPRINTK("pci_register_driver\n");
1135 rc
= pci_register_driver(&piix_pci_driver
);
1145 static void __exit
piix_exit(void)
1147 pci_unregister_driver(&piix_pci_driver
);
1150 module_init(piix_init
);
1151 module_exit(piix_exit
);