1 /*****************************************************************************/
2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
8 /* Copyright (C) 1999 IBM Corporation */
9 /* Copyright (C) 2003 Adaptec, Inc. */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
45 /* Bugs/Comments/Suggestions should be mailed to: */
46 /* ipslinux@adaptec.com */
48 /*****************************************************************************/
53 #include <linux/version.h>
54 #include <linux/nmi.h>
55 #include <asm/uaccess.h>
61 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
62 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
63 #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
64 (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
65 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
66 #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
67 (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
68 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
69 #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
70 #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
71 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
72 (IPS_IS_TROMBONE(ha) && \
73 (ips_force_i2o))) ? 1 : 0)
74 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
75 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
76 (ips_force_memio))) ? 1 : 0)
78 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
79 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
80 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
81 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
83 #define IPS_PRINTK(level, pcidev, format, arg...) \
84 dev_printk(level , &((pcidev)->dev) , format , ## arg)
89 touch_nmi_watchdog(); \
93 #define min(x,y) ((x) < (y) ? x : y)
96 #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
100 #define pci_dma_hi32(a) ((a >> 16) >> 16)
101 #define pci_dma_lo32(a) (a & 0xffffffff)
103 #if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
104 #define IPS_ENABLE_DMA64 (1)
106 #define IPS_ENABLE_DMA64 (0)
110 * Adapter address map equates
112 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
113 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
114 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
115 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
116 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
117 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
118 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
119 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
120 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
121 #define IPS_REG_CBSP 0x07 /* CBSP register */
122 #define IPS_REG_FLAP 0x18 /* Flash address port */
123 #define IPS_REG_FLDP 0x1C /* Flash data port */
124 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
125 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
126 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
127 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
128 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
129 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
130 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
131 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
134 * Adapter register bit equates
136 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
137 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
138 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
139 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
140 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
141 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
142 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
143 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
144 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
145 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
146 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
147 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
148 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
149 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
152 * Adapter Command ID Equates
154 #define IPS_CMD_GET_LD_INFO 0x19
155 #define IPS_CMD_GET_SUBSYS 0x40
156 #define IPS_CMD_READ_CONF 0x38
157 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
158 #define IPS_CMD_READ 0x02
159 #define IPS_CMD_WRITE 0x03
160 #define IPS_CMD_FFDC 0xD7
161 #define IPS_CMD_ENQUIRY 0x05
162 #define IPS_CMD_FLUSH 0x0A
163 #define IPS_CMD_READ_SG 0x82
164 #define IPS_CMD_WRITE_SG 0x83
165 #define IPS_CMD_DCDB 0x04
166 #define IPS_CMD_DCDB_SG 0x84
167 #define IPS_CMD_EXTENDED_DCDB 0x95
168 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
169 #define IPS_CMD_CONFIG_SYNC 0x58
170 #define IPS_CMD_ERROR_TABLE 0x17
171 #define IPS_CMD_DOWNLOAD 0x20
172 #define IPS_CMD_RW_BIOSFW 0x22
173 #define IPS_CMD_GET_VERSION_INFO 0xC6
174 #define IPS_CMD_RESET_CHANNEL 0x1A
180 #define IPS_POCL 0x30
181 #define IPS_NORM_STATE 0x00
182 #define IPS_MAX_ADAPTER_TYPES 3
183 #define IPS_MAX_ADAPTERS 16
184 #define IPS_MAX_IOCTL 1
185 #define IPS_MAX_IOCTL_QUEUE 8
186 #define IPS_MAX_QUEUE 128
187 #define IPS_BLKSIZE 512
188 #define IPS_MAX_SG 17
190 #define IPS_MAX_CHANNELS 4
191 #define IPS_MAX_TARGETS 15
192 #define IPS_MAX_CHUNKS 16
193 #define IPS_MAX_CMDS 128
194 #define IPS_MAX_XFER 0x10000
195 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
196 #define IPS_MAX_POST_BYTES 0x02
197 #define IPS_MAX_CONFIG_BYTES 0x02
198 #define IPS_GOOD_POST_STATUS 0x80
199 #define IPS_SEM_TIMEOUT 2000
200 #define IPS_IOCTL_COMMAND 0x0D
201 #define IPS_INTR_ON 0
202 #define IPS_INTR_IORL 1
204 #define IPS_ADAPTER_ID 0xF
205 #define IPS_VENDORID_IBM 0x1014
206 #define IPS_VENDORID_ADAPTEC 0x9005
207 #define IPS_DEVICEID_COPPERHEAD 0x002E
208 #define IPS_DEVICEID_MORPHEUS 0x01BD
209 #define IPS_DEVICEID_MARCO 0x0250
210 #define IPS_SUBDEVICEID_4M 0x01BE
211 #define IPS_SUBDEVICEID_4L 0x01BF
212 #define IPS_SUBDEVICEID_4MX 0x0208
213 #define IPS_SUBDEVICEID_4LX 0x020E
214 #define IPS_SUBDEVICEID_5I2 0x0259
215 #define IPS_SUBDEVICEID_5I1 0x0258
216 #define IPS_SUBDEVICEID_6M 0x0279
217 #define IPS_SUBDEVICEID_6I 0x028C
218 #define IPS_SUBDEVICEID_7k 0x028E
219 #define IPS_SUBDEVICEID_7M 0x028F
220 #define IPS_IOCTL_SIZE 8192
221 #define IPS_STATUS_SIZE 4
222 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
223 #define IPS_IMAGE_SIZE 500 * 1024
224 #define IPS_MEMMAP_SIZE 128
225 #define IPS_ONE_MSEC 1
226 #define IPS_ONE_SEC 1000
231 #define IPS_COMP_HEADS 128
232 #define IPS_COMP_SECTORS 32
233 #define IPS_NORM_HEADS 254
234 #define IPS_NORM_SECTORS 63
237 * Adapter Basic Status Codes
239 #define IPS_BASIC_STATUS_MASK 0xFF
240 #define IPS_GSC_STATUS_MASK 0x0F
241 #define IPS_CMD_SUCCESS 0x00
242 #define IPS_CMD_RECOVERED_ERROR 0x01
243 #define IPS_INVAL_OPCO 0x03
244 #define IPS_INVAL_CMD_BLK 0x04
245 #define IPS_INVAL_PARM_BLK 0x05
246 #define IPS_BUSY 0x08
247 #define IPS_CMD_CMPLT_WERROR 0x0C
248 #define IPS_LD_ERROR 0x0D
249 #define IPS_CMD_TIMEOUT 0x0E
250 #define IPS_PHYS_DRV_ERROR 0x0F
253 * Adapter Extended Status Equates
255 #define IPS_ERR_SEL_TO 0xF0
256 #define IPS_ERR_OU_RUN 0xF2
257 #define IPS_ERR_HOST_RESET 0xF7
258 #define IPS_ERR_DEV_RESET 0xF8
259 #define IPS_ERR_RECOVERY 0xFC
260 #define IPS_ERR_CKCOND 0xFF
263 * Operating System Defines
265 #define IPS_OS_WINDOWS_NT 0x01
266 #define IPS_OS_NETWARE 0x02
267 #define IPS_OS_OPENSERVER 0x03
268 #define IPS_OS_UNIXWARE 0x04
269 #define IPS_OS_SOLARIS 0x05
270 #define IPS_OS_OS2 0x06
271 #define IPS_OS_LINUX 0x07
272 #define IPS_OS_FREEBSD 0x08
275 * Adapter Revision ID's
277 #define IPS_REVID_SERVERAID 0x02
278 #define IPS_REVID_NAVAJO 0x03
279 #define IPS_REVID_SERVERAID2 0x04
280 #define IPS_REVID_CLARINETP1 0x05
281 #define IPS_REVID_CLARINETP2 0x07
282 #define IPS_REVID_CLARINETP3 0x0D
283 #define IPS_REVID_TROMBONE32 0x0F
284 #define IPS_REVID_TROMBONE64 0x10
287 * NVRAM Page 5 Adapter Defines
289 #define IPS_ADTYPE_SERVERAID 0x01
290 #define IPS_ADTYPE_SERVERAID2 0x02
291 #define IPS_ADTYPE_NAVAJO 0x03
292 #define IPS_ADTYPE_KIOWA 0x04
293 #define IPS_ADTYPE_SERVERAID3 0x05
294 #define IPS_ADTYPE_SERVERAID3L 0x06
295 #define IPS_ADTYPE_SERVERAID4H 0x07
296 #define IPS_ADTYPE_SERVERAID4M 0x08
297 #define IPS_ADTYPE_SERVERAID4L 0x09
298 #define IPS_ADTYPE_SERVERAID4MX 0x0A
299 #define IPS_ADTYPE_SERVERAID4LX 0x0B
300 #define IPS_ADTYPE_SERVERAID5I2 0x0C
301 #define IPS_ADTYPE_SERVERAID5I1 0x0D
302 #define IPS_ADTYPE_SERVERAID6M 0x0E
303 #define IPS_ADTYPE_SERVERAID6I 0x0F
304 #define IPS_ADTYPE_SERVERAID7t 0x10
305 #define IPS_ADTYPE_SERVERAID7k 0x11
306 #define IPS_ADTYPE_SERVERAID7M 0x12
309 * Adapter Command/Status Packet Definitions
311 #define IPS_SUCCESS 0x01 /* Successfully completed */
312 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
313 #define IPS_FAILURE 0x04 /* Completed with Error */
316 * Logical Drive Equates
318 #define IPS_LD_OFFLINE 0x02
319 #define IPS_LD_OKAY 0x03
320 #define IPS_LD_FREE 0x00
321 #define IPS_LD_SYS 0x06
322 #define IPS_LD_CRS 0x24
327 #define IPS_NO_DISCONNECT 0x00
328 #define IPS_DISCONNECT_ALLOWED 0x80
329 #define IPS_NO_AUTO_REQSEN 0x40
330 #define IPS_DATA_NONE 0x00
331 #define IPS_DATA_UNK 0x00
332 #define IPS_DATA_IN 0x01
333 #define IPS_DATA_OUT 0x02
334 #define IPS_TRANSFER64K 0x08
335 #define IPS_NOTIMEOUT 0x00
336 #define IPS_TIMEOUT10 0x10
337 #define IPS_TIMEOUT60 0x20
338 #define IPS_TIMEOUT20M 0x30
341 * SCSI Inquiry Data Flags
343 #define IPS_SCSI_INQ_TYPE_DASD 0x00
344 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
345 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
346 #define IPS_SCSI_INQ_RD_REV2 0x02
347 #define IPS_SCSI_INQ_REV2 0x02
348 #define IPS_SCSI_INQ_REV3 0x03
349 #define IPS_SCSI_INQ_Address16 0x01
350 #define IPS_SCSI_INQ_Address32 0x02
351 #define IPS_SCSI_INQ_MedChanger 0x08
352 #define IPS_SCSI_INQ_MultiPort 0x10
353 #define IPS_SCSI_INQ_EncServ 0x40
354 #define IPS_SCSI_INQ_SoftReset 0x01
355 #define IPS_SCSI_INQ_CmdQue 0x02
356 #define IPS_SCSI_INQ_Linked 0x08
357 #define IPS_SCSI_INQ_Sync 0x10
358 #define IPS_SCSI_INQ_WBus16 0x20
359 #define IPS_SCSI_INQ_WBus32 0x40
360 #define IPS_SCSI_INQ_RelAdr 0x80
363 * SCSI Request Sense Data Flags
365 #define IPS_SCSI_REQSEN_VALID 0x80
366 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
367 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
370 * SCSI Mode Page Equates
372 #define IPS_SCSI_MP3_SoftSector 0x01
373 #define IPS_SCSI_MP3_HardSector 0x02
374 #define IPS_SCSI_MP3_Removeable 0x04
375 #define IPS_SCSI_MP3_AllocateSurface 0x08
381 #define IPS_HA_ENH_SG 0x1
386 #define IPS_SCB_MAP_SG 0x00008
387 #define IPS_SCB_MAP_SINGLE 0X00010
392 #define IPS_COPPUSRCMD (('C'<<8) | 65)
393 #define IPS_COPPIOCCMD (('C'<<8) | 66)
394 #define IPS_NUMCTRLS (('C'<<8) | 68)
395 #define IPS_CTRLINFO (('C'<<8) | 69)
397 /* flashing defines */
398 #define IPS_FW_IMAGE 0x00
399 #define IPS_BIOS_IMAGE 0x01
400 #define IPS_WRITE_FW 0x01
401 #define IPS_WRITE_BIOS 0x02
402 #define IPS_ERASE_BIOS 0x03
403 #define IPS_BIOS_HEADER 0xC0
405 /* time oriented stuff */
406 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
407 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
409 #define IPS_SECS_MIN 60
410 #define IPS_SECS_HOUR 3600
411 #define IPS_SECS_8HOURS 28800
412 #define IPS_SECS_DAY 86400
413 #define IPS_DAYS_NORMAL_YEAR 365
414 #define IPS_DAYS_LEAP_YEAR 366
415 #define IPS_EPOCH_YEAR 1970
420 static int ips_proc_info(struct Scsi_Host
*, char *, char **, off_t
, int, int);
421 static int ips_biosparam(struct scsi_device
*sdev
, struct block_device
*bdev
,
422 sector_t capacity
, int geom
[]);
423 static int ips_slave_configure(struct scsi_device
*SDptr
);
426 * Raid Command Formats
435 uint16_t sector_count
;
440 } IPS_IO_CMD
, *PIPS_IO_CMD
;
447 uint32_t buffer_addr
;
451 } IPS_LD_CMD
, *PIPS_LD_CMD
;
459 uint32_t buffer_addr
;
461 } IPS_IOCTL_CMD
, *PIPS_IOCTL_CMD
;
479 uint8_t adapter_flag
;
480 } IPS_RESET_CMD
, *PIPS_RESET_CMD
;
487 uint32_t dcdb_address
;
493 } IPS_DCDB_CMD
, *PIPS_DCDB_CMD
;
499 uint8_t source_target
;
505 } IPS_CS_CMD
, *PIPS_CS_CMD
;
517 } IPS_US_CMD
, *PIPS_US_CMD
;
529 } IPS_FC_CMD
, *PIPS_FC_CMD
;
537 uint32_t buffer_addr
;
541 } IPS_STATUS_CMD
, *PIPS_STATUS_CMD
;
549 uint32_t buffer_addr
;
553 } IPS_NVRAM_CMD
, *PIPS_NVRAM_CMD
;
561 uint32_t buffer_addr
;
563 } IPS_VERSION_INFO
, *PIPS_VERSION_INFO
;
574 uint8_t reserved1
[4];
579 } IPS_FFDC_CMD
, *PIPS_FFDC_CMD
;
587 uint32_t buffer_addr
;
588 uint8_t total_packets
;
591 } IPS_FLASHFW_CMD
, *PIPS_FLASHFW_CMD
;
599 uint32_t buffer_addr
;
601 } IPS_FLASHBIOS_CMD
, *PIPS_FLASHBIOS_CMD
;
605 IPS_LD_CMD logical_info
;
606 IPS_IOCTL_CMD ioctl_info
;
608 IPS_CS_CMD config_sync
;
609 IPS_US_CMD unlock_stripe
;
610 IPS_FC_CMD flush_cache
;
611 IPS_STATUS_CMD status
;
614 IPS_FLASHFW_CMD flashfw
;
615 IPS_FLASHBIOS_CMD flashbios
;
616 IPS_VERSION_INFO version_info
;
618 } IPS_HOST_COMMAND
, *PIPS_HOST_COMMAND
;
625 uint32_t sector_count
;
626 } IPS_DRIVE_INFO
, *PIPS_DRIVE_INFO
;
629 uint8_t no_of_log_drive
;
631 IPS_DRIVE_INFO drive_info
[IPS_MAX_LD
];
632 } IPS_LD_INFO
, *PIPS_LD_INFO
;
635 uint8_t device_address
;
636 uint8_t cmd_attribute
;
637 uint16_t transfer_length
;
638 uint32_t buffer_pointer
;
640 uint8_t sense_length
;
643 uint8_t scsi_cdb
[12];
644 uint8_t sense_info
[64];
646 uint8_t reserved2
[3];
647 } IPS_DCDB_TABLE
, *PIPS_DCDB_TABLE
;
650 uint8_t device_address
;
651 uint8_t cmd_attribute
;
653 uint8_t reserved_for_LUN
;
654 uint32_t transfer_length
;
655 uint32_t buffer_pointer
;
657 uint8_t sense_length
;
660 uint8_t scsi_cdb
[16];
661 uint8_t sense_info
[56];
662 } IPS_DCDB_TABLE_TAPE
, *PIPS_DCDB_TABLE_TAPE
;
666 volatile uint8_t reserved
;
667 volatile uint8_t command_id
;
668 volatile uint8_t basic_status
;
669 volatile uint8_t extended_status
;
672 volatile uint32_t value
;
673 } IPS_STATUS
, *PIPS_STATUS
;
676 IPS_STATUS status
[IPS_MAX_CMDS
+ 1];
677 volatile PIPS_STATUS p_status_start
;
678 volatile PIPS_STATUS p_status_end
;
679 volatile PIPS_STATUS p_status_tail
;
680 volatile uint32_t hw_status_start
;
681 volatile uint32_t hw_status_tail
;
682 } IPS_ADAPTER
, *PIPS_ADAPTER
;
685 uint8_t ucLogDriveCount
;
690 uint8_t ucWrongAdrCnt
;
691 uint8_t ucUnidentCnt
;
692 uint8_t ucNVramDevChgCnt
;
693 uint8_t CodeBlkVersion
[8];
694 uint8_t BootBlkVersion
[8];
695 uint32_t ulDriveSize
[IPS_MAX_LD
];
696 uint8_t ucConcurrentCmdCount
;
697 uint8_t ucMaxPhysicalDevices
;
698 uint16_t usFlashRepgmCount
;
699 uint8_t ucDefunctDiskCount
;
700 uint8_t ucRebuildFlag
;
701 uint8_t ucOfflineLogDrvCount
;
702 uint8_t ucCriticalDrvCount
;
703 uint16_t usConfigUpdateCount
;
706 uint16_t usAddrDeadDisk
[IPS_MAX_CHANNELS
* (IPS_MAX_TARGETS
+ 1)];
707 } IPS_ENQ
, *PIPS_ENQ
;
711 uint8_t ucParameters
;
714 uint32_t ulBlockCount
;
715 uint8_t ucDeviceId
[28];
716 } IPS_DEVSTATE
, *PIPS_DEVSTATE
;
722 uint32_t ulStartSect
;
723 uint32_t ulNoOfSects
;
724 } IPS_CHUNK
, *PIPS_CHUNK
;
727 uint16_t ucUserField
;
729 uint8_t ucRaidCacheParam
;
730 uint8_t ucNoOfChunkUnits
;
731 uint8_t ucStripeSize
;
734 uint32_t ulLogDrvSize
;
735 IPS_CHUNK chunk
[IPS_MAX_CHUNKS
];
739 uint8_t board_disc
[8];
740 uint8_t processor
[8];
741 uint8_t ucNoChanType
;
742 uint8_t ucNoHostIntType
;
743 uint8_t ucCompression
;
745 uint32_t ulNvramSize
;
746 } IPS_HARDWARE
, *PIPS_HARDWARE
;
749 uint8_t ucLogDriveCount
;
755 uint8_t time_sign
[8];
758 uint8_t ucRebuildRate
;
760 IPS_HARDWARE hardware_disc
;
761 IPS_LD logical_drive
[IPS_MAX_LD
];
762 IPS_DEVSTATE dev
[IPS_MAX_CHANNELS
][IPS_MAX_TARGETS
+1];
763 uint8_t reserved
[512];
764 } IPS_CONF
, *PIPS_CONF
;
769 uint8_t adapter_slot
;
770 uint16_t adapter_type
;
771 uint8_t ctrl_bios
[8];
772 uint8_t versioning
; /* 1 = Versioning Supported, else 0 */
773 uint8_t version_mismatch
; /* 1 = Versioning MisMatch, else 0 */
775 uint8_t operating_system
;
776 uint8_t driver_high
[4];
777 uint8_t driver_low
[4];
778 uint8_t BiosCompatibilityID
[8];
779 uint8_t ReservedForOS2
[8];
780 uint8_t bios_high
[4]; /* Adapter's Flashed BIOS Version */
782 uint8_t adapter_order
[16]; /* BIOS Telling us the Sort Order */
784 } IPS_NVRAM_P5
, *PIPS_NVRAM_P5
;
786 /*--------------------------------------------------------------------------*/
787 /* Data returned from a GetVersion Command */
788 /*--------------------------------------------------------------------------*/
790 /* SubSystem Parameter[4] */
791 #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
796 uint8_t bootBlkVersion
[32];
797 uint8_t bootBlkAttributes
[4];
798 uint8_t codeBlkVersion
[32];
799 uint8_t biosVersion
[32];
800 uint8_t biosAttributes
[4];
801 uint8_t compatibilityId
[32];
806 typedef struct _IPS_SUBSYS
{
808 } IPS_SUBSYS
, *PIPS_SUBSYS
;
815 * Inquiry Data Format
819 uint8_t DeviceTypeQualifier
;
821 uint8_t ResponseDataFormat
;
822 uint8_t AdditionalLength
;
826 uint8_t ProductId
[16];
827 uint8_t ProductRevisionLevel
[4];
828 uint8_t Reserved2
; /* Provides NULL terminator to name */
829 } IPS_SCSI_INQ_DATA
, *PIPS_SCSI_INQ_DATA
;
832 * Read Capacity Data Format
840 * Request Sense Data Format
843 uint8_t ResponseCode
;
844 uint8_t SegmentNumber
;
846 uint8_t Information
[4];
847 uint8_t AdditionalLength
;
848 uint8_t CommandSpecific
[4];
849 uint8_t AdditionalSenseCode
;
850 uint8_t AdditionalSenseCodeQual
;
852 uint8_t SenseKeySpecific
[3];
856 * Sense Data Format - Page 3
861 uint16_t TracksPerZone
;
862 uint16_t AltSectorsPerZone
;
863 uint16_t AltTracksPerZone
;
864 uint16_t AltTracksPerVolume
;
865 uint16_t SectorsPerTrack
;
866 uint16_t BytesPerSector
;
869 uint16_t CylinderSkew
;
872 } IPS_SCSI_MODE_PAGE3
;
875 * Sense Data Format - Page 4
880 uint16_t CylindersHigh
;
881 uint8_t CylindersLow
;
883 uint16_t WritePrecompHigh
;
884 uint8_t WritePrecompLow
;
885 uint16_t ReducedWriteCurrentHigh
;
886 uint8_t ReducedWriteCurrentLow
;
888 uint16_t LandingZoneHigh
;
889 uint8_t LandingZoneLow
;
891 uint8_t RotationalOffset
;
893 uint16_t MediumRotationRate
;
894 uint8_t Reserved2
[2];
895 } IPS_SCSI_MODE_PAGE4
;
898 * Sense Data Format - Page 8
905 uint16_t DisPrefetchLen
;
906 uint16_t MinPrefetchLen
;
907 uint16_t MaxPrefetchLen
;
908 uint16_t MaxPrefetchCeiling
;
909 } IPS_SCSI_MODE_PAGE8
;
912 * Sense Data Format - Block Descriptor (DASD)
915 uint32_t NumberOfBlocks
;
917 uint16_t BlockLengthHigh
;
918 uint8_t BlockLengthLow
;
919 } IPS_SCSI_MODE_PAGE_BLKDESC
;
922 * Sense Data Format - Mode Page Header
928 uint8_t BlockDescLength
;
929 } IPS_SCSI_MODE_PAGE_HEADER
;
932 IPS_SCSI_MODE_PAGE_HEADER hdr
;
933 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc
;
936 IPS_SCSI_MODE_PAGE3 pg3
;
937 IPS_SCSI_MODE_PAGE4 pg4
;
938 IPS_SCSI_MODE_PAGE8 pg8
;
940 } IPS_SCSI_MODE_PAGE_DATA
;
943 * Scatter Gather list format
945 typedef struct ips_sglist
{
950 typedef struct ips_enh_sglist
{
959 IPS_STD_SG_LIST
*std_list
;
960 IPS_ENH_SG_LIST
*enh_list
;
963 typedef struct _IPS_INFOSTR
{
980 typedef struct ips_stat
{
981 uint32_t residue_len
;
983 uint8_t padding
[12 - sizeof(void *)];
989 typedef struct ips_scb_queue
{
990 struct ips_scb
*head
;
991 struct ips_scb
*tail
;
998 typedef struct ips_wait_queue
{
999 struct scsi_cmnd
*head
;
1000 struct scsi_cmnd
*tail
;
1004 typedef struct ips_copp_wait_item
{
1005 struct scsi_cmnd
*scsi_cmd
;
1006 struct ips_copp_wait_item
*next
;
1007 } ips_copp_wait_item_t
;
1009 typedef struct ips_copp_queue
{
1010 struct ips_copp_wait_item
*head
;
1011 struct ips_copp_wait_item
*tail
;
1015 /* forward decl for host structure */
1019 int (*reset
)(struct ips_ha
*);
1020 int (*issue
)(struct ips_ha
*, struct ips_scb
*);
1021 int (*isinit
)(struct ips_ha
*);
1022 int (*isintr
)(struct ips_ha
*);
1023 int (*init
)(struct ips_ha
*);
1024 int (*erasebios
)(struct ips_ha
*);
1025 int (*programbios
)(struct ips_ha
*, char *, uint32_t, uint32_t);
1026 int (*verifybios
)(struct ips_ha
*, char *, uint32_t, uint32_t);
1027 void (*statinit
)(struct ips_ha
*);
1028 int (*intr
)(struct ips_ha
*);
1029 void (*enableint
)(struct ips_ha
*);
1030 uint32_t (*statupd
)(struct ips_ha
*);
1033 typedef struct ips_ha
{
1034 uint8_t ha_id
[IPS_MAX_CHANNELS
+1];
1035 uint32_t dcdb_active
[IPS_MAX_CHANNELS
];
1036 uint32_t io_addr
; /* Base I/O address */
1037 uint8_t ntargets
; /* Number of targets */
1038 uint8_t nbus
; /* Number of buses */
1039 uint8_t nlun
; /* Number of Luns */
1040 uint16_t ad_type
; /* Adapter type */
1041 uint16_t host_num
; /* Adapter number */
1042 uint32_t max_xfer
; /* Maximum Xfer size */
1043 uint32_t max_cmds
; /* Max concurrent commands */
1044 uint32_t num_ioctl
; /* Number of Ioctls */
1045 ips_stat_t sp
; /* Status packer pointer */
1046 struct ips_scb
*scbs
; /* Array of all CCBS */
1047 struct ips_scb
*scb_freelist
; /* SCB free list */
1048 ips_wait_queue_t scb_waitlist
; /* Pending SCB list */
1049 ips_copp_queue_t copp_waitlist
; /* Pending PT list */
1050 ips_scb_queue_t scb_activelist
; /* Active SCB list */
1051 IPS_IO_CMD
*dummy
; /* dummy command */
1052 IPS_ADAPTER
*adapt
; /* Adapter status area */
1053 IPS_LD_INFO
*logical_drive_info
; /* Adapter Logical Drive Info */
1054 dma_addr_t logical_drive_info_dma_addr
; /* Logical Drive Info DMA Address */
1055 IPS_ENQ
*enq
; /* Adapter Enquiry data */
1056 IPS_CONF
*conf
; /* Adapter config data */
1057 IPS_NVRAM_P5
*nvram
; /* NVRAM page 5 data */
1058 IPS_SUBSYS
*subsys
; /* Subsystem parameters */
1059 char *ioctl_data
; /* IOCTL data area */
1060 uint32_t ioctl_datasize
; /* IOCTL data size */
1061 uint32_t cmd_in_progress
; /* Current command in progress*/
1063 uint8_t waitflag
; /* are we waiting for cmd */
1065 int ioctl_reset
; /* IOCTL Requested Reset Flag */
1066 uint16_t reset_count
; /* number of resets */
1067 time_t last_ffdc
; /* last time we sent ffdc info*/
1068 uint8_t slot_num
; /* PCI Slot Number */
1069 int ioctl_len
; /* size of ioctl buffer */
1070 dma_addr_t ioctl_busaddr
; /* dma address of ioctl buffer*/
1071 uint8_t bios_version
[8]; /* BIOS Revision */
1072 uint32_t mem_addr
; /* Memory mapped address */
1073 uint32_t io_len
; /* Size of IO Address */
1074 uint32_t mem_len
; /* Size of memory address */
1075 char __iomem
*mem_ptr
; /* Memory mapped Ptr */
1076 char __iomem
*ioremap_ptr
;/* ioremapped memory pointer */
1077 ips_hw_func_t func
; /* hw function pointers */
1078 struct pci_dev
*pcidev
; /* PCI device handle */
1079 char *flash_data
; /* Save Area for flash data */
1080 int flash_len
; /* length of flash buffer */
1081 u32 flash_datasize
; /* Save Area for flash data size */
1082 dma_addr_t flash_busaddr
; /* dma address of flash buffer*/
1083 dma_addr_t enq_busaddr
; /* dma address of enq struct */
1084 uint8_t requires_esl
; /* Requires an EraseStripeLock */
1087 typedef void (*ips_scb_callback
) (ips_ha_t
*, struct ips_scb
*);
1092 typedef struct ips_scb
{
1093 IPS_HOST_COMMAND cmd
;
1094 IPS_DCDB_TABLE dcdb
;
1099 uint32_t scb_busaddr
;
1100 uint32_t old_data_busaddr
; // Obsolete, but kept for old utility compatibility
1102 uint8_t basic_status
;
1103 uint8_t extended_status
;
1110 IPS_SG_LIST sg_list
;
1111 struct scsi_cmnd
*scsi_cmd
;
1112 struct ips_scb
*q_next
;
1113 ips_scb_callback callback
;
1114 uint32_t sg_busaddr
;
1116 dma_addr_t data_busaddr
;
1119 typedef struct ips_scb_pt
{
1120 IPS_HOST_COMMAND cmd
;
1121 IPS_DCDB_TABLE dcdb
;
1126 uint32_t scb_busaddr
;
1127 uint32_t data_busaddr
;
1129 uint8_t basic_status
;
1130 uint8_t extended_status
;
1136 IPS_SG_LIST
*sg_list
;
1137 struct scsi_cmnd
*scsi_cmd
;
1138 struct ips_scb
*q_next
;
1139 ips_scb_callback callback
;
1143 * Passthru Command Format
1151 ips_scb_pt_t CoppCP
;
1153 uint8_t BasicStatus
;
1154 uint8_t ExtendedStatus
;
1155 uint8_t AdapterType
;
1161 /* The Version Information below gets created by SED during the build process. */
1162 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1164 /*************************************************************************
1166 * VERSION.H -- version numbers and copyright notices in various formats
1168 *************************************************************************/
1170 #define IPS_VER_MAJOR 7
1171 #define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1172 #define IPS_VER_MINOR 12
1173 #define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1174 #define IPS_VER_BUILD 05
1175 #define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1176 #define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1177 IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1178 #define IPS_RELEASE_ID 0x00020000
1179 #define IPS_BUILD_IDENT 761
1180 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1181 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1182 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1183 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1185 /* Version numbers for various adapters */
1186 #define IPS_VER_SERVERAID1 "2.25.01"
1187 #define IPS_VER_SERVERAID2 "2.88.13"
1188 #define IPS_VER_NAVAJO "2.88.13"
1189 #define IPS_VER_SERVERAID3 "6.10.24"
1190 #define IPS_VER_SERVERAID4H "7.12.02"
1191 #define IPS_VER_SERVERAID4MLx "7.12.02"
1192 #define IPS_VER_SARASOTA "7.12.02"
1193 #define IPS_VER_MARCO "7.12.02"
1194 #define IPS_VER_SEBRING "7.12.02"
1195 #define IPS_VER_KEYWEST "7.12.02"
1197 /* Compatability IDs for various adapters */
1198 #define IPS_COMPAT_UNKNOWN ""
1199 #define IPS_COMPAT_CURRENT "KW710"
1200 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1201 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1202 #define IPS_COMPAT_NAVAJO "2.88.13"
1203 #define IPS_COMPAT_KIOWA "2.88.13"
1204 #define IPS_COMPAT_SERVERAID3H "SB610"
1205 #define IPS_COMPAT_SERVERAID3L "SB610"
1206 #define IPS_COMPAT_SERVERAID4H "KW710"
1207 #define IPS_COMPAT_SERVERAID4M "KW710"
1208 #define IPS_COMPAT_SERVERAID4L "KW710"
1209 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1210 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1211 #define IPS_COMPAT_SARASOTA "KW710"
1212 #define IPS_COMPAT_MARCO "KW710"
1213 #define IPS_COMPAT_SEBRING "KW710"
1214 #define IPS_COMPAT_TAMPA "KW710"
1215 #define IPS_COMPAT_KEYWEST "KW710"
1216 #define IPS_COMPAT_BIOS "KW710"
1218 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1219 #define IPS_COMPAT_ID_LENGTH 8
1221 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1222 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1223 IPS_COMPAT_UNKNOWN, \
1224 IPS_COMPAT_SERVERAID1, \
1225 IPS_COMPAT_SERVERAID2, \
1226 IPS_COMPAT_NAVAJO, \
1228 IPS_COMPAT_SERVERAID3H, \
1229 IPS_COMPAT_SERVERAID3L, \
1230 IPS_COMPAT_SERVERAID4H, \
1231 IPS_COMPAT_SERVERAID4M, \
1232 IPS_COMPAT_SERVERAID4L, \
1233 IPS_COMPAT_SERVERAID4Mx, \
1234 IPS_COMPAT_SERVERAID4Lx, \
1235 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1236 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1238 IPS_COMPAT_SEBRING, \
1240 IPS_COMPAT_KEYWEST \
1245 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1246 * Emacs will notice this stuff at the end of the file and automatically
1247 * adjust the settings for this buffer only. This must remain at the end
1249 * ---------------------------------------------------------------------------
1252 * c-brace-imaginary-offset: 0
1253 * c-brace-offset: -2
1254 * c-argdecl-indent: 2
1255 * c-label-offset: -2
1256 * c-continued-statement-offset: 2
1257 * c-continued-brace-offset: 0
1258 * indent-tabs-mode: nil