1 /**************************************************************************
2 * Copyright (c) 2007-2008, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
23 #include <linux/version.h>
26 #include "drm_global.h"
29 #include "psb_intel_drv.h"
31 #include "psb_powermgmt.h"
34 /*Append new drm mode definition here, align with libdrm definition*/
35 #define DRM_MODE_SCALE_NO_SCALE 2
37 extern struct ttm_bo_driver psb_ttm_bo_driver
;
45 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
51 #define DRIVER_NAME "pvrsrvkm"
52 #define DRIVER_DESC "drm driver for the Intel GMA500"
53 #define DRIVER_AUTHOR "Intel Corporation"
55 #define PSB_DRM_DRIVER_DATE "2009-03-10"
56 #define PSB_DRM_DRIVER_MAJOR 8
57 #define PSB_DRM_DRIVER_MINOR 1
58 #define PSB_DRM_DRIVER_PATCHLEVEL 0
61 *TTM driver private offsets.
64 #define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
66 #define PSB_OBJECT_HASH_ORDER 13
67 #define PSB_FILE_OBJECT_HASH_ORDER 12
68 #define PSB_BO_HASH_ORDER 12
70 #define PSB_VDC_OFFSET 0x00000000
71 #define PSB_VDC_SIZE 0x000080000
72 #define MRST_MMIO_SIZE 0x0000C0000
73 #define MDFLD_MMIO_SIZE 0x000100000
74 #define PSB_SGX_SIZE 0x8000
75 #define PSB_SGX_OFFSET 0x00040000
76 #define MRST_SGX_OFFSET 0x00080000
77 #define PSB_MMIO_RESOURCE 0
78 #define PSB_GATT_RESOURCE 2
79 #define PSB_GTT_RESOURCE 3
80 #define PSB_GMCH_CTRL 0x52
82 #define _PSB_GMCH_ENABLED 0x4
83 #define PSB_PGETBL_CTL 0x2020
84 #define _PSB_PGETBL_ENABLED 0x00000001
85 #define PSB_SGX_2D_SLAVE_PORT 0x4000
86 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
87 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
88 #define PSB_NUM_VALIDATE_BUFFERS 2048
91 *Flags for external memory type field.
94 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
95 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
96 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
102 #define PSB_PDE_MASK 0x003FFFFF
103 #define PSB_PDE_SHIFT 22
104 #define PSB_PTE_SHIFT 12
106 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
107 #define PSB_PTE_WO 0x0002 /* Write only */
108 #define PSB_PTE_RO 0x0004 /* Read only */
109 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
112 *VDC registers and bits
114 #define PSB_MSVDX_CLOCKGATING 0x2064
115 #define PSB_TOPAZ_CLOCKGATING 0x2068
116 #define PSB_HWSTAM 0x2098
117 #define PSB_INSTPM 0x20C0
118 #define PSB_INT_IDENTITY_R 0x20A4
119 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
120 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
121 #define _PSB_DPST_PIPEB_FLAG (1<<4)
122 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
123 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
124 #define _PSB_DPST_PIPEA_FLAG (1<<6)
125 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
126 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
127 #define _MDFLD_MIPIA_FLAG (1<<16)
128 #define _MDFLD_MIPIC_FLAG (1<<17)
129 #define _PSB_IRQ_SGX_FLAG (1<<18)
130 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
131 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
133 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
134 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
135 _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
136 #define PSB_INT_IDENTITY_R 0x20A4
137 #define PSB_INT_MASK_R 0x20A8
138 #define PSB_INT_ENABLE_R 0x20A0
140 #define _PSB_MMU_ER_MASK 0x0001FF00
141 #define _PSB_MMU_ER_HOST (1 << 16)
150 #define GPIO_CLOCK_DIR_MASK (1 << 0)
151 #define GPIO_CLOCK_DIR_IN (0 << 1)
152 #define GPIO_CLOCK_DIR_OUT (1 << 1)
153 #define GPIO_CLOCK_VAL_MASK (1 << 2)
154 #define GPIO_CLOCK_VAL_OUT (1 << 3)
155 #define GPIO_CLOCK_VAL_IN (1 << 4)
156 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
157 #define GPIO_DATA_DIR_MASK (1 << 8)
158 #define GPIO_DATA_DIR_IN (0 << 9)
159 #define GPIO_DATA_DIR_OUT (1 << 9)
160 #define GPIO_DATA_VAL_MASK (1 << 10)
161 #define GPIO_DATA_VAL_OUT (1 << 11)
162 #define GPIO_DATA_VAL_IN (1 << 12)
163 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
165 #define VCLK_DIVISOR_VGA0 0x6000
166 #define VCLK_DIVISOR_VGA1 0x6004
167 #define VCLK_POST_DIV 0x6010
169 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
170 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
171 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
172 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
173 #define PSB_COMM_USER_IRQ (1024 >> 2)
174 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
175 #define PSB_COMM_FW (2048 >> 2)
177 #define PSB_UIRQ_VISTEST 1
178 #define PSB_UIRQ_OOM_REPLY 2
179 #define PSB_UIRQ_FIRE_TA_REPLY 3
180 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
182 #define PSB_2D_SIZE (256*1024*1024)
183 #define PSB_MAX_RELOC_PAGES 1024
185 #define PSB_LOW_REG_OFFS 0x0204
186 #define PSB_HIGH_REG_OFFS 0x0600
188 #define PSB_NUM_VBLANKS 2
191 #define PSB_2D_SIZE (256*1024*1024)
192 #define PSB_MAX_RELOC_PAGES 1024
194 #define PSB_LOW_REG_OFFS 0x0204
195 #define PSB_HIGH_REG_OFFS 0x0600
197 #define PSB_NUM_VBLANKS 2
198 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
199 #define PSB_LID_DELAY (DRM_HZ / 10)
201 #define MDFLD_PNW_A0 0x00
202 #define MDFLD_PNW_B0 0x04
203 #define MDFLD_PNW_C0 0x08
205 #define PSB_PWR_STATE_ON 1
206 #define PSB_PWR_STATE_OFF 2
208 #define PSB_PMPOLICY_NOPM 0
209 #define PSB_PMPOLICY_CLOCKGATING 1
210 #define PSB_PMPOLICY_POWERDOWN 2
212 #define PSB_PMSTATE_POWERUP 0
213 #define PSB_PMSTATE_CLOCKGATED 1
214 #define PSB_PMSTATE_POWERDOWN 2
215 #define PSB_PCIx_MSI_ADDR_LOC 0x94
216 #define PSB_PCIx_MSI_DATA_LOC 0x98
218 struct opregion_header
;
219 struct opregion_acpi
;
220 struct opregion_swsci
;
221 struct opregion_asle
;
223 struct psb_intel_opregion
{
224 struct opregion_header
*header
;
225 struct opregion_acpi
*acpi
;
226 struct opregion_swsci
*swsci
;
227 struct opregion_asle
*asle
;
235 struct drm_psb_uopt
{
236 int pad
; /*keep it here in case we use it in future*/
239 struct drm_psb_private
{
244 void * dsi_configs
[2];
246 struct drm_device
*dev
;
247 struct vm_operations_struct
*ttm_vm_ops
;
249 unsigned long chipset
;
251 struct drm_psb_uopt uopt
;
255 /*GTT Memory manager*/
256 struct psb_gtt_mm
*gtt_mm
;
257 struct page
*scratch_page
;
259 struct psb_mmu_driver
*mmu
;
260 struct psb_mmu_pd
*pf_pd
;
264 uint32_t gatt_free_offset
;
271 uint32_t vdc_irq_mask
;
272 uint32_t pipestat
[PSB_NUM_PIPE
];
273 bool vblanksEnabledForFlips
;
275 spinlock_t irqmask_lock
;
280 struct psb_intel_mode_device mode_dev
;
282 struct drm_crtc
*plane_to_crtc_mapping
[PSB_NUM_PIPE
];
283 struct drm_crtc
*pipe_to_crtc_mapping
[PSB_NUM_PIPE
];
292 struct mutex temp_mem
;
295 *Relocation buffer mapping.
298 spinlock_t reloc_lock
;
299 unsigned int rel_mapped_pages
;
300 wait_queue_head_t rel_mapped_queue
;
305 struct drm_psb_sarea
*sarea_priv
;
316 struct drm_psb_sizes_arg sizes
;
319 u32 video_device_fuse
;
321 /* pci revision id for B0:D2:F0 */
322 uint8_t platform_rev_id
;
327 int backlight_duty_cycle
; /* restore backlight to this value */
328 bool panel_wants_dither
;
329 struct drm_display_mode
*panel_fixed_mode
;
330 struct drm_display_mode
*lfp_lvds_vbt_mode
;
331 struct drm_display_mode
*sdvo_lvds_vbt_mode
;
333 struct bdb_lvds_backlight
*lvds_bl
; /*LVDS backlight info from VBT*/
334 struct psb_intel_i2c_chan
*lvds_i2c_bus
;
336 /* Feature bits from the VBIOS*/
337 unsigned int int_tv_support
:1;
338 unsigned int lvds_dither
:1;
339 unsigned int lvds_vbt
:1;
340 unsigned int int_crt_support
:1;
341 unsigned int lvds_use_ssc
:1;
346 unsigned int core_freq
;
347 uint32_t iLVDS_enable
;
352 /* Moorestown specific */
353 struct mrst_vbt vbt_data
;
354 struct mrst_gct_data gct_data
;
356 /* Moorestown pipe config register value cache */
361 /* Moorestown plane control register value cache */
369 uint32_t saveDSPACNTR
;
370 uint32_t saveDSPBCNTR
;
371 uint32_t savePIPEACONF
;
372 uint32_t savePIPEBCONF
;
373 uint32_t savePIPEASRC
;
374 uint32_t savePIPEBSRC
;
378 uint32_t saveDPLL_A_MD
;
379 uint32_t saveHTOTAL_A
;
380 uint32_t saveHBLANK_A
;
381 uint32_t saveHSYNC_A
;
382 uint32_t saveVTOTAL_A
;
383 uint32_t saveVBLANK_A
;
384 uint32_t saveVSYNC_A
;
385 uint32_t saveDSPASTRIDE
;
386 uint32_t saveDSPASIZE
;
387 uint32_t saveDSPAPOS
;
388 uint32_t saveDSPABASE
;
389 uint32_t saveDSPASURF
;
393 uint32_t saveDPLL_B_MD
;
394 uint32_t saveHTOTAL_B
;
395 uint32_t saveHBLANK_B
;
396 uint32_t saveHSYNC_B
;
397 uint32_t saveVTOTAL_B
;
398 uint32_t saveVBLANK_B
;
399 uint32_t saveVSYNC_B
;
400 uint32_t saveDSPBSTRIDE
;
401 uint32_t saveDSPBSIZE
;
402 uint32_t saveDSPBPOS
;
403 uint32_t saveDSPBBASE
;
404 uint32_t saveDSPBSURF
;
405 uint32_t saveVCLK_DIVISOR_VGA0
;
406 uint32_t saveVCLK_DIVISOR_VGA1
;
407 uint32_t saveVCLK_POST_DIV
;
408 uint32_t saveVGACNTRL
;
416 uint32_t savePP_CONTROL
;
417 uint32_t savePP_CYCLE
;
418 uint32_t savePFIT_CONTROL
;
419 uint32_t savePaletteA
[256];
420 uint32_t savePaletteB
[256];
421 uint32_t saveBLC_PWM_CTL2
;
422 uint32_t saveBLC_PWM_CTL
;
423 uint32_t saveCLOCKGATING
;
425 uint32_t saveDSPATILEOFF
;
426 uint32_t saveDSPBTILEOFF
;
427 uint32_t saveDSPAADDR
;
428 uint32_t saveDSPBADDR
;
429 uint32_t savePFIT_AUTO_RATIOS
;
430 uint32_t savePFIT_PGM_RATIOS
;
431 uint32_t savePP_ON_DELAYS
;
432 uint32_t savePP_OFF_DELAYS
;
433 uint32_t savePP_DIVISOR
;
436 uint32_t saveBCLRPAT_A
;
437 uint32_t saveBCLRPAT_B
;
438 uint32_t saveDSPALINOFF
;
439 uint32_t saveDSPBLINOFF
;
440 uint32_t savePERF_MODE
;
447 uint32_t saveCHICKENBIT
;
448 uint32_t saveDSPACURSOR_CTRL
;
449 uint32_t saveDSPBCURSOR_CTRL
;
450 uint32_t saveDSPACURSOR_BASE
;
451 uint32_t saveDSPBCURSOR_BASE
;
452 uint32_t saveDSPACURSOR_POS
;
453 uint32_t saveDSPBCURSOR_POS
;
454 uint32_t save_palette_a
[256];
455 uint32_t save_palette_b
[256];
456 uint32_t saveOV_OVADD
;
457 uint32_t saveOV_OGAMC0
;
458 uint32_t saveOV_OGAMC1
;
459 uint32_t saveOV_OGAMC2
;
460 uint32_t saveOV_OGAMC3
;
461 uint32_t saveOV_OGAMC4
;
462 uint32_t saveOV_OGAMC5
;
463 uint32_t saveOVC_OVADD
;
464 uint32_t saveOVC_OGAMC0
;
465 uint32_t saveOVC_OGAMC1
;
466 uint32_t saveOVC_OGAMC2
;
467 uint32_t saveOVC_OGAMC3
;
468 uint32_t saveOVC_OGAMC4
;
469 uint32_t saveOVC_OGAMC5
;
472 * extra MDFLD Register state
474 uint32_t saveHDMIPHYMISCCTL
;
475 uint32_t saveHDMIB_CONTROL
;
476 uint32_t saveDSPCCNTR
;
477 uint32_t savePIPECCONF
;
478 uint32_t savePIPECSRC
;
479 uint32_t saveHTOTAL_C
;
480 uint32_t saveHBLANK_C
;
481 uint32_t saveHSYNC_C
;
482 uint32_t saveVTOTAL_C
;
483 uint32_t saveVBLANK_C
;
484 uint32_t saveVSYNC_C
;
485 uint32_t saveDSPCSTRIDE
;
486 uint32_t saveDSPCSIZE
;
487 uint32_t saveDSPCPOS
;
488 uint32_t saveDSPCSURF
;
489 uint32_t saveDSPCLINOFF
;
490 uint32_t saveDSPCTILEOFF
;
491 uint32_t saveDSPCCURSOR_CTRL
;
492 uint32_t saveDSPCCURSOR_BASE
;
493 uint32_t saveDSPCCURSOR_POS
;
494 uint32_t save_palette_c
[256];
495 uint32_t saveOV_OVADD_C
;
496 uint32_t saveOV_OGAMC0_C
;
497 uint32_t saveOV_OGAMC1_C
;
498 uint32_t saveOV_OGAMC2_C
;
499 uint32_t saveOV_OGAMC3_C
;
500 uint32_t saveOV_OGAMC4_C
;
501 uint32_t saveOV_OGAMC5_C
;
504 uint32_t saveDEVICE_READY_REG
;
505 uint32_t saveINTR_EN_REG
;
506 uint32_t saveDSI_FUNC_PRG_REG
;
507 uint32_t saveHS_TX_TIMEOUT_REG
;
508 uint32_t saveLP_RX_TIMEOUT_REG
;
509 uint32_t saveTURN_AROUND_TIMEOUT_REG
;
510 uint32_t saveDEVICE_RESET_REG
;
511 uint32_t saveDPI_RESOLUTION_REG
;
512 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG
;
513 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG
;
514 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG
;
515 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG
;
516 uint32_t saveVERT_SYNC_PAD_COUNT_REG
;
517 uint32_t saveVERT_BACK_PORCH_COUNT_REG
;
518 uint32_t saveVERT_FRONT_PORCH_COUNT_REG
;
519 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG
;
520 uint32_t saveINIT_COUNT_REG
;
521 uint32_t saveMAX_RET_PAK_REG
;
522 uint32_t saveVIDEO_FMT_REG
;
523 uint32_t saveEOT_DISABLE_REG
;
524 uint32_t saveLP_BYTECLK_REG
;
525 uint32_t saveHS_LS_DBI_ENABLE_REG
;
526 uint32_t saveTXCLKESC_REG
;
527 uint32_t saveDPHY_PARAM_REG
;
528 uint32_t saveMIPI_CONTROL_REG
;
531 void (*init_drvIC
)(struct drm_device
*dev
);
532 void (*dsi_prePowerState
)(struct drm_device
*dev
);
533 void (*dsi_postPowerState
)(struct drm_device
*dev
);
535 /* DPST Register Save */
536 uint32_t saveHISTOGRAM_INT_CONTROL_REG
;
537 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG
;
538 uint32_t savePWM_CONTROL_LOGIC
;
549 struct mutex reset_mutex
;
550 struct mutex cmdbuf_mutex
;
551 /*uint32_t ta_mem_pages;
552 struct psb_ta_mem *ta_mem;
553 int force_ta_mem_load;*/
560 struct timer_list lid_timer
;
561 struct psb_intel_opregion opregion
;
575 * Used for modifying backlight from
576 * xrandr -- consider removing and using HAL instead
578 struct drm_property
*backlight_property
;
586 struct psb_file_data
{ /* TODO: Audit this, remove the indirection and set
587 it up properly in open/postclose ACFIXME */
592 struct ttm_object_file
*tfile
;
595 struct psb_mmu_driver
;
597 extern int drm_crtc_probe_output_modes(struct drm_device
*dev
, int, int);
598 extern int drm_pick_crtcs(struct drm_device
*dev
);
600 static inline struct psb_fpriv
*psb_fpriv(struct drm_file
*file_priv
)
602 struct psb_file_data
*pvr_file_priv
603 = (struct psb_file_data
*)file_priv
->driver_priv
;
604 return (struct psb_fpriv
*) pvr_file_priv
->priv
;
607 static inline struct drm_psb_private
*psb_priv(struct drm_device
*dev
)
609 return (struct drm_psb_private
*) dev
->dev_private
;
616 extern struct psb_mmu_driver
*psb_mmu_driver_init(uint8_t __iomem
* registers
,
619 struct drm_psb_private
*dev_priv
);
620 extern void psb_mmu_driver_takedown(struct psb_mmu_driver
*driver
);
621 extern struct psb_mmu_pd
*psb_mmu_get_default_pd(struct psb_mmu_driver
623 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd
*pd
, uint32_t mmu_offset
,
624 uint32_t gtt_start
, uint32_t gtt_pages
);
625 extern struct psb_mmu_pd
*psb_mmu_alloc_pd(struct psb_mmu_driver
*driver
,
628 extern void psb_mmu_free_pagedir(struct psb_mmu_pd
*pd
);
629 extern void psb_mmu_flush(struct psb_mmu_driver
*driver
, int rc_prot
);
630 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd
*pd
,
631 unsigned long address
,
633 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd
*pd
,
635 unsigned long address
,
636 uint32_t num_pages
, int type
);
637 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd
*pd
, uint32_t virtual,
641 *Enable / disable MMU for different requestors.
645 extern void psb_mmu_set_pd_context(struct psb_mmu_pd
*pd
, int hw_context
);
646 extern int psb_mmu_insert_pages(struct psb_mmu_pd
*pd
, struct page
**pages
,
647 unsigned long address
, uint32_t num_pages
,
648 uint32_t desired_tile_stride
,
649 uint32_t hw_tile_stride
, int type
);
650 extern void psb_mmu_remove_pages(struct psb_mmu_pd
*pd
,
651 unsigned long address
, uint32_t num_pages
,
652 uint32_t desired_tile_stride
,
653 uint32_t hw_tile_stride
);
658 extern irqreturn_t
psb_irq_handler(DRM_IRQ_ARGS
);
659 extern int psb_irq_enable_dpst(struct drm_device
*dev
);
660 extern int psb_irq_disable_dpst(struct drm_device
*dev
);
661 extern void psb_irq_preinstall(struct drm_device
*dev
);
662 extern int psb_irq_postinstall(struct drm_device
*dev
);
663 extern void psb_irq_uninstall(struct drm_device
*dev
);
664 extern void psb_irq_preinstall_islands(struct drm_device
*dev
, int hw_islands
);
665 extern int psb_irq_postinstall_islands(struct drm_device
*dev
, int hw_islands
);
666 extern void psb_irq_turn_on_dpst(struct drm_device
*dev
);
667 extern void psb_irq_turn_off_dpst(struct drm_device
*dev
);
669 extern void psb_irq_uninstall_islands(struct drm_device
*dev
, int hw_islands
);
670 extern int psb_vblank_wait2(struct drm_device
*dev
,unsigned int *sequence
);
671 extern int psb_vblank_wait(struct drm_device
*dev
, unsigned int *sequence
);
672 extern int psb_enable_vblank(struct drm_device
*dev
, int crtc
);
673 extern void psb_disable_vblank(struct drm_device
*dev
, int crtc
);
675 psb_enable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
);
678 psb_disable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
);
680 extern u32
psb_get_vblank_counter(struct drm_device
*dev
, int crtc
);
685 extern int psb_intel_opregion_init(struct drm_device
*dev
);
690 extern int psbfb_probed(struct drm_device
*dev
);
691 extern int psbfb_remove(struct drm_device
*dev
,
692 struct drm_framebuffer
*fb
);
693 extern int psbfb_kms_off_ioctl(struct drm_device
*dev
, void *data
,
694 struct drm_file
*file_priv
);
695 extern int psbfb_kms_on_ioctl(struct drm_device
*dev
, void *data
,
696 struct drm_file
*file_priv
);
697 extern void *psbfb_vdc_reg(struct drm_device
* dev
);
702 extern void psbfb_fillrect(struct fb_info
*info
,
703 const struct fb_fillrect
*rect
);
704 extern void psbfb_copyarea(struct fb_info
*info
,
705 const struct fb_copyarea
*region
);
706 extern void psbfb_imageblit(struct fb_info
*info
,
707 const struct fb_image
*image
);
708 extern int psbfb_sync(struct fb_info
*info
);
710 extern void psb_spank(struct drm_psb_private
*dev_priv
);
716 extern void psb_lid_timer_init(struct drm_psb_private
*dev_priv
);
717 extern void psb_lid_timer_takedown(struct drm_psb_private
*dev_priv
);
718 extern void psb_print_pagefault(struct drm_psb_private
*dev_priv
);
721 extern void psb_modeset_init(struct drm_device
*dev
);
722 extern void psb_modeset_cleanup(struct drm_device
*dev
);
723 extern int psb_fbdev_init(struct drm_device
* dev
);
726 int psb_backlight_init(struct drm_device
*dev
);
727 void psb_backlight_exit(void);
728 int psb_set_brightness(struct backlight_device
*bd
);
729 int psb_get_brightness(struct backlight_device
*bd
);
730 struct backlight_device
* psb_get_backlight_device(void);
733 extern const struct drm_crtc_helper_funcs mrst_helper_funcs
;
736 extern void mrst_lvds_init(struct drm_device
*dev
,
737 struct psb_intel_mode_device
*mode_dev
);
739 /* psb_intel_lvds.c */
740 extern void psb_intel_lvds_prepare(struct drm_encoder
*encoder
);
741 extern void psb_intel_lvds_commit(struct drm_encoder
*encoder
);
742 extern const struct drm_connector_helper_funcs
743 psb_intel_lvds_connector_helper_funcs
;
744 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs
;
748 *Debug print bits setting
750 #define PSB_D_GENERAL (1 << 0)
751 #define PSB_D_INIT (1 << 1)
752 #define PSB_D_IRQ (1 << 2)
753 #define PSB_D_ENTRY (1 << 3)
754 /* debug the get H/V BP/FP count */
755 #define PSB_D_HV (1 << 4)
756 #define PSB_D_DBI_BF (1 << 5)
757 #define PSB_D_PM (1 << 6)
758 #define PSB_D_RENDER (1 << 7)
759 #define PSB_D_REG (1 << 8)
760 #define PSB_D_MSVDX (1 << 9)
761 #define PSB_D_TOPAZ (1 << 10)
763 #ifndef DRM_DEBUG_CODE
764 /* To enable debug printout, set drm_psb_debug in psb_drv.c
765 * to any combination of above print flags.
767 /* #define DRM_DEBUG_CODE 2 */
770 extern int drm_psb_debug
;
771 extern int drm_psb_no_fb
;
772 extern int drm_idle_check_interval
;
774 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
775 PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
776 #define PSB_DEBUG_INIT(_fmt, _arg...) \
777 PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
778 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
779 PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
780 #define PSB_DEBUG_ENTRY(_fmt, _arg...) \
781 PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
782 #define PSB_DEBUG_HV(_fmt, _arg...) \
783 PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
784 #define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
785 PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
786 #define PSB_DEBUG_PM(_fmt, _arg...) \
787 PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
788 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
789 PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
790 #define PSB_DEBUG_REG(_fmt, _arg...) \
791 PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
792 #define PSB_DEBUG_MSVDX(_fmt, _arg...) \
793 PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
794 #define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
795 PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
798 #define PSB_DEBUG(_flag, _fmt, _arg...) \
800 if (unlikely((_flag) & drm_psb_debug)) \
802 "[psb:0x%02x:%s] " _fmt , _flag, \
803 __func__ , ##_arg); \
806 #define PSB_DEBUG(_fmt, _arg...) do { } while (0)
812 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
814 static inline u32
MRST_MSG_READ32(uint port
, uint offset
)
816 int mcr
= (0xD0<<24) | (port
<< 16) | (offset
<< 8);
817 uint32_t ret_val
= 0;
818 struct pci_dev
*pci_root
= pci_get_bus_and_slot (0, 0);
819 pci_write_config_dword (pci_root
, 0xD0, mcr
);
820 pci_read_config_dword (pci_root
, 0xD4, &ret_val
);
821 pci_dev_put(pci_root
);
824 static inline void MRST_MSG_WRITE32(uint port
, uint offset
, u32 value
)
826 int mcr
= (0xE0<<24) | (port
<< 16) | (offset
<< 8) | 0xF0;
827 struct pci_dev
*pci_root
= pci_get_bus_and_slot (0, 0);
828 pci_write_config_dword (pci_root
, 0xD4, value
);
829 pci_write_config_dword (pci_root
, 0xD0, mcr
);
830 pci_dev_put(pci_root
);
832 static inline u32
MDFLD_MSG_READ32(uint port
, uint offset
)
834 int mcr
= (0x10<<24) | (port
<< 16) | (offset
<< 8);
835 uint32_t ret_val
= 0;
836 struct pci_dev
*pci_root
= pci_get_bus_and_slot (0, 0);
837 pci_write_config_dword (pci_root
, 0xD0, mcr
);
838 pci_read_config_dword (pci_root
, 0xD4, &ret_val
);
839 pci_dev_put(pci_root
);
842 static inline void MDFLD_MSG_WRITE32(uint port
, uint offset
, u32 value
)
844 int mcr
= (0x11<<24) | (port
<< 16) | (offset
<< 8) | 0xF0;
845 struct pci_dev
*pci_root
= pci_get_bus_and_slot (0, 0);
846 pci_write_config_dword (pci_root
, 0xD4, value
);
847 pci_write_config_dword (pci_root
, 0xD0, mcr
);
848 pci_dev_put(pci_root
);
851 static inline uint32_t REGISTER_READ(struct drm_device
*dev
, uint32_t reg
)
853 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
854 int reg_val
= ioread32(dev_priv
->vdc_reg
+ (reg
));
855 PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg
, reg_val
);
859 #define REG_READ(reg) REGISTER_READ(dev, (reg))
860 static inline void REGISTER_WRITE(struct drm_device
*dev
, uint32_t reg
,
863 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
864 if ((reg
< 0x70084 || reg
>0x70088) && (reg
< 0xa000 || reg
>0xa3ff))
865 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg
, val
);
867 iowrite32((val
), dev_priv
->vdc_reg
+ (reg
));
870 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
872 static inline void REGISTER_WRITE16(struct drm_device
*dev
,
873 uint32_t reg
, uint32_t val
)
875 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
877 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg
, val
);
879 iowrite16((val
), dev_priv
->vdc_reg
+ (reg
));
882 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
884 static inline void REGISTER_WRITE8(struct drm_device
*dev
,
885 uint32_t reg
, uint32_t val
)
887 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
889 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg
, val
);
891 iowrite8((val
), dev_priv
->vdc_reg
+ (reg
));
894 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
896 #define PSB_ALIGN_TO(_val, _align) \
897 (((_val) + ((_align) - 1)) & ~((_align) - 1))
898 #define PSB_WVDC32(_val, _offs) \
899 iowrite32(_val, dev_priv->vdc_reg + (_offs))
900 #define PSB_RVDC32(_offs) \
901 ioread32(dev_priv->vdc_reg + (_offs))
903 /* #define TRAP_SGX_PM_FAULT 1 */
904 #ifdef TRAP_SGX_PM_FAULT
905 #define PSB_RSGX32(_offs) \
907 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
908 printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
909 __FILE__, __LINE__); \
912 ioread32(dev_priv->sgx_reg + (_offs)); \
915 #define PSB_RSGX32(_offs) \
916 ioread32(dev_priv->sgx_reg + (_offs))
918 #define PSB_WSGX32(_val, _offs) \
919 iowrite32(_val, dev_priv->sgx_reg + (_offs))
921 #define MSVDX_REG_DUMP 0
924 #define PSB_WMSVDX32(_val, _offs) \
925 printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
926 iowrite32(_val, dev_priv->msvdx_reg + (_offs))
927 #define PSB_RMSVDX32(_offs) \
928 ioread32(dev_priv->msvdx_reg + (_offs))
932 #define PSB_WMSVDX32(_val, _offs) \
933 iowrite32(_val, dev_priv->msvdx_reg + (_offs))
934 #define PSB_RMSVDX32(_offs) \
935 ioread32(dev_priv->msvdx_reg + (_offs))
939 #define PSB_ALPL(_val, _base) \
940 (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
941 #define PSB_ALPLM(_val, _base) \
942 ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))