2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/timer.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/reboot.h>
33 #include <linux/usb.h>
34 #include <linux/moduleparam.h>
35 #include <linux/dma-mapping.h>
37 #include "../core/hcd.h"
39 #include <asm/byteorder.h>
42 #include <asm/system.h>
43 #include <asm/unaligned.h>
45 /*-------------------------------------------------------------------------*/
48 * EHCI hc_driver implementation ... experimental, incomplete.
49 * Based on the final 1.0 register interface specification.
51 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
52 * First was PCMCIA, like ISA; then CardBus, which is PCI.
53 * Next comes "CardBay", using USB 2.0 signals.
55 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
56 * Special thanks to Intel and VIA for providing host controllers to
57 * test this driver on, and Cypress (including In-System Design) for
58 * providing early devices for those host controllers to talk to!
62 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
63 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
64 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
65 * <sojkam@centrum.cz>, updates by DB).
67 * 2002-11-29 Correct handling for hw async_next register.
68 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
69 * only scheduling is different, no arbitrary limitations.
70 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
71 * clean up HC run state handshaking.
72 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
73 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
74 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
75 * 2002-05-07 Some error path cleanups to report better errors; wmb();
76 * use non-CVS version id; better iso bandwidth claim.
77 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
78 * errors in submit path. Bugfixes to interrupt scheduling/processing.
79 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
80 * more checking to generic hcd framework (db). Make it work with
81 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
82 * 2002-01-14 Minor cleanup; version synch.
83 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
84 * 2002-01-04 Control/Bulk queuing behaves.
86 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
87 * 2001-June Works with usb-storage and NEC EHCI on 2.4
90 #define DRIVER_VERSION "10 Dec 2004"
91 #define DRIVER_AUTHOR "David Brownell"
92 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
94 static const char hcd_name
[] = "ehci_hcd";
97 #undef EHCI_VERBOSE_DEBUG
104 /* magic numbers that can affect system performance */
105 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
106 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
107 #define EHCI_TUNE_RL_TT 0
108 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
109 #define EHCI_TUNE_MULT_TT 1
110 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
112 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
113 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
114 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
115 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
117 /* Initial IRQ latency: faster than hw default */
118 static int log2_irq_thresh
= 0; // 0 to 6
119 module_param (log2_irq_thresh
, int, S_IRUGO
);
120 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
122 /* initial park setting: slower than hw default */
123 static unsigned park
= 0;
124 module_param (park
, uint
, S_IRUGO
);
125 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
127 /* for flakey hardware, ignore overcurrent indicators */
128 static int ignore_oc
= 0;
129 module_param (ignore_oc
, bool, S_IRUGO
);
130 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
132 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
134 /*-------------------------------------------------------------------------*/
137 #include "ehci-dbg.c"
139 /*-------------------------------------------------------------------------*/
142 * handshake - spin reading hc until handshake completes or fails
143 * @ptr: address of hc register to be read
144 * @mask: bits to look at in result of read
145 * @done: value of those bits when handshake succeeds
146 * @usec: timeout in microseconds
148 * Returns negative errno, or zero on success
150 * Success happens when the "mask" bits have the specified value (hardware
151 * handshake done). There are two failure modes: "usec" have passed (major
152 * hardware flakeout), or the register reads as all-ones (hardware removed).
154 * That last failure should_only happen in cases like physical cardbus eject
155 * before driver shutdown. But it also seems to be caused by bugs in cardbus
156 * bridge shutdown: shutting down the bridge before the devices using it.
158 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
159 u32 mask
, u32 done
, int usec
)
164 result
= ehci_readl(ehci
, ptr
);
165 if (result
== ~(u32
)0) /* card removed */
176 /* force HC to halt state from unknown (EHCI spec section 2.3) */
177 static int ehci_halt (struct ehci_hcd
*ehci
)
179 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
181 /* disable any irqs left enabled by previous code */
182 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
184 if ((temp
& STS_HALT
) != 0)
187 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
189 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
190 return handshake (ehci
, &ehci
->regs
->status
,
191 STS_HALT
, STS_HALT
, 16 * 125);
194 /* put TDI/ARC silicon into EHCI mode */
195 static void tdi_reset (struct ehci_hcd
*ehci
)
197 u32 __iomem
*reg_ptr
;
200 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + USBMODE
);
201 tmp
= ehci_readl(ehci
, reg_ptr
);
202 tmp
|= USBMODE_CM_HC
;
203 /* The default byte access to MMR space is LE after
204 * controller reset. Set the required endian mode
205 * for transfer buffers to match the host microprocessor
207 if (ehci_big_endian_mmio(ehci
))
209 ehci_writel(ehci
, tmp
, reg_ptr
);
212 /* reset a non-running (STS_HALT == 1) controller */
213 static int ehci_reset (struct ehci_hcd
*ehci
)
216 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
218 command
|= CMD_RESET
;
219 dbg_cmd (ehci
, "reset", command
);
220 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
221 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
222 ehci
->next_statechange
= jiffies
;
223 retval
= handshake (ehci
, &ehci
->regs
->command
,
224 CMD_RESET
, 0, 250 * 1000);
229 if (ehci_is_TDI(ehci
))
235 /* idle the controller (from running) */
236 static void ehci_quiesce (struct ehci_hcd
*ehci
)
241 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
245 /* wait for any schedule enables/disables to take effect */
246 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
247 temp
&= STS_ASS
| STS_PSS
;
248 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
249 temp
, 16 * 125) != 0) {
250 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
254 /* then disable anything that's still active */
255 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
256 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
257 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
259 /* hardware can take 16 microframes to turn off ... */
260 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
262 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
267 /*-------------------------------------------------------------------------*/
269 static void ehci_work(struct ehci_hcd
*ehci
);
271 #include "ehci-hub.c"
272 #include "ehci-mem.c"
274 #include "ehci-sched.c"
276 /*-------------------------------------------------------------------------*/
278 static void ehci_watchdog (unsigned long param
)
280 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
283 spin_lock_irqsave (&ehci
->lock
, flags
);
285 /* lost IAA irqs wedge things badly; seen with a vt8235 */
287 u32 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
288 if (status
& STS_IAA
) {
289 ehci_vdbg (ehci
, "lost IAA\n");
290 COUNT (ehci
->stats
.lost_iaa
);
291 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
292 ehci
->reclaim_ready
= 1;
296 /* stop async processing after it's idled a bit */
297 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
298 start_unlink_async (ehci
, ehci
->async
);
300 /* ehci could run by timer, without IRQs ... */
303 spin_unlock_irqrestore (&ehci
->lock
, flags
);
306 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
307 * The firmware seems to think that powering off is a wakeup event!
308 * This routine turns off remote wakeup and everything else, on all ports.
310 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
312 int port
= HCS_N_PORTS(ehci
->hcs_params
);
315 ehci_writel(ehci
, PORT_RWC_BITS
,
316 &ehci
->regs
->port_status
[port
]);
319 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
320 * This forcibly disables dma and IRQs, helping kexec and other cases
321 * where the next system software may expect clean state.
324 ehci_shutdown (struct usb_hcd
*hcd
)
326 struct ehci_hcd
*ehci
;
328 ehci
= hcd_to_ehci (hcd
);
329 (void) ehci_halt (ehci
);
330 ehci_turn_off_all_ports(ehci
);
332 /* make BIOS/etc use companion controller during reboot */
333 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
335 /* unblock posted writes */
336 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
339 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
343 if (!HCS_PPC (ehci
->hcs_params
))
346 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
347 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
348 (void) ehci_hub_control(ehci_to_hcd(ehci
),
349 is_on
? SetPortFeature
: ClearPortFeature
,
352 /* Flush those writes */
353 ehci_readl(ehci
, &ehci
->regs
->command
);
357 /*-------------------------------------------------------------------------*/
360 * ehci_work is called from some interrupts, timers, and so on.
361 * it calls driver completion functions, after dropping ehci->lock.
363 static void ehci_work (struct ehci_hcd
*ehci
)
365 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
366 if (ehci
->reclaim_ready
)
367 end_unlink_async (ehci
);
369 /* another CPU may drop ehci->lock during a schedule scan while
370 * it reports urb completions. this flag guards against bogus
371 * attempts at re-entrant schedule scanning.
377 if (ehci
->next_uframe
!= -1)
378 scan_periodic (ehci
);
381 /* the IO watchdog guards against hardware or driver bugs that
382 * misplace IRQs, and should let us run completely without IRQs.
383 * such lossage has been observed on both VT6202 and VT8235.
385 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
386 (ehci
->async
->qh_next
.ptr
!= NULL
||
387 ehci
->periodic_sched
!= 0))
388 timer_action (ehci
, TIMER_IO_WATCHDOG
);
391 static void ehci_stop (struct usb_hcd
*hcd
)
393 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
395 ehci_dbg (ehci
, "stop\n");
397 /* Turn off port power on all root hub ports. */
398 ehci_port_power (ehci
, 0);
400 /* no more interrupts ... */
401 del_timer_sync (&ehci
->watchdog
);
403 spin_lock_irq(&ehci
->lock
);
404 if (HC_IS_RUNNING (hcd
->state
))
408 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
409 spin_unlock_irq(&ehci
->lock
);
411 /* let companion controllers work when we aren't */
412 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
414 remove_companion_file(ehci
);
415 remove_debug_files (ehci
);
417 /* root hub is shut down separately (first, when possible) */
418 spin_lock_irq (&ehci
->lock
);
421 spin_unlock_irq (&ehci
->lock
);
422 ehci_mem_cleanup (ehci
);
425 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
426 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
427 ehci
->stats
.lost_iaa
);
428 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
429 ehci
->stats
.complete
, ehci
->stats
.unlink
);
432 dbg_status (ehci
, "ehci_stop completed",
433 ehci_readl(ehci
, &ehci
->regs
->status
));
436 /* one-time init, only for memory state */
437 static int ehci_init(struct usb_hcd
*hcd
)
439 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
444 spin_lock_init(&ehci
->lock
);
446 init_timer(&ehci
->watchdog
);
447 ehci
->watchdog
.function
= ehci_watchdog
;
448 ehci
->watchdog
.data
= (unsigned long) ehci
;
451 * hw default: 1K periodic list heads, one per frame.
452 * periodic_size can shrink by USBCMD update if hcc_params allows.
454 ehci
->periodic_size
= DEFAULT_I_TDPS
;
455 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
458 /* controllers may cache some of the periodic schedule ... */
459 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
460 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
462 else // N microframes cached
463 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
465 ehci
->reclaim
= NULL
;
466 ehci
->reclaim_ready
= 0;
467 ehci
->next_uframe
= -1;
470 * dedicate a qh for the async ring head, since we couldn't unlink
471 * a 'real' qh without stopping the async schedule [4.8]. use it
472 * as the 'reclamation list head' too.
473 * its dummy is used in hw_alt_next of many tds, to prevent the qh
474 * from automatically advancing to the next td after short reads.
476 ehci
->async
->qh_next
.qh
= NULL
;
477 ehci
->async
->hw_next
= QH_NEXT(ehci
, ehci
->async
->qh_dma
);
478 ehci
->async
->hw_info1
= cpu_to_hc32(ehci
, QH_HEAD
);
479 ehci
->async
->hw_token
= cpu_to_hc32(ehci
, QTD_STS_HALT
);
480 ehci
->async
->hw_qtd_next
= EHCI_LIST_END(ehci
);
481 ehci
->async
->qh_state
= QH_STATE_LINKED
;
482 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
, ehci
->async
->dummy
->qtd_dma
);
484 /* clear interrupt enables, set irq latency */
485 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
487 temp
= 1 << (16 + log2_irq_thresh
);
488 if (HCC_CANPARK(hcc_params
)) {
489 /* HW default park == 3, on hardware that supports it (like
490 * NVidia and ALI silicon), maximizes throughput on the async
491 * schedule by avoiding QH fetches between transfers.
493 * With fast usb storage devices and NForce2, "park" seems to
494 * make problems: throughput reduction (!), data errors...
497 park
= min(park
, (unsigned) 3);
501 ehci_dbg(ehci
, "park %d\n", park
);
503 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
504 /* periodic schedule size can be smaller than default */
506 temp
|= (EHCI_TUNE_FLS
<< 2);
507 switch (EHCI_TUNE_FLS
) {
508 case 0: ehci
->periodic_size
= 1024; break;
509 case 1: ehci
->periodic_size
= 512; break;
510 case 2: ehci
->periodic_size
= 256; break;
514 ehci
->command
= temp
;
519 /* start HC running; it's halted, ehci_init() has been run (once) */
520 static int ehci_run (struct usb_hcd
*hcd
)
522 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
527 hcd
->uses_new_polling
= 1;
530 /* EHCI spec section 4.1 */
531 if ((retval
= ehci_reset(ehci
)) != 0) {
532 ehci_mem_cleanup(ehci
);
535 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
536 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
539 * hcc_params controls whether ehci->regs->segment must (!!!)
540 * be used; it constrains QH/ITD/SITD and QTD locations.
541 * pci_pool consistent memory always uses segment zero.
542 * streaming mappings for I/O buffers, like pci_map_single(),
543 * can return segments above 4GB, if the device allows.
545 * NOTE: the dma mask is visible through dma_supported(), so
546 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
547 * Scsi_Host.highmem_io, and so forth. It's readonly to all
548 * host side drivers though.
550 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
551 if (HCC_64BIT_ADDR(hcc_params
)) {
552 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
554 // this is deeply broken on almost all architectures
555 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
556 ehci_info(ehci
, "enabled 64bit DMA\n");
561 // Philips, Intel, and maybe others need CMD_RUN before the
562 // root hub will detect new devices (why?); NEC doesn't
563 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
564 ehci
->command
|= CMD_RUN
;
565 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
566 dbg_cmd (ehci
, "init", ehci
->command
);
569 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
570 * are explicitly handed to companion controller(s), so no TT is
571 * involved with the root hub. (Except where one is integrated,
572 * and there's no companion controller unless maybe for USB OTG.)
574 hcd
->state
= HC_STATE_RUNNING
;
575 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
576 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
578 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
580 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
581 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
582 temp
>> 8, temp
& 0xff, DRIVER_VERSION
,
583 ignore_oc
? ", overcurrent ignored" : "");
585 ehci_writel(ehci
, INTR_MASK
,
586 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
588 /* GRR this is run-once init(), being done every time the HC starts.
589 * So long as they're part of class devices, we can't do it init()
590 * since the class device isn't created that early.
592 create_debug_files(ehci
);
593 create_companion_file(ehci
);
598 /*-------------------------------------------------------------------------*/
600 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
602 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
603 u32 status
, pcd_status
= 0;
606 spin_lock (&ehci
->lock
);
608 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
610 /* e.g. cardbus physical eject */
611 if (status
== ~(u32
) 0) {
612 ehci_dbg (ehci
, "device removed\n");
617 if (!status
) { /* irq sharing? */
618 spin_unlock(&ehci
->lock
);
622 /* clear (just) interrupts */
623 ehci_writel(ehci
, status
, &ehci
->regs
->status
);
624 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted write */
627 #ifdef EHCI_VERBOSE_DEBUG
628 /* unrequested/ignored: Frame List Rollover */
629 dbg_status (ehci
, "irq", status
);
632 /* INT, ERR, and IAA interrupt rates can be throttled */
634 /* normal [4.15.1.2] or error [4.15.1.1] completion */
635 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
636 if (likely ((status
& STS_ERR
) == 0))
637 COUNT (ehci
->stats
.normal
);
639 COUNT (ehci
->stats
.error
);
643 /* complete the unlinking of some qh [4.15.2.3] */
644 if (status
& STS_IAA
) {
645 COUNT (ehci
->stats
.reclaim
);
646 ehci
->reclaim_ready
= 1;
650 /* remote wakeup [4.3.1] */
651 if (status
& STS_PCD
) {
652 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
655 /* resume root hub? */
656 if (!(ehci_readl(ehci
, &ehci
->regs
->command
) & CMD_RUN
))
657 usb_hcd_resume_root_hub(hcd
);
660 int pstatus
= ehci_readl(ehci
,
661 &ehci
->regs
->port_status
[i
]);
663 if (pstatus
& PORT_OWNER
)
665 if (!(pstatus
& PORT_RESUME
)
666 || ehci
->reset_done
[i
] != 0)
669 /* start 20 msec resume signaling from this port,
670 * and make khubd collect PORT_STAT_C_SUSPEND to
671 * stop that signaling.
673 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
674 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
675 mod_timer(&hcd
->rh_timer
, ehci
->reset_done
[i
]);
679 /* PCI errors [4.15.2.4] */
680 if (unlikely ((status
& STS_FATAL
) != 0)) {
681 /* bogus "fatal" IRQs appear on some chips... why? */
682 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
683 dbg_cmd (ehci
, "fatal", ehci_readl(ehci
,
684 &ehci
->regs
->command
));
685 dbg_status (ehci
, "fatal", status
);
686 if (status
& STS_HALT
) {
687 ehci_err (ehci
, "fatal error\n");
690 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
691 /* generic layer kills/unlinks all urbs, then
692 * uses ehci_stop to clean up the rest
700 spin_unlock (&ehci
->lock
);
701 if (pcd_status
& STS_PCD
)
702 usb_hcd_poll_rh_status(hcd
);
706 /*-------------------------------------------------------------------------*/
709 * non-error returns are a promise to giveback() the urb later
710 * we drop ownership so next owner (or urb unlink) can get it
712 * urb + dev is in hcd.self.controller.urb_list
713 * we're queueing TDs onto software and hardware lists
715 * hcd-specific init for hcpriv hasn't been done yet
717 * NOTE: control, bulk, and interrupt share the same code to append TDs
718 * to a (possibly active) QH, and the same QH scanning code.
720 static int ehci_urb_enqueue (
725 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
726 struct list_head qtd_list
;
728 INIT_LIST_HEAD (&qtd_list
);
730 switch (usb_pipetype (urb
->pipe
)) {
731 // case PIPE_CONTROL:
734 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
736 return submit_async(ehci
, urb
, &qtd_list
, mem_flags
);
739 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
741 return intr_submit(ehci
, urb
, &qtd_list
, mem_flags
);
743 case PIPE_ISOCHRONOUS
:
744 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
745 return itd_submit (ehci
, urb
, mem_flags
);
747 return sitd_submit (ehci
, urb
, mem_flags
);
751 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
753 /* if we need to use IAA and it's busy, defer */
754 if (qh
->qh_state
== QH_STATE_LINKED
756 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
757 struct ehci_qh
*last
;
759 for (last
= ehci
->reclaim
;
761 last
= last
->reclaim
)
763 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
766 /* bypass IAA if the hc can't care */
767 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
768 end_unlink_async (ehci
);
770 /* something else might have unlinked the qh by now */
771 if (qh
->qh_state
== QH_STATE_LINKED
)
772 start_unlink_async (ehci
, qh
);
775 /* remove from hardware lists
776 * completions normally happen asynchronously
779 static int ehci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
781 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
786 spin_lock_irqsave (&ehci
->lock
, flags
);
787 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
791 switch (usb_pipetype (urb
->pipe
)) {
792 // case PIPE_CONTROL:
795 qh
= (struct ehci_qh
*) urb
->hcpriv
;
798 unlink_async (ehci
, qh
);
802 qh
= (struct ehci_qh
*) urb
->hcpriv
;
805 switch (qh
->qh_state
) {
806 case QH_STATE_LINKED
:
807 intr_deschedule (ehci
, qh
);
810 qh_completions (ehci
, qh
);
813 ehci_dbg (ehci
, "bogus qh %p state %d\n",
818 /* reschedule QH iff another request is queued */
819 if (!list_empty (&qh
->qtd_list
)
820 && HC_IS_RUNNING (hcd
->state
)) {
823 status
= qh_schedule (ehci
, qh
);
824 spin_unlock_irqrestore (&ehci
->lock
, flags
);
827 // shouldn't happen often, but ...
828 // FIXME kill those tds' urbs
829 err ("can't reschedule qh %p, err %d",
836 case PIPE_ISOCHRONOUS
:
839 // wait till next completion, do it then.
840 // completion irqs can wait up to 1024 msec,
844 spin_unlock_irqrestore (&ehci
->lock
, flags
);
848 /*-------------------------------------------------------------------------*/
850 // bulk qh holds the data toggle
853 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
855 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
857 struct ehci_qh
*qh
, *tmp
;
859 /* ASSERT: any requests/urbs are being unlinked */
860 /* ASSERT: nobody can be submitting urbs for this any more */
863 spin_lock_irqsave (&ehci
->lock
, flags
);
868 /* endpoints can be iso streams. for now, we don't
869 * accelerate iso completions ... so spin a while.
871 if (qh
->hw_info1
== 0) {
872 ehci_vdbg (ehci
, "iso delay\n");
876 if (!HC_IS_RUNNING (hcd
->state
))
877 qh
->qh_state
= QH_STATE_IDLE
;
878 switch (qh
->qh_state
) {
879 case QH_STATE_LINKED
:
880 for (tmp
= ehci
->async
->qh_next
.qh
;
882 tmp
= tmp
->qh_next
.qh
)
884 /* periodic qh self-unlinks on empty */
887 unlink_async (ehci
, qh
);
889 case QH_STATE_UNLINK
: /* wait for hw to finish? */
891 spin_unlock_irqrestore (&ehci
->lock
, flags
);
892 schedule_timeout_uninterruptible(1);
894 case QH_STATE_IDLE
: /* fully unlinked */
895 if (list_empty (&qh
->qtd_list
)) {
899 /* else FALL THROUGH */
902 /* caller was supposed to have unlinked any requests;
903 * that's not our job. just leak this memory.
905 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
906 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
907 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
912 spin_unlock_irqrestore (&ehci
->lock
, flags
);
916 static int ehci_get_frame (struct usb_hcd
*hcd
)
918 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
919 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
923 /*-------------------------------------------------------------------------*/
925 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
927 MODULE_DESCRIPTION (DRIVER_INFO
);
928 MODULE_AUTHOR (DRIVER_AUTHOR
);
929 MODULE_LICENSE ("GPL");
932 #include "ehci-pci.c"
933 #define PCI_DRIVER ehci_pci_driver
936 #ifdef CONFIG_USB_EHCI_FSL
937 #include "ehci-fsl.c"
938 #define PLATFORM_DRIVER ehci_fsl_driver
941 #ifdef CONFIG_SOC_AU1200
942 #include "ehci-au1xxx.c"
943 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
946 #ifdef CONFIG_PPC_PS3
947 #include "ehci-ps3.c"
948 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
952 #include "ehci-ppc-soc.c"
953 #define PLATFORM_DRIVER ehci_ppc_soc_driver
956 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
957 !defined(PS3_SYSTEM_BUS_DRIVER)
958 #error "missing bus glue for ehci-hcd"
961 static int __init
ehci_hcd_init(void)
965 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
967 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
968 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
970 #ifdef PLATFORM_DRIVER
971 retval
= platform_driver_register(&PLATFORM_DRIVER
);
977 retval
= pci_register_driver(&PCI_DRIVER
);
979 #ifdef PLATFORM_DRIVER
980 platform_driver_unregister(&PLATFORM_DRIVER
);
986 #ifdef PS3_SYSTEM_BUS_DRIVER
987 retval
= ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
989 #ifdef PLATFORM_DRIVER
990 platform_driver_unregister(&PLATFORM_DRIVER
);
993 pci_unregister_driver(&PCI_DRIVER
);
1001 module_init(ehci_hcd_init
);
1003 static void __exit
ehci_hcd_cleanup(void)
1005 #ifdef PLATFORM_DRIVER
1006 platform_driver_unregister(&PLATFORM_DRIVER
);
1009 pci_unregister_driver(&PCI_DRIVER
);
1011 #ifdef PS3_SYSTEM_BUS_DRIVER
1012 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1015 module_exit(ehci_hcd_cleanup
);