2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
50 static int wm8994_drc_base
[] = {
56 static int wm8994_retune_mobile_base
[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1
,
58 WM8994_AIF1_DAC2_EQ_GAINS_1
,
59 WM8994_AIF2_EQ_GAINS_1
,
62 struct wm8994_micdet
{
63 struct snd_soc_jack
*jack
;
68 /* codec private data */
70 struct wm_hubs_data hubs
;
71 enum snd_soc_control_type control_type
;
73 struct snd_soc_codec
*codec
;
78 struct fll_config fll
[2], fll_suspend
[2];
85 /* Platform dependant DRC configuration */
86 const char **drc_texts
;
87 int drc_cfg
[WM8994_NUM_DRC
];
88 struct soc_enum drc_enum
;
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts
;
92 const char **retune_mobile_texts
;
93 int retune_mobile_cfg
[WM8994_NUM_EQ
];
94 struct soc_enum retune_mobile_enum
;
96 /* Platform dependant MBC configuration */
98 const char **mbc_texts
;
99 struct soc_enum mbc_enum
;
101 struct wm8994_micdet micdet
[2];
103 wm8958_micdet_cb jack_cb
;
109 struct wm8994_pdata
*pdata
;
112 static int wm8994_readable(unsigned int reg
)
126 case WM8994_INTERRUPT_STATUS_1
:
127 case WM8994_INTERRUPT_STATUS_2
:
128 case WM8994_INTERRUPT_RAW_STATUS_2
:
134 if (reg
>= WM8994_CACHE_SIZE
)
136 return wm8994_access_masks
[reg
].readable
!= 0;
139 static int wm8994_volatile(unsigned int reg
)
141 if (reg
>= WM8994_CACHE_SIZE
)
145 case WM8994_SOFTWARE_RESET
:
146 case WM8994_CHIP_REVISION
:
147 case WM8994_DC_SERVO_1
:
148 case WM8994_DC_SERVO_READBACK
:
149 case WM8994_RATE_STATUS
:
152 case WM8958_DSP2_EXECCONTROL
:
153 case WM8958_MIC_DETECT_3
:
160 static int wm8994_write(struct snd_soc_codec
*codec
, unsigned int reg
,
165 BUG_ON(reg
> WM8994_MAX_REGISTER
);
167 if (!wm8994_volatile(reg
)) {
168 ret
= snd_soc_cache_write(codec
, reg
, value
);
170 dev_err(codec
->dev
, "Cache write to %x failed: %d\n",
174 return wm8994_reg_write(codec
->control_data
, reg
, value
);
177 static unsigned int wm8994_read(struct snd_soc_codec
*codec
,
183 BUG_ON(reg
> WM8994_MAX_REGISTER
);
185 if (!wm8994_volatile(reg
) && wm8994_readable(reg
) &&
186 reg
< codec
->driver
->reg_cache_size
) {
187 ret
= snd_soc_cache_read(codec
, reg
, &val
);
191 dev_err(codec
->dev
, "Cache read from %x failed: %d\n",
195 return wm8994_reg_read(codec
->control_data
, reg
);
198 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
200 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
210 switch (wm8994
->sysclk
[aif
]) {
211 case WM8994_SYSCLK_MCLK1
:
212 rate
= wm8994
->mclk
[0];
215 case WM8994_SYSCLK_MCLK2
:
217 rate
= wm8994
->mclk
[1];
220 case WM8994_SYSCLK_FLL1
:
222 rate
= wm8994
->fll
[0].out
;
225 case WM8994_SYSCLK_FLL2
:
227 rate
= wm8994
->fll
[1].out
;
234 if (rate
>= 13500000) {
236 reg1
|= WM8994_AIF1CLK_DIV
;
238 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
242 if (rate
&& rate
< 3000000)
243 dev_warn(codec
->dev
, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
246 wm8994
->aifclk
[aif
] = rate
;
248 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
249 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
255 static int configure_clock(struct snd_soc_codec
*codec
)
257 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
260 /* Bring up the AIF clocks first */
261 configure_aif_clock(codec
, 0);
262 configure_aif_clock(codec
, 1);
264 /* Then switch CLK_SYS over to the higher of them; a change
265 * can only happen as a result of a clocking change which can
266 * only be made outside of DAPM so we can safely redo the
270 /* If they're equal it doesn't matter which is used */
271 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1])
274 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
275 new = WM8994_SYSCLK_SRC
;
279 old
= snd_soc_read(codec
, WM8994_CLOCKING_1
) & WM8994_SYSCLK_SRC
;
281 /* If there's no change then we're done. */
285 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
, WM8994_SYSCLK_SRC
, new);
287 snd_soc_dapm_sync(&codec
->dapm
);
292 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
293 struct snd_soc_dapm_widget
*sink
)
295 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
298 /* Check what we're currently using for CLK_SYS */
299 if (reg
& WM8994_SYSCLK_SRC
)
304 return strcmp(source
->name
, clk
) == 0;
307 static const char *sidetone_hpf_text
[] = {
308 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
311 static const struct soc_enum sidetone_hpf
=
312 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
314 static const char *adc_hpf_text
[] = {
315 "HiFi", "Voice 1", "Voice 2", "Voice 3"
318 static const struct soc_enum aif1adc1_hpf
=
319 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
321 static const struct soc_enum aif1adc2_hpf
=
322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
324 static const struct soc_enum aif2adc_hpf
=
325 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
327 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
328 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
329 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
330 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
331 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
333 #define WM8994_DRC_SWITCH(xname, reg, shift) \
334 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
335 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
336 .put = wm8994_put_drc_sw, \
337 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
339 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
340 struct snd_ctl_elem_value
*ucontrol
)
342 struct soc_mixer_control
*mc
=
343 (struct soc_mixer_control
*)kcontrol
->private_value
;
344 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
347 /* Can't enable both ADC and DAC paths simultaneously */
348 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
349 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
350 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
352 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
354 ret
= snd_soc_read(codec
, mc
->reg
);
360 return snd_soc_put_volsw(kcontrol
, ucontrol
);
363 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
365 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
366 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
367 int base
= wm8994_drc_base
[drc
];
368 int cfg
= wm8994
->drc_cfg
[drc
];
371 /* Save any enables; the configuration should clear them. */
372 save
= snd_soc_read(codec
, base
);
373 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
374 WM8994_AIF1ADC1R_DRC_ENA
;
376 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
377 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
378 pdata
->drc_cfgs
[cfg
].regs
[i
]);
380 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
381 WM8994_AIF1ADC1L_DRC_ENA
|
382 WM8994_AIF1ADC1R_DRC_ENA
, save
);
385 /* Icky as hell but saves code duplication */
386 static int wm8994_get_drc(const char *name
)
388 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
390 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
392 if (strcmp(name
, "AIF2DRC Mode") == 0)
397 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
398 struct snd_ctl_elem_value
*ucontrol
)
400 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
401 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
402 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
403 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
404 int value
= ucontrol
->value
.integer
.value
[0];
409 if (value
>= pdata
->num_drc_cfgs
)
412 wm8994
->drc_cfg
[drc
] = value
;
414 wm8994_set_drc(codec
, drc
);
419 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
420 struct snd_ctl_elem_value
*ucontrol
)
422 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
423 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
424 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
426 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
431 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
433 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
434 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
435 int base
= wm8994_retune_mobile_base
[block
];
436 int iface
, best
, best_val
, save
, i
, cfg
;
438 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
453 /* Find the version of the currently selected configuration
454 * with the nearest sample rate. */
455 cfg
= wm8994
->retune_mobile_cfg
[block
];
458 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
459 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
460 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
461 abs(pdata
->retune_mobile_cfgs
[i
].rate
462 - wm8994
->dac_rates
[iface
]) < best_val
) {
464 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
465 - wm8994
->dac_rates
[iface
]);
469 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
471 pdata
->retune_mobile_cfgs
[best
].name
,
472 pdata
->retune_mobile_cfgs
[best
].rate
,
473 wm8994
->dac_rates
[iface
]);
475 /* The EQ will be disabled while reconfiguring it, remember the
476 * current configuration.
478 save
= snd_soc_read(codec
, base
);
479 save
&= WM8994_AIF1DAC1_EQ_ENA
;
481 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
482 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
483 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
485 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
488 /* Icky as hell but saves code duplication */
489 static int wm8994_get_retune_mobile_block(const char *name
)
491 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
493 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
495 if (strcmp(name
, "AIF2 EQ Mode") == 0)
500 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
501 struct snd_ctl_elem_value
*ucontrol
)
503 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
504 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
505 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
506 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
507 int value
= ucontrol
->value
.integer
.value
[0];
512 if (value
>= pdata
->num_retune_mobile_cfgs
)
515 wm8994
->retune_mobile_cfg
[block
] = value
;
517 wm8994_set_retune_mobile(codec
, block
);
522 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
523 struct snd_ctl_elem_value
*ucontrol
)
525 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
526 struct wm8994_priv
*wm8994
=snd_soc_codec_get_drvdata(codec
);
527 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
529 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
534 static const char *aif_chan_src_text
[] = {
538 static const struct soc_enum aif1adcl_src
=
539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
541 static const struct soc_enum aif1adcr_src
=
542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
544 static const struct soc_enum aif2adcl_src
=
545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
547 static const struct soc_enum aif2adcr_src
=
548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
550 static const struct soc_enum aif1dacl_src
=
551 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
553 static const struct soc_enum aif1dacr_src
=
554 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
556 static const struct soc_enum aif2dacl_src
=
557 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
559 static const struct soc_enum aif2dacr_src
=
560 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
562 static const char *osr_text
[] = {
563 "Low Power", "High Performance",
566 static const struct soc_enum dac_osr
=
567 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
569 static const struct soc_enum adc_osr
=
570 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
572 static void wm8958_mbc_apply(struct snd_soc_codec
*codec
, int mbc
, int start
)
574 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
575 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
576 int pwr_reg
= snd_soc_read(codec
, WM8994_POWER_MANAGEMENT_5
);
577 int ena
, reg
, aif
, i
;
581 pwr_reg
&= (WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
);
585 pwr_reg
&= (WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
);
589 pwr_reg
&= (WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
);
597 /* We can only enable the MBC if the AIF is enabled and we
598 * want it to be enabled. */
599 ena
= pwr_reg
&& wm8994
->mbc_ena
[mbc
];
601 reg
= snd_soc_read(codec
, WM8958_DSP2_PROGRAM
);
603 dev_dbg(codec
->dev
, "MBC %d startup: %d, power: %x, DSP: %x\n",
604 mbc
, start
, pwr_reg
, reg
);
607 /* If the DSP is already running then noop */
608 if (reg
& WM8958_DSP2_ENA
)
611 /* Switch the clock over to the appropriate AIF */
612 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
613 WM8958_DSP2CLK_SRC
| WM8958_DSP2CLK_ENA
,
614 aif
<< WM8958_DSP2CLK_SRC_SHIFT
|
617 snd_soc_update_bits(codec
, WM8958_DSP2_PROGRAM
,
618 WM8958_DSP2_ENA
, WM8958_DSP2_ENA
);
620 /* If we've got user supplied MBC settings use them */
621 if (pdata
&& pdata
->num_mbc_cfgs
) {
622 struct wm8958_mbc_cfg
*cfg
623 = &pdata
->mbc_cfgs
[wm8994
->mbc_cfg
];
625 for (i
= 0; i
< ARRAY_SIZE(cfg
->coeff_regs
); i
++)
626 snd_soc_write(codec
, i
+ WM8958_MBC_BAND_1_K_1
,
629 for (i
= 0; i
< ARRAY_SIZE(cfg
->cutoff_regs
); i
++)
631 i
+ WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1
,
632 cfg
->cutoff_regs
[i
]);
636 snd_soc_write(codec
, WM8958_DSP2_EXECCONTROL
,
640 snd_soc_update_bits(codec
, WM8958_DSP2_CONFIG
,
641 WM8958_MBC_ENA
| WM8958_MBC_SEL_MASK
,
642 mbc
<< WM8958_MBC_SEL_SHIFT
|
645 /* If the DSP is already stopped then noop */
646 if (!(reg
& WM8958_DSP2_ENA
))
649 snd_soc_update_bits(codec
, WM8958_DSP2_CONFIG
,
651 snd_soc_update_bits(codec
, WM8958_DSP2_PROGRAM
,
653 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
654 WM8958_DSP2CLK_ENA
, 0);
658 static int wm8958_aif_ev(struct snd_soc_dapm_widget
*w
,
659 struct snd_kcontrol
*kcontrol
, int event
)
661 struct snd_soc_codec
*codec
= w
->codec
;
683 case SND_SOC_DAPM_POST_PMU
:
684 wm8958_mbc_apply(codec
, mbc
, 1);
686 case SND_SOC_DAPM_POST_PMD
:
687 wm8958_mbc_apply(codec
, mbc
, 0);
694 static int wm8958_put_mbc_enum(struct snd_kcontrol
*kcontrol
,
695 struct snd_ctl_elem_value
*ucontrol
)
697 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
698 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
699 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
700 int value
= ucontrol
->value
.integer
.value
[0];
703 /* Don't allow on the fly reconfiguration */
704 reg
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
705 if (reg
< 0 || reg
& WM8958_DSP2CLK_ENA
)
708 if (value
>= pdata
->num_mbc_cfgs
)
711 wm8994
->mbc_cfg
= value
;
716 static int wm8958_get_mbc_enum(struct snd_kcontrol
*kcontrol
,
717 struct snd_ctl_elem_value
*ucontrol
)
719 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
720 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
722 ucontrol
->value
.enumerated
.item
[0] = wm8994
->mbc_cfg
;
727 static int wm8958_mbc_info(struct snd_kcontrol
*kcontrol
,
728 struct snd_ctl_elem_info
*uinfo
)
730 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
732 uinfo
->value
.integer
.min
= 0;
733 uinfo
->value
.integer
.max
= 1;
737 static int wm8958_mbc_get(struct snd_kcontrol
*kcontrol
,
738 struct snd_ctl_elem_value
*ucontrol
)
740 int mbc
= kcontrol
->private_value
;
741 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
742 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
744 ucontrol
->value
.integer
.value
[0] = wm8994
->mbc_ena
[mbc
];
749 static int wm8958_mbc_put(struct snd_kcontrol
*kcontrol
,
750 struct snd_ctl_elem_value
*ucontrol
)
752 int mbc
= kcontrol
->private_value
;
754 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
755 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
757 if (ucontrol
->value
.integer
.value
[0] > 1)
760 for (i
= 0; i
< ARRAY_SIZE(wm8994
->mbc_ena
); i
++) {
761 if (mbc
!= i
&& wm8994
->mbc_ena
[i
]) {
762 dev_dbg(codec
->dev
, "MBC %d active already\n", mbc
);
767 wm8994
->mbc_ena
[mbc
] = ucontrol
->value
.integer
.value
[0];
769 wm8958_mbc_apply(codec
, mbc
, wm8994
->mbc_ena
[mbc
]);
774 #define WM8958_MBC_SWITCH(xname, xval) {\
775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
776 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
777 .info = wm8958_mbc_info, \
778 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
779 .private_value = xval }
781 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
782 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
783 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
784 1, 119, 0, digital_tlv
),
785 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
786 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
787 1, 119, 0, digital_tlv
),
788 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
789 WM8994_AIF2_ADC_RIGHT_VOLUME
,
790 1, 119, 0, digital_tlv
),
792 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
793 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
794 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
795 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
797 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
798 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
799 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
800 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
802 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
803 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
804 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
805 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
806 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
807 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
809 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
810 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
812 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
813 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
814 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
816 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
817 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
818 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
820 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
821 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
822 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
824 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
825 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
826 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
828 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
830 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
832 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
834 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
836 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
837 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
839 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
840 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
842 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
843 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
845 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
846 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
848 SOC_ENUM("ADC OSR", adc_osr
),
849 SOC_ENUM("DAC OSR", dac_osr
),
851 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
852 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
853 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
854 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
856 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
857 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
858 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
859 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
861 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
862 6, 1, 1, wm_hubs_spkmix_tlv
),
863 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
864 2, 1, 1, wm_hubs_spkmix_tlv
),
866 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
867 6, 1, 1, wm_hubs_spkmix_tlv
),
868 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
869 2, 1, 1, wm_hubs_spkmix_tlv
),
871 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
872 10, 15, 0, wm8994_3d_tlv
),
873 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
875 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
876 10, 15, 0, wm8994_3d_tlv
),
877 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
879 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
880 10, 15, 0, wm8994_3d_tlv
),
881 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
885 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
886 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
888 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
890 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
892 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
894 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
897 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
899 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
901 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
903 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
905 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
908 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
910 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
912 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
914 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
916 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
920 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
921 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
922 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
923 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
924 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
927 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
928 struct snd_kcontrol
*kcontrol
, int event
)
930 struct snd_soc_codec
*codec
= w
->codec
;
933 case SND_SOC_DAPM_PRE_PMU
:
934 return configure_clock(codec
);
936 case SND_SOC_DAPM_POST_PMD
:
937 configure_clock(codec
);
944 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
946 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
948 int source
= 0; /* GCC flow analysis can't track enable */
951 /* Only support direct DAC->headphone paths */
952 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
953 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
954 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
958 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
959 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
960 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
964 /* We also need the same setting for L/R and only one path */
965 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
967 case WM8994_AIF2DACL_TO_DAC1L
:
968 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
969 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
971 case WM8994_AIF1DAC2L_TO_DAC1L
:
972 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
973 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
975 case WM8994_AIF1DAC1L_TO_DAC1L
:
976 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
977 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
980 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
985 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
987 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
992 dev_dbg(codec
->dev
, "Class W enabled\n");
993 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
995 WM8994_CP_DYN_SRC_SEL_MASK
,
996 source
| WM8994_CP_DYN_PWR
);
997 wm8994
->hubs
.class_w
= true;
1000 dev_dbg(codec
->dev
, "Class W disabled\n");
1001 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
1002 WM8994_CP_DYN_PWR
, 0);
1003 wm8994
->hubs
.class_w
= false;
1007 static const char *hp_mux_text
[] = {
1012 #define WM8994_HP_ENUM(xname, xenum) \
1013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1014 .info = snd_soc_info_enum_double, \
1015 .get = snd_soc_dapm_get_enum_double, \
1016 .put = wm8994_put_hp_enum, \
1017 .private_value = (unsigned long)&xenum }
1019 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1020 struct snd_ctl_elem_value
*ucontrol
)
1022 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
1023 struct snd_soc_codec
*codec
= w
->codec
;
1026 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1028 wm8994_update_class_w(codec
);
1033 static const struct soc_enum hpl_enum
=
1034 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1036 static const struct snd_kcontrol_new hpl_mux
=
1037 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1039 static const struct soc_enum hpr_enum
=
1040 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1042 static const struct snd_kcontrol_new hpr_mux
=
1043 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1045 static const char *adc_mux_text
[] = {
1050 static const struct soc_enum adc_enum
=
1051 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1053 static const struct snd_kcontrol_new adcl_mux
=
1054 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1056 static const struct snd_kcontrol_new adcr_mux
=
1057 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1059 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1060 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1061 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1062 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1063 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1064 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1067 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1068 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1069 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1070 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1071 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1072 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1075 /* Debugging; dump chip status after DAPM transitions */
1076 static int post_ev(struct snd_soc_dapm_widget
*w
,
1077 struct snd_kcontrol
*kcontrol
, int event
)
1079 struct snd_soc_codec
*codec
= w
->codec
;
1080 dev_dbg(codec
->dev
, "SRC status: %x\n",
1082 WM8994_RATE_STATUS
));
1086 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1087 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1089 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1093 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1094 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1096 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1100 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1101 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1103 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1107 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1108 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1110 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1114 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1115 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1117 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1119 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1121 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1123 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1127 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1128 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1130 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1132 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1134 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1136 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1140 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1141 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1142 .info = snd_soc_info_volsw, \
1143 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1144 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1146 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1147 struct snd_ctl_elem_value
*ucontrol
)
1149 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
1150 struct snd_soc_codec
*codec
= w
->codec
;
1153 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1155 wm8994_update_class_w(codec
);
1160 static const struct snd_kcontrol_new dac1l_mix
[] = {
1161 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1163 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1165 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1167 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1169 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1173 static const struct snd_kcontrol_new dac1r_mix
[] = {
1174 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1176 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1178 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1180 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1182 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1186 static const char *sidetone_text
[] = {
1187 "ADC/DMIC1", "DMIC2",
1190 static const struct soc_enum sidetone1_enum
=
1191 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1193 static const struct snd_kcontrol_new sidetone1_mux
=
1194 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1196 static const struct soc_enum sidetone2_enum
=
1197 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1199 static const struct snd_kcontrol_new sidetone2_mux
=
1200 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1202 static const char *aif1dac_text
[] = {
1203 "AIF1DACDAT", "AIF3DACDAT",
1206 static const struct soc_enum aif1dac_enum
=
1207 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1209 static const struct snd_kcontrol_new aif1dac_mux
=
1210 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1212 static const char *aif2dac_text
[] = {
1213 "AIF2DACDAT", "AIF3DACDAT",
1216 static const struct soc_enum aif2dac_enum
=
1217 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1219 static const struct snd_kcontrol_new aif2dac_mux
=
1220 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1222 static const char *aif2adc_text
[] = {
1223 "AIF2ADCDAT", "AIF3DACDAT",
1226 static const struct soc_enum aif2adc_enum
=
1227 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1229 static const struct snd_kcontrol_new aif2adc_mux
=
1230 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1232 static const char *aif3adc_text
[] = {
1233 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1236 static const struct soc_enum wm8994_aif3adc_enum
=
1237 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1239 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1240 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1242 static const struct soc_enum wm8958_aif3adc_enum
=
1243 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1245 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1246 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1248 static const char *mono_pcm_out_text
[] = {
1249 "None", "AIF2ADCL", "AIF2ADCR",
1252 static const struct soc_enum mono_pcm_out_enum
=
1253 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1255 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1256 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1258 static const char *aif2dac_src_text
[] = {
1262 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1263 static const struct soc_enum aif2dacl_src_enum
=
1264 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1266 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1267 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1269 static const struct soc_enum aif2dacr_src_enum
=
1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1272 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1273 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1275 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1276 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1277 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1278 SND_SOC_DAPM_INPUT("Clock"),
1280 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1281 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1283 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1284 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1285 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1287 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1288 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0),
1290 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1291 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1292 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1293 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1294 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1295 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1296 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1297 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1298 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1299 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1301 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1302 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1303 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1304 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1305 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1306 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1307 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1308 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1309 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1310 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1312 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1313 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1314 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1315 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1317 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1318 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1319 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1320 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1322 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1323 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1324 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1325 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1327 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1328 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1330 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1331 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1332 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1333 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1335 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1336 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1337 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1338 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1339 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1340 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1341 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1342 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1343 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1344 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1346 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1347 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1348 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1349 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1351 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1352 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1353 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1355 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1356 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1358 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1360 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1361 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1362 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1363 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1365 /* Power is done with the muxes since the ADC power also controls the
1366 * downsampling chain, the chip will automatically manage the analogue
1367 * specific portions.
1369 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1370 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1372 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1373 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1375 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1376 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1377 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1378 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1380 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1381 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1383 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1384 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1385 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1386 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1388 SND_SOC_DAPM_POST("Debug log", post_ev
),
1391 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1392 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1395 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1396 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1397 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1398 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1399 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1402 static const struct snd_soc_dapm_route intercon
[] = {
1403 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1404 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1406 { "DSP1CLK", NULL
, "CLK_SYS" },
1407 { "DSP2CLK", NULL
, "CLK_SYS" },
1408 { "DSPINTCLK", NULL
, "CLK_SYS" },
1410 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1411 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1412 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1413 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1414 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1416 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1417 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1418 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1419 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1420 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1422 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1423 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1424 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1425 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1426 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1428 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1429 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1430 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1431 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1432 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1434 { "AIF2ADCL", NULL
, "AIF2CLK" },
1435 { "AIF2ADCL", NULL
, "DSP2CLK" },
1436 { "AIF2ADCR", NULL
, "AIF2CLK" },
1437 { "AIF2ADCR", NULL
, "DSP2CLK" },
1438 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1440 { "AIF2DACL", NULL
, "AIF2CLK" },
1441 { "AIF2DACL", NULL
, "DSP2CLK" },
1442 { "AIF2DACR", NULL
, "AIF2CLK" },
1443 { "AIF2DACR", NULL
, "DSP2CLK" },
1444 { "AIF2DACR", NULL
, "DSPINTCLK" },
1446 { "DMIC1L", NULL
, "DMIC1DAT" },
1447 { "DMIC1L", NULL
, "CLK_SYS" },
1448 { "DMIC1R", NULL
, "DMIC1DAT" },
1449 { "DMIC1R", NULL
, "CLK_SYS" },
1450 { "DMIC2L", NULL
, "DMIC2DAT" },
1451 { "DMIC2L", NULL
, "CLK_SYS" },
1452 { "DMIC2R", NULL
, "DMIC2DAT" },
1453 { "DMIC2R", NULL
, "CLK_SYS" },
1455 { "ADCL", NULL
, "AIF1CLK" },
1456 { "ADCL", NULL
, "DSP1CLK" },
1457 { "ADCL", NULL
, "DSPINTCLK" },
1459 { "ADCR", NULL
, "AIF1CLK" },
1460 { "ADCR", NULL
, "DSP1CLK" },
1461 { "ADCR", NULL
, "DSPINTCLK" },
1463 { "ADCL Mux", "ADC", "ADCL" },
1464 { "ADCL Mux", "DMIC", "DMIC1L" },
1465 { "ADCR Mux", "ADC", "ADCR" },
1466 { "ADCR Mux", "DMIC", "DMIC1R" },
1468 { "DAC1L", NULL
, "AIF1CLK" },
1469 { "DAC1L", NULL
, "DSP1CLK" },
1470 { "DAC1L", NULL
, "DSPINTCLK" },
1472 { "DAC1R", NULL
, "AIF1CLK" },
1473 { "DAC1R", NULL
, "DSP1CLK" },
1474 { "DAC1R", NULL
, "DSPINTCLK" },
1476 { "DAC2L", NULL
, "AIF2CLK" },
1477 { "DAC2L", NULL
, "DSP2CLK" },
1478 { "DAC2L", NULL
, "DSPINTCLK" },
1480 { "DAC2R", NULL
, "AIF2DACR" },
1481 { "DAC2R", NULL
, "AIF2CLK" },
1482 { "DAC2R", NULL
, "DSP2CLK" },
1483 { "DAC2R", NULL
, "DSPINTCLK" },
1485 { "TOCLK", NULL
, "CLK_SYS" },
1488 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1489 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1490 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1492 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1493 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1494 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1496 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1497 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1498 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1500 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1501 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1502 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1504 /* Pin level routing for AIF3 */
1505 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1506 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1507 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1508 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1510 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1511 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1512 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1513 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1514 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1515 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1516 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1519 { "DAC1L", NULL
, "DAC1L Mixer" },
1520 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1521 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1522 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1523 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1524 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1526 { "DAC1R", NULL
, "DAC1R Mixer" },
1527 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1528 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1529 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1530 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1531 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1533 /* DAC2/AIF2 outputs */
1534 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1535 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1536 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1537 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1538 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1539 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1540 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1542 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1543 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1544 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1545 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1546 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1547 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1548 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1550 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1551 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1552 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1553 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1555 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1558 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1559 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1560 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1561 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1562 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1563 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1564 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1565 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1568 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1569 { "Left Sidetone", "DMIC2", "DMIC2L" },
1570 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1571 { "Right Sidetone", "DMIC2", "DMIC2R" },
1574 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1575 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1577 { "SPKL", "DAC1 Switch", "DAC1L" },
1578 { "SPKL", "DAC2 Switch", "DAC2L" },
1580 { "SPKR", "DAC1 Switch", "DAC1R" },
1581 { "SPKR", "DAC2 Switch", "DAC2R" },
1583 { "Left Headphone Mux", "DAC", "DAC1L" },
1584 { "Right Headphone Mux", "DAC", "DAC1R" },
1587 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1588 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1589 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1590 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1591 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1594 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1595 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1596 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1599 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1600 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1601 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1603 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1604 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1605 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1606 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1608 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1609 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1611 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1614 /* The size in bits of the FLL divide multiplied by 10
1615 * to allow rounding later */
1616 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1626 static int wm8994_get_fll_config(struct fll_div
*fll
,
1627 int freq_in
, int freq_out
)
1630 unsigned int K
, Ndiv
, Nmod
;
1632 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1634 /* Scale the input frequency down to <= 13.5MHz */
1635 fll
->clk_ref_div
= 0;
1636 while (freq_in
> 13500000) {
1640 if (fll
->clk_ref_div
> 3)
1643 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1645 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1647 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1649 if (fll
->outdiv
> 63)
1652 freq_out
*= fll
->outdiv
+ 1;
1653 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1655 if (freq_in
> 1000000) {
1656 fll
->fll_fratio
= 0;
1657 } else if (freq_in
> 256000) {
1658 fll
->fll_fratio
= 1;
1660 } else if (freq_in
> 128000) {
1661 fll
->fll_fratio
= 2;
1663 } else if (freq_in
> 64000) {
1664 fll
->fll_fratio
= 3;
1667 fll
->fll_fratio
= 4;
1670 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1672 /* Now, calculate N.K */
1673 Ndiv
= freq_out
/ freq_in
;
1676 Nmod
= freq_out
% freq_in
;
1677 pr_debug("Nmod=%d\n", Nmod
);
1679 /* Calculate fractional part - scale up so we can round. */
1680 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1682 do_div(Kpart
, freq_in
);
1684 K
= Kpart
& 0xFFFFFFFF;
1689 /* Move down to proper range now rounding is done */
1692 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1697 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1698 unsigned int freq_in
, unsigned int freq_out
)
1700 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1701 int reg_offset
, ret
;
1703 u16 reg
, aif1
, aif2
;
1705 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1706 & WM8994_AIF1CLK_ENA
;
1708 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1709 & WM8994_AIF2CLK_ENA
;
1726 /* Allow no source specification when stopping */
1729 src
= wm8994
->fll
[id
].src
;
1731 case WM8994_FLL_SRC_MCLK1
:
1732 case WM8994_FLL_SRC_MCLK2
:
1733 case WM8994_FLL_SRC_LRCLK
:
1734 case WM8994_FLL_SRC_BCLK
:
1740 /* Are we changing anything? */
1741 if (wm8994
->fll
[id
].src
== src
&&
1742 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1745 /* If we're stopping the FLL redo the old config - no
1746 * registers will actually be written but we avoid GCC flow
1747 * analysis bugs spewing warnings.
1750 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1752 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1753 wm8994
->fll
[id
].out
);
1757 /* Gate the AIF clocks while we reclock */
1758 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1759 WM8994_AIF1CLK_ENA
, 0);
1760 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1761 WM8994_AIF2CLK_ENA
, 0);
1763 /* We always need to disable the FLL while reconfiguring */
1764 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1765 WM8994_FLL1_ENA
, 0);
1767 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1768 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1769 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1770 WM8994_FLL1_OUTDIV_MASK
|
1771 WM8994_FLL1_FRATIO_MASK
, reg
);
1773 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1775 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1777 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1779 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1780 WM8994_FLL1_REFCLK_DIV_MASK
|
1781 WM8994_FLL1_REFCLK_SRC_MASK
,
1782 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1785 /* Enable (with fractional mode if required) */
1788 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1790 reg
= WM8994_FLL1_ENA
;
1791 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1792 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1796 wm8994
->fll
[id
].in
= freq_in
;
1797 wm8994
->fll
[id
].out
= freq_out
;
1798 wm8994
->fll
[id
].src
= src
;
1800 /* Enable any gated AIF clocks */
1801 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1802 WM8994_AIF1CLK_ENA
, aif1
);
1803 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1804 WM8994_AIF2CLK_ENA
, aif2
);
1806 configure_clock(codec
);
1812 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1814 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1815 unsigned int freq_in
, unsigned int freq_out
)
1817 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
1820 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
1821 int clk_id
, unsigned int freq
, int dir
)
1823 struct snd_soc_codec
*codec
= dai
->codec
;
1824 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1833 /* AIF3 shares clocking with AIF1/2 */
1838 case WM8994_SYSCLK_MCLK1
:
1839 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
1840 wm8994
->mclk
[0] = freq
;
1841 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
1845 case WM8994_SYSCLK_MCLK2
:
1846 /* TODO: Set GPIO AF */
1847 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
1848 wm8994
->mclk
[1] = freq
;
1849 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
1853 case WM8994_SYSCLK_FLL1
:
1854 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
1855 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
1858 case WM8994_SYSCLK_FLL2
:
1859 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
1860 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
1863 case WM8994_SYSCLK_OPCLK
:
1864 /* Special case - a division (times 10) is given and
1865 * no effect on main clocking.
1868 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
1869 if (opclk_divs
[i
] == freq
)
1871 if (i
== ARRAY_SIZE(opclk_divs
))
1873 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
1874 WM8994_OPCLK_DIV_MASK
, i
);
1875 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1876 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
1878 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1879 WM8994_OPCLK_ENA
, 0);
1886 configure_clock(codec
);
1891 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
1892 enum snd_soc_bias_level level
)
1894 struct wm8994
*control
= codec
->control_data
;
1895 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1898 case SND_SOC_BIAS_ON
:
1901 case SND_SOC_BIAS_PREPARE
:
1903 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1904 WM8994_VMID_SEL_MASK
, 0x2);
1907 case SND_SOC_BIAS_STANDBY
:
1908 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1909 pm_runtime_get_sync(codec
->dev
);
1911 switch (control
->type
) {
1913 if (wm8994
->revision
< 4) {
1914 /* Tweak DC servo and DSP
1915 * configuration for improved
1917 snd_soc_write(codec
, 0x102, 0x3);
1918 snd_soc_write(codec
, 0x56, 0x3);
1919 snd_soc_write(codec
, 0x817, 0);
1920 snd_soc_write(codec
, 0x102, 0);
1925 if (wm8994
->revision
== 0) {
1926 /* Optimise performance for rev A */
1927 snd_soc_write(codec
, 0x102, 0x3);
1928 snd_soc_write(codec
, 0xcb, 0x81);
1929 snd_soc_write(codec
, 0x817, 0);
1930 snd_soc_write(codec
, 0x102, 0);
1932 snd_soc_update_bits(codec
,
1933 WM8958_CHARGE_PUMP_2
,
1940 /* Discharge LINEOUT1 & 2 */
1941 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1942 WM8994_LINEOUT1_DISCH
|
1943 WM8994_LINEOUT2_DISCH
,
1944 WM8994_LINEOUT1_DISCH
|
1945 WM8994_LINEOUT2_DISCH
);
1947 /* Startup bias, VMID ramp & buffer */
1948 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1949 WM8994_STARTUP_BIAS_ENA
|
1950 WM8994_VMID_BUF_ENA
|
1951 WM8994_VMID_RAMP_MASK
,
1952 WM8994_STARTUP_BIAS_ENA
|
1953 WM8994_VMID_BUF_ENA
|
1954 (0x11 << WM8994_VMID_RAMP_SHIFT
));
1956 /* Main bias enable, VMID=2x40k */
1957 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1959 WM8994_VMID_SEL_MASK
,
1960 WM8994_BIAS_ENA
| 0x2);
1966 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1967 WM8994_VMID_SEL_MASK
, 0x4);
1971 case SND_SOC_BIAS_OFF
:
1972 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
) {
1973 /* Switch over to startup biases */
1974 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1976 WM8994_STARTUP_BIAS_ENA
|
1977 WM8994_VMID_BUF_ENA
|
1978 WM8994_VMID_RAMP_MASK
,
1980 WM8994_STARTUP_BIAS_ENA
|
1981 WM8994_VMID_BUF_ENA
|
1982 (1 << WM8994_VMID_RAMP_SHIFT
));
1984 /* Disable main biases */
1985 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1987 WM8994_VMID_SEL_MASK
, 0);
1989 /* Discharge line */
1990 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1991 WM8994_LINEOUT1_DISCH
|
1992 WM8994_LINEOUT2_DISCH
,
1993 WM8994_LINEOUT1_DISCH
|
1994 WM8994_LINEOUT2_DISCH
);
1998 /* Switch off startup biases */
1999 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
2001 WM8994_STARTUP_BIAS_ENA
|
2002 WM8994_VMID_BUF_ENA
|
2003 WM8994_VMID_RAMP_MASK
, 0);
2005 pm_runtime_put(codec
->dev
);
2009 codec
->dapm
.bias_level
= level
;
2013 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2015 struct snd_soc_codec
*codec
= dai
->codec
;
2016 struct wm8994
*control
= codec
->control_data
;
2024 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2025 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2028 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2029 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2035 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2036 case SND_SOC_DAIFMT_CBS_CFS
:
2038 case SND_SOC_DAIFMT_CBM_CFM
:
2039 ms
= WM8994_AIF1_MSTR
;
2045 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2046 case SND_SOC_DAIFMT_DSP_B
:
2047 aif1
|= WM8994_AIF1_LRCLK_INV
;
2048 case SND_SOC_DAIFMT_DSP_A
:
2051 case SND_SOC_DAIFMT_I2S
:
2054 case SND_SOC_DAIFMT_RIGHT_J
:
2056 case SND_SOC_DAIFMT_LEFT_J
:
2063 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2064 case SND_SOC_DAIFMT_DSP_A
:
2065 case SND_SOC_DAIFMT_DSP_B
:
2066 /* frame inversion not valid for DSP modes */
2067 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2068 case SND_SOC_DAIFMT_NB_NF
:
2070 case SND_SOC_DAIFMT_IB_NF
:
2071 aif1
|= WM8994_AIF1_BCLK_INV
;
2078 case SND_SOC_DAIFMT_I2S
:
2079 case SND_SOC_DAIFMT_RIGHT_J
:
2080 case SND_SOC_DAIFMT_LEFT_J
:
2081 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2082 case SND_SOC_DAIFMT_NB_NF
:
2084 case SND_SOC_DAIFMT_IB_IF
:
2085 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2087 case SND_SOC_DAIFMT_IB_NF
:
2088 aif1
|= WM8994_AIF1_BCLK_INV
;
2090 case SND_SOC_DAIFMT_NB_IF
:
2091 aif1
|= WM8994_AIF1_LRCLK_INV
;
2101 /* The AIF2 format configuration needs to be mirrored to AIF3
2102 * on WM8958 if it's in use so just do it all the time. */
2103 if (control
->type
== WM8958
&& dai
->id
== 2)
2104 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2105 WM8994_AIF1_LRCLK_INV
|
2106 WM8958_AIF3_FMT_MASK
, aif1
);
2108 snd_soc_update_bits(codec
, aif1_reg
,
2109 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2110 WM8994_AIF1_FMT_MASK
,
2112 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2134 static int fs_ratios
[] = {
2135 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2138 static int bclk_divs
[] = {
2139 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2140 640, 880, 960, 1280, 1760, 1920
2143 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2144 struct snd_pcm_hw_params
*params
,
2145 struct snd_soc_dai
*dai
)
2147 struct snd_soc_codec
*codec
= dai
->codec
;
2148 struct wm8994
*control
= codec
->control_data
;
2149 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2160 int id
= dai
->id
- 1;
2162 int i
, cur_val
, best_val
, bclk_rate
, best
;
2166 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2167 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2168 bclk_reg
= WM8994_AIF1_BCLK
;
2169 rate_reg
= WM8994_AIF1_RATE
;
2170 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2171 wm8994
->lrclk_shared
[0]) {
2172 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2174 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2175 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2179 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2180 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2181 bclk_reg
= WM8994_AIF2_BCLK
;
2182 rate_reg
= WM8994_AIF2_RATE
;
2183 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2184 wm8994
->lrclk_shared
[1]) {
2185 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2187 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2188 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2192 switch (control
->type
) {
2194 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2203 bclk_rate
= params_rate(params
) * 2;
2204 switch (params_format(params
)) {
2205 case SNDRV_PCM_FORMAT_S16_LE
:
2208 case SNDRV_PCM_FORMAT_S20_3LE
:
2212 case SNDRV_PCM_FORMAT_S24_LE
:
2216 case SNDRV_PCM_FORMAT_S32_LE
:
2224 /* Try to find an appropriate sample rate; look for an exact match. */
2225 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2226 if (srs
[i
].rate
== params_rate(params
))
2228 if (i
== ARRAY_SIZE(srs
))
2230 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2232 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2233 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2234 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2236 if (params_channels(params
) == 1 &&
2237 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2238 aif2
|= WM8994_AIF1_MONO
;
2240 if (wm8994
->aifclk
[id
] == 0) {
2241 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2245 /* AIFCLK/fs ratio; look for a close match in either direction */
2247 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2248 - wm8994
->aifclk
[id
]);
2249 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2250 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2251 - wm8994
->aifclk
[id
]);
2252 if (cur_val
>= best_val
)
2257 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2258 dai
->id
, fs_ratios
[best
]);
2261 /* We may not get quite the right frequency if using
2262 * approximate clocks so look for the closest match that is
2263 * higher than the target (we need to ensure that there enough
2264 * BCLKs to clock out the samples).
2267 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2268 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2269 if (cur_val
< 0) /* BCLK table is sorted */
2273 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2274 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2275 bclk_divs
[best
], bclk_rate
);
2276 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2278 lrclk
= bclk_rate
/ params_rate(params
);
2279 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2280 lrclk
, bclk_rate
/ lrclk
);
2282 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2283 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2284 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2285 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2287 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2288 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2290 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2293 wm8994
->dac_rates
[0] = params_rate(params
);
2294 wm8994_set_retune_mobile(codec
, 0);
2295 wm8994_set_retune_mobile(codec
, 1);
2298 wm8994
->dac_rates
[1] = params_rate(params
);
2299 wm8994_set_retune_mobile(codec
, 2);
2307 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2308 struct snd_pcm_hw_params
*params
,
2309 struct snd_soc_dai
*dai
)
2311 struct snd_soc_codec
*codec
= dai
->codec
;
2312 struct wm8994
*control
= codec
->control_data
;
2318 switch (control
->type
) {
2320 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2329 switch (params_format(params
)) {
2330 case SNDRV_PCM_FORMAT_S16_LE
:
2332 case SNDRV_PCM_FORMAT_S20_3LE
:
2335 case SNDRV_PCM_FORMAT_S24_LE
:
2338 case SNDRV_PCM_FORMAT_S32_LE
:
2345 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2348 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2350 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2354 switch (codec_dai
->id
) {
2356 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2359 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2366 reg
= WM8994_AIF1DAC1_MUTE
;
2370 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2375 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2377 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2380 switch (codec_dai
->id
) {
2382 reg
= WM8994_AIF1_MASTER_SLAVE
;
2383 mask
= WM8994_AIF1_TRI
;
2386 reg
= WM8994_AIF2_MASTER_SLAVE
;
2387 mask
= WM8994_AIF2_TRI
;
2390 reg
= WM8994_POWER_MANAGEMENT_6
;
2391 mask
= WM8994_AIF3_TRI
;
2402 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2405 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2407 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2408 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2410 static struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2411 .set_sysclk
= wm8994_set_dai_sysclk
,
2412 .set_fmt
= wm8994_set_dai_fmt
,
2413 .hw_params
= wm8994_hw_params
,
2414 .digital_mute
= wm8994_aif_mute
,
2415 .set_pll
= wm8994_set_fll
,
2416 .set_tristate
= wm8994_set_tristate
,
2419 static struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2420 .set_sysclk
= wm8994_set_dai_sysclk
,
2421 .set_fmt
= wm8994_set_dai_fmt
,
2422 .hw_params
= wm8994_hw_params
,
2423 .digital_mute
= wm8994_aif_mute
,
2424 .set_pll
= wm8994_set_fll
,
2425 .set_tristate
= wm8994_set_tristate
,
2428 static struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2429 .hw_params
= wm8994_aif3_hw_params
,
2430 .set_tristate
= wm8994_set_tristate
,
2433 static struct snd_soc_dai_driver wm8994_dai
[] = {
2435 .name
= "wm8994-aif1",
2438 .stream_name
= "AIF1 Playback",
2441 .rates
= WM8994_RATES
,
2442 .formats
= WM8994_FORMATS
,
2445 .stream_name
= "AIF1 Capture",
2448 .rates
= WM8994_RATES
,
2449 .formats
= WM8994_FORMATS
,
2451 .ops
= &wm8994_aif1_dai_ops
,
2454 .name
= "wm8994-aif2",
2457 .stream_name
= "AIF2 Playback",
2460 .rates
= WM8994_RATES
,
2461 .formats
= WM8994_FORMATS
,
2464 .stream_name
= "AIF2 Capture",
2467 .rates
= WM8994_RATES
,
2468 .formats
= WM8994_FORMATS
,
2470 .ops
= &wm8994_aif2_dai_ops
,
2473 .name
= "wm8994-aif3",
2476 .stream_name
= "AIF3 Playback",
2479 .rates
= WM8994_RATES
,
2480 .formats
= WM8994_FORMATS
,
2483 .stream_name
= "AIF3 Capture",
2486 .rates
= WM8994_RATES
,
2487 .formats
= WM8994_FORMATS
,
2489 .ops
= &wm8994_aif3_dai_ops
,
2494 static int wm8994_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
2496 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2499 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2500 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2501 sizeof(struct fll_config
));
2502 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2504 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2508 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2513 static int wm8994_resume(struct snd_soc_codec
*codec
)
2515 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2518 /* Restore the registers */
2519 ret
= snd_soc_cache_sync(codec
);
2521 dev_err(codec
->dev
, "Failed to sync cache: %d\n", ret
);
2523 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2525 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2526 if (!wm8994
->fll_suspend
[i
].out
)
2529 ret
= _wm8994_set_fll(codec
, i
+ 1,
2530 wm8994
->fll_suspend
[i
].src
,
2531 wm8994
->fll_suspend
[i
].in
,
2532 wm8994
->fll_suspend
[i
].out
);
2534 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2541 #define wm8994_suspend NULL
2542 #define wm8994_resume NULL
2545 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2547 struct snd_soc_codec
*codec
= wm8994
->codec
;
2548 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2549 struct snd_kcontrol_new controls
[] = {
2550 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2551 wm8994
->retune_mobile_enum
,
2552 wm8994_get_retune_mobile_enum
,
2553 wm8994_put_retune_mobile_enum
),
2554 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2555 wm8994
->retune_mobile_enum
,
2556 wm8994_get_retune_mobile_enum
,
2557 wm8994_put_retune_mobile_enum
),
2558 SOC_ENUM_EXT("AIF2 EQ Mode",
2559 wm8994
->retune_mobile_enum
,
2560 wm8994_get_retune_mobile_enum
,
2561 wm8994_put_retune_mobile_enum
),
2566 /* We need an array of texts for the enum API but the number
2567 * of texts is likely to be less than the number of
2568 * configurations due to the sample rate dependency of the
2569 * configurations. */
2570 wm8994
->num_retune_mobile_texts
= 0;
2571 wm8994
->retune_mobile_texts
= NULL
;
2572 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2573 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2574 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2575 wm8994
->retune_mobile_texts
[j
]) == 0)
2579 if (j
!= wm8994
->num_retune_mobile_texts
)
2582 /* Expand the array... */
2583 t
= krealloc(wm8994
->retune_mobile_texts
,
2585 (wm8994
->num_retune_mobile_texts
+ 1),
2590 /* ...store the new entry... */
2591 t
[wm8994
->num_retune_mobile_texts
] =
2592 pdata
->retune_mobile_cfgs
[i
].name
;
2594 /* ...and remember the new version. */
2595 wm8994
->num_retune_mobile_texts
++;
2596 wm8994
->retune_mobile_texts
= t
;
2599 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2600 wm8994
->num_retune_mobile_texts
);
2602 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2603 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2605 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2606 ARRAY_SIZE(controls
));
2608 dev_err(wm8994
->codec
->dev
,
2609 "Failed to add ReTune Mobile controls: %d\n", ret
);
2612 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2614 struct snd_soc_codec
*codec
= wm8994
->codec
;
2615 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2621 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2622 pdata
->lineout2_diff
,
2627 pdata
->micbias1_lvl
,
2628 pdata
->micbias2_lvl
);
2630 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2632 if (pdata
->num_drc_cfgs
) {
2633 struct snd_kcontrol_new controls
[] = {
2634 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2635 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2636 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2637 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2638 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2639 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2642 /* We need an array of texts for the enum API */
2643 wm8994
->drc_texts
= kmalloc(sizeof(char *)
2644 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2645 if (!wm8994
->drc_texts
) {
2646 dev_err(wm8994
->codec
->dev
,
2647 "Failed to allocate %d DRC config texts\n",
2648 pdata
->num_drc_cfgs
);
2652 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2653 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2655 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2656 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2658 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2659 ARRAY_SIZE(controls
));
2661 dev_err(wm8994
->codec
->dev
,
2662 "Failed to add DRC mode controls: %d\n", ret
);
2664 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2665 wm8994_set_drc(codec
, i
);
2668 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2669 pdata
->num_retune_mobile_cfgs
);
2671 if (pdata
->num_mbc_cfgs
) {
2672 struct snd_kcontrol_new control
[] = {
2673 SOC_ENUM_EXT("MBC Mode", wm8994
->mbc_enum
,
2674 wm8958_get_mbc_enum
, wm8958_put_mbc_enum
),
2677 /* We need an array of texts for the enum API */
2678 wm8994
->mbc_texts
= kmalloc(sizeof(char *)
2679 * pdata
->num_mbc_cfgs
, GFP_KERNEL
);
2680 if (!wm8994
->mbc_texts
) {
2681 dev_err(wm8994
->codec
->dev
,
2682 "Failed to allocate %d MBC config texts\n",
2683 pdata
->num_mbc_cfgs
);
2687 for (i
= 0; i
< pdata
->num_mbc_cfgs
; i
++)
2688 wm8994
->mbc_texts
[i
] = pdata
->mbc_cfgs
[i
].name
;
2690 wm8994
->mbc_enum
.max
= pdata
->num_mbc_cfgs
;
2691 wm8994
->mbc_enum
.texts
= wm8994
->mbc_texts
;
2693 ret
= snd_soc_add_controls(wm8994
->codec
, control
, 1);
2695 dev_err(wm8994
->codec
->dev
,
2696 "Failed to add MBC mode controls: %d\n", ret
);
2699 if (pdata
->num_retune_mobile_cfgs
)
2700 wm8994_handle_retune_mobile_pdata(wm8994
);
2702 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2703 ARRAY_SIZE(wm8994_eq_controls
));
2707 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2709 * @codec: WM8994 codec
2710 * @jack: jack to report detection events on
2711 * @micbias: microphone bias to detect on
2712 * @det: value to report for presence detection
2713 * @shrt: value to report for short detection
2715 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2716 * being used to bring out signals to the processor then only platform
2717 * data configuration is needed for WM8994 and processor GPIOs should
2718 * be configured using snd_soc_jack_add_gpios() instead.
2720 * Configuration of detection levels is available via the micbias1_lvl
2721 * and micbias2_lvl platform data members.
2723 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2724 int micbias
, int det
, int shrt
)
2726 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2727 struct wm8994_micdet
*micdet
;
2728 struct wm8994
*control
= codec
->control_data
;
2731 if (control
->type
!= WM8994
)
2736 micdet
= &wm8994
->micdet
[0];
2739 micdet
= &wm8994
->micdet
[1];
2745 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2746 micbias
, det
, shrt
);
2748 /* Store the configuration */
2749 micdet
->jack
= jack
;
2751 micdet
->shrt
= shrt
;
2753 /* If either of the jacks is set up then enable detection */
2754 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2755 reg
= WM8994_MICD_ENA
;
2759 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
2763 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
2765 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
2767 struct wm8994_priv
*priv
= data
;
2768 struct snd_soc_codec
*codec
= priv
->codec
;
2772 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2773 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
2776 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
2778 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
2783 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
2786 if (reg
& WM8994_MIC1_DET_STS
)
2787 report
|= priv
->micdet
[0].det
;
2788 if (reg
& WM8994_MIC1_SHRT_STS
)
2789 report
|= priv
->micdet
[0].shrt
;
2790 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
2791 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
2794 if (reg
& WM8994_MIC2_DET_STS
)
2795 report
|= priv
->micdet
[1].det
;
2796 if (reg
& WM8994_MIC2_SHRT_STS
)
2797 report
|= priv
->micdet
[1].shrt
;
2798 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
2799 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
2804 /* Default microphone detection handler for WM8958 - the user can
2805 * override this if they wish.
2807 static void wm8958_default_micdet(u16 status
, void *data
)
2809 struct snd_soc_codec
*codec
= data
;
2810 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2813 /* If nothing present then clear our statuses */
2814 if (!(status
& WM8958_MICD_STS
)) {
2815 wm8994
->jack_is_video
= false;
2816 wm8994
->jack_is_mic
= false;
2820 /* Assume anything over 475 ohms is a microphone and remember
2821 * that we've seen one (since buttons override it) */
2823 wm8994
->jack_is_mic
= true;
2824 if (wm8994
->jack_is_mic
)
2825 report
|= SND_JACK_MICROPHONE
;
2827 /* Video has an impedence of approximately 75 ohms; assume
2828 * this isn't used as a button and remember it since buttons
2831 wm8994
->jack_is_video
= true;
2832 if (wm8994
->jack_is_video
)
2833 report
|= SND_JACK_VIDEOOUT
;
2835 /* Everything else is buttons; just assign slots */
2837 report
|= SND_JACK_BTN_0
;
2839 report
|= SND_JACK_BTN_1
;
2841 report
|= SND_JACK_BTN_2
;
2843 report
|= SND_JACK_BTN_3
;
2845 report
|= SND_JACK_BTN_4
;
2847 report
|= SND_JACK_BTN_5
;
2850 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
2851 SND_JACK_BTN_0
| SND_JACK_BTN_1
| SND_JACK_BTN_2
|
2852 SND_JACK_BTN_3
| SND_JACK_BTN_4
| SND_JACK_BTN_5
|
2853 SND_JACK_MICROPHONE
| SND_JACK_VIDEOOUT
,
2858 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2860 * @codec: WM8958 codec
2861 * @jack: jack to report detection events on
2863 * Enable microphone detection functionality for the WM8958. By
2864 * default simple detection which supports the detection of up to 6
2865 * buttons plus video and microphone functionality is supported.
2867 * The WM8958 has an advanced jack detection facility which is able to
2868 * support complex accessory detection, especially when used in
2869 * conjunction with external circuitry. In order to provide maximum
2870 * flexiblity a callback is provided which allows a completely custom
2871 * detection algorithm.
2873 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2874 wm8958_micdet_cb cb
, void *cb_data
)
2876 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2877 struct wm8994
*control
= codec
->control_data
;
2879 if (control
->type
!= WM8958
)
2884 dev_dbg(codec
->dev
, "Using default micdet callback\n");
2885 cb
= wm8958_default_micdet
;
2889 wm8994
->micdet
[0].jack
= jack
;
2890 wm8994
->jack_cb
= cb
;
2891 wm8994
->jack_cb_data
= cb_data
;
2893 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2894 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
2896 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2897 WM8958_MICD_ENA
, 0);
2902 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
2904 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
2906 struct wm8994_priv
*wm8994
= data
;
2907 struct snd_soc_codec
*codec
= wm8994
->codec
;
2910 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
2912 dev_err(codec
->dev
, "Failed to read mic detect status: %d\n",
2917 if (!(reg
& WM8958_MICD_VALID
)) {
2918 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
2922 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2923 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
2926 if (wm8994
->jack_cb
)
2927 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
2929 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
2935 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
2937 struct wm8994
*control
;
2938 struct wm8994_priv
*wm8994
;
2939 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
2942 codec
->control_data
= dev_get_drvdata(codec
->dev
->parent
);
2943 control
= codec
->control_data
;
2945 wm8994
= kzalloc(sizeof(struct wm8994_priv
), GFP_KERNEL
);
2948 snd_soc_codec_set_drvdata(codec
, wm8994
);
2950 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
2951 wm8994
->codec
= codec
;
2953 pm_runtime_enable(codec
->dev
);
2954 pm_runtime_resume(codec
->dev
);
2956 /* Read our current status back from the chip - we don't want to
2957 * reset as this may interfere with the GPIO or LDO operation. */
2958 for (i
= 0; i
< WM8994_CACHE_SIZE
; i
++) {
2959 if (!wm8994_readable(i
) || wm8994_volatile(i
))
2962 ret
= wm8994_reg_read(codec
->control_data
, i
);
2966 ret
= snd_soc_cache_write(codec
, i
, ret
);
2969 "Failed to initialise cache for 0x%x: %d\n",
2975 /* Set revision-specific configuration */
2976 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
2977 switch (control
->type
) {
2979 switch (wm8994
->revision
) {
2982 wm8994
->hubs
.dcs_codes
= -5;
2983 wm8994
->hubs
.hp_startup_mode
= 1;
2984 wm8994
->hubs
.dcs_readback_mode
= 1;
2987 wm8994
->hubs
.dcs_readback_mode
= 1;
2992 wm8994
->hubs
.dcs_readback_mode
= 1;
2999 switch (control
->type
) {
3001 ret
= wm8994_request_irq(codec
->control_data
,
3002 WM8994_IRQ_MIC1_DET
,
3003 wm8994_mic_irq
, "Mic 1 detect",
3006 dev_warn(codec
->dev
,
3007 "Failed to request Mic1 detect IRQ: %d\n",
3010 ret
= wm8994_request_irq(codec
->control_data
,
3011 WM8994_IRQ_MIC1_SHRT
,
3012 wm8994_mic_irq
, "Mic 1 short",
3015 dev_warn(codec
->dev
,
3016 "Failed to request Mic1 short IRQ: %d\n",
3019 ret
= wm8994_request_irq(codec
->control_data
,
3020 WM8994_IRQ_MIC2_DET
,
3021 wm8994_mic_irq
, "Mic 2 detect",
3024 dev_warn(codec
->dev
,
3025 "Failed to request Mic2 detect IRQ: %d\n",
3028 ret
= wm8994_request_irq(codec
->control_data
,
3029 WM8994_IRQ_MIC2_SHRT
,
3030 wm8994_mic_irq
, "Mic 2 short",
3033 dev_warn(codec
->dev
,
3034 "Failed to request Mic2 short IRQ: %d\n",
3039 ret
= wm8994_request_irq(codec
->control_data
,
3040 WM8994_IRQ_MIC1_DET
,
3041 wm8958_mic_irq
, "Mic detect",
3044 dev_warn(codec
->dev
,
3045 "Failed to request Mic detect IRQ: %d\n",
3050 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3051 * configured on init - if a system wants to do this dynamically
3052 * at runtime we can deal with that then.
3054 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_1
);
3056 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3059 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3060 wm8994
->lrclk_shared
[0] = 1;
3061 wm8994_dai
[0].symmetric_rates
= 1;
3063 wm8994
->lrclk_shared
[0] = 0;
3066 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_6
);
3068 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3071 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3072 wm8994
->lrclk_shared
[1] = 1;
3073 wm8994_dai
[1].symmetric_rates
= 1;
3075 wm8994
->lrclk_shared
[1] = 0;
3078 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
3080 /* Latch volume updates (right only; we always do left then right). */
3081 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3082 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3083 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3084 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3085 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3086 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3087 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3088 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3089 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3090 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3091 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3092 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3093 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3094 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3095 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3096 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3098 /* Set the low bit of the 3D stereo depth so TLV matches */
3099 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3100 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3101 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3102 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3103 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3104 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3105 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3106 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3107 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3109 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3110 * behaviour on idle TDM clock cycles. */
3111 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3112 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3114 wm8994_update_class_w(codec
);
3116 wm8994_handle_pdata(wm8994
);
3118 wm_hubs_add_analogue_controls(codec
);
3119 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3120 ARRAY_SIZE(wm8994_snd_controls
));
3121 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3122 ARRAY_SIZE(wm8994_dapm_widgets
));
3124 switch (control
->type
) {
3126 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3127 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3130 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3131 ARRAY_SIZE(wm8958_snd_controls
));
3132 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3133 ARRAY_SIZE(wm8958_dapm_widgets
));
3138 wm_hubs_add_analogue_routes(codec
, 0, 0);
3139 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3141 switch (control
->type
) {
3143 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3144 ARRAY_SIZE(wm8994_intercon
));
3146 if (wm8994
->revision
< 4)
3147 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3148 ARRAY_SIZE(wm8994_revd_intercon
));
3152 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3153 ARRAY_SIZE(wm8958_intercon
));
3160 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3161 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
, wm8994
);
3162 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3163 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
, wm8994
);
3169 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3171 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3172 struct wm8994
*control
= codec
->control_data
;
3174 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3176 pm_runtime_disable(codec
->dev
);
3178 switch (control
->type
) {
3180 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
,
3182 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
,
3184 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
,
3186 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
3191 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
3195 kfree(wm8994
->retune_mobile_texts
);
3196 kfree(wm8994
->drc_texts
);
3202 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3203 .probe
= wm8994_codec_probe
,
3204 .remove
= wm8994_codec_remove
,
3205 .suspend
= wm8994_suspend
,
3206 .resume
= wm8994_resume
,
3207 .read
= wm8994_read
,
3208 .write
= wm8994_write
,
3209 .readable_register
= wm8994_readable
,
3210 .volatile_register
= wm8994_volatile
,
3211 .set_bias_level
= wm8994_set_bias_level
,
3213 .reg_cache_size
= WM8994_CACHE_SIZE
,
3214 .reg_cache_default
= wm8994_reg_defaults
,
3216 .compress_type
= SND_SOC_RBTREE_COMPRESSION
,
3219 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3221 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3222 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3225 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3227 snd_soc_unregister_codec(&pdev
->dev
);
3231 static struct platform_driver wm8994_codec_driver
= {
3233 .name
= "wm8994-codec",
3234 .owner
= THIS_MODULE
,
3236 .probe
= wm8994_probe
,
3237 .remove
= __devexit_p(wm8994_remove
),
3240 static __init
int wm8994_init(void)
3242 return platform_driver_register(&wm8994_codec_driver
);
3244 module_init(wm8994_init
);
3246 static __exit
void wm8994_exit(void)
3248 platform_driver_unregister(&wm8994_codec_driver
);
3250 module_exit(wm8994_exit
);
3253 MODULE_DESCRIPTION("ASoC WM8994 driver");
3254 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3255 MODULE_LICENSE("GPL");
3256 MODULE_ALIAS("platform:wm8994-codec");