drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25
  26 #include "xhci.h"
  27
  28 /* Device for a quirk */
  29 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  31
  32 #define PCI_VENDOR_ID_ETRON             0x1b6f
  33 #define PCI_DEVICE_ID_ASROCK_P67        0x7023
  34
  35 static const char hcd_name[] = "xhci_hcd";
  36
  37 /* called after powerup, by probe or system-pm "wakeup" */
  38 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  39 {
  40         /*
  41          * TODO: Implement finding debug ports later.
  42          * TODO: see if there are any quirks that need to be added to handle
  43          * new extended capabilities.
  44          */
  45
  46         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  47         if (!pci_set_mwi(pdev))
  48                 xhci_dbg(xhci, "MWI active\n");
  49
  50         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  51         return 0;
  52 }
  53
  54 /* called during probe() after chip reset completes */
  55 static int xhci_pci_setup(struct usb_hcd *hcd)
  56 {
  57         struct xhci_hcd         *xhci;
  58         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  59         int                     retval;
  60         u32                     temp;
  61
  62         hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
  63
  64         if (usb_hcd_is_primary_hcd(hcd)) {
  65                 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  66                 if (!xhci)
  67                         return -ENOMEM;
  68                 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  69                 xhci->main_hcd = hcd;
  70                 /* Mark the first roothub as being USB 2.0.
  71                  * The xHCI driver will register the USB 3.0 roothub.
  72                  */
  73                 hcd->speed = HCD_USB2;
  74                 hcd->self.root_hub->speed = USB_SPEED_HIGH;
  75                 /*
  76                  * USB 2.0 roothub under xHCI has an integrated TT,
  77                  * (rate matching hub) as opposed to having an OHCI/UHCI
  78                  * companion controller.
  79                  */
  80                 hcd->has_tt = 1;
  81         } else {
  82                 /* xHCI private pointer was set in xhci_pci_probe for the second
  83                  * registered roothub.
  84                  */
  85                 xhci = hcd_to_xhci(hcd);
  86                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  87                 if (HCC_64BIT_ADDR(temp)) {
  88                         xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  89                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
  90                 } else {
  91                         dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
  92                 }
  93                 return 0;
  94         }
  95
  96         xhci->cap_regs = hcd->regs;
  97         xhci->op_regs = hcd->regs +
  98                 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  99         xhci->run_regs = hcd->regs +
 100                 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
 101         /* Cache read-only capability registers */
 102         xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
 103         xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
 104         xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 105         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
 106         xhci->hci_version = HC_VERSION(xhci->hcc_params);
 107         xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 108         xhci_print_registers(xhci);
 109
 110         /* Look for vendor-specific quirks */
 111         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 112                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
 113                 if (pdev->revision == 0x0) {
 114                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 115                         xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
 116                                         " endpoint cmd after reset endpoint\n");
 117                 }
 118                 /* Fresco Logic confirms: all revisions of this chip do not
 119                  * support MSI, even though some of them claim to in their PCI
 120                  * capabilities.
 121                  */
 122                 xhci->quirks |= XHCI_BROKEN_MSI;
 123                 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
 124                                 "has broken MSI implementation\n",
 125                                 pdev->revision);
 126         }
 127
 128         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 129                 xhci->quirks |= XHCI_NEC_HOST;
 130
 131         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 132                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 133
 134         /* AMD PLL quirk */
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 136                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 137         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 138                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 139                 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 140                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 141                 xhci->limit_active_eps = 64;
 142         }
 143         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 144                         pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
 145                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 146                 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
 147         }
 148
 149         /* Make sure the HC is halted. */
 150         retval = xhci_halt(xhci);
 151         if (retval)
 152                 goto error;
 153
 154         xhci_dbg(xhci, "Resetting HCD\n");
 155         /* Reset the internal HC memory state and registers. */
 156         retval = xhci_reset(xhci);
 157         if (retval)
 158                 goto error;
 159         xhci_dbg(xhci, "Reset complete\n");
 160
 161         temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 162         if (HCC_64BIT_ADDR(temp)) {
 163                 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
 164                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
 165         } else {
 166                 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
 167         }
 168
 169         xhci_dbg(xhci, "Calling HCD init\n");
 170         /* Initialize HCD and host controller data structures. */
 171         retval = xhci_init(hcd);
 172         if (retval)
 173                 goto error;
 174         xhci_dbg(xhci, "Called HCD init\n");
 175
 176         pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 177         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 178
 179         /* Find any debug ports */
 180         retval = xhci_pci_reinit(xhci, pdev);
 181         if (!retval)
 182                 return retval;
 183
 184 error:
 185         kfree(xhci);
 186         return retval;
 187 }
 188
 189 /*
 190  * We need to register our own PCI probe function (instead of the USB core's
 191  * function) in order to create a second roothub under xHCI.
 192  */
 193 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 194 {
 195         int retval;
 196         struct xhci_hcd *xhci;
 197         struct hc_driver *driver;
 198         struct usb_hcd *hcd;
 199
 200         driver = (struct hc_driver *)id->driver_data;
 201         /* Register the USB 2.0 roothub.
 202          * FIXME: USB core must know to register the USB 2.0 roothub first.
 203          * This is sort of silly, because we could just set the HCD driver flags
 204          * to say USB 2.0, but I'm not sure what the implications would be in
 205          * the other parts of the HCD code.
 206          */
 207         retval = usb_hcd_pci_probe(dev, id);
 208
 209         if (retval)
 210                 return retval;
 211
 212         /* USB 2.0 roothub is stored in the PCI device now. */
 213         hcd = dev_get_drvdata(&dev->dev);
 214         xhci = hcd_to_xhci(hcd);
 215         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 216                                 pci_name(dev), hcd);
 217         if (!xhci->shared_hcd) {
 218                 retval = -ENOMEM;
 219                 goto dealloc_usb2_hcd;
 220         }
 221
 222         /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
 223          * is called by usb_add_hcd().
 224          */
 225         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
 226
 227         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 228                         IRQF_DISABLED | IRQF_SHARED);
 229         if (retval)
 230                 goto put_usb3_hcd;
 231         /* Roothub already marked as USB 3.0 speed */
 232         return 0;
 233
 234 put_usb3_hcd:
 235         usb_put_hcd(xhci->shared_hcd);
 236 dealloc_usb2_hcd:
 237         usb_hcd_pci_remove(dev);
 238         return retval;
 239 }
 240
 241 static void xhci_pci_remove(struct pci_dev *dev)
 242 {
 243         struct xhci_hcd *xhci;
 244
 245         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 246         if (xhci->shared_hcd) {
 247                 usb_remove_hcd(xhci->shared_hcd);
 248                 usb_put_hcd(xhci->shared_hcd);
 249         }
 250         usb_hcd_pci_remove(dev);
 251         kfree(xhci);
 252 }
 253
 254 #ifdef CONFIG_PM
 255 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 256 {
 257         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 258         int     retval = 0;
 259
 260         if (hcd->state != HC_STATE_SUSPENDED ||
 261                         xhci->shared_hcd->state != HC_STATE_SUSPENDED)
 262                 return -EINVAL;
 263
 264         retval = xhci_suspend(xhci);
 265
 266         return retval;
 267 }
 268
 269 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 270 {
 271         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 272         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 273         int                     retval = 0;
 274
 275         /* The BIOS on systems with the Intel Panther Point chipset may or may
 276          * not support xHCI natively.  That means that during system resume, it
 277          * may switch the ports back to EHCI so that users can use their
 278          * keyboard to select a kernel from GRUB after resume from hibernate.
 279          *
 280          * The BIOS is supposed to remember whether the OS had xHCI ports
 281          * enabled before resume, and switch the ports back to xHCI when the
 282          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 283          * writers.
 284          *
 285          * Unconditionally switch the ports back to xHCI after a system resume.
 286          * We can't tell whether the EHCI or xHCI controller will be resumed
 287          * first, so we have to do the port switchover in both drivers.  Writing
 288          * a '1' to the port switchover registers should have no effect if the
 289          * port was already switched over.
 290          */
 291         if (usb_is_intel_switchable_xhci(pdev))
 292                 usb_enable_xhci_ports(pdev);
 293
 294         retval = xhci_resume(xhci, hibernated);
 295         return retval;
 296 }
 297 #endif /* CONFIG_PM */
 298
 299 static const struct hc_driver xhci_pci_hc_driver = {
 300         .description =          hcd_name,
 301         .product_desc =         "xHCI Host Controller",
 302         .hcd_priv_size =        sizeof(struct xhci_hcd *),
 303
 304         /*
 305          * generic hardware linkage
 306          */
 307         .irq =                  xhci_irq,
 308         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
 309
 310         /*
 311          * basic lifecycle operations
 312          */
 313         .reset =                xhci_pci_setup,
 314         .start =                xhci_run,
 315 #ifdef CONFIG_PM
 316         .pci_suspend =          xhci_pci_suspend,
 317         .pci_resume =           xhci_pci_resume,
 318 #endif
 319         .stop =                 xhci_stop,
 320         .shutdown =             xhci_shutdown,
 321
 322         /*
 323          * managing i/o requests and associated device resources
 324          */
 325         .urb_enqueue =          xhci_urb_enqueue,
 326         .urb_dequeue =          xhci_urb_dequeue,
 327         .alloc_dev =            xhci_alloc_dev,
 328         .free_dev =             xhci_free_dev,
 329         .alloc_streams =        xhci_alloc_streams,
 330         .free_streams =         xhci_free_streams,
 331         .add_endpoint =         xhci_add_endpoint,
 332         .drop_endpoint =        xhci_drop_endpoint,
 333         .endpoint_reset =       xhci_endpoint_reset,
 334         .check_bandwidth =      xhci_check_bandwidth,
 335         .reset_bandwidth =      xhci_reset_bandwidth,
 336         .address_device =       xhci_address_device,
 337         .update_hub_device =    xhci_update_hub_device,
 338         .reset_device =         xhci_discover_or_reset_device,
 339
 340         /*
 341          * scheduling support
 342          */
 343         .get_frame_number =     xhci_get_frame,
 344
 345         /* Root hub support */
 346         .hub_control =          xhci_hub_control,
 347         .hub_status_data =      xhci_hub_status_data,
 348         .bus_suspend =          xhci_bus_suspend,
 349         .bus_resume =           xhci_bus_resume,
 350 };
 351
 352 /*-------------------------------------------------------------------------*/
 353
 354 /* PCI driver selection metadata; PCI hotplugging uses this */
 355 static const struct pci_device_id pci_ids[] = { {
 356         /* handle any USB 3.0 xHCI controller */
 357         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 358         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 359         },
 360         { /* end: all zeroes */ }
 361 };
 362 MODULE_DEVICE_TABLE(pci, pci_ids);
 363
 364 /* pci driver glue; this is a "new style" PCI driver module */
 365 static struct pci_driver xhci_pci_driver = {
 366         .name =         (char *) hcd_name,
 367         .id_table =     pci_ids,
 368
 369         .probe =        xhci_pci_probe,
 370         .remove =       xhci_pci_remove,
 371         /* suspend and resume implemented later */
 372
 373         .shutdown =     usb_hcd_pci_shutdown,
 374 #ifdef CONFIG_PM_SLEEP
 375         .driver = {
 376                 .pm = &usb_hcd_pci_pm_ops
 377         },
 378 #endif
 379 };
 380
 381 int xhci_register_pci(void)
 382 {
 383         return pci_register_driver(&xhci_pci_driver);
 384 }
 385
 386 void xhci_unregister_pci(void)
 387 {
 388         pci_unregister_driver(&xhci_pci_driver);
 389 }