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fuse: fix llseek bug
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / host / ohci-pxa27x.c
blob80be5472783a4f30e8a791a205958f176ff2dbf1
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 * (C) Copyright 2002 Hewlett-Packard Company
7 *
8 * Bus Glue for pxa27x
9 *
10 * Written by Christopher Hoover <ch@hpl.hp.com>
11 * Based on fragments of previous driver by Russell King et al.
12 *
13 * Modified for LH7A404 from ohci-sa1111.c
14 * by Durgesh Pattamatta <pattamattad@sharpsec.com>
15 *
16 * Modified for pxa27x from ohci-lh7a404.c
17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
18 *
19 * This file is licenced under the GPL.
20 */
21
22 #include <linux/device.h>
23 #include <linux/signal.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <mach/ohci.h>
27 #include <mach/pxa3xx-u2d.h>
28
29 /*
30 * UHC: USB Host Controller (OHCI-like) register definitions
31 */
32 #define UHCREV (0x0000) /* UHC HCI Spec Revision */
33 #define UHCHCON (0x0004) /* UHC Host Control Register */
34 #define UHCCOMS (0x0008) /* UHC Command Status Register */
35 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
36 #define UHCINTE (0x0010) /* UHC Interrupt Enable */
37 #define UHCINTD (0x0014) /* UHC Interrupt Disable */
38 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
39 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
40 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
41 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
42 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
43 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
44 #define UHCDHEAD (0x0030) /* UHC Done Head */
45 #define UHCFMI (0x0034) /* UHC Frame Interval */
46 #define UHCFMR (0x0038) /* UHC Frame Remaining */
47 #define UHCFMN (0x003C) /* UHC Frame Number */
48 #define UHCPERS (0x0040) /* UHC Periodic Start */
49 #define UHCLS (0x0044) /* UHC Low Speed Threshold */
50
51 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
52 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
53 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
54 #define UHCRHDA_POTPGT(x) \
55 (((x) & 0xff) << 24) /* Power On To Power Good Time */
56
57 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
58 #define UHCRHS (0x0050) /* UHC Root Hub Status */
59 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
60 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
61 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
62
63 #define UHCSTAT (0x0060) /* UHC Status Register */
64 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
65 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
66 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
67 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
68 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
69 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
70 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
71 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
72 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
73
74 #define UHCHR (0x0064) /* UHC Reset Register */
75 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
76 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
77 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
78 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
79 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
80 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
81 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
82 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
83 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
84 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
85 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
86
87 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
88 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
89 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
90 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
91 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
92 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
93 Interrupt Enable*/
94 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
95 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
96
97 #define UHCHIT (0x006C) /* UHC Interrupt Test register */
98
99 #define PXA_UHC_MAX_PORTNUM 3
100
101 struct pxa27x_ohci {
102 /* must be 1st member here for hcd_to_ohci() to work */
103 struct ohci_hcd ohci;
104
105 struct device *dev;
106 struct clk *clk;
107 void __iomem *mmio_base;
108 };
109
110 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
111
112 /*
113 PMM_NPS_MODE -- PMM Non-power switching mode
114 Ports are powered continuously.
115
116 PMM_GLOBAL_MODE -- PMM global switching mode
117 All ports are powered at the same time.
118
119 PMM_PERPORT_MODE -- PMM per port switching mode
120 Ports are powered individually.
121 */
122 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
123 {
124 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
125 uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
126
127 switch (mode) {
128 case PMM_NPS_MODE:
129 uhcrhda |= RH_A_NPS;
130 break;
131 case PMM_GLOBAL_MODE:
132 uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
133 break;
134 case PMM_PERPORT_MODE:
135 uhcrhda &= ~(RH_A_NPS);
136 uhcrhda |= RH_A_PSM;
137
138 /* Set port power control mask bits, only 3 ports. */
139 uhcrhdb |= (0x7<<17);
140 break;
141 default:
142 printk( KERN_ERR
143 "Invalid mode %d, set to non-power switch mode.\n",
144 mode );
145
146 uhcrhda |= RH_A_NPS;
147 }
148
149 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
150 __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
151 return 0;
152 }
153
154 extern int usb_disabled(void);
155
156 /*-------------------------------------------------------------------------*/
157
158 static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
159 struct pxaohci_platform_data *inf)
160 {
161 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
162 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
163
164 if (inf->flags & ENABLE_PORT1)
165 uhchr &= ~UHCHR_SSEP1;
166
167 if (inf->flags & ENABLE_PORT2)
168 uhchr &= ~UHCHR_SSEP2;
169
170 if (inf->flags & ENABLE_PORT3)
171 uhchr &= ~UHCHR_SSEP3;
172
173 if (inf->flags & POWER_CONTROL_LOW)
174 uhchr |= UHCHR_PCPL;
175
176 if (inf->flags & POWER_SENSE_LOW)
177 uhchr |= UHCHR_PSPL;
178
179 if (inf->flags & NO_OC_PROTECTION)
180 uhcrhda |= UHCRHDA_NOCP;
181 else
182 uhcrhda &= ~UHCRHDA_NOCP;
183
184 if (inf->flags & OC_MODE_PERPORT)
185 uhcrhda |= UHCRHDA_OCPM;
186 else
187 uhcrhda &= ~UHCRHDA_OCPM;
188
189 if (inf->power_on_delay) {
190 uhcrhda &= ~UHCRHDA_POTPGT(0xff);
191 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
192 }
193
194 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
195 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
196 }
197
198 static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
199 {
200 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
201
202 __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
203 udelay(11);
204 __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
205 }
206
207 #ifdef CONFIG_PXA27x
208 extern void pxa27x_clear_otgph(void);
209 #else
210 #define pxa27x_clear_otgph() do {} while (0)
211 #endif
212
213 static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
214 {
215 int retval = 0;
216 struct pxaohci_platform_data *inf;
217 uint32_t uhchr;
218
219 inf = dev->platform_data;
220
221 clk_enable(ohci->clk);
222
223 pxa27x_reset_hc(ohci);
224
225 uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
226 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
227
228 while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
229 cpu_relax();
230
231 pxa27x_setup_hc(ohci, inf);
232
233 if (inf->init)
234 retval = inf->init(dev);
235
236 if (retval < 0)
237 return retval;
238
239 if (cpu_is_pxa3xx())
240 pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
241
242 uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
243 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
244 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
245
246 /* Clear any OTG Pin Hold */
247 pxa27x_clear_otgph();
248 return 0;
249 }
250
251 static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
252 {
253 struct pxaohci_platform_data *inf;
254 uint32_t uhccoms;
255
256 inf = dev->platform_data;
257
258 if (cpu_is_pxa3xx())
259 pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
260
261 if (inf->exit)
262 inf->exit(dev);
263
264 pxa27x_reset_hc(ohci);
265
266 /* Host Controller Reset */
267 uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
268 __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
269 udelay(10);
270
271 clk_disable(ohci->clk);
272 }
273
274
275 /*-------------------------------------------------------------------------*/
276
277 /* configure so an HC device and id are always provided */
278 /* always called with process context; sleeping is OK */
279
280
281 /**
282 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
283 * Context: !in_interrupt()
284 *
285 * Allocates basic resources for this USB host controller, and
286 * then invokes the start() method for the HCD associated with it
287 * through the hotplug entry's driver_data.
288 *
289 */
290 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
291 {
292 int retval, irq;
293 struct usb_hcd *hcd;
294 struct pxaohci_platform_data *inf;
295 struct pxa27x_ohci *ohci;
296 struct resource *r;
297 struct clk *usb_clk;
298
299 inf = pdev->dev.platform_data;
300
301 if (!inf)
302 return -ENODEV;
303
304 irq = platform_get_irq(pdev, 0);
305 if (irq < 0) {
306 pr_err("no resource of IORESOURCE_IRQ");
307 return -ENXIO;
308 }
309
310 usb_clk = clk_get(&pdev->dev, NULL);
311 if (IS_ERR(usb_clk))
312 return PTR_ERR(usb_clk);
313
314 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
315 if (!hcd) {
316 retval = -ENOMEM;
317 goto err0;
318 }
319
320 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 if (!r) {
322 pr_err("no resource of IORESOURCE_MEM");
323 retval = -ENXIO;
324 goto err1;
325 }
326
327 hcd->rsrc_start = r->start;
328 hcd->rsrc_len = resource_size(r);
329
330 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
331 pr_debug("request_mem_region failed");
332 retval = -EBUSY;
333 goto err1;
334 }
335
336 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
337 if (!hcd->regs) {
338 pr_debug("ioremap failed");
339 retval = -ENOMEM;
340 goto err2;
341 }
342
343 /* initialize "struct pxa27x_ohci" */
344 ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
345 ohci->dev = &pdev->dev;
346 ohci->clk = usb_clk;
347 ohci->mmio_base = (void __iomem *)hcd->regs;
348
349 if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
350 pr_debug("pxa27x_start_hc failed");
351 goto err3;
352 }
353
354 /* Select Power Management Mode */
355 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
356
357 if (inf->power_budget)
358 hcd->power_budget = inf->power_budget;
359
360 ohci_hcd_init(hcd_to_ohci(hcd));
361
362 retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
363 if (retval == 0)
364 return retval;
365
366 pxa27x_stop_hc(ohci, &pdev->dev);
367 err3:
368 iounmap(hcd->regs);
369 err2:
370 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
371 err1:
372 usb_put_hcd(hcd);
373 err0:
374 clk_put(usb_clk);
375 return retval;
376 }
377
378
379 /* may be called without controller electrically present */
380 /* may be called with controller, bus, and devices active */
381
382 /**
383 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
384 * @dev: USB Host Controller being removed
385 * Context: !in_interrupt()
386 *
387 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
388 * the HCD's stop() method. It is always called from a thread
389 * context, normally "rmmod", "apmd", or something similar.
390 *
391 */
392 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
393 {
394 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
395
396 usb_remove_hcd(hcd);
397 pxa27x_stop_hc(ohci, &pdev->dev);
398 iounmap(hcd->regs);
399 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
400 usb_put_hcd(hcd);
401 clk_put(ohci->clk);
402 }
403
404 /*-------------------------------------------------------------------------*/
405
406 static int __devinit
407 ohci_pxa27x_start (struct usb_hcd *hcd)
408 {
409 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
410 int ret;
411
412 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
413
414 /* The value of NDP in roothub_a is incorrect on this hardware */
415 ohci->num_ports = 3;
416
417 if ((ret = ohci_init(ohci)) < 0)
418 return ret;
419
420 if ((ret = ohci_run (ohci)) < 0) {
421 err ("can't start %s", hcd->self.bus_name);
422 ohci_stop (hcd);
423 return ret;
424 }
425
426 return 0;
427 }
428
429 /*-------------------------------------------------------------------------*/
430
431 static const struct hc_driver ohci_pxa27x_hc_driver = {
432 .description = hcd_name,
433 .product_desc = "PXA27x OHCI",
434 .hcd_priv_size = sizeof(struct pxa27x_ohci),
435
436 /*
437 * generic hardware linkage
438 */
439 .irq = ohci_irq,
440 .flags = HCD_USB11 | HCD_MEMORY,
441
442 /*
443 * basic lifecycle operations
444 */
445 .start = ohci_pxa27x_start,
446 .stop = ohci_stop,
447 .shutdown = ohci_shutdown,
448
449 /*
450 * managing i/o requests and associated device resources
451 */
452 .urb_enqueue = ohci_urb_enqueue,
453 .urb_dequeue = ohci_urb_dequeue,
454 .endpoint_disable = ohci_endpoint_disable,
455
456 /*
457 * scheduling support
458 */
459 .get_frame_number = ohci_get_frame,
460
461 /*
462 * root hub support
463 */
464 .hub_status_data = ohci_hub_status_data,
465 .hub_control = ohci_hub_control,
466 #ifdef CONFIG_PM
467 .bus_suspend = ohci_bus_suspend,
468 .bus_resume = ohci_bus_resume,
469 #endif
470 .start_port_reset = ohci_start_port_reset,
471 };
472
473 /*-------------------------------------------------------------------------*/
474
475 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
476 {
477 pr_debug ("In ohci_hcd_pxa27x_drv_probe");
478
479 if (usb_disabled())
480 return -ENODEV;
481
482 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
483 }
484
485 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
486 {
487 struct usb_hcd *hcd = platform_get_drvdata(pdev);
488
489 usb_hcd_pxa27x_remove(hcd, pdev);
490 platform_set_drvdata(pdev, NULL);
491 return 0;
492 }
493
494 #ifdef CONFIG_PM
495 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
496 {
497 struct usb_hcd *hcd = dev_get_drvdata(dev);
498 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
499
500 if (time_before(jiffies, ohci->ohci.next_statechange))
501 msleep(5);
502 ohci->ohci.next_statechange = jiffies;
503
504 pxa27x_stop_hc(ohci, dev);
505 hcd->state = HC_STATE_SUSPENDED;
506
507 return 0;
508 }
509
510 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
511 {
512 struct usb_hcd *hcd = dev_get_drvdata(dev);
513 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
514 struct pxaohci_platform_data *inf = dev->platform_data;
515 int status;
516
517 if (time_before(jiffies, ohci->ohci.next_statechange))
518 msleep(5);
519 ohci->ohci.next_statechange = jiffies;
520
521 if ((status = pxa27x_start_hc(ohci, dev)) < 0)
522 return status;
523
524 /* Select Power Management Mode */
525 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
526
527 ohci_finish_controller_resume(hcd);
528 return 0;
529 }
530
531 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
532 .suspend = ohci_hcd_pxa27x_drv_suspend,
533 .resume = ohci_hcd_pxa27x_drv_resume,
534 };
535 #endif
536
537 /* work with hotplug and coldplug */
538 MODULE_ALIAS("platform:pxa27x-ohci");
539
540 static struct platform_driver ohci_hcd_pxa27x_driver = {
541 .probe = ohci_hcd_pxa27x_drv_probe,
542 .remove = ohci_hcd_pxa27x_drv_remove,
543 .shutdown = usb_hcd_platform_shutdown,
544 .driver = {
545 .name = "pxa27x-ohci",
546 .owner = THIS_MODULE,
547 #ifdef CONFIG_PM
548 .pm = &ohci_hcd_pxa27x_pm_ops,
549 #endif
550 },
551 };
552
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