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macvlan: Support creating macvlans from macvlans
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / gianfar.c
blobbed30ef43797cd56776a868e15091dc523e40c5e
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_platform.h>
79 #include <linux/ip.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
82 #include <linux/in.h>
83
84 #include <asm/io.h>
85 #include <asm/irq.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
93 #include <linux/of.h>
94
95 #include "gianfar.h"
96 #include "fsl_pq_mdio.h"
97
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
101
102 const char gfar_driver_name[] = "Gianfar Ethernet";
103 const char gfar_driver_version[] = "1.3";
104
105 static int gfar_enet_open(struct net_device *dev);
106 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
107 static void gfar_reset_task(struct work_struct *work);
108 static void gfar_timeout(struct net_device *dev);
109 static int gfar_close(struct net_device *dev);
110 struct sk_buff *gfar_new_skb(struct net_device *dev);
111 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
112 struct sk_buff *skb);
113 static int gfar_set_mac_address(struct net_device *dev);
114 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
115 static irqreturn_t gfar_error(int irq, void *dev_id);
116 static irqreturn_t gfar_transmit(int irq, void *dev_id);
117 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
118 static void adjust_link(struct net_device *dev);
119 static void init_registers(struct net_device *dev);
120 static int init_phy(struct net_device *dev);
121 static int gfar_probe(struct of_device *ofdev,
122 const struct of_device_id *match);
123 static int gfar_remove(struct of_device *ofdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
131 #endif
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
135 int amount_pull);
136 static void gfar_vlan_rx_register(struct net_device *netdev,
137 struct vlan_group *grp);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
144
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
148
149 static const struct net_device_ops gfar_netdev_ops = {
150 .ndo_open = gfar_enet_open,
151 .ndo_start_xmit = gfar_start_xmit,
152 .ndo_stop = gfar_close,
153 .ndo_change_mtu = gfar_change_mtu,
154 .ndo_set_multicast_list = gfar_set_multi,
155 .ndo_tx_timeout = gfar_timeout,
156 .ndo_do_ioctl = gfar_ioctl,
157 .ndo_vlan_rx_register = gfar_vlan_rx_register,
158 #ifdef CONFIG_NET_POLL_CONTROLLER
159 .ndo_poll_controller = gfar_netpoll,
160 #endif
161 };
162
163 /* Returns 1 if incoming frames use an FCB */
164 static inline int gfar_uses_fcb(struct gfar_private *priv)
165 {
166 return priv->vlgrp || priv->rx_csum_enable;
167 }
168
169 static int gfar_of_init(struct net_device *dev)
170 {
171 struct device_node *phy, *mdio;
172 const unsigned int *id;
173 const char *model;
174 const char *ctype;
175 const void *mac_addr;
176 const phandle *ph;
177 u64 addr, size;
178 int err = 0;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
181 char bus_name[MII_BUS_ID_SIZE];
182 const u32 *stash;
183 const u32 *stash_len;
184 const u32 *stash_idx;
185
186 if (!np || !of_device_is_available(np))
187 return -ENODEV;
188
189 /* get a pointer to the register memory */
190 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
191 priv->regs = ioremap(addr, size);
192
193 if (priv->regs == NULL)
194 return -ENOMEM;
195
196 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
197
198 model = of_get_property(np, "model", NULL);
199
200 /* If we aren't the FEC we have multiple interrupts */
201 if (model && strcasecmp(model, "FEC")) {
202 priv->interruptReceive = irq_of_parse_and_map(np, 1);
203
204 priv->interruptError = irq_of_parse_and_map(np, 2);
205
206 if (priv->interruptTransmit < 0 ||
207 priv->interruptReceive < 0 ||
208 priv->interruptError < 0) {
209 err = -EINVAL;
210 goto err_out;
211 }
212 }
213
214 stash = of_get_property(np, "bd-stash", NULL);
215
216 if(stash) {
217 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
218 priv->bd_stash_en = 1;
219 }
220
221 stash_len = of_get_property(np, "rx-stash-len", NULL);
222
223 if (stash_len)
224 priv->rx_stash_size = *stash_len;
225
226 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
227
228 if (stash_idx)
229 priv->rx_stash_index = *stash_idx;
230
231 if (stash_len || stash_idx)
232 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
233
234 mac_addr = of_get_mac_address(np);
235 if (mac_addr)
236 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
237
238 if (model && !strcasecmp(model, "TSEC"))
239 priv->device_flags =
240 FSL_GIANFAR_DEV_HAS_GIGABIT |
241 FSL_GIANFAR_DEV_HAS_COALESCE |
242 FSL_GIANFAR_DEV_HAS_RMON |
243 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
244 if (model && !strcasecmp(model, "eTSEC"))
245 priv->device_flags =
246 FSL_GIANFAR_DEV_HAS_GIGABIT |
247 FSL_GIANFAR_DEV_HAS_COALESCE |
248 FSL_GIANFAR_DEV_HAS_RMON |
249 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
250 FSL_GIANFAR_DEV_HAS_PADDING |
251 FSL_GIANFAR_DEV_HAS_CSUM |
252 FSL_GIANFAR_DEV_HAS_VLAN |
253 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
254 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
255
256 ctype = of_get_property(np, "phy-connection-type", NULL);
257
258 /* We only care about rgmii-id. The rest are autodetected */
259 if (ctype && !strcmp(ctype, "rgmii-id"))
260 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
261 else
262 priv->interface = PHY_INTERFACE_MODE_MII;
263
264 if (of_get_property(np, "fsl,magic-packet", NULL))
265 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
266
267 ph = of_get_property(np, "phy-handle", NULL);
268 if (ph == NULL) {
269 u32 *fixed_link;
270
271 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
272 if (!fixed_link) {
273 err = -ENODEV;
274 goto err_out;
275 }
276
277 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id),
278 PHY_ID_FMT, "0", fixed_link[0]);
279 } else {
280 phy = of_find_node_by_phandle(*ph);
281
282 if (phy == NULL) {
283 err = -ENODEV;
284 goto err_out;
285 }
286
287 mdio = of_get_parent(phy);
288
289 id = of_get_property(phy, "reg", NULL);
290
291 of_node_put(phy);
292 of_node_put(mdio);
293
294 fsl_pq_mdio_bus_name(bus_name, mdio);
295 snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x",
296 bus_name, *id);
297 }
298
299 /* Find the TBI PHY. If it's not there, we don't support SGMII */
300 ph = of_get_property(np, "tbi-handle", NULL);
301 if (ph) {
302 struct device_node *tbi = of_find_node_by_phandle(*ph);
303 struct of_device *ofdev;
304 struct mii_bus *bus;
305
306 if (!tbi)
307 return 0;
308
309 mdio = of_get_parent(tbi);
310 if (!mdio)
311 return 0;
312
313 ofdev = of_find_device_by_node(mdio);
314
315 of_node_put(mdio);
316
317 id = of_get_property(tbi, "reg", NULL);
318 if (!id)
319 return 0;
320
321 of_node_put(tbi);
322
323 bus = dev_get_drvdata(&ofdev->dev);
324
325 priv->tbiphy = bus->phy_map[*id];
326 }
327
328 return 0;
329
330 err_out:
331 iounmap(priv->regs);
332 return err;
333 }
334
335 /* Ioctl MII Interface */
336 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
337 {
338 struct gfar_private *priv = netdev_priv(dev);
339
340 if (!netif_running(dev))
341 return -EINVAL;
342
343 if (!priv->phydev)
344 return -ENODEV;
345
346 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
347 }
348
349 /* Set up the ethernet device structure, private data,
350 * and anything else we need before we start */
351 static int gfar_probe(struct of_device *ofdev,
352 const struct of_device_id *match)
353 {
354 u32 tempval;
355 struct net_device *dev = NULL;
356 struct gfar_private *priv = NULL;
357 DECLARE_MAC_BUF(mac);
358 int err = 0;
359 int len_devname;
360
361 /* Create an ethernet device instance */
362 dev = alloc_etherdev(sizeof (*priv));
363
364 if (NULL == dev)
365 return -ENOMEM;
366
367 priv = netdev_priv(dev);
368 priv->dev = dev;
369 priv->node = ofdev->node;
370
371 err = gfar_of_init(dev);
372
373 if (err)
374 goto regs_fail;
375
376 spin_lock_init(&priv->txlock);
377 spin_lock_init(&priv->rxlock);
378 spin_lock_init(&priv->bflock);
379 INIT_WORK(&priv->reset_task, gfar_reset_task);
380
381 dev_set_drvdata(&ofdev->dev, priv);
382
383 /* Stop the DMA engine now, in case it was running before */
384 /* (The firmware could have used it, and left it running). */
385 gfar_halt(dev);
386
387 /* Reset MAC layer */
388 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
389
390 /* We need to delay at least 3 TX clocks */
391 udelay(2);
392
393 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
394 gfar_write(&priv->regs->maccfg1, tempval);
395
396 /* Initialize MACCFG2. */
397 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
398
399 /* Initialize ECNTRL */
400 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
401
402 /* Set the dev->base_addr to the gfar reg region */
403 dev->base_addr = (unsigned long) (priv->regs);
404
405 SET_NETDEV_DEV(dev, &ofdev->dev);
406
407 /* Fill in the dev structure */
408 dev->watchdog_timeo = TX_TIMEOUT;
409 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
410 dev->mtu = 1500;
411
412 dev->netdev_ops = &gfar_netdev_ops;
413 dev->ethtool_ops = &gfar_ethtool_ops;
414
415 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
416 priv->rx_csum_enable = 1;
417 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
418 } else
419 priv->rx_csum_enable = 0;
420
421 priv->vlgrp = NULL;
422
423 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
424 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
425
426 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
427 priv->extended_hash = 1;
428 priv->hash_width = 9;
429
430 priv->hash_regs[0] = &priv->regs->igaddr0;
431 priv->hash_regs[1] = &priv->regs->igaddr1;
432 priv->hash_regs[2] = &priv->regs->igaddr2;
433 priv->hash_regs[3] = &priv->regs->igaddr3;
434 priv->hash_regs[4] = &priv->regs->igaddr4;
435 priv->hash_regs[5] = &priv->regs->igaddr5;
436 priv->hash_regs[6] = &priv->regs->igaddr6;
437 priv->hash_regs[7] = &priv->regs->igaddr7;
438 priv->hash_regs[8] = &priv->regs->gaddr0;
439 priv->hash_regs[9] = &priv->regs->gaddr1;
440 priv->hash_regs[10] = &priv->regs->gaddr2;
441 priv->hash_regs[11] = &priv->regs->gaddr3;
442 priv->hash_regs[12] = &priv->regs->gaddr4;
443 priv->hash_regs[13] = &priv->regs->gaddr5;
444 priv->hash_regs[14] = &priv->regs->gaddr6;
445 priv->hash_regs[15] = &priv->regs->gaddr7;
446
447 } else {
448 priv->extended_hash = 0;
449 priv->hash_width = 8;
450
451 priv->hash_regs[0] = &priv->regs->gaddr0;
452 priv->hash_regs[1] = &priv->regs->gaddr1;
453 priv->hash_regs[2] = &priv->regs->gaddr2;
454 priv->hash_regs[3] = &priv->regs->gaddr3;
455 priv->hash_regs[4] = &priv->regs->gaddr4;
456 priv->hash_regs[5] = &priv->regs->gaddr5;
457 priv->hash_regs[6] = &priv->regs->gaddr6;
458 priv->hash_regs[7] = &priv->regs->gaddr7;
459 }
460
461 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
462 priv->padding = DEFAULT_PADDING;
463 else
464 priv->padding = 0;
465
466 if (dev->features & NETIF_F_IP_CSUM)
467 dev->hard_header_len += GMAC_FCB_LEN;
468
469 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
470 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
471 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
472 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
473
474 priv->txcoalescing = DEFAULT_TX_COALESCE;
475 priv->txic = DEFAULT_TXIC;
476 priv->rxcoalescing = DEFAULT_RX_COALESCE;
477 priv->rxic = DEFAULT_RXIC;
478
479 /* Enable most messages by default */
480 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
481
482 /* Carrier starts down, phylib will bring it up */
483 netif_carrier_off(dev);
484
485 err = register_netdev(dev);
486
487 if (err) {
488 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
489 dev->name);
490 goto register_fail;
491 }
492
493 device_init_wakeup(&dev->dev,
494 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
495
496 /* fill out IRQ number and name fields */
497 len_devname = strlen(dev->name);
498 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
499 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
500 strncpy(&priv->int_name_tx[len_devname],
501 "_tx", sizeof("_tx") + 1);
502
503 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
504 strncpy(&priv->int_name_rx[len_devname],
505 "_rx", sizeof("_rx") + 1);
506
507 strncpy(&priv->int_name_er[0], dev->name, len_devname);
508 strncpy(&priv->int_name_er[len_devname],
509 "_er", sizeof("_er") + 1);
510 } else
511 priv->int_name_tx[len_devname] = '\0';
512
513 /* Create all the sysfs files */
514 gfar_init_sysfs(dev);
515
516 /* Print out the device info */
517 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
518
519 /* Even more device info helps when determining which kernel */
520 /* provided which set of benchmarks. */
521 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
522 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
523 dev->name, priv->rx_ring_size, priv->tx_ring_size);
524
525 return 0;
526
527 register_fail:
528 iounmap(priv->regs);
529 regs_fail:
530 free_netdev(dev);
531 return err;
532 }
533
534 static int gfar_remove(struct of_device *ofdev)
535 {
536 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
537
538 dev_set_drvdata(&ofdev->dev, NULL);
539
540 iounmap(priv->regs);
541 free_netdev(priv->dev);
542
543 return 0;
544 }
545
546 #ifdef CONFIG_PM
547 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
548 {
549 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
550 struct net_device *dev = priv->dev;
551 unsigned long flags;
552 u32 tempval;
553
554 int magic_packet = priv->wol_en &&
555 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
556
557 netif_device_detach(dev);
558
559 if (netif_running(dev)) {
560 spin_lock_irqsave(&priv->txlock, flags);
561 spin_lock(&priv->rxlock);
562
563 gfar_halt_nodisable(dev);
564
565 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
566 tempval = gfar_read(&priv->regs->maccfg1);
567
568 tempval &= ~MACCFG1_TX_EN;
569
570 if (!magic_packet)
571 tempval &= ~MACCFG1_RX_EN;
572
573 gfar_write(&priv->regs->maccfg1, tempval);
574
575 spin_unlock(&priv->rxlock);
576 spin_unlock_irqrestore(&priv->txlock, flags);
577
578 napi_disable(&priv->napi);
579
580 if (magic_packet) {
581 /* Enable interrupt on Magic Packet */
582 gfar_write(&priv->regs->imask, IMASK_MAG);
583
584 /* Enable Magic Packet mode */
585 tempval = gfar_read(&priv->regs->maccfg2);
586 tempval |= MACCFG2_MPEN;
587 gfar_write(&priv->regs->maccfg2, tempval);
588 } else {
589 phy_stop(priv->phydev);
590 }
591 }
592
593 return 0;
594 }
595
596 static int gfar_resume(struct of_device *ofdev)
597 {
598 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
599 struct net_device *dev = priv->dev;
600 unsigned long flags;
601 u32 tempval;
602 int magic_packet = priv->wol_en &&
603 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
604
605 if (!netif_running(dev)) {
606 netif_device_attach(dev);
607 return 0;
608 }
609
610 if (!magic_packet && priv->phydev)
611 phy_start(priv->phydev);
612
613 /* Disable Magic Packet mode, in case something
614 * else woke us up.
615 */
616
617 spin_lock_irqsave(&priv->txlock, flags);
618 spin_lock(&priv->rxlock);
619
620 tempval = gfar_read(&priv->regs->maccfg2);
621 tempval &= ~MACCFG2_MPEN;
622 gfar_write(&priv->regs->maccfg2, tempval);
623
624 gfar_start(dev);
625
626 spin_unlock(&priv->rxlock);
627 spin_unlock_irqrestore(&priv->txlock, flags);
628
629 netif_device_attach(dev);
630
631 napi_enable(&priv->napi);
632
633 return 0;
634 }
635 #else
636 #define gfar_suspend NULL
637 #define gfar_resume NULL
638 #endif
639
640 /* Reads the controller's registers to determine what interface
641 * connects it to the PHY.
642 */
643 static phy_interface_t gfar_get_interface(struct net_device *dev)
644 {
645 struct gfar_private *priv = netdev_priv(dev);
646 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
647
648 if (ecntrl & ECNTRL_SGMII_MODE)
649 return PHY_INTERFACE_MODE_SGMII;
650
651 if (ecntrl & ECNTRL_TBI_MODE) {
652 if (ecntrl & ECNTRL_REDUCED_MODE)
653 return PHY_INTERFACE_MODE_RTBI;
654 else
655 return PHY_INTERFACE_MODE_TBI;
656 }
657
658 if (ecntrl & ECNTRL_REDUCED_MODE) {
659 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
660 return PHY_INTERFACE_MODE_RMII;
661 else {
662 phy_interface_t interface = priv->interface;
663
664 /*
665 * This isn't autodetected right now, so it must
666 * be set by the device tree or platform code.
667 */
668 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
669 return PHY_INTERFACE_MODE_RGMII_ID;
670
671 return PHY_INTERFACE_MODE_RGMII;
672 }
673 }
674
675 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
676 return PHY_INTERFACE_MODE_GMII;
677
678 return PHY_INTERFACE_MODE_MII;
679 }
680
681
682 /* Initializes driver's PHY state, and attaches to the PHY.
683 * Returns 0 on success.
684 */
685 static int init_phy(struct net_device *dev)
686 {
687 struct gfar_private *priv = netdev_priv(dev);
688 uint gigabit_support =
689 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
690 SUPPORTED_1000baseT_Full : 0;
691 struct phy_device *phydev;
692 phy_interface_t interface;
693
694 priv->oldlink = 0;
695 priv->oldspeed = 0;
696 priv->oldduplex = -1;
697
698 interface = gfar_get_interface(dev);
699
700 phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface);
701
702 if (interface == PHY_INTERFACE_MODE_SGMII)
703 gfar_configure_serdes(dev);
704
705 if (IS_ERR(phydev)) {
706 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
707 return PTR_ERR(phydev);
708 }
709
710 /* Remove any features not supported by the controller */
711 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
712 phydev->advertising = phydev->supported;
713
714 priv->phydev = phydev;
715
716 return 0;
717 }
718
719 /*
720 * Initialize TBI PHY interface for communicating with the
721 * SERDES lynx PHY on the chip. We communicate with this PHY
722 * through the MDIO bus on each controller, treating it as a
723 * "normal" PHY at the address found in the TBIPA register. We assume
724 * that the TBIPA register is valid. Either the MDIO bus code will set
725 * it to a value that doesn't conflict with other PHYs on the bus, or the
726 * value doesn't matter, as there are no other PHYs on the bus.
727 */
728 static void gfar_configure_serdes(struct net_device *dev)
729 {
730 struct gfar_private *priv = netdev_priv(dev);
731
732 if (!priv->tbiphy) {
733 printk(KERN_WARNING "SGMII mode requires that the device "
734 "tree specify a tbi-handle\n");
735 return;
736 }
737
738 /*
739 * If the link is already up, we must already be ok, and don't need to
740 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
741 * everything for us? Resetting it takes the link down and requires
742 * several seconds for it to come back.
743 */
744 if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS)
745 return;
746
747 /* Single clk mode, mii mode off(for serdes communication) */
748 phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT);
749
750 phy_write(priv->tbiphy, MII_ADVERTISE,
751 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
752 ADVERTISE_1000XPSE_ASYM);
753
754 phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE |
755 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
756 }
757
758 static void init_registers(struct net_device *dev)
759 {
760 struct gfar_private *priv = netdev_priv(dev);
761
762 /* Clear IEVENT */
763 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
764
765 /* Initialize IMASK */
766 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
767
768 /* Init hash registers to zero */
769 gfar_write(&priv->regs->igaddr0, 0);
770 gfar_write(&priv->regs->igaddr1, 0);
771 gfar_write(&priv->regs->igaddr2, 0);
772 gfar_write(&priv->regs->igaddr3, 0);
773 gfar_write(&priv->regs->igaddr4, 0);
774 gfar_write(&priv->regs->igaddr5, 0);
775 gfar_write(&priv->regs->igaddr6, 0);
776 gfar_write(&priv->regs->igaddr7, 0);
777
778 gfar_write(&priv->regs->gaddr0, 0);
779 gfar_write(&priv->regs->gaddr1, 0);
780 gfar_write(&priv->regs->gaddr2, 0);
781 gfar_write(&priv->regs->gaddr3, 0);
782 gfar_write(&priv->regs->gaddr4, 0);
783 gfar_write(&priv->regs->gaddr5, 0);
784 gfar_write(&priv->regs->gaddr6, 0);
785 gfar_write(&priv->regs->gaddr7, 0);
786
787 /* Zero out the rmon mib registers if it has them */
788 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
789 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
790
791 /* Mask off the CAM interrupts */
792 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
793 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
794 }
795
796 /* Initialize the max receive buffer length */
797 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
798
799 /* Initialize the Minimum Frame Length Register */
800 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
801 }
802
803
804 /* Halt the receive and transmit queues */
805 static void gfar_halt_nodisable(struct net_device *dev)
806 {
807 struct gfar_private *priv = netdev_priv(dev);
808 struct gfar __iomem *regs = priv->regs;
809 u32 tempval;
810
811 /* Mask all interrupts */
812 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
813
814 /* Clear all interrupts */
815 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
816
817 /* Stop the DMA, and wait for it to stop */
818 tempval = gfar_read(&priv->regs->dmactrl);
819 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
820 != (DMACTRL_GRS | DMACTRL_GTS)) {
821 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
822 gfar_write(&priv->regs->dmactrl, tempval);
823
824 while (!(gfar_read(&priv->regs->ievent) &
825 (IEVENT_GRSC | IEVENT_GTSC)))
826 cpu_relax();
827 }
828 }
829
830 /* Halt the receive and transmit queues */
831 void gfar_halt(struct net_device *dev)
832 {
833 struct gfar_private *priv = netdev_priv(dev);
834 struct gfar __iomem *regs = priv->regs;
835 u32 tempval;
836
837 gfar_halt_nodisable(dev);
838
839 /* Disable Rx and Tx */
840 tempval = gfar_read(&regs->maccfg1);
841 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
842 gfar_write(&regs->maccfg1, tempval);
843 }
844
845 void stop_gfar(struct net_device *dev)
846 {
847 struct gfar_private *priv = netdev_priv(dev);
848 struct gfar __iomem *regs = priv->regs;
849 unsigned long flags;
850
851 phy_stop(priv->phydev);
852
853 /* Lock it down */
854 spin_lock_irqsave(&priv->txlock, flags);
855 spin_lock(&priv->rxlock);
856
857 gfar_halt(dev);
858
859 spin_unlock(&priv->rxlock);
860 spin_unlock_irqrestore(&priv->txlock, flags);
861
862 /* Free the IRQs */
863 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
864 free_irq(priv->interruptError, dev);
865 free_irq(priv->interruptTransmit, dev);
866 free_irq(priv->interruptReceive, dev);
867 } else {
868 free_irq(priv->interruptTransmit, dev);
869 }
870
871 free_skb_resources(priv);
872
873 dma_free_coherent(&dev->dev,
874 sizeof(struct txbd8)*priv->tx_ring_size
875 + sizeof(struct rxbd8)*priv->rx_ring_size,
876 priv->tx_bd_base,
877 gfar_read(&regs->tbase0));
878 }
879
880 /* If there are any tx skbs or rx skbs still around, free them.
881 * Then free tx_skbuff and rx_skbuff */
882 static void free_skb_resources(struct gfar_private *priv)
883 {
884 struct rxbd8 *rxbdp;
885 struct txbd8 *txbdp;
886 int i, j;
887
888 /* Go through all the buffer descriptors and free their data buffers */
889 txbdp = priv->tx_bd_base;
890
891 for (i = 0; i < priv->tx_ring_size; i++) {
892 if (!priv->tx_skbuff[i])
893 continue;
894
895 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
896 txbdp->length, DMA_TO_DEVICE);
897 txbdp->lstatus = 0;
898 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
899 txbdp++;
900 dma_unmap_page(&priv->dev->dev, txbdp->bufPtr,
901 txbdp->length, DMA_TO_DEVICE);
902 }
903 txbdp++;
904 dev_kfree_skb_any(priv->tx_skbuff[i]);
905 priv->tx_skbuff[i] = NULL;
906 }
907
908 kfree(priv->tx_skbuff);
909
910 rxbdp = priv->rx_bd_base;
911
912 /* rx_skbuff is not guaranteed to be allocated, so only
913 * free it and its contents if it is allocated */
914 if(priv->rx_skbuff != NULL) {
915 for (i = 0; i < priv->rx_ring_size; i++) {
916 if (priv->rx_skbuff[i]) {
917 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
918 priv->rx_buffer_size,
919 DMA_FROM_DEVICE);
920
921 dev_kfree_skb_any(priv->rx_skbuff[i]);
922 priv->rx_skbuff[i] = NULL;
923 }
924
925 rxbdp->lstatus = 0;
926 rxbdp->bufPtr = 0;
927
928 rxbdp++;
929 }
930
931 kfree(priv->rx_skbuff);
932 }
933 }
934
935 void gfar_start(struct net_device *dev)
936 {
937 struct gfar_private *priv = netdev_priv(dev);
938 struct gfar __iomem *regs = priv->regs;
939 u32 tempval;
940
941 /* Enable Rx and Tx in MACCFG1 */
942 tempval = gfar_read(&regs->maccfg1);
943 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
944 gfar_write(&regs->maccfg1, tempval);
945
946 /* Initialize DMACTRL to have WWR and WOP */
947 tempval = gfar_read(&priv->regs->dmactrl);
948 tempval |= DMACTRL_INIT_SETTINGS;
949 gfar_write(&priv->regs->dmactrl, tempval);
950
951 /* Make sure we aren't stopped */
952 tempval = gfar_read(&priv->regs->dmactrl);
953 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
954 gfar_write(&priv->regs->dmactrl, tempval);
955
956 /* Clear THLT/RHLT, so that the DMA starts polling now */
957 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
958 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
959
960 /* Unmask the interrupts we look for */
961 gfar_write(&regs->imask, IMASK_DEFAULT);
962
963 dev->trans_start = jiffies;
964 }
965
966 /* Bring the controller up and running */
967 int startup_gfar(struct net_device *dev)
968 {
969 struct txbd8 *txbdp;
970 struct rxbd8 *rxbdp;
971 dma_addr_t addr = 0;
972 unsigned long vaddr;
973 int i;
974 struct gfar_private *priv = netdev_priv(dev);
975 struct gfar __iomem *regs = priv->regs;
976 int err = 0;
977 u32 rctrl = 0;
978 u32 attrs = 0;
979
980 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
981
982 /* Allocate memory for the buffer descriptors */
983 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
984 sizeof (struct txbd8) * priv->tx_ring_size +
985 sizeof (struct rxbd8) * priv->rx_ring_size,
986 &addr, GFP_KERNEL);
987
988 if (vaddr == 0) {
989 if (netif_msg_ifup(priv))
990 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
991 dev->name);
992 return -ENOMEM;
993 }
994
995 priv->tx_bd_base = (struct txbd8 *) vaddr;
996
997 /* enet DMA only understands physical addresses */
998 gfar_write(&regs->tbase0, addr);
999
1000 /* Start the rx descriptor ring where the tx ring leaves off */
1001 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
1002 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
1003 priv->rx_bd_base = (struct rxbd8 *) vaddr;
1004 gfar_write(&regs->rbase0, addr);
1005
1006 /* Setup the skbuff rings */
1007 priv->tx_skbuff =
1008 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1009 priv->tx_ring_size, GFP_KERNEL);
1010
1011 if (NULL == priv->tx_skbuff) {
1012 if (netif_msg_ifup(priv))
1013 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
1014 dev->name);
1015 err = -ENOMEM;
1016 goto tx_skb_fail;
1017 }
1018
1019 for (i = 0; i < priv->tx_ring_size; i++)
1020 priv->tx_skbuff[i] = NULL;
1021
1022 priv->rx_skbuff =
1023 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
1024 priv->rx_ring_size, GFP_KERNEL);
1025
1026 if (NULL == priv->rx_skbuff) {
1027 if (netif_msg_ifup(priv))
1028 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1029 dev->name);
1030 err = -ENOMEM;
1031 goto rx_skb_fail;
1032 }
1033
1034 for (i = 0; i < priv->rx_ring_size; i++)
1035 priv->rx_skbuff[i] = NULL;
1036
1037 /* Initialize some variables in our dev structure */
1038 priv->num_txbdfree = priv->tx_ring_size;
1039 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1040 priv->cur_rx = priv->rx_bd_base;
1041 priv->skb_curtx = priv->skb_dirtytx = 0;
1042 priv->skb_currx = 0;
1043
1044 /* Initialize Transmit Descriptor Ring */
1045 txbdp = priv->tx_bd_base;
1046 for (i = 0; i < priv->tx_ring_size; i++) {
1047 txbdp->lstatus = 0;
1048 txbdp->bufPtr = 0;
1049 txbdp++;
1050 }
1051
1052 /* Set the last descriptor in the ring to indicate wrap */
1053 txbdp--;
1054 txbdp->status |= TXBD_WRAP;
1055
1056 rxbdp = priv->rx_bd_base;
1057 for (i = 0; i < priv->rx_ring_size; i++) {
1058 struct sk_buff *skb;
1059
1060 skb = gfar_new_skb(dev);
1061
1062 if (!skb) {
1063 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1064 dev->name);
1065
1066 goto err_rxalloc_fail;
1067 }
1068
1069 priv->rx_skbuff[i] = skb;
1070
1071 gfar_new_rxbdp(dev, rxbdp, skb);
1072
1073 rxbdp++;
1074 }
1075
1076 /* Set the last descriptor in the ring to wrap */
1077 rxbdp--;
1078 rxbdp->status |= RXBD_WRAP;
1079
1080 /* If the device has multiple interrupts, register for
1081 * them. Otherwise, only register for the one */
1082 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1083 /* Install our interrupt handlers for Error,
1084 * Transmit, and Receive */
1085 if (request_irq(priv->interruptError, gfar_error,
1086 0, priv->int_name_er, dev) < 0) {
1087 if (netif_msg_intr(priv))
1088 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1089 dev->name, priv->interruptError);
1090
1091 err = -1;
1092 goto err_irq_fail;
1093 }
1094
1095 if (request_irq(priv->interruptTransmit, gfar_transmit,
1096 0, priv->int_name_tx, dev) < 0) {
1097 if (netif_msg_intr(priv))
1098 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1099 dev->name, priv->interruptTransmit);
1100
1101 err = -1;
1102
1103 goto tx_irq_fail;
1104 }
1105
1106 if (request_irq(priv->interruptReceive, gfar_receive,
1107 0, priv->int_name_rx, dev) < 0) {
1108 if (netif_msg_intr(priv))
1109 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1110 dev->name, priv->interruptReceive);
1111
1112 err = -1;
1113 goto rx_irq_fail;
1114 }
1115 } else {
1116 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1117 0, priv->int_name_tx, dev) < 0) {
1118 if (netif_msg_intr(priv))
1119 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1120 dev->name, priv->interruptTransmit);
1121
1122 err = -1;
1123 goto err_irq_fail;
1124 }
1125 }
1126
1127 phy_start(priv->phydev);
1128
1129 /* Configure the coalescing support */
1130 gfar_write(&regs->txic, 0);
1131 if (priv->txcoalescing)
1132 gfar_write(&regs->txic, priv->txic);
1133
1134 gfar_write(&regs->rxic, 0);
1135 if (priv->rxcoalescing)
1136 gfar_write(&regs->rxic, priv->rxic);
1137
1138 if (priv->rx_csum_enable)
1139 rctrl |= RCTRL_CHECKSUMMING;
1140
1141 if (priv->extended_hash) {
1142 rctrl |= RCTRL_EXTHASH;
1143
1144 gfar_clear_exact_match(dev);
1145 rctrl |= RCTRL_EMEN;
1146 }
1147
1148 if (priv->padding) {
1149 rctrl &= ~RCTRL_PAL_MASK;
1150 rctrl |= RCTRL_PADDING(priv->padding);
1151 }
1152
1153 /* Init rctrl based on our settings */
1154 gfar_write(&priv->regs->rctrl, rctrl);
1155
1156 if (dev->features & NETIF_F_IP_CSUM)
1157 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1158
1159 /* Set the extraction length and index */
1160 attrs = ATTRELI_EL(priv->rx_stash_size) |
1161 ATTRELI_EI(priv->rx_stash_index);
1162
1163 gfar_write(&priv->regs->attreli, attrs);
1164
1165 /* Start with defaults, and add stashing or locking
1166 * depending on the approprate variables */
1167 attrs = ATTR_INIT_SETTINGS;
1168
1169 if (priv->bd_stash_en)
1170 attrs |= ATTR_BDSTASH;
1171
1172 if (priv->rx_stash_size != 0)
1173 attrs |= ATTR_BUFSTASH;
1174
1175 gfar_write(&priv->regs->attr, attrs);
1176
1177 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1178 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1179 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1180
1181 /* Start the controller */
1182 gfar_start(dev);
1183
1184 return 0;
1185
1186 rx_irq_fail:
1187 free_irq(priv->interruptTransmit, dev);
1188 tx_irq_fail:
1189 free_irq(priv->interruptError, dev);
1190 err_irq_fail:
1191 err_rxalloc_fail:
1192 rx_skb_fail:
1193 free_skb_resources(priv);
1194 tx_skb_fail:
1195 dma_free_coherent(&dev->dev,
1196 sizeof(struct txbd8)*priv->tx_ring_size
1197 + sizeof(struct rxbd8)*priv->rx_ring_size,
1198 priv->tx_bd_base,
1199 gfar_read(&regs->tbase0));
1200
1201 return err;
1202 }
1203
1204 /* Called when something needs to use the ethernet device */
1205 /* Returns 0 for success. */
1206 static int gfar_enet_open(struct net_device *dev)
1207 {
1208 struct gfar_private *priv = netdev_priv(dev);
1209 int err;
1210
1211 napi_enable(&priv->napi);
1212
1213 skb_queue_head_init(&priv->rx_recycle);
1214
1215 /* Initialize a bunch of registers */
1216 init_registers(dev);
1217
1218 gfar_set_mac_address(dev);
1219
1220 err = init_phy(dev);
1221
1222 if(err) {
1223 napi_disable(&priv->napi);
1224 return err;
1225 }
1226
1227 err = startup_gfar(dev);
1228 if (err) {
1229 napi_disable(&priv->napi);
1230 return err;
1231 }
1232
1233 netif_start_queue(dev);
1234
1235 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1236
1237 return err;
1238 }
1239
1240 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1241 {
1242 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1243
1244 cacheable_memzero(fcb, GMAC_FCB_LEN);
1245
1246 return fcb;
1247 }
1248
1249 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1250 {
1251 u8 flags = 0;
1252
1253 /* If we're here, it's a IP packet with a TCP or UDP
1254 * payload. We set it to checksum, using a pseudo-header
1255 * we provide
1256 */
1257 flags = TXFCB_DEFAULT;
1258
1259 /* Tell the controller what the protocol is */
1260 /* And provide the already calculated phcs */
1261 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1262 flags |= TXFCB_UDP;
1263 fcb->phcs = udp_hdr(skb)->check;
1264 } else
1265 fcb->phcs = tcp_hdr(skb)->check;
1266
1267 /* l3os is the distance between the start of the
1268 * frame (skb->data) and the start of the IP hdr.
1269 * l4os is the distance between the start of the
1270 * l3 hdr and the l4 hdr */
1271 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1272 fcb->l4os = skb_network_header_len(skb);
1273
1274 fcb->flags = flags;
1275 }
1276
1277 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1278 {
1279 fcb->flags |= TXFCB_VLN;
1280 fcb->vlctl = vlan_tx_tag_get(skb);
1281 }
1282
1283 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1284 struct txbd8 *base, int ring_size)
1285 {
1286 struct txbd8 *new_bd = bdp + stride;
1287
1288 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1289 }
1290
1291 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1292 int ring_size)
1293 {
1294 return skip_txbd(bdp, 1, base, ring_size);
1295 }
1296
1297 /* This is called by the kernel when a frame is ready for transmission. */
1298 /* It is pointed to by the dev->hard_start_xmit function pointer */
1299 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1300 {
1301 struct gfar_private *priv = netdev_priv(dev);
1302 struct txfcb *fcb = NULL;
1303 struct txbd8 *txbdp, *txbdp_start, *base;
1304 u32 lstatus;
1305 int i;
1306 u32 bufaddr;
1307 unsigned long flags;
1308 unsigned int nr_frags, length;
1309
1310 base = priv->tx_bd_base;
1311
1312 /* total number of fragments in the SKB */
1313 nr_frags = skb_shinfo(skb)->nr_frags;
1314
1315 spin_lock_irqsave(&priv->txlock, flags);
1316
1317 /* check if there is space to queue this packet */
1318 if ((nr_frags+1) > priv->num_txbdfree) {
1319 /* no space, stop the queue */
1320 netif_stop_queue(dev);
1321 dev->stats.tx_fifo_errors++;
1322 spin_unlock_irqrestore(&priv->txlock, flags);
1323 return NETDEV_TX_BUSY;
1324 }
1325
1326 /* Update transmit stats */
1327 dev->stats.tx_bytes += skb->len;
1328
1329 txbdp = txbdp_start = priv->cur_tx;
1330
1331 if (nr_frags == 0) {
1332 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1333 } else {
1334 /* Place the fragment addresses and lengths into the TxBDs */
1335 for (i = 0; i < nr_frags; i++) {
1336 /* Point at the next BD, wrapping as needed */
1337 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1338
1339 length = skb_shinfo(skb)->frags[i].size;
1340
1341 lstatus = txbdp->lstatus | length |
1342 BD_LFLAG(TXBD_READY);
1343
1344 /* Handle the last BD specially */
1345 if (i == nr_frags - 1)
1346 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1347
1348 bufaddr = dma_map_page(&dev->dev,
1349 skb_shinfo(skb)->frags[i].page,
1350 skb_shinfo(skb)->frags[i].page_offset,
1351 length,
1352 DMA_TO_DEVICE);
1353
1354 /* set the TxBD length and buffer pointer */
1355 txbdp->bufPtr = bufaddr;
1356 txbdp->lstatus = lstatus;
1357 }
1358
1359 lstatus = txbdp_start->lstatus;
1360 }
1361
1362 /* Set up checksumming */
1363 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1364 fcb = gfar_add_fcb(skb);
1365 lstatus |= BD_LFLAG(TXBD_TOE);
1366 gfar_tx_checksum(skb, fcb);
1367 }
1368
1369 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1370 if (unlikely(NULL == fcb)) {
1371 fcb = gfar_add_fcb(skb);
1372 lstatus |= BD_LFLAG(TXBD_TOE);
1373 }
1374
1375 gfar_tx_vlan(skb, fcb);
1376 }
1377
1378 /* setup the TxBD length and buffer pointer for the first BD */
1379 priv->tx_skbuff[priv->skb_curtx] = skb;
1380 txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data,
1381 skb_headlen(skb), DMA_TO_DEVICE);
1382
1383 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1384
1385 /*
1386 * The powerpc-specific eieio() is used, as wmb() has too strong
1387 * semantics (it requires synchronization between cacheable and
1388 * uncacheable mappings, which eieio doesn't provide and which we
1389 * don't need), thus requiring a more expensive sync instruction. At
1390 * some point, the set of architecture-independent barrier functions
1391 * should be expanded to include weaker barriers.
1392 */
1393 eieio();
1394
1395 txbdp_start->lstatus = lstatus;
1396
1397 /* Update the current skb pointer to the next entry we will use
1398 * (wrapping if necessary) */
1399 priv->skb_curtx = (priv->skb_curtx + 1) &
1400 TX_RING_MOD_MASK(priv->tx_ring_size);
1401
1402 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1403
1404 /* reduce TxBD free count */
1405 priv->num_txbdfree -= (nr_frags + 1);
1406
1407 dev->trans_start = jiffies;
1408
1409 /* If the next BD still needs to be cleaned up, then the bds
1410 are full. We need to tell the kernel to stop sending us stuff. */
1411 if (!priv->num_txbdfree) {
1412 netif_stop_queue(dev);
1413
1414 dev->stats.tx_fifo_errors++;
1415 }
1416
1417 /* Tell the DMA to go go go */
1418 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1419
1420 /* Unlock priv */
1421 spin_unlock_irqrestore(&priv->txlock, flags);
1422
1423 return 0;
1424 }
1425
1426 /* Stops the kernel queue, and halts the controller */
1427 static int gfar_close(struct net_device *dev)
1428 {
1429 struct gfar_private *priv = netdev_priv(dev);
1430
1431 napi_disable(&priv->napi);
1432
1433 skb_queue_purge(&priv->rx_recycle);
1434 cancel_work_sync(&priv->reset_task);
1435 stop_gfar(dev);
1436
1437 /* Disconnect from the PHY */
1438 phy_disconnect(priv->phydev);
1439 priv->phydev = NULL;
1440
1441 netif_stop_queue(dev);
1442
1443 return 0;
1444 }
1445
1446 /* Changes the mac address if the controller is not running. */
1447 static int gfar_set_mac_address(struct net_device *dev)
1448 {
1449 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1450
1451 return 0;
1452 }
1453
1454
1455 /* Enables and disables VLAN insertion/extraction */
1456 static void gfar_vlan_rx_register(struct net_device *dev,
1457 struct vlan_group *grp)
1458 {
1459 struct gfar_private *priv = netdev_priv(dev);
1460 unsigned long flags;
1461 u32 tempval;
1462
1463 spin_lock_irqsave(&priv->rxlock, flags);
1464
1465 priv->vlgrp = grp;
1466
1467 if (grp) {
1468 /* Enable VLAN tag insertion */
1469 tempval = gfar_read(&priv->regs->tctrl);
1470 tempval |= TCTRL_VLINS;
1471
1472 gfar_write(&priv->regs->tctrl, tempval);
1473
1474 /* Enable VLAN tag extraction */
1475 tempval = gfar_read(&priv->regs->rctrl);
1476 tempval |= RCTRL_VLEX;
1477 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1478 gfar_write(&priv->regs->rctrl, tempval);
1479 } else {
1480 /* Disable VLAN tag insertion */
1481 tempval = gfar_read(&priv->regs->tctrl);
1482 tempval &= ~TCTRL_VLINS;
1483 gfar_write(&priv->regs->tctrl, tempval);
1484
1485 /* Disable VLAN tag extraction */
1486 tempval = gfar_read(&priv->regs->rctrl);
1487 tempval &= ~RCTRL_VLEX;
1488 /* If parse is no longer required, then disable parser */
1489 if (tempval & RCTRL_REQ_PARSER)
1490 tempval |= RCTRL_PRSDEP_INIT;
1491 else
1492 tempval &= ~RCTRL_PRSDEP_INIT;
1493 gfar_write(&priv->regs->rctrl, tempval);
1494 }
1495
1496 gfar_change_mtu(dev, dev->mtu);
1497
1498 spin_unlock_irqrestore(&priv->rxlock, flags);
1499 }
1500
1501 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1502 {
1503 int tempsize, tempval;
1504 struct gfar_private *priv = netdev_priv(dev);
1505 int oldsize = priv->rx_buffer_size;
1506 int frame_size = new_mtu + ETH_HLEN;
1507
1508 if (priv->vlgrp)
1509 frame_size += VLAN_HLEN;
1510
1511 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1512 if (netif_msg_drv(priv))
1513 printk(KERN_ERR "%s: Invalid MTU setting\n",
1514 dev->name);
1515 return -EINVAL;
1516 }
1517
1518 if (gfar_uses_fcb(priv))
1519 frame_size += GMAC_FCB_LEN;
1520
1521 frame_size += priv->padding;
1522
1523 tempsize =
1524 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1525 INCREMENTAL_BUFFER_SIZE;
1526
1527 /* Only stop and start the controller if it isn't already
1528 * stopped, and we changed something */
1529 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1530 stop_gfar(dev);
1531
1532 priv->rx_buffer_size = tempsize;
1533
1534 dev->mtu = new_mtu;
1535
1536 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1537 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1538
1539 /* If the mtu is larger than the max size for standard
1540 * ethernet frames (ie, a jumbo frame), then set maccfg2
1541 * to allow huge frames, and to check the length */
1542 tempval = gfar_read(&priv->regs->maccfg2);
1543
1544 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1545 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1546 else
1547 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1548
1549 gfar_write(&priv->regs->maccfg2, tempval);
1550
1551 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1552 startup_gfar(dev);
1553
1554 return 0;
1555 }
1556
1557 /* gfar_reset_task gets scheduled when a packet has not been
1558 * transmitted after a set amount of time.
1559 * For now, assume that clearing out all the structures, and
1560 * starting over will fix the problem.
1561 */
1562 static void gfar_reset_task(struct work_struct *work)
1563 {
1564 struct gfar_private *priv = container_of(work, struct gfar_private,
1565 reset_task);
1566 struct net_device *dev = priv->dev;
1567
1568 if (dev->flags & IFF_UP) {
1569 stop_gfar(dev);
1570 startup_gfar(dev);
1571 }
1572
1573 netif_tx_schedule_all(dev);
1574 }
1575
1576 static void gfar_timeout(struct net_device *dev)
1577 {
1578 struct gfar_private *priv = netdev_priv(dev);
1579
1580 dev->stats.tx_errors++;
1581 schedule_work(&priv->reset_task);
1582 }
1583
1584 /* Interrupt Handler for Transmit complete */
1585 static int gfar_clean_tx_ring(struct net_device *dev)
1586 {
1587 struct gfar_private *priv = netdev_priv(dev);
1588 struct txbd8 *bdp;
1589 struct txbd8 *lbdp = NULL;
1590 struct txbd8 *base = priv->tx_bd_base;
1591 struct sk_buff *skb;
1592 int skb_dirtytx;
1593 int tx_ring_size = priv->tx_ring_size;
1594 int frags = 0;
1595 int i;
1596 int howmany = 0;
1597 u32 lstatus;
1598
1599 bdp = priv->dirty_tx;
1600 skb_dirtytx = priv->skb_dirtytx;
1601
1602 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1603 frags = skb_shinfo(skb)->nr_frags;
1604 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1605
1606 lstatus = lbdp->lstatus;
1607
1608 /* Only clean completed frames */
1609 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1610 (lstatus & BD_LENGTH_MASK))
1611 break;
1612
1613 dma_unmap_single(&dev->dev,
1614 bdp->bufPtr,
1615 bdp->length,
1616 DMA_TO_DEVICE);
1617
1618 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1619 bdp = next_txbd(bdp, base, tx_ring_size);
1620
1621 for (i = 0; i < frags; i++) {
1622 dma_unmap_page(&dev->dev,
1623 bdp->bufPtr,
1624 bdp->length,
1625 DMA_TO_DEVICE);
1626 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1627 bdp = next_txbd(bdp, base, tx_ring_size);
1628 }
1629
1630 /*
1631 * If there's room in the queue (limit it to rx_buffer_size)
1632 * we add this skb back into the pool, if it's the right size
1633 */
1634 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1635 skb_recycle_check(skb, priv->rx_buffer_size +
1636 RXBUF_ALIGNMENT))
1637 __skb_queue_head(&priv->rx_recycle, skb);
1638 else
1639 dev_kfree_skb_any(skb);
1640
1641 priv->tx_skbuff[skb_dirtytx] = NULL;
1642
1643 skb_dirtytx = (skb_dirtytx + 1) &
1644 TX_RING_MOD_MASK(tx_ring_size);
1645
1646 howmany++;
1647 priv->num_txbdfree += frags + 1;
1648 }
1649
1650 /* If we freed a buffer, we can restart transmission, if necessary */
1651 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1652 netif_wake_queue(dev);
1653
1654 /* Update dirty indicators */
1655 priv->skb_dirtytx = skb_dirtytx;
1656 priv->dirty_tx = bdp;
1657
1658 dev->stats.tx_packets += howmany;
1659
1660 return howmany;
1661 }
1662
1663 static void gfar_schedule_cleanup(struct net_device *dev)
1664 {
1665 struct gfar_private *priv = netdev_priv(dev);
1666 unsigned long flags;
1667
1668 spin_lock_irqsave(&priv->txlock, flags);
1669 spin_lock(&priv->rxlock);
1670
1671 if (napi_schedule_prep(&priv->napi)) {
1672 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1673 __napi_schedule(&priv->napi);
1674 } else {
1675 /*
1676 * Clear IEVENT, so interrupts aren't called again
1677 * because of the packets that have already arrived.
1678 */
1679 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1680 }
1681
1682 spin_unlock(&priv->rxlock);
1683 spin_unlock_irqrestore(&priv->txlock, flags);
1684 }
1685
1686 /* Interrupt Handler for Transmit complete */
1687 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1688 {
1689 gfar_schedule_cleanup((struct net_device *)dev_id);
1690 return IRQ_HANDLED;
1691 }
1692
1693 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1694 struct sk_buff *skb)
1695 {
1696 struct gfar_private *priv = netdev_priv(dev);
1697 u32 lstatus;
1698
1699 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1700 priv->rx_buffer_size, DMA_FROM_DEVICE);
1701
1702 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1703
1704 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1705 lstatus |= BD_LFLAG(RXBD_WRAP);
1706
1707 eieio();
1708
1709 bdp->lstatus = lstatus;
1710 }
1711
1712
1713 struct sk_buff * gfar_new_skb(struct net_device *dev)
1714 {
1715 unsigned int alignamount;
1716 struct gfar_private *priv = netdev_priv(dev);
1717 struct sk_buff *skb = NULL;
1718
1719 skb = __skb_dequeue(&priv->rx_recycle);
1720 if (!skb)
1721 skb = netdev_alloc_skb(dev,
1722 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1723
1724 if (!skb)
1725 return NULL;
1726
1727 alignamount = RXBUF_ALIGNMENT -
1728 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1729
1730 /* We need the data buffer to be aligned properly. We will reserve
1731 * as many bytes as needed to align the data properly
1732 */
1733 skb_reserve(skb, alignamount);
1734
1735 return skb;
1736 }
1737
1738 static inline void count_errors(unsigned short status, struct net_device *dev)
1739 {
1740 struct gfar_private *priv = netdev_priv(dev);
1741 struct net_device_stats *stats = &dev->stats;
1742 struct gfar_extra_stats *estats = &priv->extra_stats;
1743
1744 /* If the packet was truncated, none of the other errors
1745 * matter */
1746 if (status & RXBD_TRUNCATED) {
1747 stats->rx_length_errors++;
1748
1749 estats->rx_trunc++;
1750
1751 return;
1752 }
1753 /* Count the errors, if there were any */
1754 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1755 stats->rx_length_errors++;
1756
1757 if (status & RXBD_LARGE)
1758 estats->rx_large++;
1759 else
1760 estats->rx_short++;
1761 }
1762 if (status & RXBD_NONOCTET) {
1763 stats->rx_frame_errors++;
1764 estats->rx_nonoctet++;
1765 }
1766 if (status & RXBD_CRCERR) {
1767 estats->rx_crcerr++;
1768 stats->rx_crc_errors++;
1769 }
1770 if (status & RXBD_OVERRUN) {
1771 estats->rx_overrun++;
1772 stats->rx_crc_errors++;
1773 }
1774 }
1775
1776 irqreturn_t gfar_receive(int irq, void *dev_id)
1777 {
1778 gfar_schedule_cleanup((struct net_device *)dev_id);
1779 return IRQ_HANDLED;
1780 }
1781
1782 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1783 {
1784 /* If valid headers were found, and valid sums
1785 * were verified, then we tell the kernel that no
1786 * checksumming is necessary. Otherwise, it is */
1787 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1788 skb->ip_summed = CHECKSUM_UNNECESSARY;
1789 else
1790 skb->ip_summed = CHECKSUM_NONE;
1791 }
1792
1793
1794 /* gfar_process_frame() -- handle one incoming packet if skb
1795 * isn't NULL. */
1796 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1797 int amount_pull)
1798 {
1799 struct gfar_private *priv = netdev_priv(dev);
1800 struct rxfcb *fcb = NULL;
1801
1802 int ret;
1803
1804 /* fcb is at the beginning if exists */
1805 fcb = (struct rxfcb *)skb->data;
1806
1807 /* Remove the FCB from the skb */
1808 /* Remove the padded bytes, if there are any */
1809 if (amount_pull)
1810 skb_pull(skb, amount_pull);
1811
1812 if (priv->rx_csum_enable)
1813 gfar_rx_checksum(skb, fcb);
1814
1815 /* Tell the skb what kind of packet this is */
1816 skb->protocol = eth_type_trans(skb, dev);
1817
1818 /* Send the packet up the stack */
1819 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1820 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1821 else
1822 ret = netif_receive_skb(skb);
1823
1824 if (NET_RX_DROP == ret)
1825 priv->extra_stats.kernel_dropped++;
1826
1827 return 0;
1828 }
1829
1830 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1831 * until the budget/quota has been reached. Returns the number
1832 * of frames handled
1833 */
1834 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1835 {
1836 struct rxbd8 *bdp, *base;
1837 struct sk_buff *skb;
1838 int pkt_len;
1839 int amount_pull;
1840 int howmany = 0;
1841 struct gfar_private *priv = netdev_priv(dev);
1842
1843 /* Get the first full descriptor */
1844 bdp = priv->cur_rx;
1845 base = priv->rx_bd_base;
1846
1847 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1848 priv->padding;
1849
1850 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1851 struct sk_buff *newskb;
1852 rmb();
1853
1854 /* Add another skb for the future */
1855 newskb = gfar_new_skb(dev);
1856
1857 skb = priv->rx_skbuff[priv->skb_currx];
1858
1859 dma_unmap_single(&priv->dev->dev, bdp->bufPtr,
1860 priv->rx_buffer_size, DMA_FROM_DEVICE);
1861
1862 /* We drop the frame if we failed to allocate a new buffer */
1863 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1864 bdp->status & RXBD_ERR)) {
1865 count_errors(bdp->status, dev);
1866
1867 if (unlikely(!newskb))
1868 newskb = skb;
1869 else if (skb)
1870 __skb_queue_head(&priv->rx_recycle, skb);
1871 } else {
1872 /* Increment the number of packets */
1873 dev->stats.rx_packets++;
1874 howmany++;
1875
1876 if (likely(skb)) {
1877 pkt_len = bdp->length - ETH_FCS_LEN;
1878 /* Remove the FCS from the packet length */
1879 skb_put(skb, pkt_len);
1880 dev->stats.rx_bytes += pkt_len;
1881
1882 if (in_irq() || irqs_disabled())
1883 printk("Interrupt problem!\n");
1884 gfar_process_frame(dev, skb, amount_pull);
1885
1886 } else {
1887 if (netif_msg_rx_err(priv))
1888 printk(KERN_WARNING
1889 "%s: Missing skb!\n", dev->name);
1890 dev->stats.rx_dropped++;
1891 priv->extra_stats.rx_skbmissing++;
1892 }
1893
1894 }
1895
1896 priv->rx_skbuff[priv->skb_currx] = newskb;
1897
1898 /* Setup the new bdp */
1899 gfar_new_rxbdp(dev, bdp, newskb);
1900
1901 /* Update to the next pointer */
1902 bdp = next_bd(bdp, base, priv->rx_ring_size);
1903
1904 /* update to point at the next skb */
1905 priv->skb_currx =
1906 (priv->skb_currx + 1) &
1907 RX_RING_MOD_MASK(priv->rx_ring_size);
1908 }
1909
1910 /* Update the current rxbd pointer to be the next one */
1911 priv->cur_rx = bdp;
1912
1913 return howmany;
1914 }
1915
1916 static int gfar_poll(struct napi_struct *napi, int budget)
1917 {
1918 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1919 struct net_device *dev = priv->dev;
1920 int tx_cleaned = 0;
1921 int rx_cleaned = 0;
1922 unsigned long flags;
1923
1924 /* Clear IEVENT, so interrupts aren't called again
1925 * because of the packets that have already arrived */
1926 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1927
1928 /* If we fail to get the lock, don't bother with the TX BDs */
1929 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1930 tx_cleaned = gfar_clean_tx_ring(dev);
1931 spin_unlock_irqrestore(&priv->txlock, flags);
1932 }
1933
1934 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1935
1936 if (tx_cleaned)
1937 return budget;
1938
1939 if (rx_cleaned < budget) {
1940 napi_complete(napi);
1941
1942 /* Clear the halt bit in RSTAT */
1943 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1944
1945 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1946
1947 /* If we are coalescing interrupts, update the timer */
1948 /* Otherwise, clear it */
1949 if (likely(priv->rxcoalescing)) {
1950 gfar_write(&priv->regs->rxic, 0);
1951 gfar_write(&priv->regs->rxic, priv->rxic);
1952 }
1953 if (likely(priv->txcoalescing)) {
1954 gfar_write(&priv->regs->txic, 0);
1955 gfar_write(&priv->regs->txic, priv->txic);
1956 }
1957 }
1958
1959 return rx_cleaned;
1960 }
1961
1962 #ifdef CONFIG_NET_POLL_CONTROLLER
1963 /*
1964 * Polling 'interrupt' - used by things like netconsole to send skbs
1965 * without having to re-enable interrupts. It's not called while
1966 * the interrupt routine is executing.
1967 */
1968 static void gfar_netpoll(struct net_device *dev)
1969 {
1970 struct gfar_private *priv = netdev_priv(dev);
1971
1972 /* If the device has multiple interrupts, run tx/rx */
1973 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1974 disable_irq(priv->interruptTransmit);
1975 disable_irq(priv->interruptReceive);
1976 disable_irq(priv->interruptError);
1977 gfar_interrupt(priv->interruptTransmit, dev);
1978 enable_irq(priv->interruptError);
1979 enable_irq(priv->interruptReceive);
1980 enable_irq(priv->interruptTransmit);
1981 } else {
1982 disable_irq(priv->interruptTransmit);
1983 gfar_interrupt(priv->interruptTransmit, dev);
1984 enable_irq(priv->interruptTransmit);
1985 }
1986 }
1987 #endif
1988
1989 /* The interrupt handler for devices with one interrupt */
1990 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1991 {
1992 struct net_device *dev = dev_id;
1993 struct gfar_private *priv = netdev_priv(dev);
1994
1995 /* Save ievent for future reference */
1996 u32 events = gfar_read(&priv->regs->ievent);
1997
1998 /* Check for reception */
1999 if (events & IEVENT_RX_MASK)
2000 gfar_receive(irq, dev_id);
2001
2002 /* Check for transmit completion */
2003 if (events & IEVENT_TX_MASK)
2004 gfar_transmit(irq, dev_id);
2005
2006 /* Check for errors */
2007 if (events & IEVENT_ERR_MASK)
2008 gfar_error(irq, dev_id);
2009
2010 return IRQ_HANDLED;
2011 }
2012
2013 /* Called every time the controller might need to be made
2014 * aware of new link state. The PHY code conveys this
2015 * information through variables in the phydev structure, and this
2016 * function converts those variables into the appropriate
2017 * register values, and can bring down the device if needed.
2018 */
2019 static void adjust_link(struct net_device *dev)
2020 {
2021 struct gfar_private *priv = netdev_priv(dev);
2022 struct gfar __iomem *regs = priv->regs;
2023 unsigned long flags;
2024 struct phy_device *phydev = priv->phydev;
2025 int new_state = 0;
2026
2027 spin_lock_irqsave(&priv->txlock, flags);
2028 if (phydev->link) {
2029 u32 tempval = gfar_read(&regs->maccfg2);
2030 u32 ecntrl = gfar_read(&regs->ecntrl);
2031
2032 /* Now we make sure that we can be in full duplex mode.
2033 * If not, we operate in half-duplex mode. */
2034 if (phydev->duplex != priv->oldduplex) {
2035 new_state = 1;
2036 if (!(phydev->duplex))
2037 tempval &= ~(MACCFG2_FULL_DUPLEX);
2038 else
2039 tempval |= MACCFG2_FULL_DUPLEX;
2040
2041 priv->oldduplex = phydev->duplex;
2042 }
2043
2044 if (phydev->speed != priv->oldspeed) {
2045 new_state = 1;
2046 switch (phydev->speed) {
2047 case 1000:
2048 tempval =
2049 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2050
2051 ecntrl &= ~(ECNTRL_R100);
2052 break;
2053 case 100:
2054 case 10:
2055 tempval =
2056 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2057
2058 /* Reduced mode distinguishes
2059 * between 10 and 100 */
2060 if (phydev->speed == SPEED_100)
2061 ecntrl |= ECNTRL_R100;
2062 else
2063 ecntrl &= ~(ECNTRL_R100);
2064 break;
2065 default:
2066 if (netif_msg_link(priv))
2067 printk(KERN_WARNING
2068 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2069 dev->name, phydev->speed);
2070 break;
2071 }
2072
2073 priv->oldspeed = phydev->speed;
2074 }
2075
2076 gfar_write(&regs->maccfg2, tempval);
2077 gfar_write(&regs->ecntrl, ecntrl);
2078
2079 if (!priv->oldlink) {
2080 new_state = 1;
2081 priv->oldlink = 1;
2082 }
2083 } else if (priv->oldlink) {
2084 new_state = 1;
2085 priv->oldlink = 0;
2086 priv->oldspeed = 0;
2087 priv->oldduplex = -1;
2088 }
2089
2090 if (new_state && netif_msg_link(priv))
2091 phy_print_status(phydev);
2092
2093 spin_unlock_irqrestore(&priv->txlock, flags);
2094 }
2095
2096 /* Update the hash table based on the current list of multicast
2097 * addresses we subscribe to. Also, change the promiscuity of
2098 * the device based on the flags (this function is called
2099 * whenever dev->flags is changed */
2100 static void gfar_set_multi(struct net_device *dev)
2101 {
2102 struct dev_mc_list *mc_ptr;
2103 struct gfar_private *priv = netdev_priv(dev);
2104 struct gfar __iomem *regs = priv->regs;
2105 u32 tempval;
2106
2107 if(dev->flags & IFF_PROMISC) {
2108 /* Set RCTRL to PROM */
2109 tempval = gfar_read(&regs->rctrl);
2110 tempval |= RCTRL_PROM;
2111 gfar_write(&regs->rctrl, tempval);
2112 } else {
2113 /* Set RCTRL to not PROM */
2114 tempval = gfar_read(&regs->rctrl);
2115 tempval &= ~(RCTRL_PROM);
2116 gfar_write(&regs->rctrl, tempval);
2117 }
2118
2119 if(dev->flags & IFF_ALLMULTI) {
2120 /* Set the hash to rx all multicast frames */
2121 gfar_write(&regs->igaddr0, 0xffffffff);
2122 gfar_write(&regs->igaddr1, 0xffffffff);
2123 gfar_write(&regs->igaddr2, 0xffffffff);
2124 gfar_write(&regs->igaddr3, 0xffffffff);
2125 gfar_write(&regs->igaddr4, 0xffffffff);
2126 gfar_write(&regs->igaddr5, 0xffffffff);
2127 gfar_write(&regs->igaddr6, 0xffffffff);
2128 gfar_write(&regs->igaddr7, 0xffffffff);
2129 gfar_write(&regs->gaddr0, 0xffffffff);
2130 gfar_write(&regs->gaddr1, 0xffffffff);
2131 gfar_write(&regs->gaddr2, 0xffffffff);
2132 gfar_write(&regs->gaddr3, 0xffffffff);
2133 gfar_write(&regs->gaddr4, 0xffffffff);
2134 gfar_write(&regs->gaddr5, 0xffffffff);
2135 gfar_write(&regs->gaddr6, 0xffffffff);
2136 gfar_write(&regs->gaddr7, 0xffffffff);
2137 } else {
2138 int em_num;
2139 int idx;
2140
2141 /* zero out the hash */
2142 gfar_write(&regs->igaddr0, 0x0);
2143 gfar_write(&regs->igaddr1, 0x0);
2144 gfar_write(&regs->igaddr2, 0x0);
2145 gfar_write(&regs->igaddr3, 0x0);
2146 gfar_write(&regs->igaddr4, 0x0);
2147 gfar_write(&regs->igaddr5, 0x0);
2148 gfar_write(&regs->igaddr6, 0x0);
2149 gfar_write(&regs->igaddr7, 0x0);
2150 gfar_write(&regs->gaddr0, 0x0);
2151 gfar_write(&regs->gaddr1, 0x0);
2152 gfar_write(&regs->gaddr2, 0x0);
2153 gfar_write(&regs->gaddr3, 0x0);
2154 gfar_write(&regs->gaddr4, 0x0);
2155 gfar_write(&regs->gaddr5, 0x0);
2156 gfar_write(&regs->gaddr6, 0x0);
2157 gfar_write(&regs->gaddr7, 0x0);
2158
2159 /* If we have extended hash tables, we need to
2160 * clear the exact match registers to prepare for
2161 * setting them */
2162 if (priv->extended_hash) {
2163 em_num = GFAR_EM_NUM + 1;
2164 gfar_clear_exact_match(dev);
2165 idx = 1;
2166 } else {
2167 idx = 0;
2168 em_num = 0;
2169 }
2170
2171 if(dev->mc_count == 0)
2172 return;
2173
2174 /* Parse the list, and set the appropriate bits */
2175 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2176 if (idx < em_num) {
2177 gfar_set_mac_for_addr(dev, idx,
2178 mc_ptr->dmi_addr);
2179 idx++;
2180 } else
2181 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2182 }
2183 }
2184
2185 return;
2186 }
2187
2188
2189 /* Clears each of the exact match registers to zero, so they
2190 * don't interfere with normal reception */
2191 static void gfar_clear_exact_match(struct net_device *dev)
2192 {
2193 int idx;
2194 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2195
2196 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2197 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2198 }
2199
2200 /* Set the appropriate hash bit for the given addr */
2201 /* The algorithm works like so:
2202 * 1) Take the Destination Address (ie the multicast address), and
2203 * do a CRC on it (little endian), and reverse the bits of the
2204 * result.
2205 * 2) Use the 8 most significant bits as a hash into a 256-entry
2206 * table. The table is controlled through 8 32-bit registers:
2207 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2208 * gaddr7. This means that the 3 most significant bits in the
2209 * hash index which gaddr register to use, and the 5 other bits
2210 * indicate which bit (assuming an IBM numbering scheme, which
2211 * for PowerPC (tm) is usually the case) in the register holds
2212 * the entry. */
2213 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2214 {
2215 u32 tempval;
2216 struct gfar_private *priv = netdev_priv(dev);
2217 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2218 int width = priv->hash_width;
2219 u8 whichbit = (result >> (32 - width)) & 0x1f;
2220 u8 whichreg = result >> (32 - width + 5);
2221 u32 value = (1 << (31-whichbit));
2222
2223 tempval = gfar_read(priv->hash_regs[whichreg]);
2224 tempval |= value;
2225 gfar_write(priv->hash_regs[whichreg], tempval);
2226
2227 return;
2228 }
2229
2230
2231 /* There are multiple MAC Address register pairs on some controllers
2232 * This function sets the numth pair to a given address
2233 */
2234 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2235 {
2236 struct gfar_private *priv = netdev_priv(dev);
2237 int idx;
2238 char tmpbuf[MAC_ADDR_LEN];
2239 u32 tempval;
2240 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2241
2242 macptr += num*2;
2243
2244 /* Now copy it into the mac registers backwards, cuz */
2245 /* little endian is silly */
2246 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2247 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2248
2249 gfar_write(macptr, *((u32 *) (tmpbuf)));
2250
2251 tempval = *((u32 *) (tmpbuf + 4));
2252
2253 gfar_write(macptr+1, tempval);
2254 }
2255
2256 /* GFAR error interrupt handler */
2257 static irqreturn_t gfar_error(int irq, void *dev_id)
2258 {
2259 struct net_device *dev = dev_id;
2260 struct gfar_private *priv = netdev_priv(dev);
2261
2262 /* Save ievent for future reference */
2263 u32 events = gfar_read(&priv->regs->ievent);
2264
2265 /* Clear IEVENT */
2266 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2267
2268 /* Magic Packet is not an error. */
2269 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2270 (events & IEVENT_MAG))
2271 events &= ~IEVENT_MAG;
2272
2273 /* Hmm... */
2274 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2275 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2276 dev->name, events, gfar_read(&priv->regs->imask));
2277
2278 /* Update the error counters */
2279 if (events & IEVENT_TXE) {
2280 dev->stats.tx_errors++;
2281
2282 if (events & IEVENT_LC)
2283 dev->stats.tx_window_errors++;
2284 if (events & IEVENT_CRL)
2285 dev->stats.tx_aborted_errors++;
2286 if (events & IEVENT_XFUN) {
2287 if (netif_msg_tx_err(priv))
2288 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2289 "packet dropped.\n", dev->name);
2290 dev->stats.tx_dropped++;
2291 priv->extra_stats.tx_underrun++;
2292
2293 /* Reactivate the Tx Queues */
2294 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2295 }
2296 if (netif_msg_tx_err(priv))
2297 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2298 }
2299 if (events & IEVENT_BSY) {
2300 dev->stats.rx_errors++;
2301 priv->extra_stats.rx_bsy++;
2302
2303 gfar_receive(irq, dev_id);
2304
2305 if (netif_msg_rx_err(priv))
2306 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2307 dev->name, gfar_read(&priv->regs->rstat));
2308 }
2309 if (events & IEVENT_BABR) {
2310 dev->stats.rx_errors++;
2311 priv->extra_stats.rx_babr++;
2312
2313 if (netif_msg_rx_err(priv))
2314 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2315 }
2316 if (events & IEVENT_EBERR) {
2317 priv->extra_stats.eberr++;
2318 if (netif_msg_rx_err(priv))
2319 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2320 }
2321 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2322 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2323
2324 if (events & IEVENT_BABT) {
2325 priv->extra_stats.tx_babt++;
2326 if (netif_msg_tx_err(priv))
2327 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2328 }
2329 return IRQ_HANDLED;
2330 }
2331
2332 /* work with hotplug and coldplug */
2333 MODULE_ALIAS("platform:fsl-gianfar");
2334
2335 static struct of_device_id gfar_match[] =
2336 {
2337 {
2338 .type = "network",
2339 .compatible = "gianfar",
2340 },
2341 {},
2342 };
2343
2344 /* Structure for a device driver */
2345 static struct of_platform_driver gfar_driver = {
2346 .name = "fsl-gianfar",
2347 .match_table = gfar_match,
2348
2349 .probe = gfar_probe,
2350 .remove = gfar_remove,
2351 .suspend = gfar_suspend,
2352 .resume = gfar_resume,
2353 };
2354
2355 static int __init gfar_init(void)
2356 {
2357 return of_register_platform_driver(&gfar_driver);
2358 }
2359
2360 static void __exit gfar_exit(void)
2361 {
2362 of_unregister_platform_driver(&gfar_driver);
2363 }
2364
2365 module_init(gfar_init);
2366 module_exit(gfar_exit);
2367
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