1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
48 #include <net/mac80211.h>
50 #include <asm/div64.h>
52 #define DRV_NAME "iwlagn"
54 #include "iwl-eeprom.h"
58 #include "iwl-helpers.h"
60 #include "iwl-calib.h"
64 /******************************************************************************
68 ******************************************************************************/
71 * module name, copyright, version, etc.
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75 #ifdef CONFIG_IWLWIFI_DEBUG
81 #define DRV_VERSION IWLWIFI_VERSION VD
84 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
85 MODULE_VERSION(DRV_VERSION
);
86 MODULE_AUTHOR(DRV_COPYRIGHT
" " DRV_AUTHOR
);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
90 static int iwlagn_ant_coupling
;
91 static bool iwlagn_bt_ch_announce
= 1;
94 * iwl_commit_rxon - commit staging_rxon to hardware
96 * The RXON command in staging_rxon is committed to the hardware and
97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
101 int iwl_commit_rxon(struct iwl_priv
*priv
, struct iwl_rxon_context
*ctx
)
103 /* cast away the const for active_rxon in this function */
104 struct iwl_rxon_cmd
*active_rxon
= (void *)&ctx
->active
;
107 !!(ctx
->staging
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
108 bool old_assoc
= !!(ctx
->active
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
110 if (!iwl_is_alive(priv
))
113 /* always get timestamp with Rx frame */
114 ctx
->staging
.flags
|= RXON_FLG_TSF2HOST_MSK
;
116 ret
= iwl_check_rxon_cmd(priv
, ctx
);
118 IWL_ERR(priv
, "Invalid RXON configuration. Not committing.\n");
123 * receive commit_rxon request
124 * abort any previous channel switch if still in process
126 if (priv
->switch_rxon
.switch_in_progress
&&
127 (priv
->switch_rxon
.channel
!= ctx
->staging
.channel
)) {
128 IWL_DEBUG_11H(priv
, "abort channel switch on %d\n",
129 le16_to_cpu(priv
->switch_rxon
.channel
));
130 iwl_chswitch_done(priv
, false);
133 /* If we don't need to send a full RXON, we can use
134 * iwl_rxon_assoc_cmd which is used to reconfigure filter
135 * and other flags for the current radio configuration. */
136 if (!iwl_full_rxon_required(priv
, ctx
)) {
137 ret
= iwl_send_rxon_assoc(priv
, ctx
);
139 IWL_ERR(priv
, "Error setting RXON_ASSOC (%d)\n", ret
);
143 memcpy(active_rxon
, &ctx
->staging
, sizeof(*active_rxon
));
144 iwl_print_rx_config_cmd(priv
, ctx
);
148 /* If we are currently associated and the new config requires
149 * an RXON_ASSOC and the new config wants the associated mask enabled,
150 * we must clear the associated from the active configuration
151 * before we apply the new config */
152 if (iwl_is_associated_ctx(ctx
) && new_assoc
) {
153 IWL_DEBUG_INFO(priv
, "Toggling associated bit on current RXON\n");
154 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
156 ret
= iwl_send_cmd_pdu(priv
, ctx
->rxon_cmd
,
157 sizeof(struct iwl_rxon_cmd
),
160 /* If the mask clearing failed then we set
161 * active_rxon back to what it was previously */
163 active_rxon
->filter_flags
|= RXON_FILTER_ASSOC_MSK
;
164 IWL_ERR(priv
, "Error clearing ASSOC_MSK (%d)\n", ret
);
167 iwl_clear_ucode_stations(priv
, ctx
);
168 iwl_restore_stations(priv
, ctx
);
169 ret
= iwl_restore_default_wep_keys(priv
, ctx
);
171 IWL_ERR(priv
, "Failed to restore WEP keys (%d)\n", ret
);
176 IWL_DEBUG_INFO(priv
, "Sending RXON\n"
177 "* with%s RXON_FILTER_ASSOC_MSK\n"
180 (new_assoc
? "" : "out"),
181 le16_to_cpu(ctx
->staging
.channel
),
182 ctx
->staging
.bssid_addr
);
184 iwl_set_rxon_hwcrypto(priv
, ctx
, !priv
->cfg
->mod_params
->sw_crypto
);
188 * First of all, before setting associated, we need to
189 * send RXON timing so the device knows about the DTIM
190 * period and other timing values
192 ret
= iwl_send_rxon_timing(priv
, ctx
);
194 IWL_ERR(priv
, "Error setting RXON timing!\n");
199 if (priv
->cfg
->ops
->hcmd
->set_pan_params
) {
200 ret
= priv
->cfg
->ops
->hcmd
->set_pan_params(priv
);
205 /* Apply the new configuration
206 * RXON unassoc clears the station table in uCode so restoration of
207 * stations is needed after it (the RXON command) completes
210 ret
= iwl_send_cmd_pdu(priv
, ctx
->rxon_cmd
,
211 sizeof(struct iwl_rxon_cmd
), &ctx
->staging
);
213 IWL_ERR(priv
, "Error setting new RXON (%d)\n", ret
);
216 IWL_DEBUG_INFO(priv
, "Return from !new_assoc RXON.\n");
217 memcpy(active_rxon
, &ctx
->staging
, sizeof(*active_rxon
));
218 iwl_clear_ucode_stations(priv
, ctx
);
219 iwl_restore_stations(priv
, ctx
);
220 ret
= iwl_restore_default_wep_keys(priv
, ctx
);
222 IWL_ERR(priv
, "Failed to restore WEP keys (%d)\n", ret
);
227 priv
->start_calib
= 0;
229 /* Apply the new configuration
230 * RXON assoc doesn't clear the station table in uCode,
232 ret
= iwl_send_cmd_pdu(priv
, ctx
->rxon_cmd
,
233 sizeof(struct iwl_rxon_cmd
), &ctx
->staging
);
235 IWL_ERR(priv
, "Error setting new RXON (%d)\n", ret
);
238 memcpy(active_rxon
, &ctx
->staging
, sizeof(*active_rxon
));
240 iwl_print_rx_config_cmd(priv
, ctx
);
242 iwl_init_sensitivity(priv
);
244 /* If we issue a new RXON command which required a tune then we must
245 * send a new TXPOWER command or we won't be able to Tx any frames */
246 ret
= iwl_set_tx_power(priv
, priv
->tx_power_user_lmt
, true);
248 IWL_ERR(priv
, "Error sending TX power (%d)\n", ret
);
255 void iwl_update_chain_flags(struct iwl_priv
*priv
)
257 struct iwl_rxon_context
*ctx
;
259 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
) {
260 for_each_context(priv
, ctx
) {
261 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
262 iwlcore_commit_rxon(priv
, ctx
);
267 static void iwl_clear_free_frames(struct iwl_priv
*priv
)
269 struct list_head
*element
;
271 IWL_DEBUG_INFO(priv
, "%d frames on pre-allocated heap on clear.\n",
274 while (!list_empty(&priv
->free_frames
)) {
275 element
= priv
->free_frames
.next
;
277 kfree(list_entry(element
, struct iwl_frame
, list
));
278 priv
->frames_count
--;
281 if (priv
->frames_count
) {
282 IWL_WARN(priv
, "%d frames still in use. Did we lose one?\n",
284 priv
->frames_count
= 0;
288 static struct iwl_frame
*iwl_get_free_frame(struct iwl_priv
*priv
)
290 struct iwl_frame
*frame
;
291 struct list_head
*element
;
292 if (list_empty(&priv
->free_frames
)) {
293 frame
= kzalloc(sizeof(*frame
), GFP_KERNEL
);
295 IWL_ERR(priv
, "Could not allocate frame!\n");
299 priv
->frames_count
++;
303 element
= priv
->free_frames
.next
;
305 return list_entry(element
, struct iwl_frame
, list
);
308 static void iwl_free_frame(struct iwl_priv
*priv
, struct iwl_frame
*frame
)
310 memset(frame
, 0, sizeof(*frame
));
311 list_add(&frame
->list
, &priv
->free_frames
);
314 static u32
iwl_fill_beacon_frame(struct iwl_priv
*priv
,
315 struct ieee80211_hdr
*hdr
,
318 if (!priv
->ibss_beacon
)
321 if (priv
->ibss_beacon
->len
> left
)
324 memcpy(hdr
, priv
->ibss_beacon
->data
, priv
->ibss_beacon
->len
);
326 return priv
->ibss_beacon
->len
;
329 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
330 static void iwl_set_beacon_tim(struct iwl_priv
*priv
,
331 struct iwl_tx_beacon_cmd
*tx_beacon_cmd
,
332 u8
*beacon
, u32 frame_size
)
335 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)beacon
;
338 * The index is relative to frame start but we start looking at the
339 * variable-length part of the beacon.
341 tim_idx
= mgmt
->u
.beacon
.variable
- beacon
;
343 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
344 while ((tim_idx
< (frame_size
- 2)) &&
345 (beacon
[tim_idx
] != WLAN_EID_TIM
))
346 tim_idx
+= beacon
[tim_idx
+1] + 2;
348 /* If TIM field was found, set variables */
349 if ((tim_idx
< (frame_size
- 1)) && (beacon
[tim_idx
] == WLAN_EID_TIM
)) {
350 tx_beacon_cmd
->tim_idx
= cpu_to_le16(tim_idx
);
351 tx_beacon_cmd
->tim_size
= beacon
[tim_idx
+1];
353 IWL_WARN(priv
, "Unable to find TIM Element in beacon\n");
356 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv
*priv
,
357 struct iwl_frame
*frame
)
359 struct iwl_tx_beacon_cmd
*tx_beacon_cmd
;
364 * We have to set up the TX command, the TX Beacon command, and the
368 lockdep_assert_held(&priv
->mutex
);
370 if (!priv
->beacon_ctx
) {
371 IWL_ERR(priv
, "trying to build beacon w/o beacon context!\n");
375 /* Initialize memory */
376 tx_beacon_cmd
= &frame
->u
.beacon
;
377 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
379 /* Set up TX beacon contents */
380 frame_size
= iwl_fill_beacon_frame(priv
, tx_beacon_cmd
->frame
,
381 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
382 if (WARN_ON_ONCE(frame_size
> MAX_MPDU_SIZE
))
385 /* Set up TX command fields */
386 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
387 tx_beacon_cmd
->tx
.sta_id
= priv
->beacon_ctx
->bcast_sta_id
;
388 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
389 tx_beacon_cmd
->tx
.tx_flags
= TX_CMD_FLG_SEQ_CTL_MSK
|
390 TX_CMD_FLG_TSF_MSK
| TX_CMD_FLG_STA_RATE_MSK
;
392 /* Set up TX beacon command fields */
393 iwl_set_beacon_tim(priv
, tx_beacon_cmd
, (u8
*)tx_beacon_cmd
->frame
,
396 /* Set up packet rate and flags */
397 rate
= iwl_rate_get_lowest_plcp(priv
, priv
->beacon_ctx
);
398 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
,
399 priv
->hw_params
.valid_tx_ant
);
400 rate_flags
= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
401 if ((rate
>= IWL_FIRST_CCK_RATE
) && (rate
<= IWL_LAST_CCK_RATE
))
402 rate_flags
|= RATE_MCS_CCK_MSK
;
403 tx_beacon_cmd
->tx
.rate_n_flags
= iwl_hw_set_rate_n_flags(rate
,
406 return sizeof(*tx_beacon_cmd
) + frame_size
;
408 static int iwl_send_beacon_cmd(struct iwl_priv
*priv
)
410 struct iwl_frame
*frame
;
411 unsigned int frame_size
;
414 frame
= iwl_get_free_frame(priv
);
416 IWL_ERR(priv
, "Could not obtain free frame buffer for beacon "
421 frame_size
= iwl_hw_get_beacon_cmd(priv
, frame
);
423 IWL_ERR(priv
, "Error configuring the beacon command\n");
424 iwl_free_frame(priv
, frame
);
428 rc
= iwl_send_cmd_pdu(priv
, REPLY_TX_BEACON
, frame_size
,
431 iwl_free_frame(priv
, frame
);
436 static inline dma_addr_t
iwl_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
438 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
440 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
441 if (sizeof(dma_addr_t
) > sizeof(u32
))
443 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
448 static inline u16
iwl_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
450 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
452 return le16_to_cpu(tb
->hi_n_len
) >> 4;
455 static inline void iwl_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
456 dma_addr_t addr
, u16 len
)
458 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
459 u16 hi_n_len
= len
<< 4;
461 put_unaligned_le32(addr
, &tb
->lo
);
462 if (sizeof(dma_addr_t
) > sizeof(u32
))
463 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
465 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
467 tfd
->num_tbs
= idx
+ 1;
470 static inline u8
iwl_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
472 return tfd
->num_tbs
& 0x1f;
476 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
477 * @priv - driver private data
480 * Does NOT advance any TFD circular buffer read/write indexes
481 * Does NOT free the TFD itself (which is within circular buffer)
483 void iwl_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
485 struct iwl_tfd
*tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
487 struct pci_dev
*dev
= priv
->pci_dev
;
488 int index
= txq
->q
.read_ptr
;
492 tfd
= &tfd_tmp
[index
];
494 /* Sanity check on number of chunks */
495 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
497 if (num_tbs
>= IWL_NUM_OF_TBS
) {
498 IWL_ERR(priv
, "Too many chunks: %i\n", num_tbs
);
499 /* @todo issue fatal error, it is quite serious situation */
505 pci_unmap_single(dev
,
506 dma_unmap_addr(&txq
->meta
[index
], mapping
),
507 dma_unmap_len(&txq
->meta
[index
], len
),
508 PCI_DMA_BIDIRECTIONAL
);
510 /* Unmap chunks, if any. */
511 for (i
= 1; i
< num_tbs
; i
++)
512 pci_unmap_single(dev
, iwl_tfd_tb_get_addr(tfd
, i
),
513 iwl_tfd_tb_get_len(tfd
, i
), PCI_DMA_TODEVICE
);
519 skb
= txq
->txb
[txq
->q
.read_ptr
].skb
;
521 /* can be called from irqs-disabled context */
523 dev_kfree_skb_any(skb
);
524 txq
->txb
[txq
->q
.read_ptr
].skb
= NULL
;
529 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
530 struct iwl_tx_queue
*txq
,
531 dma_addr_t addr
, u16 len
,
535 struct iwl_tfd
*tfd
, *tfd_tmp
;
539 tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
540 tfd
= &tfd_tmp
[q
->write_ptr
];
543 memset(tfd
, 0, sizeof(*tfd
));
545 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
547 /* Each TFD can point to a maximum 20 Tx buffers */
548 if (num_tbs
>= IWL_NUM_OF_TBS
) {
549 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
554 BUG_ON(addr
& ~DMA_BIT_MASK(36));
555 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
556 IWL_ERR(priv
, "Unaligned address = %llx\n",
557 (unsigned long long)addr
);
559 iwl_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
565 * Tell nic where to find circular buffer of Tx Frame Descriptors for
566 * given Tx queue, and enable the DMA channel used for that queue.
568 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
569 * channels supported in hardware.
571 int iwl_hw_tx_queue_init(struct iwl_priv
*priv
,
572 struct iwl_tx_queue
*txq
)
574 int txq_id
= txq
->q
.id
;
576 /* Circular buffer (TFD queue in DRAM) physical base address */
577 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
578 txq
->q
.dma_addr
>> 8);
583 /******************************************************************************
585 * Generic RX handler implementations
587 ******************************************************************************/
588 static void iwl_rx_reply_alive(struct iwl_priv
*priv
,
589 struct iwl_rx_mem_buffer
*rxb
)
591 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
592 struct iwl_alive_resp
*palive
;
593 struct delayed_work
*pwork
;
595 palive
= &pkt
->u
.alive_frame
;
597 IWL_DEBUG_INFO(priv
, "Alive ucode status 0x%08X revision "
599 palive
->is_valid
, palive
->ver_type
,
600 palive
->ver_subtype
);
602 if (palive
->ver_subtype
== INITIALIZE_SUBTYPE
) {
603 IWL_DEBUG_INFO(priv
, "Initialization Alive received.\n");
604 memcpy(&priv
->card_alive_init
,
606 sizeof(struct iwl_init_alive_resp
));
607 pwork
= &priv
->init_alive_start
;
609 IWL_DEBUG_INFO(priv
, "Runtime Alive received.\n");
610 memcpy(&priv
->card_alive
, &pkt
->u
.alive_frame
,
611 sizeof(struct iwl_alive_resp
));
612 pwork
= &priv
->alive_start
;
615 /* We delay the ALIVE response by 5ms to
616 * give the HW RF Kill time to activate... */
617 if (palive
->is_valid
== UCODE_VALID_OK
)
618 queue_delayed_work(priv
->workqueue
, pwork
,
619 msecs_to_jiffies(5));
621 IWL_WARN(priv
, "uCode did not respond OK.\n");
624 static void iwl_bg_beacon_update(struct work_struct
*work
)
626 struct iwl_priv
*priv
=
627 container_of(work
, struct iwl_priv
, beacon_update
);
628 struct sk_buff
*beacon
;
630 mutex_lock(&priv
->mutex
);
631 if (!priv
->beacon_ctx
) {
632 IWL_ERR(priv
, "updating beacon w/o beacon context!\n");
636 if (priv
->beacon_ctx
->vif
->type
!= NL80211_IFTYPE_AP
) {
638 * The ucode will send beacon notifications even in
639 * IBSS mode, but we don't want to process them. But
640 * we need to defer the type check to here due to
641 * requiring locking around the beacon_ctx access.
646 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
647 beacon
= ieee80211_beacon_get(priv
->hw
, priv
->beacon_ctx
->vif
);
649 IWL_ERR(priv
, "update beacon failed\n");
653 /* new beacon skb is allocated every time; dispose previous.*/
654 if (priv
->ibss_beacon
)
655 dev_kfree_skb(priv
->ibss_beacon
);
657 priv
->ibss_beacon
= beacon
;
659 iwl_send_beacon_cmd(priv
);
661 mutex_unlock(&priv
->mutex
);
664 static void iwl_bg_bt_runtime_config(struct work_struct
*work
)
666 struct iwl_priv
*priv
=
667 container_of(work
, struct iwl_priv
, bt_runtime_config
);
669 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
672 /* dont send host command if rf-kill is on */
673 if (!iwl_is_ready_rf(priv
))
675 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
678 static void iwl_bg_bt_full_concurrency(struct work_struct
*work
)
680 struct iwl_priv
*priv
=
681 container_of(work
, struct iwl_priv
, bt_full_concurrency
);
682 struct iwl_rxon_context
*ctx
;
684 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
687 /* dont send host command if rf-kill is on */
688 if (!iwl_is_ready_rf(priv
))
691 IWL_DEBUG_INFO(priv
, "BT coex in %s mode\n",
692 priv
->bt_full_concurrent
?
693 "full concurrency" : "3-wire");
696 * LQ & RXON updated cmds must be sent before BT Config cmd
697 * to avoid 3-wire collisions
699 mutex_lock(&priv
->mutex
);
700 for_each_context(priv
, ctx
) {
701 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
702 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
703 iwlcore_commit_rxon(priv
, ctx
);
705 mutex_unlock(&priv
->mutex
);
707 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
711 * iwl_bg_statistics_periodic - Timer callback to queue statistics
713 * This callback is provided in order to send a statistics request.
715 * This timer function is continually reset to execute within
716 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
717 * was received. We need to ensure we receive the statistics in order
718 * to update the temperature used for calibrating the TXPOWER.
720 static void iwl_bg_statistics_periodic(unsigned long data
)
722 struct iwl_priv
*priv
= (struct iwl_priv
*)data
;
724 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
727 /* dont send host command if rf-kill is on */
728 if (!iwl_is_ready_rf(priv
))
731 iwl_send_statistics_request(priv
, CMD_ASYNC
, false);
735 static void iwl_print_cont_event_trace(struct iwl_priv
*priv
, u32 base
,
736 u32 start_idx
, u32 num_events
,
740 u32 ptr
; /* SRAM byte address of log data */
741 u32 ev
, time
, data
; /* event log data */
742 unsigned long reg_flags
;
745 ptr
= base
+ (4 * sizeof(u32
)) + (start_idx
* 2 * sizeof(u32
));
747 ptr
= base
+ (4 * sizeof(u32
)) + (start_idx
* 3 * sizeof(u32
));
749 /* Make sure device is powered up for SRAM reads */
750 spin_lock_irqsave(&priv
->reg_lock
, reg_flags
);
751 if (iwl_grab_nic_access(priv
)) {
752 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
756 /* Set starting address; reads will auto-increment */
757 _iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, ptr
);
761 * "time" is actually "data" for mode 0 (no timestamp).
762 * place event id # at far right for easier visual parsing.
764 for (i
= 0; i
< num_events
; i
++) {
765 ev
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
766 time
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
768 trace_iwlwifi_dev_ucode_cont_event(priv
,
771 data
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
772 trace_iwlwifi_dev_ucode_cont_event(priv
,
776 /* Allow device to power down */
777 iwl_release_nic_access(priv
);
778 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
781 static void iwl_continuous_event_trace(struct iwl_priv
*priv
)
783 u32 capacity
; /* event log capacity in # entries */
784 u32 base
; /* SRAM byte address of event log header */
785 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
786 u32 num_wraps
; /* # times uCode wrapped to top of log */
787 u32 next_entry
; /* index of next entry to be written by uCode */
789 if (priv
->ucode_type
== UCODE_INIT
)
790 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
792 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
793 if (priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
794 capacity
= iwl_read_targ_mem(priv
, base
);
795 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
796 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
797 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
801 if (num_wraps
== priv
->event_log
.num_wraps
) {
802 iwl_print_cont_event_trace(priv
,
803 base
, priv
->event_log
.next_entry
,
804 next_entry
- priv
->event_log
.next_entry
,
806 priv
->event_log
.non_wraps_count
++;
808 if ((num_wraps
- priv
->event_log
.num_wraps
) > 1)
809 priv
->event_log
.wraps_more_count
++;
811 priv
->event_log
.wraps_once_count
++;
812 trace_iwlwifi_dev_ucode_wrap_event(priv
,
813 num_wraps
- priv
->event_log
.num_wraps
,
814 next_entry
, priv
->event_log
.next_entry
);
815 if (next_entry
< priv
->event_log
.next_entry
) {
816 iwl_print_cont_event_trace(priv
, base
,
817 priv
->event_log
.next_entry
,
818 capacity
- priv
->event_log
.next_entry
,
821 iwl_print_cont_event_trace(priv
, base
, 0,
824 iwl_print_cont_event_trace(priv
, base
,
825 next_entry
, capacity
- next_entry
,
828 iwl_print_cont_event_trace(priv
, base
, 0,
832 priv
->event_log
.num_wraps
= num_wraps
;
833 priv
->event_log
.next_entry
= next_entry
;
837 * iwl_bg_ucode_trace - Timer callback to log ucode event
839 * The timer is continually set to execute every
840 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
841 * this function is to perform continuous uCode event logging operation
844 static void iwl_bg_ucode_trace(unsigned long data
)
846 struct iwl_priv
*priv
= (struct iwl_priv
*)data
;
848 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
851 if (priv
->event_log
.ucode_trace
) {
852 iwl_continuous_event_trace(priv
);
853 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
854 mod_timer(&priv
->ucode_trace
,
855 jiffies
+ msecs_to_jiffies(UCODE_TRACE_PERIOD
));
859 static void iwl_rx_beacon_notif(struct iwl_priv
*priv
,
860 struct iwl_rx_mem_buffer
*rxb
)
862 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
863 struct iwl4965_beacon_notif
*beacon
=
864 (struct iwl4965_beacon_notif
*)pkt
->u
.raw
;
865 #ifdef CONFIG_IWLWIFI_DEBUG
866 u8 rate
= iwl_hw_get_rate(beacon
->beacon_notify_hdr
.rate_n_flags
);
868 IWL_DEBUG_RX(priv
, "beacon status %x retries %d iss %d "
869 "tsf %d %d rate %d\n",
870 le32_to_cpu(beacon
->beacon_notify_hdr
.u
.status
) & TX_STATUS_MSK
,
871 beacon
->beacon_notify_hdr
.failure_frame
,
872 le32_to_cpu(beacon
->ibss_mgr_status
),
873 le32_to_cpu(beacon
->high_tsf
),
874 le32_to_cpu(beacon
->low_tsf
), rate
);
877 priv
->ibss_manager
= le32_to_cpu(beacon
->ibss_mgr_status
);
879 if (!test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
880 queue_work(priv
->workqueue
, &priv
->beacon_update
);
883 /* Handle notification from uCode that card's power state is changing
884 * due to software, hardware, or critical temperature RFKILL */
885 static void iwl_rx_card_state_notif(struct iwl_priv
*priv
,
886 struct iwl_rx_mem_buffer
*rxb
)
888 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
889 u32 flags
= le32_to_cpu(pkt
->u
.card_state_notif
.flags
);
890 unsigned long status
= priv
->status
;
892 IWL_DEBUG_RF_KILL(priv
, "Card state received: HW:%s SW:%s CT:%s\n",
893 (flags
& HW_CARD_DISABLED
) ? "Kill" : "On",
894 (flags
& SW_CARD_DISABLED
) ? "Kill" : "On",
895 (flags
& CT_CARD_DISABLED
) ?
896 "Reached" : "Not reached");
898 if (flags
& (SW_CARD_DISABLED
| HW_CARD_DISABLED
|
901 iwl_write32(priv
, CSR_UCODE_DRV_GP1_SET
,
902 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
904 iwl_write_direct32(priv
, HBUS_TARG_MBX_C
,
905 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED
);
907 if (!(flags
& RXON_CARD_DISABLED
)) {
908 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
909 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
910 iwl_write_direct32(priv
, HBUS_TARG_MBX_C
,
911 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED
);
913 if (flags
& CT_CARD_DISABLED
)
914 iwl_tt_enter_ct_kill(priv
);
916 if (!(flags
& CT_CARD_DISABLED
))
917 iwl_tt_exit_ct_kill(priv
);
919 if (flags
& HW_CARD_DISABLED
)
920 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
922 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
925 if (!(flags
& RXON_CARD_DISABLED
))
926 iwl_scan_cancel(priv
);
928 if ((test_bit(STATUS_RF_KILL_HW
, &status
) !=
929 test_bit(STATUS_RF_KILL_HW
, &priv
->status
)))
930 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
,
931 test_bit(STATUS_RF_KILL_HW
, &priv
->status
));
933 wake_up_interruptible(&priv
->wait_command_queue
);
936 int iwl_set_pwr_src(struct iwl_priv
*priv
, enum iwl_pwr_src src
)
938 if (src
== IWL_PWR_SRC_VAUX
) {
939 if (pci_pme_capable(priv
->pci_dev
, PCI_D3cold
))
940 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
942 ~APMG_PS_CTRL_MSK_PWR_SRC
);
944 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
945 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
946 ~APMG_PS_CTRL_MSK_PWR_SRC
);
952 static void iwl_bg_tx_flush(struct work_struct
*work
)
954 struct iwl_priv
*priv
=
955 container_of(work
, struct iwl_priv
, tx_flush
);
957 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
960 /* do nothing if rf-kill is on */
961 if (!iwl_is_ready_rf(priv
))
964 if (priv
->cfg
->ops
->lib
->txfifo_flush
) {
965 IWL_DEBUG_INFO(priv
, "device request: flush all tx frames\n");
966 iwlagn_dev_txfifo_flush(priv
, IWL_DROP_ALL
);
971 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
973 * Setup the RX handlers for each of the reply types sent from the uCode
976 * This function chains into the hardware specific files for them to setup
977 * any hardware specific handlers as well.
979 static void iwl_setup_rx_handlers(struct iwl_priv
*priv
)
981 priv
->rx_handlers
[REPLY_ALIVE
] = iwl_rx_reply_alive
;
982 priv
->rx_handlers
[REPLY_ERROR
] = iwl_rx_reply_error
;
983 priv
->rx_handlers
[CHANNEL_SWITCH_NOTIFICATION
] = iwl_rx_csa
;
984 priv
->rx_handlers
[SPECTRUM_MEASURE_NOTIFICATION
] =
985 iwl_rx_spectrum_measure_notif
;
986 priv
->rx_handlers
[PM_SLEEP_NOTIFICATION
] = iwl_rx_pm_sleep_notif
;
987 priv
->rx_handlers
[PM_DEBUG_STATISTIC_NOTIFIC
] =
988 iwl_rx_pm_debug_statistics_notif
;
989 priv
->rx_handlers
[BEACON_NOTIFICATION
] = iwl_rx_beacon_notif
;
992 * The same handler is used for both the REPLY to a discrete
993 * statistics request from the host as well as for the periodic
994 * statistics notifications (after received beacons) from the uCode.
996 priv
->rx_handlers
[REPLY_STATISTICS_CMD
] = iwl_reply_statistics
;
997 priv
->rx_handlers
[STATISTICS_NOTIFICATION
] = iwl_rx_statistics
;
999 iwl_setup_rx_scan_handlers(priv
);
1001 /* status change handler */
1002 priv
->rx_handlers
[CARD_STATE_NOTIFICATION
] = iwl_rx_card_state_notif
;
1004 priv
->rx_handlers
[MISSED_BEACONS_NOTIFICATION
] =
1005 iwl_rx_missed_beacon_notif
;
1007 priv
->rx_handlers
[REPLY_RX_PHY_CMD
] = iwlagn_rx_reply_rx_phy
;
1008 priv
->rx_handlers
[REPLY_RX_MPDU_CMD
] = iwlagn_rx_reply_rx
;
1010 priv
->rx_handlers
[REPLY_COMPRESSED_BA
] = iwlagn_rx_reply_compressed_ba
;
1011 /* Set up hardware specific Rx handlers */
1012 priv
->cfg
->ops
->lib
->rx_handler_setup(priv
);
1016 * iwl_rx_handle - Main entry function for receiving responses from uCode
1018 * Uses the priv->rx_handlers callback function array to invoke
1019 * the appropriate handlers, including command responses,
1020 * frame-received notifications, and other notifications.
1022 void iwl_rx_handle(struct iwl_priv
*priv
)
1024 struct iwl_rx_mem_buffer
*rxb
;
1025 struct iwl_rx_packet
*pkt
;
1026 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
1029 unsigned long flags
;
1034 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1035 * buffer that the driver may process (last buffer filled by ucode). */
1036 r
= le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF;
1039 /* Rx interrupt, but nothing sent from uCode */
1041 IWL_DEBUG_RX(priv
, "r = %d, i = %d\n", r
, i
);
1043 /* calculate total frames need to be restock after handling RX */
1044 total_empty
= r
- rxq
->write_actual
;
1045 if (total_empty
< 0)
1046 total_empty
+= RX_QUEUE_SIZE
;
1048 if (total_empty
> (RX_QUEUE_SIZE
/ 2))
1054 rxb
= rxq
->queue
[i
];
1056 /* If an RXB doesn't have a Rx queue slot associated with it,
1057 * then a bug has been introduced in the queue refilling
1058 * routines -- catch it here */
1059 BUG_ON(rxb
== NULL
);
1061 rxq
->queue
[i
] = NULL
;
1063 pci_unmap_page(priv
->pci_dev
, rxb
->page_dma
,
1064 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
1065 PCI_DMA_FROMDEVICE
);
1066 pkt
= rxb_addr(rxb
);
1068 len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
1069 len
+= sizeof(u32
); /* account for status word */
1070 trace_iwlwifi_dev_rx(priv
, pkt
, len
);
1072 /* Reclaim a command buffer only if this packet is a response
1073 * to a (driver-originated) command.
1074 * If the packet (e.g. Rx frame) originated from uCode,
1075 * there is no command buffer to reclaim.
1076 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1077 * but apparently a few don't get set; catch them here. */
1078 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
) &&
1079 (pkt
->hdr
.cmd
!= REPLY_RX_PHY_CMD
) &&
1080 (pkt
->hdr
.cmd
!= REPLY_RX
) &&
1081 (pkt
->hdr
.cmd
!= REPLY_RX_MPDU_CMD
) &&
1082 (pkt
->hdr
.cmd
!= REPLY_COMPRESSED_BA
) &&
1083 (pkt
->hdr
.cmd
!= STATISTICS_NOTIFICATION
) &&
1084 (pkt
->hdr
.cmd
!= REPLY_TX
);
1086 /* Based on type of command response or notification,
1087 * handle those that need handling via function in
1088 * rx_handlers table. See iwl_setup_rx_handlers() */
1089 if (priv
->rx_handlers
[pkt
->hdr
.cmd
]) {
1090 IWL_DEBUG_RX(priv
, "r = %d, i = %d, %s, 0x%02x\n", r
,
1091 i
, get_cmd_string(pkt
->hdr
.cmd
), pkt
->hdr
.cmd
);
1092 priv
->isr_stats
.rx_handlers
[pkt
->hdr
.cmd
]++;
1093 priv
->rx_handlers
[pkt
->hdr
.cmd
] (priv
, rxb
);
1095 /* No handling needed */
1097 "r %d i %d No handler needed for %s, 0x%02x\n",
1098 r
, i
, get_cmd_string(pkt
->hdr
.cmd
),
1103 * XXX: After here, we should always check rxb->page
1104 * against NULL before touching it or its virtual
1105 * memory (pkt). Because some rx_handler might have
1106 * already taken or freed the pages.
1110 /* Invoke any callbacks, transfer the buffer to caller,
1111 * and fire off the (possibly) blocking iwl_send_cmd()
1112 * as we reclaim the driver command queue */
1114 iwl_tx_cmd_complete(priv
, rxb
);
1116 IWL_WARN(priv
, "Claim null rxb?\n");
1119 /* Reuse the page if possible. For notification packets and
1120 * SKBs that fail to Rx correctly, add them back into the
1121 * rx_free list for reuse later. */
1122 spin_lock_irqsave(&rxq
->lock
, flags
);
1123 if (rxb
->page
!= NULL
) {
1124 rxb
->page_dma
= pci_map_page(priv
->pci_dev
, rxb
->page
,
1125 0, PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
1126 PCI_DMA_FROMDEVICE
);
1127 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
1130 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
1132 spin_unlock_irqrestore(&rxq
->lock
, flags
);
1134 i
= (i
+ 1) & RX_QUEUE_MASK
;
1135 /* If there are a lot of unused frames,
1136 * restock the Rx queue so ucode wont assert. */
1141 iwlagn_rx_replenish_now(priv
);
1147 /* Backtrack one entry */
1150 iwlagn_rx_replenish_now(priv
);
1152 iwlagn_rx_queue_restock(priv
);
1155 /* call this function to flush any scheduled tasklet */
1156 static inline void iwl_synchronize_irq(struct iwl_priv
*priv
)
1158 /* wait to make sure we flush pending tasklet*/
1159 synchronize_irq(priv
->pci_dev
->irq
);
1160 tasklet_kill(&priv
->irq_tasklet
);
1163 static void iwl_irq_tasklet_legacy(struct iwl_priv
*priv
)
1165 u32 inta
, handled
= 0;
1167 unsigned long flags
;
1169 #ifdef CONFIG_IWLWIFI_DEBUG
1173 spin_lock_irqsave(&priv
->lock
, flags
);
1175 /* Ack/clear/reset pending uCode interrupts.
1176 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1177 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1178 inta
= iwl_read32(priv
, CSR_INT
);
1179 iwl_write32(priv
, CSR_INT
, inta
);
1181 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1182 * Any new interrupts that happen after this, either while we're
1183 * in this tasklet, or later, will show up in next ISR/tasklet. */
1184 inta_fh
= iwl_read32(priv
, CSR_FH_INT_STATUS
);
1185 iwl_write32(priv
, CSR_FH_INT_STATUS
, inta_fh
);
1187 #ifdef CONFIG_IWLWIFI_DEBUG
1188 if (iwl_get_debug_level(priv
) & IWL_DL_ISR
) {
1189 /* just for debug */
1190 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
);
1191 IWL_DEBUG_ISR(priv
, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1192 inta
, inta_mask
, inta_fh
);
1196 spin_unlock_irqrestore(&priv
->lock
, flags
);
1198 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1199 * atomic, make sure that inta covers all the interrupts that
1200 * we've discovered, even if FH interrupt came in just after
1201 * reading CSR_INT. */
1202 if (inta_fh
& CSR49_FH_INT_RX_MASK
)
1203 inta
|= CSR_INT_BIT_FH_RX
;
1204 if (inta_fh
& CSR49_FH_INT_TX_MASK
)
1205 inta
|= CSR_INT_BIT_FH_TX
;
1207 /* Now service all interrupt bits discovered above. */
1208 if (inta
& CSR_INT_BIT_HW_ERR
) {
1209 IWL_ERR(priv
, "Hardware error detected. Restarting.\n");
1211 /* Tell the device to stop sending interrupts */
1212 iwl_disable_interrupts(priv
);
1214 priv
->isr_stats
.hw
++;
1215 iwl_irq_handle_error(priv
);
1217 handled
|= CSR_INT_BIT_HW_ERR
;
1222 #ifdef CONFIG_IWLWIFI_DEBUG
1223 if (iwl_get_debug_level(priv
) & (IWL_DL_ISR
)) {
1224 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1225 if (inta
& CSR_INT_BIT_SCD
) {
1226 IWL_DEBUG_ISR(priv
, "Scheduler finished to transmit "
1227 "the frame/frames.\n");
1228 priv
->isr_stats
.sch
++;
1231 /* Alive notification via Rx interrupt will do the real work */
1232 if (inta
& CSR_INT_BIT_ALIVE
) {
1233 IWL_DEBUG_ISR(priv
, "Alive interrupt\n");
1234 priv
->isr_stats
.alive
++;
1238 /* Safely ignore these bits for debug checks below */
1239 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
1241 /* HW RF KILL switch toggled */
1242 if (inta
& CSR_INT_BIT_RF_KILL
) {
1244 if (!(iwl_read32(priv
, CSR_GP_CNTRL
) &
1245 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1248 IWL_WARN(priv
, "RF_KILL bit toggled to %s.\n",
1249 hw_rf_kill
? "disable radio" : "enable radio");
1251 priv
->isr_stats
.rfkill
++;
1253 /* driver only loads ucode once setting the interface up.
1254 * the driver allows loading the ucode even if the radio
1255 * is killed. Hence update the killswitch state here. The
1256 * rfkill handler will care about restarting if needed.
1258 if (!test_bit(STATUS_ALIVE
, &priv
->status
)) {
1260 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
1262 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
1263 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, hw_rf_kill
);
1266 handled
|= CSR_INT_BIT_RF_KILL
;
1269 /* Chip got too hot and stopped itself */
1270 if (inta
& CSR_INT_BIT_CT_KILL
) {
1271 IWL_ERR(priv
, "Microcode CT kill error detected.\n");
1272 priv
->isr_stats
.ctkill
++;
1273 handled
|= CSR_INT_BIT_CT_KILL
;
1276 /* Error detected by uCode */
1277 if (inta
& CSR_INT_BIT_SW_ERR
) {
1278 IWL_ERR(priv
, "Microcode SW error detected. "
1279 " Restarting 0x%X.\n", inta
);
1280 priv
->isr_stats
.sw
++;
1281 priv
->isr_stats
.sw_err
= inta
;
1282 iwl_irq_handle_error(priv
);
1283 handled
|= CSR_INT_BIT_SW_ERR
;
1287 * uCode wakes up after power-down sleep.
1288 * Tell device about any new tx or host commands enqueued,
1289 * and about any Rx buffers made available while asleep.
1291 if (inta
& CSR_INT_BIT_WAKEUP
) {
1292 IWL_DEBUG_ISR(priv
, "Wakeup interrupt\n");
1293 iwl_rx_queue_update_write_ptr(priv
, &priv
->rxq
);
1294 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++)
1295 iwl_txq_update_write_ptr(priv
, &priv
->txq
[i
]);
1296 priv
->isr_stats
.wakeup
++;
1297 handled
|= CSR_INT_BIT_WAKEUP
;
1300 /* All uCode command responses, including Tx command responses,
1301 * Rx "responses" (frame-received notification), and other
1302 * notifications from uCode come through here*/
1303 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
1304 iwl_rx_handle(priv
);
1305 priv
->isr_stats
.rx
++;
1306 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
1309 /* This "Tx" DMA channel is used only for loading uCode */
1310 if (inta
& CSR_INT_BIT_FH_TX
) {
1311 IWL_DEBUG_ISR(priv
, "uCode load interrupt\n");
1312 priv
->isr_stats
.tx
++;
1313 handled
|= CSR_INT_BIT_FH_TX
;
1314 /* Wake up uCode load routine, now that load is complete */
1315 priv
->ucode_write_complete
= 1;
1316 wake_up_interruptible(&priv
->wait_command_queue
);
1319 if (inta
& ~handled
) {
1320 IWL_ERR(priv
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
1321 priv
->isr_stats
.unhandled
++;
1324 if (inta
& ~(priv
->inta_mask
)) {
1325 IWL_WARN(priv
, "Disabled INTA bits 0x%08x were pending\n",
1326 inta
& ~priv
->inta_mask
);
1327 IWL_WARN(priv
, " with FH_INT = 0x%08x\n", inta_fh
);
1330 /* Re-enable all interrupts */
1331 /* only Re-enable if diabled by irq */
1332 if (test_bit(STATUS_INT_ENABLED
, &priv
->status
))
1333 iwl_enable_interrupts(priv
);
1335 #ifdef CONFIG_IWLWIFI_DEBUG
1336 if (iwl_get_debug_level(priv
) & (IWL_DL_ISR
)) {
1337 inta
= iwl_read32(priv
, CSR_INT
);
1338 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
);
1339 inta_fh
= iwl_read32(priv
, CSR_FH_INT_STATUS
);
1340 IWL_DEBUG_ISR(priv
, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1341 "flags 0x%08lx\n", inta
, inta_mask
, inta_fh
, flags
);
1346 /* tasklet for iwlagn interrupt */
1347 static void iwl_irq_tasklet(struct iwl_priv
*priv
)
1351 unsigned long flags
;
1353 #ifdef CONFIG_IWLWIFI_DEBUG
1357 spin_lock_irqsave(&priv
->lock
, flags
);
1359 /* Ack/clear/reset pending uCode interrupts.
1360 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1362 /* There is a hardware bug in the interrupt mask function that some
1363 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1364 * they are disabled in the CSR_INT_MASK register. Furthermore the
1365 * ICT interrupt handling mechanism has another bug that might cause
1366 * these unmasked interrupts fail to be detected. We workaround the
1367 * hardware bugs here by ACKing all the possible interrupts so that
1368 * interrupt coalescing can still be achieved.
1370 iwl_write32(priv
, CSR_INT
, priv
->_agn
.inta
| ~priv
->inta_mask
);
1372 inta
= priv
->_agn
.inta
;
1374 #ifdef CONFIG_IWLWIFI_DEBUG
1375 if (iwl_get_debug_level(priv
) & IWL_DL_ISR
) {
1376 /* just for debug */
1377 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
);
1378 IWL_DEBUG_ISR(priv
, "inta 0x%08x, enabled 0x%08x\n ",
1383 spin_unlock_irqrestore(&priv
->lock
, flags
);
1385 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1386 priv
->_agn
.inta
= 0;
1388 /* Now service all interrupt bits discovered above. */
1389 if (inta
& CSR_INT_BIT_HW_ERR
) {
1390 IWL_ERR(priv
, "Hardware error detected. Restarting.\n");
1392 /* Tell the device to stop sending interrupts */
1393 iwl_disable_interrupts(priv
);
1395 priv
->isr_stats
.hw
++;
1396 iwl_irq_handle_error(priv
);
1398 handled
|= CSR_INT_BIT_HW_ERR
;
1403 #ifdef CONFIG_IWLWIFI_DEBUG
1404 if (iwl_get_debug_level(priv
) & (IWL_DL_ISR
)) {
1405 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1406 if (inta
& CSR_INT_BIT_SCD
) {
1407 IWL_DEBUG_ISR(priv
, "Scheduler finished to transmit "
1408 "the frame/frames.\n");
1409 priv
->isr_stats
.sch
++;
1412 /* Alive notification via Rx interrupt will do the real work */
1413 if (inta
& CSR_INT_BIT_ALIVE
) {
1414 IWL_DEBUG_ISR(priv
, "Alive interrupt\n");
1415 priv
->isr_stats
.alive
++;
1419 /* Safely ignore these bits for debug checks below */
1420 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
1422 /* HW RF KILL switch toggled */
1423 if (inta
& CSR_INT_BIT_RF_KILL
) {
1425 if (!(iwl_read32(priv
, CSR_GP_CNTRL
) &
1426 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
1429 IWL_WARN(priv
, "RF_KILL bit toggled to %s.\n",
1430 hw_rf_kill
? "disable radio" : "enable radio");
1432 priv
->isr_stats
.rfkill
++;
1434 /* driver only loads ucode once setting the interface up.
1435 * the driver allows loading the ucode even if the radio
1436 * is killed. Hence update the killswitch state here. The
1437 * rfkill handler will care about restarting if needed.
1439 if (!test_bit(STATUS_ALIVE
, &priv
->status
)) {
1441 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
1443 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
1444 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, hw_rf_kill
);
1447 handled
|= CSR_INT_BIT_RF_KILL
;
1450 /* Chip got too hot and stopped itself */
1451 if (inta
& CSR_INT_BIT_CT_KILL
) {
1452 IWL_ERR(priv
, "Microcode CT kill error detected.\n");
1453 priv
->isr_stats
.ctkill
++;
1454 handled
|= CSR_INT_BIT_CT_KILL
;
1457 /* Error detected by uCode */
1458 if (inta
& CSR_INT_BIT_SW_ERR
) {
1459 IWL_ERR(priv
, "Microcode SW error detected. "
1460 " Restarting 0x%X.\n", inta
);
1461 priv
->isr_stats
.sw
++;
1462 priv
->isr_stats
.sw_err
= inta
;
1463 iwl_irq_handle_error(priv
);
1464 handled
|= CSR_INT_BIT_SW_ERR
;
1467 /* uCode wakes up after power-down sleep */
1468 if (inta
& CSR_INT_BIT_WAKEUP
) {
1469 IWL_DEBUG_ISR(priv
, "Wakeup interrupt\n");
1470 iwl_rx_queue_update_write_ptr(priv
, &priv
->rxq
);
1471 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++)
1472 iwl_txq_update_write_ptr(priv
, &priv
->txq
[i
]);
1474 priv
->isr_stats
.wakeup
++;
1476 handled
|= CSR_INT_BIT_WAKEUP
;
1479 /* All uCode command responses, including Tx command responses,
1480 * Rx "responses" (frame-received notification), and other
1481 * notifications from uCode come through here*/
1482 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
1483 CSR_INT_BIT_RX_PERIODIC
)) {
1484 IWL_DEBUG_ISR(priv
, "Rx interrupt\n");
1485 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
1486 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
1487 iwl_write32(priv
, CSR_FH_INT_STATUS
,
1488 CSR49_FH_INT_RX_MASK
);
1490 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
1491 handled
|= CSR_INT_BIT_RX_PERIODIC
;
1492 iwl_write32(priv
, CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
1494 /* Sending RX interrupt require many steps to be done in the
1496 * 1- write interrupt to current index in ICT table.
1498 * 3- update RX shared data to indicate last write index.
1499 * 4- send interrupt.
1500 * This could lead to RX race, driver could receive RX interrupt
1501 * but the shared data changes does not reflect this;
1502 * periodic interrupt will detect any dangling Rx activity.
1505 /* Disable periodic interrupt; we use it as just a one-shot. */
1506 iwl_write8(priv
, CSR_INT_PERIODIC_REG
,
1507 CSR_INT_PERIODIC_DIS
);
1508 iwl_rx_handle(priv
);
1511 * Enable periodic interrupt in 8 msec only if we received
1512 * real RX interrupt (instead of just periodic int), to catch
1513 * any dangling Rx interrupt. If it was just the periodic
1514 * interrupt, there was no dangling Rx activity, and no need
1515 * to extend the periodic interrupt; one-shot is enough.
1517 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
1518 iwl_write8(priv
, CSR_INT_PERIODIC_REG
,
1519 CSR_INT_PERIODIC_ENA
);
1521 priv
->isr_stats
.rx
++;
1524 /* This "Tx" DMA channel is used only for loading uCode */
1525 if (inta
& CSR_INT_BIT_FH_TX
) {
1526 iwl_write32(priv
, CSR_FH_INT_STATUS
, CSR49_FH_INT_TX_MASK
);
1527 IWL_DEBUG_ISR(priv
, "uCode load interrupt\n");
1528 priv
->isr_stats
.tx
++;
1529 handled
|= CSR_INT_BIT_FH_TX
;
1530 /* Wake up uCode load routine, now that load is complete */
1531 priv
->ucode_write_complete
= 1;
1532 wake_up_interruptible(&priv
->wait_command_queue
);
1535 if (inta
& ~handled
) {
1536 IWL_ERR(priv
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
1537 priv
->isr_stats
.unhandled
++;
1540 if (inta
& ~(priv
->inta_mask
)) {
1541 IWL_WARN(priv
, "Disabled INTA bits 0x%08x were pending\n",
1542 inta
& ~priv
->inta_mask
);
1545 /* Re-enable all interrupts */
1546 /* only Re-enable if diabled by irq */
1547 if (test_bit(STATUS_INT_ENABLED
, &priv
->status
))
1548 iwl_enable_interrupts(priv
);
1551 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1552 #define ACK_CNT_RATIO (50)
1553 #define BA_TIMEOUT_CNT (5)
1554 #define BA_TIMEOUT_MAX (16)
1557 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1559 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1560 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1563 bool iwl_good_ack_health(struct iwl_priv
*priv
,
1564 struct iwl_rx_packet
*pkt
)
1567 int actual_ack_cnt_delta
, expected_ack_cnt_delta
;
1568 int ba_timeout_delta
;
1570 actual_ack_cnt_delta
=
1571 le32_to_cpu(pkt
->u
.stats
.tx
.actual_ack_cnt
) -
1572 le32_to_cpu(priv
->_agn
.statistics
.tx
.actual_ack_cnt
);
1573 expected_ack_cnt_delta
=
1574 le32_to_cpu(pkt
->u
.stats
.tx
.expected_ack_cnt
) -
1575 le32_to_cpu(priv
->_agn
.statistics
.tx
.expected_ack_cnt
);
1577 le32_to_cpu(pkt
->u
.stats
.tx
.agg
.ba_timeout
) -
1578 le32_to_cpu(priv
->_agn
.statistics
.tx
.agg
.ba_timeout
);
1579 if ((priv
->_agn
.agg_tids_count
> 0) &&
1580 (expected_ack_cnt_delta
> 0) &&
1581 (((actual_ack_cnt_delta
* 100) / expected_ack_cnt_delta
)
1583 (ba_timeout_delta
> BA_TIMEOUT_CNT
)) {
1584 IWL_DEBUG_RADIO(priv
, "actual_ack_cnt delta = %d,"
1585 " expected_ack_cnt = %d\n",
1586 actual_ack_cnt_delta
, expected_ack_cnt_delta
);
1588 #ifdef CONFIG_IWLWIFI_DEBUGFS
1590 * This is ifdef'ed on DEBUGFS because otherwise the
1591 * statistics aren't available. If DEBUGFS is set but
1592 * DEBUG is not, these will just compile out.
1594 IWL_DEBUG_RADIO(priv
, "rx_detected_cnt delta = %d\n",
1595 priv
->_agn
.delta_statistics
.tx
.rx_detected_cnt
);
1596 IWL_DEBUG_RADIO(priv
,
1597 "ack_or_ba_timeout_collision delta = %d\n",
1598 priv
->_agn
.delta_statistics
.tx
.
1599 ack_or_ba_timeout_collision
);
1601 IWL_DEBUG_RADIO(priv
, "agg ba_timeout delta = %d\n",
1603 if (!actual_ack_cnt_delta
&&
1604 (ba_timeout_delta
>= BA_TIMEOUT_MAX
))
1611 /*****************************************************************************
1615 *****************************************************************************/
1617 #ifdef CONFIG_IWLWIFI_DEBUG
1620 * The following adds a new attribute to the sysfs representation
1621 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1622 * used for controlling the debug level.
1624 * See the level definitions in iwl for details.
1626 * The debug_level being managed using sysfs below is a per device debug
1627 * level that is used instead of the global debug level if it (the per
1628 * device debug level) is set.
1630 static ssize_t
show_debug_level(struct device
*d
,
1631 struct device_attribute
*attr
, char *buf
)
1633 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1634 return sprintf(buf
, "0x%08X\n", iwl_get_debug_level(priv
));
1636 static ssize_t
store_debug_level(struct device
*d
,
1637 struct device_attribute
*attr
,
1638 const char *buf
, size_t count
)
1640 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1644 ret
= strict_strtoul(buf
, 0, &val
);
1646 IWL_ERR(priv
, "%s is not in hex or decimal form.\n", buf
);
1648 priv
->debug_level
= val
;
1649 if (iwl_alloc_traffic_mem(priv
))
1651 "Not enough memory to generate traffic log\n");
1653 return strnlen(buf
, count
);
1656 static DEVICE_ATTR(debug_level
, S_IWUSR
| S_IRUGO
,
1657 show_debug_level
, store_debug_level
);
1660 #endif /* CONFIG_IWLWIFI_DEBUG */
1663 static ssize_t
show_temperature(struct device
*d
,
1664 struct device_attribute
*attr
, char *buf
)
1666 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1668 if (!iwl_is_alive(priv
))
1671 return sprintf(buf
, "%d\n", priv
->temperature
);
1674 static DEVICE_ATTR(temperature
, S_IRUGO
, show_temperature
, NULL
);
1676 static ssize_t
show_tx_power(struct device
*d
,
1677 struct device_attribute
*attr
, char *buf
)
1679 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1681 if (!iwl_is_ready_rf(priv
))
1682 return sprintf(buf
, "off\n");
1684 return sprintf(buf
, "%d\n", priv
->tx_power_user_lmt
);
1687 static ssize_t
store_tx_power(struct device
*d
,
1688 struct device_attribute
*attr
,
1689 const char *buf
, size_t count
)
1691 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1695 ret
= strict_strtoul(buf
, 10, &val
);
1697 IWL_INFO(priv
, "%s is not in decimal form.\n", buf
);
1699 ret
= iwl_set_tx_power(priv
, val
, false);
1701 IWL_ERR(priv
, "failed setting tx power (0x%d).\n",
1709 static DEVICE_ATTR(tx_power
, S_IWUSR
| S_IRUGO
, show_tx_power
, store_tx_power
);
1711 static struct attribute
*iwl_sysfs_entries
[] = {
1712 &dev_attr_temperature
.attr
,
1713 &dev_attr_tx_power
.attr
,
1714 #ifdef CONFIG_IWLWIFI_DEBUG
1715 &dev_attr_debug_level
.attr
,
1720 static struct attribute_group iwl_attribute_group
= {
1721 .name
= NULL
, /* put in device directory */
1722 .attrs
= iwl_sysfs_entries
,
1725 /******************************************************************************
1727 * uCode download functions
1729 ******************************************************************************/
1731 static void iwl_dealloc_ucode_pci(struct iwl_priv
*priv
)
1733 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_code
);
1734 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_data
);
1735 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_data_backup
);
1736 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_init
);
1737 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_init_data
);
1738 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_boot
);
1741 static void iwl_nic_start(struct iwl_priv
*priv
)
1743 /* Remove all resets to allow NIC to operate */
1744 iwl_write32(priv
, CSR_RESET
, 0);
1747 struct iwlagn_ucode_capabilities
{
1748 u32 max_probe_length
;
1749 u32 standard_phy_calibration_size
;
1753 static void iwl_ucode_callback(const struct firmware
*ucode_raw
, void *context
);
1754 static int iwl_mac_setup_register(struct iwl_priv
*priv
,
1755 struct iwlagn_ucode_capabilities
*capa
);
1757 #define UCODE_EXPERIMENTAL_INDEX 100
1758 #define UCODE_EXPERIMENTAL_TAG "exp"
1760 static int __must_check
iwl_request_firmware(struct iwl_priv
*priv
, bool first
)
1762 const char *name_pre
= priv
->cfg
->fw_name_pre
;
1766 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1767 priv
->fw_index
= UCODE_EXPERIMENTAL_INDEX
;
1768 strcpy(tag
, UCODE_EXPERIMENTAL_TAG
);
1769 } else if (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
) {
1771 priv
->fw_index
= priv
->cfg
->ucode_api_max
;
1772 sprintf(tag
, "%d", priv
->fw_index
);
1775 sprintf(tag
, "%d", priv
->fw_index
);
1778 if (priv
->fw_index
< priv
->cfg
->ucode_api_min
) {
1779 IWL_ERR(priv
, "no suitable firmware found!\n");
1783 sprintf(priv
->firmware_name
, "%s%s%s", name_pre
, tag
, ".ucode");
1785 IWL_DEBUG_INFO(priv
, "attempting to load firmware %s'%s'\n",
1786 (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
)
1787 ? "EXPERIMENTAL " : "",
1788 priv
->firmware_name
);
1790 return request_firmware_nowait(THIS_MODULE
, 1, priv
->firmware_name
,
1791 &priv
->pci_dev
->dev
, GFP_KERNEL
, priv
,
1792 iwl_ucode_callback
);
1795 struct iwlagn_firmware_pieces
{
1796 const void *inst
, *data
, *init
, *init_data
, *boot
;
1797 size_t inst_size
, data_size
, init_size
, init_data_size
, boot_size
;
1801 u32 init_evtlog_ptr
, init_evtlog_size
, init_errlog_ptr
;
1802 u32 inst_evtlog_ptr
, inst_evtlog_size
, inst_errlog_ptr
;
1805 static int iwlagn_load_legacy_firmware(struct iwl_priv
*priv
,
1806 const struct firmware
*ucode_raw
,
1807 struct iwlagn_firmware_pieces
*pieces
)
1809 struct iwl_ucode_header
*ucode
= (void *)ucode_raw
->data
;
1810 u32 api_ver
, hdr_size
;
1813 priv
->ucode_ver
= le32_to_cpu(ucode
->ver
);
1814 api_ver
= IWL_UCODE_API(priv
->ucode_ver
);
1819 * 4965 doesn't revision the firmware file format
1820 * along with the API version, it always uses v1
1823 if ((priv
->hw_rev
& CSR_HW_REV_TYPE_MSK
) !=
1824 CSR_HW_REV_TYPE_4965
) {
1826 if (ucode_raw
->size
< hdr_size
) {
1827 IWL_ERR(priv
, "File size too small!\n");
1830 pieces
->build
= le32_to_cpu(ucode
->u
.v2
.build
);
1831 pieces
->inst_size
= le32_to_cpu(ucode
->u
.v2
.inst_size
);
1832 pieces
->data_size
= le32_to_cpu(ucode
->u
.v2
.data_size
);
1833 pieces
->init_size
= le32_to_cpu(ucode
->u
.v2
.init_size
);
1834 pieces
->init_data_size
= le32_to_cpu(ucode
->u
.v2
.init_data_size
);
1835 pieces
->boot_size
= le32_to_cpu(ucode
->u
.v2
.boot_size
);
1836 src
= ucode
->u
.v2
.data
;
1839 /* fall through for 4965 */
1844 if (ucode_raw
->size
< hdr_size
) {
1845 IWL_ERR(priv
, "File size too small!\n");
1849 pieces
->inst_size
= le32_to_cpu(ucode
->u
.v1
.inst_size
);
1850 pieces
->data_size
= le32_to_cpu(ucode
->u
.v1
.data_size
);
1851 pieces
->init_size
= le32_to_cpu(ucode
->u
.v1
.init_size
);
1852 pieces
->init_data_size
= le32_to_cpu(ucode
->u
.v1
.init_data_size
);
1853 pieces
->boot_size
= le32_to_cpu(ucode
->u
.v1
.boot_size
);
1854 src
= ucode
->u
.v1
.data
;
1858 /* Verify size of file vs. image size info in file's header */
1859 if (ucode_raw
->size
!= hdr_size
+ pieces
->inst_size
+
1860 pieces
->data_size
+ pieces
->init_size
+
1861 pieces
->init_data_size
+ pieces
->boot_size
) {
1864 "uCode file size %d does not match expected size\n",
1865 (int)ucode_raw
->size
);
1870 src
+= pieces
->inst_size
;
1872 src
+= pieces
->data_size
;
1874 src
+= pieces
->init_size
;
1875 pieces
->init_data
= src
;
1876 src
+= pieces
->init_data_size
;
1878 src
+= pieces
->boot_size
;
1883 static int iwlagn_wanted_ucode_alternative
= 1;
1885 static int iwlagn_load_firmware(struct iwl_priv
*priv
,
1886 const struct firmware
*ucode_raw
,
1887 struct iwlagn_firmware_pieces
*pieces
,
1888 struct iwlagn_ucode_capabilities
*capa
)
1890 struct iwl_tlv_ucode_header
*ucode
= (void *)ucode_raw
->data
;
1891 struct iwl_ucode_tlv
*tlv
;
1892 size_t len
= ucode_raw
->size
;
1894 int wanted_alternative
= iwlagn_wanted_ucode_alternative
, tmp
;
1897 enum iwl_ucode_tlv_type tlv_type
;
1900 if (len
< sizeof(*ucode
)) {
1901 IWL_ERR(priv
, "uCode has invalid length: %zd\n", len
);
1905 if (ucode
->magic
!= cpu_to_le32(IWL_TLV_UCODE_MAGIC
)) {
1906 IWL_ERR(priv
, "invalid uCode magic: 0X%x\n",
1907 le32_to_cpu(ucode
->magic
));
1912 * Check which alternatives are present, and "downgrade"
1913 * when the chosen alternative is not present, warning
1914 * the user when that happens. Some files may not have
1915 * any alternatives, so don't warn in that case.
1917 alternatives
= le64_to_cpu(ucode
->alternatives
);
1918 tmp
= wanted_alternative
;
1919 if (wanted_alternative
> 63)
1920 wanted_alternative
= 63;
1921 while (wanted_alternative
&& !(alternatives
& BIT(wanted_alternative
)))
1922 wanted_alternative
--;
1923 if (wanted_alternative
&& wanted_alternative
!= tmp
)
1925 "uCode alternative %d not available, choosing %d\n",
1926 tmp
, wanted_alternative
);
1928 priv
->ucode_ver
= le32_to_cpu(ucode
->ver
);
1929 pieces
->build
= le32_to_cpu(ucode
->build
);
1932 len
-= sizeof(*ucode
);
1934 while (len
>= sizeof(*tlv
)) {
1937 len
-= sizeof(*tlv
);
1940 tlv_len
= le32_to_cpu(tlv
->length
);
1941 tlv_type
= le16_to_cpu(tlv
->type
);
1942 tlv_alt
= le16_to_cpu(tlv
->alternative
);
1943 tlv_data
= tlv
->data
;
1945 if (len
< tlv_len
) {
1946 IWL_ERR(priv
, "invalid TLV len: %zd/%u\n",
1950 len
-= ALIGN(tlv_len
, 4);
1951 data
+= sizeof(*tlv
) + ALIGN(tlv_len
, 4);
1954 * Alternative 0 is always valid.
1956 * Skip alternative TLVs that are not selected.
1958 if (tlv_alt
!= 0 && tlv_alt
!= wanted_alternative
)
1962 case IWL_UCODE_TLV_INST
:
1963 pieces
->inst
= tlv_data
;
1964 pieces
->inst_size
= tlv_len
;
1966 case IWL_UCODE_TLV_DATA
:
1967 pieces
->data
= tlv_data
;
1968 pieces
->data_size
= tlv_len
;
1970 case IWL_UCODE_TLV_INIT
:
1971 pieces
->init
= tlv_data
;
1972 pieces
->init_size
= tlv_len
;
1974 case IWL_UCODE_TLV_INIT_DATA
:
1975 pieces
->init_data
= tlv_data
;
1976 pieces
->init_data_size
= tlv_len
;
1978 case IWL_UCODE_TLV_BOOT
:
1979 pieces
->boot
= tlv_data
;
1980 pieces
->boot_size
= tlv_len
;
1982 case IWL_UCODE_TLV_PROBE_MAX_LEN
:
1983 if (tlv_len
!= sizeof(u32
))
1984 goto invalid_tlv_len
;
1985 capa
->max_probe_length
=
1986 le32_to_cpup((__le32
*)tlv_data
);
1988 case IWL_UCODE_TLV_PAN
:
1990 goto invalid_tlv_len
;
1993 case IWL_UCODE_TLV_INIT_EVTLOG_PTR
:
1994 if (tlv_len
!= sizeof(u32
))
1995 goto invalid_tlv_len
;
1996 pieces
->init_evtlog_ptr
=
1997 le32_to_cpup((__le32
*)tlv_data
);
1999 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE
:
2000 if (tlv_len
!= sizeof(u32
))
2001 goto invalid_tlv_len
;
2002 pieces
->init_evtlog_size
=
2003 le32_to_cpup((__le32
*)tlv_data
);
2005 case IWL_UCODE_TLV_INIT_ERRLOG_PTR
:
2006 if (tlv_len
!= sizeof(u32
))
2007 goto invalid_tlv_len
;
2008 pieces
->init_errlog_ptr
=
2009 le32_to_cpup((__le32
*)tlv_data
);
2011 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR
:
2012 if (tlv_len
!= sizeof(u32
))
2013 goto invalid_tlv_len
;
2014 pieces
->inst_evtlog_ptr
=
2015 le32_to_cpup((__le32
*)tlv_data
);
2017 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE
:
2018 if (tlv_len
!= sizeof(u32
))
2019 goto invalid_tlv_len
;
2020 pieces
->inst_evtlog_size
=
2021 le32_to_cpup((__le32
*)tlv_data
);
2023 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR
:
2024 if (tlv_len
!= sizeof(u32
))
2025 goto invalid_tlv_len
;
2026 pieces
->inst_errlog_ptr
=
2027 le32_to_cpup((__le32
*)tlv_data
);
2029 case IWL_UCODE_TLV_ENHANCE_SENS_TBL
:
2031 goto invalid_tlv_len
;
2032 priv
->enhance_sensitivity_table
= true;
2034 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE
:
2035 if (tlv_len
!= sizeof(u32
))
2036 goto invalid_tlv_len
;
2037 capa
->standard_phy_calibration_size
=
2038 le32_to_cpup((__le32
*)tlv_data
);
2041 IWL_WARN(priv
, "unknown TLV: %d\n", tlv_type
);
2047 IWL_ERR(priv
, "invalid TLV after parsing: %zd\n", len
);
2048 iwl_print_hex_dump(priv
, IWL_DL_FW
, (u8
*)data
, len
);
2055 IWL_ERR(priv
, "TLV %d has invalid size: %u\n", tlv_type
, tlv_len
);
2056 iwl_print_hex_dump(priv
, IWL_DL_FW
, tlv_data
, tlv_len
);
2062 * iwl_ucode_callback - callback when firmware was loaded
2064 * If loaded successfully, copies the firmware into buffers
2065 * for the card to fetch (via DMA).
2067 static void iwl_ucode_callback(const struct firmware
*ucode_raw
, void *context
)
2069 struct iwl_priv
*priv
= context
;
2070 struct iwl_ucode_header
*ucode
;
2072 struct iwlagn_firmware_pieces pieces
;
2073 const unsigned int api_max
= priv
->cfg
->ucode_api_max
;
2074 const unsigned int api_min
= priv
->cfg
->ucode_api_min
;
2078 struct iwlagn_ucode_capabilities ucode_capa
= {
2079 .max_probe_length
= 200,
2080 .standard_phy_calibration_size
=
2081 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE
,
2084 memset(&pieces
, 0, sizeof(pieces
));
2087 if (priv
->fw_index
<= priv
->cfg
->ucode_api_max
)
2089 "request for firmware file '%s' failed.\n",
2090 priv
->firmware_name
);
2094 IWL_DEBUG_INFO(priv
, "Loaded firmware file '%s' (%zd bytes).\n",
2095 priv
->firmware_name
, ucode_raw
->size
);
2097 /* Make sure that we got at least the API version number */
2098 if (ucode_raw
->size
< 4) {
2099 IWL_ERR(priv
, "File size way too small!\n");
2103 /* Data from ucode file: header followed by uCode images */
2104 ucode
= (struct iwl_ucode_header
*)ucode_raw
->data
;
2107 err
= iwlagn_load_legacy_firmware(priv
, ucode_raw
, &pieces
);
2109 err
= iwlagn_load_firmware(priv
, ucode_raw
, &pieces
,
2115 api_ver
= IWL_UCODE_API(priv
->ucode_ver
);
2116 build
= pieces
.build
;
2119 * api_ver should match the api version forming part of the
2120 * firmware filename ... but we don't check for that and only rely
2121 * on the API version read from firmware header from here on forward
2123 if (api_ver
< api_min
|| api_ver
> api_max
) {
2124 IWL_ERR(priv
, "Driver unable to support your firmware API. "
2125 "Driver supports v%u, firmware is v%u.\n",
2130 if (api_ver
!= api_max
)
2131 IWL_ERR(priv
, "Firmware has old API version. Expected v%u, "
2132 "got v%u. New firmware can be obtained "
2133 "from http://www.intellinuxwireless.org.\n",
2137 sprintf(buildstr
, " build %u%s", build
,
2138 (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
)
2143 IWL_INFO(priv
, "loaded firmware version %u.%u.%u.%u%s\n",
2144 IWL_UCODE_MAJOR(priv
->ucode_ver
),
2145 IWL_UCODE_MINOR(priv
->ucode_ver
),
2146 IWL_UCODE_API(priv
->ucode_ver
),
2147 IWL_UCODE_SERIAL(priv
->ucode_ver
),
2150 snprintf(priv
->hw
->wiphy
->fw_version
,
2151 sizeof(priv
->hw
->wiphy
->fw_version
),
2153 IWL_UCODE_MAJOR(priv
->ucode_ver
),
2154 IWL_UCODE_MINOR(priv
->ucode_ver
),
2155 IWL_UCODE_API(priv
->ucode_ver
),
2156 IWL_UCODE_SERIAL(priv
->ucode_ver
),
2160 * For any of the failures below (before allocating pci memory)
2161 * we will try to load a version with a smaller API -- maybe the
2162 * user just got a corrupted version of the latest API.
2165 IWL_DEBUG_INFO(priv
, "f/w package hdr ucode version raw = 0x%x\n",
2167 IWL_DEBUG_INFO(priv
, "f/w package hdr runtime inst size = %Zd\n",
2169 IWL_DEBUG_INFO(priv
, "f/w package hdr runtime data size = %Zd\n",
2171 IWL_DEBUG_INFO(priv
, "f/w package hdr init inst size = %Zd\n",
2173 IWL_DEBUG_INFO(priv
, "f/w package hdr init data size = %Zd\n",
2174 pieces
.init_data_size
);
2175 IWL_DEBUG_INFO(priv
, "f/w package hdr boot inst size = %Zd\n",
2178 /* Verify that uCode images will fit in card's SRAM */
2179 if (pieces
.inst_size
> priv
->hw_params
.max_inst_size
) {
2180 IWL_ERR(priv
, "uCode instr len %Zd too large to fit in\n",
2185 if (pieces
.data_size
> priv
->hw_params
.max_data_size
) {
2186 IWL_ERR(priv
, "uCode data len %Zd too large to fit in\n",
2191 if (pieces
.init_size
> priv
->hw_params
.max_inst_size
) {
2192 IWL_ERR(priv
, "uCode init instr len %Zd too large to fit in\n",
2197 if (pieces
.init_data_size
> priv
->hw_params
.max_data_size
) {
2198 IWL_ERR(priv
, "uCode init data len %Zd too large to fit in\n",
2199 pieces
.init_data_size
);
2203 if (pieces
.boot_size
> priv
->hw_params
.max_bsm_size
) {
2204 IWL_ERR(priv
, "uCode boot instr len %Zd too large to fit in\n",
2209 /* Allocate ucode buffers for card's bus-master loading ... */
2211 /* Runtime instructions and 2 copies of data:
2212 * 1) unmodified from disk
2213 * 2) backup cache for save/restore during power-downs */
2214 priv
->ucode_code
.len
= pieces
.inst_size
;
2215 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_code
);
2217 priv
->ucode_data
.len
= pieces
.data_size
;
2218 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_data
);
2220 priv
->ucode_data_backup
.len
= pieces
.data_size
;
2221 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_data_backup
);
2223 if (!priv
->ucode_code
.v_addr
|| !priv
->ucode_data
.v_addr
||
2224 !priv
->ucode_data_backup
.v_addr
)
2227 /* Initialization instructions and data */
2228 if (pieces
.init_size
&& pieces
.init_data_size
) {
2229 priv
->ucode_init
.len
= pieces
.init_size
;
2230 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_init
);
2232 priv
->ucode_init_data
.len
= pieces
.init_data_size
;
2233 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_init_data
);
2235 if (!priv
->ucode_init
.v_addr
|| !priv
->ucode_init_data
.v_addr
)
2239 /* Bootstrap (instructions only, no data) */
2240 if (pieces
.boot_size
) {
2241 priv
->ucode_boot
.len
= pieces
.boot_size
;
2242 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_boot
);
2244 if (!priv
->ucode_boot
.v_addr
)
2248 /* Now that we can no longer fail, copy information */
2251 * The (size - 16) / 12 formula is based on the information recorded
2252 * for each event, which is of mode 1 (including timestamp) for all
2253 * new microcodes that include this information.
2255 priv
->_agn
.init_evtlog_ptr
= pieces
.init_evtlog_ptr
;
2256 if (pieces
.init_evtlog_size
)
2257 priv
->_agn
.init_evtlog_size
= (pieces
.init_evtlog_size
- 16)/12;
2259 priv
->_agn
.init_evtlog_size
= priv
->cfg
->max_event_log_size
;
2260 priv
->_agn
.init_errlog_ptr
= pieces
.init_errlog_ptr
;
2261 priv
->_agn
.inst_evtlog_ptr
= pieces
.inst_evtlog_ptr
;
2262 if (pieces
.inst_evtlog_size
)
2263 priv
->_agn
.inst_evtlog_size
= (pieces
.inst_evtlog_size
- 16)/12;
2265 priv
->_agn
.inst_evtlog_size
= priv
->cfg
->max_event_log_size
;
2266 priv
->_agn
.inst_errlog_ptr
= pieces
.inst_errlog_ptr
;
2268 if (ucode_capa
.pan
) {
2269 priv
->valid_contexts
|= BIT(IWL_RXON_CTX_PAN
);
2270 priv
->sta_key_max_num
= STA_KEY_MAX_NUM_PAN
;
2272 priv
->sta_key_max_num
= STA_KEY_MAX_NUM
;
2274 /* Copy images into buffers for card's bus-master reads ... */
2276 /* Runtime instructions (first block of data in file) */
2277 IWL_DEBUG_INFO(priv
, "Copying (but not loading) uCode instr len %Zd\n",
2279 memcpy(priv
->ucode_code
.v_addr
, pieces
.inst
, pieces
.inst_size
);
2281 IWL_DEBUG_INFO(priv
, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2282 priv
->ucode_code
.v_addr
, (u32
)priv
->ucode_code
.p_addr
);
2286 * NOTE: Copy into backup buffer will be done in iwl_up()
2288 IWL_DEBUG_INFO(priv
, "Copying (but not loading) uCode data len %Zd\n",
2290 memcpy(priv
->ucode_data
.v_addr
, pieces
.data
, pieces
.data_size
);
2291 memcpy(priv
->ucode_data_backup
.v_addr
, pieces
.data
, pieces
.data_size
);
2293 /* Initialization instructions */
2294 if (pieces
.init_size
) {
2295 IWL_DEBUG_INFO(priv
, "Copying (but not loading) init instr len %Zd\n",
2297 memcpy(priv
->ucode_init
.v_addr
, pieces
.init
, pieces
.init_size
);
2300 /* Initialization data */
2301 if (pieces
.init_data_size
) {
2302 IWL_DEBUG_INFO(priv
, "Copying (but not loading) init data len %Zd\n",
2303 pieces
.init_data_size
);
2304 memcpy(priv
->ucode_init_data
.v_addr
, pieces
.init_data
,
2305 pieces
.init_data_size
);
2308 /* Bootstrap instructions */
2309 IWL_DEBUG_INFO(priv
, "Copying (but not loading) boot instr len %Zd\n",
2311 memcpy(priv
->ucode_boot
.v_addr
, pieces
.boot
, pieces
.boot_size
);
2314 * figure out the offset of chain noise reset and gain commands
2315 * base on the size of standard phy calibration commands table size
2317 if (ucode_capa
.standard_phy_calibration_size
>
2318 IWL_MAX_PHY_CALIBRATE_TBL_SIZE
)
2319 ucode_capa
.standard_phy_calibration_size
=
2320 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE
;
2322 priv
->_agn
.phy_calib_chain_noise_reset_cmd
=
2323 ucode_capa
.standard_phy_calibration_size
;
2324 priv
->_agn
.phy_calib_chain_noise_gain_cmd
=
2325 ucode_capa
.standard_phy_calibration_size
+ 1;
2327 /**************************************************
2328 * This is still part of probe() in a sense...
2330 * 9. Setup and register with mac80211 and debugfs
2331 **************************************************/
2332 err
= iwl_mac_setup_register(priv
, &ucode_capa
);
2336 err
= iwl_dbgfs_register(priv
, DRV_NAME
);
2338 IWL_ERR(priv
, "failed to create debugfs files. Ignoring error: %d\n", err
);
2340 err
= sysfs_create_group(&priv
->pci_dev
->dev
.kobj
,
2341 &iwl_attribute_group
);
2343 IWL_ERR(priv
, "failed to create sysfs device attributes\n");
2347 /* We have our copies now, allow OS release its copies */
2348 release_firmware(ucode_raw
);
2349 complete(&priv
->_agn
.firmware_loading_complete
);
2353 /* try next, if any */
2354 if (iwl_request_firmware(priv
, false))
2356 release_firmware(ucode_raw
);
2360 IWL_ERR(priv
, "failed to allocate pci memory\n");
2361 iwl_dealloc_ucode_pci(priv
);
2363 complete(&priv
->_agn
.firmware_loading_complete
);
2364 device_release_driver(&priv
->pci_dev
->dev
);
2365 release_firmware(ucode_raw
);
2368 static const char *desc_lookup_text
[] = {
2373 "NMI_INTERRUPT_WDG",
2377 "HW_ERROR_TUNE_LOCK",
2378 "HW_ERROR_TEMPERATURE",
2379 "ILLEGAL_CHAN_FREQ",
2382 "NMI_INTERRUPT_HOST",
2383 "NMI_INTERRUPT_ACTION_PT",
2384 "NMI_INTERRUPT_UNKNOWN",
2385 "UCODE_VERSION_MISMATCH",
2386 "HW_ERROR_ABS_LOCK",
2387 "HW_ERROR_CAL_LOCK_FAIL",
2388 "NMI_INTERRUPT_INST_ACTION_PT",
2389 "NMI_INTERRUPT_DATA_ACTION_PT",
2391 "NMI_INTERRUPT_TRM",
2392 "NMI_INTERRUPT_BREAK_POINT"
2399 static struct { char *name
; u8 num
; } advanced_lookup
[] = {
2400 { "NMI_INTERRUPT_WDG", 0x34 },
2401 { "SYSASSERT", 0x35 },
2402 { "UCODE_VERSION_MISMATCH", 0x37 },
2403 { "BAD_COMMAND", 0x38 },
2404 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2405 { "FATAL_ERROR", 0x3D },
2406 { "NMI_TRM_HW_ERR", 0x46 },
2407 { "NMI_INTERRUPT_TRM", 0x4C },
2408 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2409 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2410 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2411 { "NMI_INTERRUPT_HOST", 0x66 },
2412 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2413 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2414 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2415 { "ADVANCED_SYSASSERT", 0 },
2418 static const char *desc_lookup(u32 num
)
2421 int max
= ARRAY_SIZE(desc_lookup_text
);
2424 return desc_lookup_text
[num
];
2426 max
= ARRAY_SIZE(advanced_lookup
) - 1;
2427 for (i
= 0; i
< max
; i
++) {
2428 if (advanced_lookup
[i
].num
== num
)
2431 return advanced_lookup
[i
].name
;
2434 #define ERROR_START_OFFSET (1 * sizeof(u32))
2435 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
2437 void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
2440 u32 desc
, time
, count
, base
, data1
;
2441 u32 blink1
, blink2
, ilink1
, ilink2
;
2444 if (priv
->ucode_type
== UCODE_INIT
) {
2445 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
2447 base
= priv
->_agn
.init_errlog_ptr
;
2449 base
= le32_to_cpu(priv
->card_alive
.error_event_table_ptr
);
2451 base
= priv
->_agn
.inst_errlog_ptr
;
2454 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
2456 "Not valid error log pointer 0x%08X for %s uCode\n",
2457 base
, (priv
->ucode_type
== UCODE_INIT
) ? "Init" : "RT");
2461 count
= iwl_read_targ_mem(priv
, base
);
2463 if (ERROR_START_OFFSET
<= count
* ERROR_ELEM_SIZE
) {
2464 IWL_ERR(priv
, "Start IWL Error Log Dump:\n");
2465 IWL_ERR(priv
, "Status: 0x%08lX, count: %d\n",
2466 priv
->status
, count
);
2469 desc
= iwl_read_targ_mem(priv
, base
+ 1 * sizeof(u32
));
2470 pc
= iwl_read_targ_mem(priv
, base
+ 2 * sizeof(u32
));
2471 blink1
= iwl_read_targ_mem(priv
, base
+ 3 * sizeof(u32
));
2472 blink2
= iwl_read_targ_mem(priv
, base
+ 4 * sizeof(u32
));
2473 ilink1
= iwl_read_targ_mem(priv
, base
+ 5 * sizeof(u32
));
2474 ilink2
= iwl_read_targ_mem(priv
, base
+ 6 * sizeof(u32
));
2475 data1
= iwl_read_targ_mem(priv
, base
+ 7 * sizeof(u32
));
2476 data2
= iwl_read_targ_mem(priv
, base
+ 8 * sizeof(u32
));
2477 line
= iwl_read_targ_mem(priv
, base
+ 9 * sizeof(u32
));
2478 time
= iwl_read_targ_mem(priv
, base
+ 11 * sizeof(u32
));
2479 hcmd
= iwl_read_targ_mem(priv
, base
+ 22 * sizeof(u32
));
2481 trace_iwlwifi_dev_ucode_error(priv
, desc
, time
, data1
, data2
, line
,
2482 blink1
, blink2
, ilink1
, ilink2
);
2484 IWL_ERR(priv
, "Desc Time "
2485 "data1 data2 line\n");
2486 IWL_ERR(priv
, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2487 desc_lookup(desc
), desc
, time
, data1
, data2
, line
);
2488 IWL_ERR(priv
, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2489 IWL_ERR(priv
, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2490 pc
, blink1
, blink2
, ilink1
, ilink2
, hcmd
);
2493 #define EVENT_START_OFFSET (4 * sizeof(u32))
2496 * iwl_print_event_log - Dump error event log to syslog
2499 static int iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
2500 u32 num_events
, u32 mode
,
2501 int pos
, char **buf
, size_t bufsz
)
2504 u32 base
; /* SRAM byte address of event log header */
2505 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
2506 u32 ptr
; /* SRAM byte address of log data */
2507 u32 ev
, time
, data
; /* event log data */
2508 unsigned long reg_flags
;
2510 if (num_events
== 0)
2513 if (priv
->ucode_type
== UCODE_INIT
) {
2514 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
2516 base
= priv
->_agn
.init_evtlog_ptr
;
2518 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
2520 base
= priv
->_agn
.inst_evtlog_ptr
;
2524 event_size
= 2 * sizeof(u32
);
2526 event_size
= 3 * sizeof(u32
);
2528 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
2530 /* Make sure device is powered up for SRAM reads */
2531 spin_lock_irqsave(&priv
->reg_lock
, reg_flags
);
2532 iwl_grab_nic_access(priv
);
2534 /* Set starting address; reads will auto-increment */
2535 _iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, ptr
);
2538 /* "time" is actually "data" for mode 0 (no timestamp).
2539 * place event id # at far right for easier visual parsing. */
2540 for (i
= 0; i
< num_events
; i
++) {
2541 ev
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
2542 time
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
2546 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2547 "EVT_LOG:0x%08x:%04u\n",
2550 trace_iwlwifi_dev_ucode_event(priv
, 0,
2552 IWL_ERR(priv
, "EVT_LOG:0x%08x:%04u\n",
2556 data
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
2558 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2559 "EVT_LOGT:%010u:0x%08x:%04u\n",
2562 IWL_ERR(priv
, "EVT_LOGT:%010u:0x%08x:%04u\n",
2564 trace_iwlwifi_dev_ucode_event(priv
, time
,
2570 /* Allow device to power down */
2571 iwl_release_nic_access(priv
);
2572 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
2577 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2579 static int iwl_print_last_event_logs(struct iwl_priv
*priv
, u32 capacity
,
2580 u32 num_wraps
, u32 next_entry
,
2582 int pos
, char **buf
, size_t bufsz
)
2585 * display the newest DEFAULT_LOG_ENTRIES entries
2586 * i.e the entries just before the next ont that uCode would fill.
2589 if (next_entry
< size
) {
2590 pos
= iwl_print_event_log(priv
,
2591 capacity
- (size
- next_entry
),
2592 size
- next_entry
, mode
,
2594 pos
= iwl_print_event_log(priv
, 0,
2598 pos
= iwl_print_event_log(priv
, next_entry
- size
,
2599 size
, mode
, pos
, buf
, bufsz
);
2601 if (next_entry
< size
) {
2602 pos
= iwl_print_event_log(priv
, 0, next_entry
,
2603 mode
, pos
, buf
, bufsz
);
2605 pos
= iwl_print_event_log(priv
, next_entry
- size
,
2606 size
, mode
, pos
, buf
, bufsz
);
2612 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2614 int iwl_dump_nic_event_log(struct iwl_priv
*priv
, bool full_log
,
2615 char **buf
, bool display
)
2617 u32 base
; /* SRAM byte address of event log header */
2618 u32 capacity
; /* event log capacity in # entries */
2619 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
2620 u32 num_wraps
; /* # times uCode wrapped to top of log */
2621 u32 next_entry
; /* index of next entry to be written by uCode */
2622 u32 size
; /* # entries that we'll print */
2627 if (priv
->ucode_type
== UCODE_INIT
) {
2628 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
2629 logsize
= priv
->_agn
.init_evtlog_size
;
2631 base
= priv
->_agn
.init_evtlog_ptr
;
2633 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
2634 logsize
= priv
->_agn
.inst_evtlog_size
;
2636 base
= priv
->_agn
.inst_evtlog_ptr
;
2639 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
2641 "Invalid event log pointer 0x%08X for %s uCode\n",
2642 base
, (priv
->ucode_type
== UCODE_INIT
) ? "Init" : "RT");
2646 /* event log header */
2647 capacity
= iwl_read_targ_mem(priv
, base
);
2648 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
2649 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
2650 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
2652 if (capacity
> logsize
) {
2653 IWL_ERR(priv
, "Log capacity %d is bogus, limit to %d entries\n",
2658 if (next_entry
> logsize
) {
2659 IWL_ERR(priv
, "Log write index %d is bogus, limit to %d\n",
2660 next_entry
, logsize
);
2661 next_entry
= logsize
;
2664 size
= num_wraps
? capacity
: next_entry
;
2666 /* bail out if nothing in log */
2668 IWL_ERR(priv
, "Start IWL Event Log Dump: nothing in log\n");
2672 /* enable/disable bt channel announcement */
2673 priv
->bt_ch_announce
= iwlagn_bt_ch_announce
;
2675 #ifdef CONFIG_IWLWIFI_DEBUG
2676 if (!(iwl_get_debug_level(priv
) & IWL_DL_FW_ERRORS
) && !full_log
)
2677 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
2678 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
2680 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
2681 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
2683 IWL_ERR(priv
, "Start IWL Event Log Dump: display last %u entries\n",
2686 #ifdef CONFIG_IWLWIFI_DEBUG
2689 bufsz
= capacity
* 48;
2692 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
2696 if ((iwl_get_debug_level(priv
) & IWL_DL_FW_ERRORS
) || full_log
) {
2698 * if uCode has wrapped back to top of log,
2699 * start at the oldest entry,
2700 * i.e the next one that uCode would fill.
2703 pos
= iwl_print_event_log(priv
, next_entry
,
2704 capacity
- next_entry
, mode
,
2706 /* (then/else) start at top of log */
2707 pos
= iwl_print_event_log(priv
, 0,
2708 next_entry
, mode
, pos
, buf
, bufsz
);
2710 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
2711 next_entry
, size
, mode
,
2714 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
2715 next_entry
, size
, mode
,
2721 static void iwl_rf_kill_ct_config(struct iwl_priv
*priv
)
2723 struct iwl_ct_kill_config cmd
;
2724 struct iwl_ct_kill_throttling_config adv_cmd
;
2725 unsigned long flags
;
2728 spin_lock_irqsave(&priv
->lock
, flags
);
2729 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
2730 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT
);
2731 spin_unlock_irqrestore(&priv
->lock
, flags
);
2732 priv
->thermal_throttle
.ct_kill_toggle
= false;
2734 if (priv
->cfg
->support_ct_kill_exit
) {
2735 adv_cmd
.critical_temperature_enter
=
2736 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
2737 adv_cmd
.critical_temperature_exit
=
2738 cpu_to_le32(priv
->hw_params
.ct_kill_exit_threshold
);
2740 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
2741 sizeof(adv_cmd
), &adv_cmd
);
2743 IWL_ERR(priv
, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2745 IWL_DEBUG_INFO(priv
, "REPLY_CT_KILL_CONFIG_CMD "
2747 "critical temperature enter is %d,"
2749 priv
->hw_params
.ct_kill_threshold
,
2750 priv
->hw_params
.ct_kill_exit_threshold
);
2752 cmd
.critical_temperature_R
=
2753 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
2755 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
2758 IWL_ERR(priv
, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2760 IWL_DEBUG_INFO(priv
, "REPLY_CT_KILL_CONFIG_CMD "
2762 "critical temperature is %d\n",
2763 priv
->hw_params
.ct_kill_threshold
);
2768 * iwl_alive_start - called after REPLY_ALIVE notification received
2769 * from protocol/runtime uCode (initialization uCode's
2770 * Alive gets handled by iwl_init_alive_start()).
2772 static void iwl_alive_start(struct iwl_priv
*priv
)
2775 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
2777 IWL_DEBUG_INFO(priv
, "Runtime Alive received.\n");
2779 if (priv
->card_alive
.is_valid
!= UCODE_VALID_OK
) {
2780 /* We had an error bringing up the hardware, so take it
2781 * all the way back down so we can try again */
2782 IWL_DEBUG_INFO(priv
, "Alive failed.\n");
2786 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2787 * This is a paranoid check, because we would not have gotten the
2788 * "runtime" alive if code weren't properly loaded. */
2789 if (iwl_verify_ucode(priv
)) {
2790 /* Runtime instruction load was bad;
2791 * take it all the way back down so we can try again */
2792 IWL_DEBUG_INFO(priv
, "Bad runtime uCode load.\n");
2796 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
2799 "Could not complete ALIVE transition [ntf]: %d\n", ret
);
2803 /* After the ALIVE response, we can send host commands to the uCode */
2804 set_bit(STATUS_ALIVE
, &priv
->status
);
2806 if (priv
->cfg
->ops
->lib
->recover_from_tx_stall
) {
2807 /* Enable timer to monitor the driver queues */
2808 mod_timer(&priv
->monitor_recover
,
2810 msecs_to_jiffies(priv
->cfg
->monitor_recover_period
));
2813 if (iwl_is_rfkill(priv
))
2816 ieee80211_wake_queues(priv
->hw
);
2818 priv
->active_rate
= IWL_RATES_MASK
;
2820 /* Configure Tx antenna selection based on H/W config */
2821 if (priv
->cfg
->ops
->hcmd
->set_tx_ant
)
2822 priv
->cfg
->ops
->hcmd
->set_tx_ant(priv
, priv
->cfg
->valid_tx_ant
);
2824 if (iwl_is_associated_ctx(ctx
)) {
2825 struct iwl_rxon_cmd
*active_rxon
=
2826 (struct iwl_rxon_cmd
*)&ctx
->active
;
2827 /* apply any changes in staging */
2828 ctx
->staging
.filter_flags
|= RXON_FILTER_ASSOC_MSK
;
2829 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
2831 /* Initialize our rx_config data */
2832 iwl_connection_init_rx_config(priv
, NULL
);
2834 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
2835 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
2838 if (!priv
->cfg
->advanced_bt_coexist
) {
2839 /* Configure Bluetooth device coexistence support */
2840 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
2843 iwl_reset_run_time_calib(priv
);
2845 /* Configure the adapter for unassociated operation */
2846 iwlcore_commit_rxon(priv
, ctx
);
2848 /* At this point, the NIC is initialized and operational */
2849 iwl_rf_kill_ct_config(priv
);
2851 iwl_leds_init(priv
);
2853 IWL_DEBUG_INFO(priv
, "ALIVE processing complete.\n");
2854 set_bit(STATUS_READY
, &priv
->status
);
2855 wake_up_interruptible(&priv
->wait_command_queue
);
2857 iwl_power_update_mode(priv
, true);
2858 IWL_DEBUG_INFO(priv
, "Updated power mode\n");
2864 queue_work(priv
->workqueue
, &priv
->restart
);
2867 static void iwl_cancel_deferred_work(struct iwl_priv
*priv
);
2869 static void __iwl_down(struct iwl_priv
*priv
)
2871 unsigned long flags
;
2872 int exit_pending
= test_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2874 IWL_DEBUG_INFO(priv
, DRV_NAME
" is going down\n");
2877 set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2879 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2880 * to prevent rearm timer */
2881 if (priv
->cfg
->ops
->lib
->recover_from_tx_stall
)
2882 del_timer_sync(&priv
->monitor_recover
);
2884 iwl_clear_ucode_stations(priv
, NULL
);
2885 iwl_dealloc_bcast_stations(priv
);
2886 iwl_clear_driver_stations(priv
);
2888 /* reset BT coex data */
2889 priv
->bt_status
= 0;
2890 priv
->bt_traffic_load
= priv
->cfg
->bt_init_traffic_load
;
2891 priv
->bt_sco_active
= false;
2892 priv
->bt_full_concurrent
= false;
2893 priv
->bt_ci_compliance
= 0;
2895 /* Unblock any waiting calls */
2896 wake_up_interruptible_all(&priv
->wait_command_queue
);
2898 /* Wipe out the EXIT_PENDING status bit if we are not actually
2899 * exiting the module */
2901 clear_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2903 /* stop and reset the on-board processor */
2904 iwl_write32(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
2906 /* tell the device to stop sending interrupts */
2907 spin_lock_irqsave(&priv
->lock
, flags
);
2908 iwl_disable_interrupts(priv
);
2909 spin_unlock_irqrestore(&priv
->lock
, flags
);
2910 iwl_synchronize_irq(priv
);
2912 if (priv
->mac80211_registered
)
2913 ieee80211_stop_queues(priv
->hw
);
2915 /* If we have not previously called iwl_init() then
2916 * clear all bits but the RF Kill bit and return */
2917 if (!iwl_is_init(priv
)) {
2918 priv
->status
= test_bit(STATUS_RF_KILL_HW
, &priv
->status
) <<
2920 test_bit(STATUS_GEO_CONFIGURED
, &priv
->status
) <<
2921 STATUS_GEO_CONFIGURED
|
2922 test_bit(STATUS_EXIT_PENDING
, &priv
->status
) <<
2923 STATUS_EXIT_PENDING
;
2927 /* ...otherwise clear out all the status bits but the RF Kill
2928 * bit and continue taking the NIC down. */
2929 priv
->status
&= test_bit(STATUS_RF_KILL_HW
, &priv
->status
) <<
2931 test_bit(STATUS_GEO_CONFIGURED
, &priv
->status
) <<
2932 STATUS_GEO_CONFIGURED
|
2933 test_bit(STATUS_FW_ERROR
, &priv
->status
) <<
2935 test_bit(STATUS_EXIT_PENDING
, &priv
->status
) <<
2936 STATUS_EXIT_PENDING
;
2938 /* device going down, Stop using ICT table */
2939 iwl_disable_ict(priv
);
2941 iwlagn_txq_ctx_stop(priv
);
2942 iwlagn_rxq_stop(priv
);
2944 /* Power-down device's busmaster DMA clocks */
2945 iwl_write_prph(priv
, APMG_CLK_DIS_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
2948 /* Make sure (redundant) we've released our request to stay awake */
2949 iwl_clear_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
2951 /* Stop the device, and put it in low power state */
2952 priv
->cfg
->ops
->lib
->apm_ops
.stop(priv
);
2955 memset(&priv
->card_alive
, 0, sizeof(struct iwl_alive_resp
));
2957 if (priv
->ibss_beacon
)
2958 dev_kfree_skb(priv
->ibss_beacon
);
2959 priv
->ibss_beacon
= NULL
;
2961 /* clear out any free frames */
2962 iwl_clear_free_frames(priv
);
2965 static void iwl_down(struct iwl_priv
*priv
)
2967 mutex_lock(&priv
->mutex
);
2969 mutex_unlock(&priv
->mutex
);
2971 iwl_cancel_deferred_work(priv
);
2974 #define HW_READY_TIMEOUT (50)
2976 static int iwl_set_hw_ready(struct iwl_priv
*priv
)
2980 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2981 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
2983 /* See if we got it */
2984 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2985 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
2986 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
2988 if (ret
!= -ETIMEDOUT
)
2989 priv
->hw_ready
= true;
2991 priv
->hw_ready
= false;
2993 IWL_DEBUG_INFO(priv
, "hardware %s\n",
2994 (priv
->hw_ready
== 1) ? "ready" : "not ready");
2998 static int iwl_prepare_card_hw(struct iwl_priv
*priv
)
3002 IWL_DEBUG_INFO(priv
, "iwl_prepare_card_hw enter\n");
3004 ret
= iwl_set_hw_ready(priv
);
3008 /* If HW is not ready, prepare the conditions to check again */
3009 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
3010 CSR_HW_IF_CONFIG_REG_PREPARE
);
3012 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
3013 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
3014 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
3016 /* HW should be ready by now, check again. */
3017 if (ret
!= -ETIMEDOUT
)
3018 iwl_set_hw_ready(priv
);
3023 #define MAX_HW_RESTARTS 5
3025 static int __iwl_up(struct iwl_priv
*priv
)
3027 struct iwl_rxon_context
*ctx
;
3031 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
)) {
3032 IWL_WARN(priv
, "Exit pending; will not bring the NIC up\n");
3036 if (!priv
->ucode_data_backup
.v_addr
|| !priv
->ucode_data
.v_addr
) {
3037 IWL_ERR(priv
, "ucode not available for device bringup\n");
3041 for_each_context(priv
, ctx
) {
3042 ret
= iwl_alloc_bcast_station(priv
, ctx
, true);
3044 iwl_dealloc_bcast_stations(priv
);
3049 iwl_prepare_card_hw(priv
);
3051 if (!priv
->hw_ready
) {
3052 IWL_WARN(priv
, "Exit HW not ready\n");
3056 /* If platform's RF_KILL switch is NOT set to KILL */
3057 if (iwl_read32(priv
, CSR_GP_CNTRL
) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
3058 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
3060 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
3062 if (iwl_is_rfkill(priv
)) {
3063 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, true);
3065 iwl_enable_interrupts(priv
);
3066 IWL_WARN(priv
, "Radio disabled by HW RF Kill switch\n");
3070 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
3072 /* must be initialised before iwl_hw_nic_init */
3073 if (priv
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
3074 priv
->cmd_queue
= IWL_IPAN_CMD_QUEUE_NUM
;
3076 priv
->cmd_queue
= IWL_DEFAULT_CMD_QUEUE_NUM
;
3078 ret
= iwlagn_hw_nic_init(priv
);
3080 IWL_ERR(priv
, "Unable to init nic\n");
3084 /* make sure rfkill handshake bits are cleared */
3085 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
3086 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
3087 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
3089 /* clear (again), then enable host interrupts */
3090 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
3091 iwl_enable_interrupts(priv
);
3093 /* really make sure rfkill handshake bits are cleared */
3094 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
3095 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
3097 /* Copy original ucode data image from disk into backup cache.
3098 * This will be used to initialize the on-board processor's
3099 * data SRAM for a clean start when the runtime program first loads. */
3100 memcpy(priv
->ucode_data_backup
.v_addr
, priv
->ucode_data
.v_addr
,
3101 priv
->ucode_data
.len
);
3103 for (i
= 0; i
< MAX_HW_RESTARTS
; i
++) {
3105 /* load bootstrap state machine,
3106 * load bootstrap program into processor's memory,
3107 * prepare to load the "initialize" uCode */
3108 ret
= priv
->cfg
->ops
->lib
->load_ucode(priv
);
3111 IWL_ERR(priv
, "Unable to set up bootstrap uCode: %d\n",
3116 /* start card; "initialize" will load runtime ucode */
3117 iwl_nic_start(priv
);
3119 IWL_DEBUG_INFO(priv
, DRV_NAME
" is coming up\n");
3124 set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
3126 clear_bit(STATUS_EXIT_PENDING
, &priv
->status
);
3128 /* tried to restart and config the device for as long as our
3129 * patience could withstand */
3130 IWL_ERR(priv
, "Unable to initialize device after %d attempts.\n", i
);
3135 /*****************************************************************************
3137 * Workqueue callbacks
3139 *****************************************************************************/
3141 static void iwl_bg_init_alive_start(struct work_struct
*data
)
3143 struct iwl_priv
*priv
=
3144 container_of(data
, struct iwl_priv
, init_alive_start
.work
);
3146 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3149 mutex_lock(&priv
->mutex
);
3150 priv
->cfg
->ops
->lib
->init_alive_start(priv
);
3151 mutex_unlock(&priv
->mutex
);
3154 static void iwl_bg_alive_start(struct work_struct
*data
)
3156 struct iwl_priv
*priv
=
3157 container_of(data
, struct iwl_priv
, alive_start
.work
);
3159 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3162 /* enable dram interrupt */
3163 iwl_reset_ict(priv
);
3165 mutex_lock(&priv
->mutex
);
3166 iwl_alive_start(priv
);
3167 mutex_unlock(&priv
->mutex
);
3170 static void iwl_bg_run_time_calib_work(struct work_struct
*work
)
3172 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
3173 run_time_calib_work
);
3175 mutex_lock(&priv
->mutex
);
3177 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
) ||
3178 test_bit(STATUS_SCANNING
, &priv
->status
)) {
3179 mutex_unlock(&priv
->mutex
);
3183 if (priv
->start_calib
) {
3184 if (priv
->cfg
->bt_statistics
) {
3185 iwl_chain_noise_calibration(priv
,
3186 (void *)&priv
->_agn
.statistics_bt
);
3187 iwl_sensitivity_calibration(priv
,
3188 (void *)&priv
->_agn
.statistics_bt
);
3190 iwl_chain_noise_calibration(priv
,
3191 (void *)&priv
->_agn
.statistics
);
3192 iwl_sensitivity_calibration(priv
,
3193 (void *)&priv
->_agn
.statistics
);
3197 mutex_unlock(&priv
->mutex
);
3200 static void iwl_bg_restart(struct work_struct
*data
)
3202 struct iwl_priv
*priv
= container_of(data
, struct iwl_priv
, restart
);
3204 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3207 if (test_and_clear_bit(STATUS_FW_ERROR
, &priv
->status
)) {
3208 struct iwl_rxon_context
*ctx
;
3209 bool bt_sco
, bt_full_concurrent
;
3210 u8 bt_ci_compliance
;
3214 mutex_lock(&priv
->mutex
);
3215 for_each_context(priv
, ctx
)
3220 * __iwl_down() will clear the BT status variables,
3221 * which is correct, but when we restart we really
3222 * want to keep them so restore them afterwards.
3224 * The restart process will later pick them up and
3225 * re-configure the hw when we reconfigure the BT
3228 bt_sco
= priv
->bt_sco_active
;
3229 bt_full_concurrent
= priv
->bt_full_concurrent
;
3230 bt_ci_compliance
= priv
->bt_ci_compliance
;
3231 bt_load
= priv
->bt_traffic_load
;
3232 bt_status
= priv
->bt_status
;
3236 priv
->bt_sco_active
= bt_sco
;
3237 priv
->bt_full_concurrent
= bt_full_concurrent
;
3238 priv
->bt_ci_compliance
= bt_ci_compliance
;
3239 priv
->bt_traffic_load
= bt_load
;
3240 priv
->bt_status
= bt_status
;
3242 mutex_unlock(&priv
->mutex
);
3243 iwl_cancel_deferred_work(priv
);
3244 ieee80211_restart_hw(priv
->hw
);
3248 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3251 mutex_lock(&priv
->mutex
);
3253 mutex_unlock(&priv
->mutex
);
3257 static void iwl_bg_rx_replenish(struct work_struct
*data
)
3259 struct iwl_priv
*priv
=
3260 container_of(data
, struct iwl_priv
, rx_replenish
);
3262 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3265 mutex_lock(&priv
->mutex
);
3266 iwlagn_rx_replenish(priv
);
3267 mutex_unlock(&priv
->mutex
);
3270 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3272 void iwl_post_associate(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
)
3274 struct iwl_rxon_context
*ctx
;
3275 struct ieee80211_conf
*conf
= NULL
;
3278 if (!vif
|| !priv
->is_open
)
3281 ctx
= iwl_rxon_ctx_from_vif(vif
);
3283 if (vif
->type
== NL80211_IFTYPE_AP
) {
3284 IWL_ERR(priv
, "%s Should not be called in AP mode\n", __func__
);
3288 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3291 iwl_scan_cancel_timeout(priv
, 200);
3293 conf
= ieee80211_get_hw_conf(priv
->hw
);
3295 ctx
->staging
.filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
3296 iwlcore_commit_rxon(priv
, ctx
);
3298 ret
= iwl_send_rxon_timing(priv
, ctx
);
3300 IWL_WARN(priv
, "RXON timing - "
3301 "Attempting to continue.\n");
3303 ctx
->staging
.filter_flags
|= RXON_FILTER_ASSOC_MSK
;
3305 iwl_set_rxon_ht(priv
, &priv
->current_ht_config
);
3307 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
3308 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
3310 ctx
->staging
.assoc_id
= cpu_to_le16(vif
->bss_conf
.aid
);
3312 IWL_DEBUG_ASSOC(priv
, "assoc id %d beacon interval %d\n",
3313 vif
->bss_conf
.aid
, vif
->bss_conf
.beacon_int
);
3315 if (vif
->bss_conf
.use_short_preamble
)
3316 ctx
->staging
.flags
|= RXON_FLG_SHORT_PREAMBLE_MSK
;
3318 ctx
->staging
.flags
&= ~RXON_FLG_SHORT_PREAMBLE_MSK
;
3320 if (ctx
->staging
.flags
& RXON_FLG_BAND_24G_MSK
) {
3321 if (vif
->bss_conf
.use_short_slot
)
3322 ctx
->staging
.flags
|= RXON_FLG_SHORT_SLOT_MSK
;
3324 ctx
->staging
.flags
&= ~RXON_FLG_SHORT_SLOT_MSK
;
3327 iwlcore_commit_rxon(priv
, ctx
);
3329 IWL_DEBUG_ASSOC(priv
, "Associated as %d to: %pM\n",
3330 vif
->bss_conf
.aid
, ctx
->active
.bssid_addr
);
3332 switch (vif
->type
) {
3333 case NL80211_IFTYPE_STATION
:
3335 case NL80211_IFTYPE_ADHOC
:
3336 iwl_send_beacon_cmd(priv
);
3339 IWL_ERR(priv
, "%s Should not be called in %d mode\n",
3340 __func__
, vif
->type
);
3344 /* the chain noise calibration will enabled PM upon completion
3345 * If chain noise has already been run, then we need to enable
3346 * power management here */
3347 if (priv
->chain_noise_data
.state
== IWL_CHAIN_NOISE_DONE
)
3348 iwl_power_update_mode(priv
, false);
3350 /* Enable Rx differential gain and sensitivity calibrations */
3351 iwl_chain_noise_reset(priv
);
3352 priv
->start_calib
= 1;
3356 /*****************************************************************************
3358 * mac80211 entry point functions
3360 *****************************************************************************/
3362 #define UCODE_READY_TIMEOUT (4 * HZ)
3365 * Not a mac80211 entry point function, but it fits in with all the
3366 * other mac80211 functions grouped here.
3368 static int iwl_mac_setup_register(struct iwl_priv
*priv
,
3369 struct iwlagn_ucode_capabilities
*capa
)
3372 struct ieee80211_hw
*hw
= priv
->hw
;
3373 hw
->rate_control_algorithm
= "iwl-agn-rs";
3375 /* Tell mac80211 our characteristics */
3376 hw
->flags
= IEEE80211_HW_SIGNAL_DBM
|
3377 IEEE80211_HW_AMPDU_AGGREGATION
|
3378 IEEE80211_HW_NEED_DTIM_PERIOD
|
3379 IEEE80211_HW_SPECTRUM_MGMT
;
3381 if (!priv
->cfg
->broken_powersave
)
3382 hw
->flags
|= IEEE80211_HW_SUPPORTS_PS
|
3383 IEEE80211_HW_SUPPORTS_DYNAMIC_PS
;
3385 if (priv
->cfg
->sku
& IWL_SKU_N
)
3386 hw
->flags
|= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS
|
3387 IEEE80211_HW_SUPPORTS_STATIC_SMPS
;
3389 hw
->sta_data_size
= sizeof(struct iwl_station_priv
);
3390 hw
->vif_data_size
= sizeof(struct iwl_vif_priv
);
3392 hw
->wiphy
->interface_modes
=
3393 BIT(NL80211_IFTYPE_STATION
) |
3394 BIT(NL80211_IFTYPE_ADHOC
);
3396 hw
->wiphy
->flags
|= WIPHY_FLAG_CUSTOM_REGULATORY
|
3397 WIPHY_FLAG_DISABLE_BEACON_HINTS
;
3400 * For now, disable PS by default because it affects
3401 * RX performance significantly.
3403 hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
3405 hw
->wiphy
->max_scan_ssids
= PROBE_OPTION_MAX
;
3406 /* we create the 802.11 header and a zero-length SSID element */
3407 hw
->wiphy
->max_scan_ie_len
= capa
->max_probe_length
- 24 - 2;
3409 /* Default value; 4 EDCA QOS priorities */
3412 hw
->max_listen_interval
= IWL_CONN_MAX_LISTEN_INTERVAL
;
3414 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
3415 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
3416 &priv
->bands
[IEEE80211_BAND_2GHZ
];
3417 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
3418 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
3419 &priv
->bands
[IEEE80211_BAND_5GHZ
];
3421 ret
= ieee80211_register_hw(priv
->hw
);
3423 IWL_ERR(priv
, "Failed to register hw (error %d)\n", ret
);
3426 priv
->mac80211_registered
= 1;
3432 static int iwl_mac_start(struct ieee80211_hw
*hw
)
3434 struct iwl_priv
*priv
= hw
->priv
;
3437 IWL_DEBUG_MAC80211(priv
, "enter\n");
3439 /* we should be verifying the device is ready to be opened */
3440 mutex_lock(&priv
->mutex
);
3441 ret
= __iwl_up(priv
);
3442 mutex_unlock(&priv
->mutex
);
3447 if (iwl_is_rfkill(priv
))
3450 IWL_DEBUG_INFO(priv
, "Start UP work done.\n");
3452 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3453 * mac80211 will not be run successfully. */
3454 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
3455 test_bit(STATUS_READY
, &priv
->status
),
3456 UCODE_READY_TIMEOUT
);
3458 if (!test_bit(STATUS_READY
, &priv
->status
)) {
3459 IWL_ERR(priv
, "START_ALIVE timeout after %dms.\n",
3460 jiffies_to_msecs(UCODE_READY_TIMEOUT
));
3465 iwl_led_start(priv
);
3469 IWL_DEBUG_MAC80211(priv
, "leave\n");
3473 static void iwl_mac_stop(struct ieee80211_hw
*hw
)
3475 struct iwl_priv
*priv
= hw
->priv
;
3477 IWL_DEBUG_MAC80211(priv
, "enter\n");
3484 if (iwl_is_ready_rf(priv
) || test_bit(STATUS_SCAN_HW
, &priv
->status
)) {
3485 /* stop mac, cancel any scan request and clear
3486 * RXON_FILTER_ASSOC_MSK BIT
3488 mutex_lock(&priv
->mutex
);
3489 iwl_scan_cancel_timeout(priv
, 100);
3490 mutex_unlock(&priv
->mutex
);
3495 flush_workqueue(priv
->workqueue
);
3497 /* enable interrupts again in order to receive rfkill changes */
3498 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
3499 iwl_enable_interrupts(priv
);
3501 IWL_DEBUG_MAC80211(priv
, "leave\n");
3504 static int iwl_mac_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3506 struct iwl_priv
*priv
= hw
->priv
;
3508 IWL_DEBUG_MACDUMP(priv
, "enter\n");
3510 IWL_DEBUG_TX(priv
, "dev->xmit(%d bytes) at rate 0x%02x\n", skb
->len
,
3511 ieee80211_get_tx_rate(hw
, IEEE80211_SKB_CB(skb
))->bitrate
);
3513 if (iwlagn_tx_skb(priv
, skb
))
3514 dev_kfree_skb_any(skb
);
3516 IWL_DEBUG_MACDUMP(priv
, "leave\n");
3517 return NETDEV_TX_OK
;
3520 void iwl_config_ap(struct iwl_priv
*priv
, struct ieee80211_vif
*vif
)
3522 struct iwl_rxon_context
*ctx
= iwl_rxon_ctx_from_vif(vif
);
3525 lockdep_assert_held(&priv
->mutex
);
3527 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3530 /* The following should be done only at AP bring up */
3531 if (!iwl_is_associated_ctx(ctx
)) {
3533 /* RXON - unassoc (to set timing command) */
3534 ctx
->staging
.filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
3535 iwlcore_commit_rxon(priv
, ctx
);
3538 ret
= iwl_send_rxon_timing(priv
, ctx
);
3540 IWL_WARN(priv
, "RXON timing failed - "
3541 "Attempting to continue.\n");
3543 /* AP has all antennas */
3544 priv
->chain_noise_data
.active_chains
=
3545 priv
->hw_params
.valid_rx_ant
;
3546 iwl_set_rxon_ht(priv
, &priv
->current_ht_config
);
3547 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
3548 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
3550 ctx
->staging
.assoc_id
= 0;
3552 if (vif
->bss_conf
.use_short_preamble
)
3553 ctx
->staging
.flags
|=
3554 RXON_FLG_SHORT_PREAMBLE_MSK
;
3556 ctx
->staging
.flags
&=
3557 ~RXON_FLG_SHORT_PREAMBLE_MSK
;
3559 if (ctx
->staging
.flags
& RXON_FLG_BAND_24G_MSK
) {
3560 if (vif
->bss_conf
.use_short_slot
)
3561 ctx
->staging
.flags
|=
3562 RXON_FLG_SHORT_SLOT_MSK
;
3564 ctx
->staging
.flags
&=
3565 ~RXON_FLG_SHORT_SLOT_MSK
;
3567 /* need to send beacon cmd before committing assoc RXON! */
3568 iwl_send_beacon_cmd(priv
);
3569 /* restore RXON assoc */
3570 ctx
->staging
.filter_flags
|= RXON_FILTER_ASSOC_MSK
;
3571 iwlcore_commit_rxon(priv
, ctx
);
3573 iwl_send_beacon_cmd(priv
);
3575 /* FIXME - we need to add code here to detect a totally new
3576 * configuration, reset the AP, unassoc, rxon timing, assoc,
3577 * clear sta table, add BCAST sta... */
3580 static void iwl_mac_update_tkip_key(struct ieee80211_hw
*hw
,
3581 struct ieee80211_vif
*vif
,
3582 struct ieee80211_key_conf
*keyconf
,
3583 struct ieee80211_sta
*sta
,
3584 u32 iv32
, u16
*phase1key
)
3587 struct iwl_priv
*priv
= hw
->priv
;
3588 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3590 IWL_DEBUG_MAC80211(priv
, "enter\n");
3592 iwl_update_tkip_key(priv
, vif_priv
->ctx
, keyconf
, sta
,
3595 IWL_DEBUG_MAC80211(priv
, "leave\n");
3598 static int iwl_mac_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3599 struct ieee80211_vif
*vif
,
3600 struct ieee80211_sta
*sta
,
3601 struct ieee80211_key_conf
*key
)
3603 struct iwl_priv
*priv
= hw
->priv
;
3604 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3605 struct iwl_rxon_context
*ctx
= vif_priv
->ctx
;
3608 bool is_default_wep_key
= false;
3610 IWL_DEBUG_MAC80211(priv
, "enter\n");
3612 if (priv
->cfg
->mod_params
->sw_crypto
) {
3613 IWL_DEBUG_MAC80211(priv
, "leave - hwcrypto disabled\n");
3617 sta_id
= iwl_sta_id_or_broadcast(priv
, vif_priv
->ctx
, sta
);
3618 if (sta_id
== IWL_INVALID_STATION
)
3621 mutex_lock(&priv
->mutex
);
3622 iwl_scan_cancel_timeout(priv
, 100);
3625 * If we are getting WEP group key and we didn't receive any key mapping
3626 * so far, we are in legacy wep mode (group key only), otherwise we are
3628 * In legacy wep mode, we use another host command to the uCode.
3630 if ((key
->cipher
== WLAN_CIPHER_SUITE_WEP40
||
3631 key
->cipher
== WLAN_CIPHER_SUITE_WEP104
) &&
3634 is_default_wep_key
= !ctx
->key_mapping_keys
;
3636 is_default_wep_key
=
3637 (key
->hw_key_idx
== HW_KEY_DEFAULT
);
3642 if (is_default_wep_key
)
3643 ret
= iwl_set_default_wep_key(priv
, vif_priv
->ctx
, key
);
3645 ret
= iwl_set_dynamic_key(priv
, vif_priv
->ctx
,
3648 IWL_DEBUG_MAC80211(priv
, "enable hwcrypto key\n");
3651 if (is_default_wep_key
)
3652 ret
= iwl_remove_default_wep_key(priv
, ctx
, key
);
3654 ret
= iwl_remove_dynamic_key(priv
, ctx
, key
, sta_id
);
3656 IWL_DEBUG_MAC80211(priv
, "disable hwcrypto key\n");
3662 mutex_unlock(&priv
->mutex
);
3663 IWL_DEBUG_MAC80211(priv
, "leave\n");
3668 static int iwl_mac_ampdu_action(struct ieee80211_hw
*hw
,
3669 struct ieee80211_vif
*vif
,
3670 enum ieee80211_ampdu_mlme_action action
,
3671 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
)
3673 struct iwl_priv
*priv
= hw
->priv
;
3676 IWL_DEBUG_HT(priv
, "A-MPDU action on addr %pM tid %d\n",
3679 if (!(priv
->cfg
->sku
& IWL_SKU_N
))
3682 mutex_lock(&priv
->mutex
);
3685 case IEEE80211_AMPDU_RX_START
:
3686 IWL_DEBUG_HT(priv
, "start Rx\n");
3687 ret
= iwl_sta_rx_agg_start(priv
, sta
, tid
, *ssn
);
3689 case IEEE80211_AMPDU_RX_STOP
:
3690 IWL_DEBUG_HT(priv
, "stop Rx\n");
3691 ret
= iwl_sta_rx_agg_stop(priv
, sta
, tid
);
3692 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3695 case IEEE80211_AMPDU_TX_START
:
3696 IWL_DEBUG_HT(priv
, "start Tx\n");
3697 ret
= iwlagn_tx_agg_start(priv
, vif
, sta
, tid
, ssn
);
3699 priv
->_agn
.agg_tids_count
++;
3700 IWL_DEBUG_HT(priv
, "priv->_agn.agg_tids_count = %u\n",
3701 priv
->_agn
.agg_tids_count
);
3704 case IEEE80211_AMPDU_TX_STOP
:
3705 IWL_DEBUG_HT(priv
, "stop Tx\n");
3706 ret
= iwlagn_tx_agg_stop(priv
, vif
, sta
, tid
);
3707 if ((ret
== 0) && (priv
->_agn
.agg_tids_count
> 0)) {
3708 priv
->_agn
.agg_tids_count
--;
3709 IWL_DEBUG_HT(priv
, "priv->_agn.agg_tids_count = %u\n",
3710 priv
->_agn
.agg_tids_count
);
3712 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3714 if (priv
->cfg
->use_rts_for_aggregation
) {
3715 struct iwl_station_priv
*sta_priv
=
3716 (void *) sta
->drv_priv
;
3718 * switch off RTS/CTS if it was previously enabled
3721 sta_priv
->lq_sta
.lq
.general_params
.flags
&=
3722 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK
;
3723 iwl_send_lq_cmd(priv
, iwl_rxon_ctx_from_vif(vif
),
3724 &sta_priv
->lq_sta
.lq
, CMD_ASYNC
, false);
3727 case IEEE80211_AMPDU_TX_OPERATIONAL
:
3728 if (priv
->cfg
->use_rts_for_aggregation
) {
3729 struct iwl_station_priv
*sta_priv
=
3730 (void *) sta
->drv_priv
;
3733 * switch to RTS/CTS if it is the prefer protection
3734 * method for HT traffic
3737 sta_priv
->lq_sta
.lq
.general_params
.flags
|=
3738 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK
;
3739 iwl_send_lq_cmd(priv
, iwl_rxon_ctx_from_vif(vif
),
3740 &sta_priv
->lq_sta
.lq
, CMD_ASYNC
, false);
3745 mutex_unlock(&priv
->mutex
);
3750 static void iwl_mac_sta_notify(struct ieee80211_hw
*hw
,
3751 struct ieee80211_vif
*vif
,
3752 enum sta_notify_cmd cmd
,
3753 struct ieee80211_sta
*sta
)
3755 struct iwl_priv
*priv
= hw
->priv
;
3756 struct iwl_station_priv
*sta_priv
= (void *)sta
->drv_priv
;
3760 case STA_NOTIFY_SLEEP
:
3761 WARN_ON(!sta_priv
->client
);
3762 sta_priv
->asleep
= true;
3763 if (atomic_read(&sta_priv
->pending_frames
) > 0)
3764 ieee80211_sta_block_awake(hw
, sta
, true);
3766 case STA_NOTIFY_AWAKE
:
3767 WARN_ON(!sta_priv
->client
);
3768 if (!sta_priv
->asleep
)
3770 sta_priv
->asleep
= false;
3771 sta_id
= iwl_sta_id(sta
);
3772 if (sta_id
!= IWL_INVALID_STATION
)
3773 iwl_sta_modify_ps_wake(priv
, sta_id
);
3780 static int iwlagn_mac_sta_add(struct ieee80211_hw
*hw
,
3781 struct ieee80211_vif
*vif
,
3782 struct ieee80211_sta
*sta
)
3784 struct iwl_priv
*priv
= hw
->priv
;
3785 struct iwl_station_priv
*sta_priv
= (void *)sta
->drv_priv
;
3786 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3787 bool is_ap
= vif
->type
== NL80211_IFTYPE_STATION
;
3791 IWL_DEBUG_INFO(priv
, "received request to add station %pM\n",
3793 mutex_lock(&priv
->mutex
);
3794 IWL_DEBUG_INFO(priv
, "proceeding to add station %pM\n",
3796 sta_priv
->common
.sta_id
= IWL_INVALID_STATION
;
3798 atomic_set(&sta_priv
->pending_frames
, 0);
3799 if (vif
->type
== NL80211_IFTYPE_AP
)
3800 sta_priv
->client
= true;
3802 ret
= iwl_add_station_common(priv
, vif_priv
->ctx
, sta
->addr
,
3803 is_ap
, sta
, &sta_id
);
3805 IWL_ERR(priv
, "Unable to add station %pM (%d)\n",
3807 /* Should we return success if return code is EEXIST ? */
3808 mutex_unlock(&priv
->mutex
);
3812 sta_priv
->common
.sta_id
= sta_id
;
3814 /* Initialize rate scaling */
3815 IWL_DEBUG_INFO(priv
, "Initializing rate scaling for station %pM\n",
3817 iwl_rs_rate_init(priv
, sta
, sta_id
);
3818 mutex_unlock(&priv
->mutex
);
3823 static void iwl_mac_channel_switch(struct ieee80211_hw
*hw
,
3824 struct ieee80211_channel_switch
*ch_switch
)
3826 struct iwl_priv
*priv
= hw
->priv
;
3827 const struct iwl_channel_info
*ch_info
;
3828 struct ieee80211_conf
*conf
= &hw
->conf
;
3829 struct ieee80211_channel
*channel
= ch_switch
->channel
;
3830 struct iwl_ht_config
*ht_conf
= &priv
->current_ht_config
;
3833 * When we add support for multiple interfaces, we need to
3834 * revisit this. The channel switch command in the device
3835 * only affects the BSS context, but what does that really
3836 * mean? And what if we get a CSA on the second interface?
3837 * This needs a lot of work.
3839 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
3841 unsigned long flags
= 0;
3843 IWL_DEBUG_MAC80211(priv
, "enter\n");
3845 if (iwl_is_rfkill(priv
))
3848 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
) ||
3849 test_bit(STATUS_SCANNING
, &priv
->status
))
3852 if (!iwl_is_associated_ctx(ctx
))
3855 /* channel switch in progress */
3856 if (priv
->switch_rxon
.switch_in_progress
== true)
3859 mutex_lock(&priv
->mutex
);
3860 if (priv
->cfg
->ops
->lib
->set_channel_switch
) {
3862 ch
= channel
->hw_value
;
3863 if (le16_to_cpu(ctx
->active
.channel
) != ch
) {
3864 ch_info
= iwl_get_channel_info(priv
,
3867 if (!is_channel_valid(ch_info
)) {
3868 IWL_DEBUG_MAC80211(priv
, "invalid channel\n");
3871 spin_lock_irqsave(&priv
->lock
, flags
);
3873 priv
->current_ht_config
.smps
= conf
->smps_mode
;
3875 /* Configure HT40 channels */
3876 ctx
->ht
.enabled
= conf_is_ht(conf
);
3877 if (ctx
->ht
.enabled
) {
3878 if (conf_is_ht40_minus(conf
)) {
3879 ctx
->ht
.extension_chan_offset
=
3880 IEEE80211_HT_PARAM_CHA_SEC_BELOW
;
3881 ctx
->ht
.is_40mhz
= true;
3882 } else if (conf_is_ht40_plus(conf
)) {
3883 ctx
->ht
.extension_chan_offset
=
3884 IEEE80211_HT_PARAM_CHA_SEC_ABOVE
;
3885 ctx
->ht
.is_40mhz
= true;
3887 ctx
->ht
.extension_chan_offset
=
3888 IEEE80211_HT_PARAM_CHA_SEC_NONE
;
3889 ctx
->ht
.is_40mhz
= false;
3892 ctx
->ht
.is_40mhz
= false;
3894 if ((le16_to_cpu(ctx
->staging
.channel
) != ch
))
3895 ctx
->staging
.flags
= 0;
3897 iwl_set_rxon_channel(priv
, channel
, ctx
);
3898 iwl_set_rxon_ht(priv
, ht_conf
);
3899 iwl_set_flags_for_band(priv
, ctx
, channel
->band
,
3901 spin_unlock_irqrestore(&priv
->lock
, flags
);
3905 * at this point, staging_rxon has the
3906 * configuration for channel switch
3908 if (priv
->cfg
->ops
->lib
->set_channel_switch(priv
,
3910 priv
->switch_rxon
.switch_in_progress
= false;
3914 mutex_unlock(&priv
->mutex
);
3916 if (!priv
->switch_rxon
.switch_in_progress
)
3917 ieee80211_chswitch_done(ctx
->vif
, false);
3918 IWL_DEBUG_MAC80211(priv
, "leave\n");
3921 static void iwlagn_configure_filter(struct ieee80211_hw
*hw
,
3922 unsigned int changed_flags
,
3923 unsigned int *total_flags
,
3926 struct iwl_priv
*priv
= hw
->priv
;
3927 __le32 filter_or
= 0, filter_nand
= 0;
3928 struct iwl_rxon_context
*ctx
;
3930 #define CHK(test, flag) do { \
3931 if (*total_flags & (test)) \
3932 filter_or |= (flag); \
3934 filter_nand |= (flag); \
3937 IWL_DEBUG_MAC80211(priv
, "Enter: changed: 0x%x, total: 0x%x\n",
3938 changed_flags
, *total_flags
);
3940 CHK(FIF_OTHER_BSS
| FIF_PROMISC_IN_BSS
, RXON_FILTER_PROMISC_MSK
);
3941 CHK(FIF_CONTROL
, RXON_FILTER_CTL2HOST_MSK
);
3942 CHK(FIF_BCN_PRBRESP_PROMISC
, RXON_FILTER_BCON_AWARE_MSK
);
3946 mutex_lock(&priv
->mutex
);
3948 for_each_context(priv
, ctx
) {
3949 ctx
->staging
.filter_flags
&= ~filter_nand
;
3950 ctx
->staging
.filter_flags
|= filter_or
;
3951 iwlcore_commit_rxon(priv
, ctx
);
3954 mutex_unlock(&priv
->mutex
);
3957 * Receiving all multicast frames is always enabled by the
3958 * default flags setup in iwl_connection_init_rx_config()
3959 * since we currently do not support programming multicast
3960 * filters into the device.
3962 *total_flags
&= FIF_OTHER_BSS
| FIF_ALLMULTI
| FIF_PROMISC_IN_BSS
|
3963 FIF_BCN_PRBRESP_PROMISC
| FIF_CONTROL
;
3966 static void iwl_mac_flush(struct ieee80211_hw
*hw
, bool drop
)
3968 struct iwl_priv
*priv
= hw
->priv
;
3970 mutex_lock(&priv
->mutex
);
3971 IWL_DEBUG_MAC80211(priv
, "enter\n");
3973 /* do not support "flush" */
3974 if (!priv
->cfg
->ops
->lib
->txfifo_flush
)
3977 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
)) {
3978 IWL_DEBUG_TX(priv
, "Aborting flush due to device shutdown\n");
3981 if (iwl_is_rfkill(priv
)) {
3982 IWL_DEBUG_TX(priv
, "Aborting flush due to RF Kill\n");
3987 * mac80211 will not push any more frames for transmit
3988 * until the flush is completed
3991 IWL_DEBUG_MAC80211(priv
, "send flush command\n");
3992 if (priv
->cfg
->ops
->lib
->txfifo_flush(priv
, IWL_DROP_ALL
)) {
3993 IWL_ERR(priv
, "flush request fail\n");
3997 IWL_DEBUG_MAC80211(priv
, "wait transmit/flush all frames\n");
3998 iwlagn_wait_tx_queue_empty(priv
);
4000 mutex_unlock(&priv
->mutex
);
4001 IWL_DEBUG_MAC80211(priv
, "leave\n");
4004 /*****************************************************************************
4006 * driver setup and teardown
4008 *****************************************************************************/
4010 static void iwl_setup_deferred_work(struct iwl_priv
*priv
)
4012 priv
->workqueue
= create_singlethread_workqueue(DRV_NAME
);
4014 init_waitqueue_head(&priv
->wait_command_queue
);
4016 INIT_WORK(&priv
->restart
, iwl_bg_restart
);
4017 INIT_WORK(&priv
->rx_replenish
, iwl_bg_rx_replenish
);
4018 INIT_WORK(&priv
->beacon_update
, iwl_bg_beacon_update
);
4019 INIT_WORK(&priv
->run_time_calib_work
, iwl_bg_run_time_calib_work
);
4020 INIT_WORK(&priv
->tx_flush
, iwl_bg_tx_flush
);
4021 INIT_WORK(&priv
->bt_full_concurrency
, iwl_bg_bt_full_concurrency
);
4022 INIT_WORK(&priv
->bt_runtime_config
, iwl_bg_bt_runtime_config
);
4023 INIT_DELAYED_WORK(&priv
->init_alive_start
, iwl_bg_init_alive_start
);
4024 INIT_DELAYED_WORK(&priv
->alive_start
, iwl_bg_alive_start
);
4026 iwl_setup_scan_deferred_work(priv
);
4028 if (priv
->cfg
->ops
->lib
->setup_deferred_work
)
4029 priv
->cfg
->ops
->lib
->setup_deferred_work(priv
);
4031 init_timer(&priv
->statistics_periodic
);
4032 priv
->statistics_periodic
.data
= (unsigned long)priv
;
4033 priv
->statistics_periodic
.function
= iwl_bg_statistics_periodic
;
4035 init_timer(&priv
->ucode_trace
);
4036 priv
->ucode_trace
.data
= (unsigned long)priv
;
4037 priv
->ucode_trace
.function
= iwl_bg_ucode_trace
;
4039 if (priv
->cfg
->ops
->lib
->recover_from_tx_stall
) {
4040 init_timer(&priv
->monitor_recover
);
4041 priv
->monitor_recover
.data
= (unsigned long)priv
;
4042 priv
->monitor_recover
.function
=
4043 priv
->cfg
->ops
->lib
->recover_from_tx_stall
;
4046 if (!priv
->cfg
->use_isr_legacy
)
4047 tasklet_init(&priv
->irq_tasklet
, (void (*)(unsigned long))
4048 iwl_irq_tasklet
, (unsigned long)priv
);
4050 tasklet_init(&priv
->irq_tasklet
, (void (*)(unsigned long))
4051 iwl_irq_tasklet_legacy
, (unsigned long)priv
);
4054 static void iwl_cancel_deferred_work(struct iwl_priv
*priv
)
4056 if (priv
->cfg
->ops
->lib
->cancel_deferred_work
)
4057 priv
->cfg
->ops
->lib
->cancel_deferred_work(priv
);
4059 cancel_delayed_work_sync(&priv
->init_alive_start
);
4060 cancel_delayed_work(&priv
->scan_check
);
4061 cancel_work_sync(&priv
->start_internal_scan
);
4062 cancel_delayed_work(&priv
->alive_start
);
4063 cancel_work_sync(&priv
->run_time_calib_work
);
4064 cancel_work_sync(&priv
->beacon_update
);
4065 cancel_work_sync(&priv
->bt_full_concurrency
);
4066 cancel_work_sync(&priv
->bt_runtime_config
);
4067 del_timer_sync(&priv
->statistics_periodic
);
4068 del_timer_sync(&priv
->ucode_trace
);
4071 static void iwl_init_hw_rates(struct iwl_priv
*priv
,
4072 struct ieee80211_rate
*rates
)
4076 for (i
= 0; i
< IWL_RATE_COUNT_LEGACY
; i
++) {
4077 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
4078 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
4079 rates
[i
].hw_value_short
= i
;
4081 if ((i
>= IWL_FIRST_CCK_RATE
) && (i
<= IWL_LAST_CCK_RATE
)) {
4083 * If CCK != 1M then set short preamble rate flag.
4086 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
4087 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
4092 static int iwl_init_drv(struct iwl_priv
*priv
)
4096 priv
->ibss_beacon
= NULL
;
4098 spin_lock_init(&priv
->sta_lock
);
4099 spin_lock_init(&priv
->hcmd_lock
);
4101 INIT_LIST_HEAD(&priv
->free_frames
);
4103 mutex_init(&priv
->mutex
);
4104 mutex_init(&priv
->sync_cmd_mutex
);
4106 priv
->ieee_channels
= NULL
;
4107 priv
->ieee_rates
= NULL
;
4108 priv
->band
= IEEE80211_BAND_2GHZ
;
4110 priv
->iw_mode
= NL80211_IFTYPE_STATION
;
4111 priv
->current_ht_config
.smps
= IEEE80211_SMPS_STATIC
;
4112 priv
->missed_beacon_threshold
= IWL_MISSED_BEACON_THRESHOLD_DEF
;
4113 priv
->_agn
.agg_tids_count
= 0;
4115 /* initialize force reset */
4116 priv
->force_reset
[IWL_RF_RESET
].reset_duration
=
4117 IWL_DELAY_NEXT_FORCE_RF_RESET
;
4118 priv
->force_reset
[IWL_FW_RESET
].reset_duration
=
4119 IWL_DELAY_NEXT_FORCE_FW_RELOAD
;
4121 /* Choose which receivers/antennas to use */
4122 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
4123 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
,
4124 &priv
->contexts
[IWL_RXON_CTX_BSS
]);
4126 iwl_init_scan_params(priv
);
4129 if (priv
->cfg
->advanced_bt_coexist
) {
4130 priv
->kill_ack_mask
= IWLAGN_BT_KILL_ACK_MASK_DEFAULT
;
4131 priv
->kill_cts_mask
= IWLAGN_BT_KILL_CTS_MASK_DEFAULT
;
4132 priv
->bt_valid
= IWLAGN_BT_ALL_VALID_MSK
;
4133 priv
->bt_on_thresh
= BT_ON_THRESHOLD_DEF
;
4134 priv
->bt_duration
= BT_DURATION_LIMIT_DEF
;
4135 priv
->dynamic_frag_thresh
= BT_FRAG_THRESHOLD_DEF
;
4136 priv
->dynamic_agg_thresh
= BT_AGG_THRESHOLD_DEF
;
4139 /* Set the tx_power_user_lmt to the lowest power level
4140 * this value will get overwritten by channel max power avg
4142 priv
->tx_power_user_lmt
= IWLAGN_TX_POWER_TARGET_POWER_MIN
;
4144 ret
= iwl_init_channel_map(priv
);
4146 IWL_ERR(priv
, "initializing regulatory failed: %d\n", ret
);
4150 ret
= iwlcore_init_geos(priv
);
4152 IWL_ERR(priv
, "initializing geos failed: %d\n", ret
);
4153 goto err_free_channel_map
;
4155 iwl_init_hw_rates(priv
, priv
->ieee_rates
);
4159 err_free_channel_map
:
4160 iwl_free_channel_map(priv
);
4165 static void iwl_uninit_drv(struct iwl_priv
*priv
)
4167 iwl_calib_free_results(priv
);
4168 iwlcore_free_geos(priv
);
4169 iwl_free_channel_map(priv
);
4170 kfree(priv
->scan_cmd
);
4173 static struct ieee80211_ops iwl_hw_ops
= {
4175 .start
= iwl_mac_start
,
4176 .stop
= iwl_mac_stop
,
4177 .add_interface
= iwl_mac_add_interface
,
4178 .remove_interface
= iwl_mac_remove_interface
,
4179 .config
= iwl_mac_config
,
4180 .configure_filter
= iwlagn_configure_filter
,
4181 .set_key
= iwl_mac_set_key
,
4182 .update_tkip_key
= iwl_mac_update_tkip_key
,
4183 .conf_tx
= iwl_mac_conf_tx
,
4184 .reset_tsf
= iwl_mac_reset_tsf
,
4185 .bss_info_changed
= iwl_bss_info_changed
,
4186 .ampdu_action
= iwl_mac_ampdu_action
,
4187 .hw_scan
= iwl_mac_hw_scan
,
4188 .sta_notify
= iwl_mac_sta_notify
,
4189 .sta_add
= iwlagn_mac_sta_add
,
4190 .sta_remove
= iwl_mac_sta_remove
,
4191 .channel_switch
= iwl_mac_channel_switch
,
4192 .flush
= iwl_mac_flush
,
4193 .tx_last_beacon
= iwl_mac_tx_last_beacon
,
4196 static void iwl_hw_detect(struct iwl_priv
*priv
)
4198 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
4199 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
4200 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &priv
->rev_id
);
4201 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", priv
->rev_id
);
4204 static int iwl_set_hw_params(struct iwl_priv
*priv
)
4206 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
4207 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
4208 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
4209 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_8K
);
4211 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_4K
);
4213 priv
->hw_params
.max_beacon_itrvl
= IWL_MAX_UCODE_BEACON_INTERVAL
;
4215 if (priv
->cfg
->mod_params
->disable_11n
)
4216 priv
->cfg
->sku
&= ~IWL_SKU_N
;
4218 /* Device-specific setup */
4219 return priv
->cfg
->ops
->lib
->set_hw_params(priv
);
4222 static const u8 iwlagn_bss_ac_to_fifo
[] = {
4229 static const u8 iwlagn_bss_ac_to_queue
[] = {
4233 static const u8 iwlagn_pan_ac_to_fifo
[] = {
4234 IWL_TX_FIFO_VO_IPAN
,
4235 IWL_TX_FIFO_VI_IPAN
,
4236 IWL_TX_FIFO_BE_IPAN
,
4237 IWL_TX_FIFO_BK_IPAN
,
4240 static const u8 iwlagn_pan_ac_to_queue
[] = {
4244 static int iwl_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
4247 struct iwl_priv
*priv
;
4248 struct ieee80211_hw
*hw
;
4249 struct iwl_cfg
*cfg
= (struct iwl_cfg
*)(ent
->driver_data
);
4250 unsigned long flags
;
4251 u16 pci_cmd
, num_mac
;
4253 /************************
4254 * 1. Allocating HW data
4255 ************************/
4257 /* Disabling hardware scan means that mac80211 will perform scans
4258 * "the hard way", rather than using device's scan. */
4259 if (cfg
->mod_params
->disable_hw_scan
) {
4260 if (iwl_debug_level
& IWL_DL_INFO
)
4261 dev_printk(KERN_DEBUG
, &(pdev
->dev
),
4262 "Disabling hw_scan\n");
4263 iwl_hw_ops
.hw_scan
= NULL
;
4266 hw
= iwl_alloc_all(cfg
, &iwl_hw_ops
);
4272 /* At this point both hw and priv are allocated. */
4275 * The default context is always valid,
4276 * more may be discovered when firmware
4279 priv
->valid_contexts
= BIT(IWL_RXON_CTX_BSS
);
4281 for (i
= 0; i
< NUM_IWL_RXON_CTX
; i
++)
4282 priv
->contexts
[i
].ctxid
= i
;
4284 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_cmd
= REPLY_RXON
;
4285 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_timing_cmd
= REPLY_RXON_TIMING
;
4286 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_assoc_cmd
= REPLY_RXON_ASSOC
;
4287 priv
->contexts
[IWL_RXON_CTX_BSS
].qos_cmd
= REPLY_QOS_PARAM
;
4288 priv
->contexts
[IWL_RXON_CTX_BSS
].ap_sta_id
= IWL_AP_ID
;
4289 priv
->contexts
[IWL_RXON_CTX_BSS
].wep_key_cmd
= REPLY_WEPKEY
;
4290 priv
->contexts
[IWL_RXON_CTX_BSS
].ac_to_fifo
= iwlagn_bss_ac_to_fifo
;
4291 priv
->contexts
[IWL_RXON_CTX_BSS
].ac_to_queue
= iwlagn_bss_ac_to_queue
;
4293 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_cmd
= REPLY_WIPAN_RXON
;
4294 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_timing_cmd
= REPLY_WIPAN_RXON_TIMING
;
4295 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_assoc_cmd
= REPLY_WIPAN_RXON_ASSOC
;
4296 priv
->contexts
[IWL_RXON_CTX_PAN
].qos_cmd
= REPLY_WIPAN_QOS_PARAM
;
4297 priv
->contexts
[IWL_RXON_CTX_PAN
].ap_sta_id
= IWL_AP_ID_PAN
;
4298 priv
->contexts
[IWL_RXON_CTX_PAN
].wep_key_cmd
= REPLY_WIPAN_WEPKEY
;
4299 priv
->contexts
[IWL_RXON_CTX_PAN
].bcast_sta_id
= IWLAGN_PAN_BCAST_ID
;
4300 priv
->contexts
[IWL_RXON_CTX_PAN
].station_flags
= STA_FLG_PAN_STATION
;
4301 priv
->contexts
[IWL_RXON_CTX_PAN
].ac_to_fifo
= iwlagn_pan_ac_to_fifo
;
4302 priv
->contexts
[IWL_RXON_CTX_PAN
].ac_to_queue
= iwlagn_pan_ac_to_queue
;
4303 priv
->contexts
[IWL_RXON_CTX_PAN
].mcast_queue
= IWL_IPAN_MCAST_QUEUE
;
4305 BUILD_BUG_ON(NUM_IWL_RXON_CTX
!= 2);
4307 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
4309 IWL_DEBUG_INFO(priv
, "*** LOAD DRIVER ***\n");
4311 priv
->pci_dev
= pdev
;
4312 priv
->inta_mask
= CSR_INI_SET_MASK
;
4314 /* is antenna coupling more than 35dB ? */
4315 priv
->bt_ant_couple_ok
=
4316 (iwlagn_ant_coupling
> IWL_BT_ANTENNA_COUPLING_THRESHOLD
) ?
4319 /* enable/disable bt channel announcement */
4320 priv
->bt_ch_announce
= iwlagn_bt_ch_announce
;
4322 if (iwl_alloc_traffic_mem(priv
))
4323 IWL_ERR(priv
, "Not enough memory to generate traffic log\n");
4325 /**************************
4326 * 2. Initializing PCI bus
4327 **************************/
4328 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
4329 PCIE_LINK_STATE_CLKPM
);
4331 if (pci_enable_device(pdev
)) {
4333 goto out_ieee80211_free_hw
;
4336 pci_set_master(pdev
);
4338 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
4340 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
4342 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4344 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
4345 /* both attempts failed: */
4347 IWL_WARN(priv
, "No suitable DMA available.\n");
4348 goto out_pci_disable_device
;
4352 err
= pci_request_regions(pdev
, DRV_NAME
);
4354 goto out_pci_disable_device
;
4356 pci_set_drvdata(pdev
, priv
);
4359 /***********************
4360 * 3. Read REV register
4361 ***********************/
4362 priv
->hw_base
= pci_iomap(pdev
, 0, 0);
4363 if (!priv
->hw_base
) {
4365 goto out_pci_release_regions
;
4368 IWL_DEBUG_INFO(priv
, "pci_resource_len = 0x%08llx\n",
4369 (unsigned long long) pci_resource_len(pdev
, 0));
4370 IWL_DEBUG_INFO(priv
, "pci_resource_base = %p\n", priv
->hw_base
);
4372 /* these spin locks will be used in apm_ops.init and EEPROM access
4373 * we should init now
4375 spin_lock_init(&priv
->reg_lock
);
4376 spin_lock_init(&priv
->lock
);
4379 * stop and reset the on-board processor just in case it is in a
4380 * strange state ... like being left stranded by a primary kernel
4381 * and this is now the kdump kernel trying to start up
4383 iwl_write32(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
4385 iwl_hw_detect(priv
);
4386 IWL_INFO(priv
, "Detected %s, REV=0x%X\n",
4387 priv
->cfg
->name
, priv
->hw_rev
);
4389 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4390 * PCI Tx retries from interfering with C3 CPU state */
4391 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
4393 iwl_prepare_card_hw(priv
);
4394 if (!priv
->hw_ready
) {
4395 IWL_WARN(priv
, "Failed, HW not ready\n");
4402 /* Read the EEPROM */
4403 err
= iwl_eeprom_init(priv
);
4405 IWL_ERR(priv
, "Unable to init EEPROM\n");
4408 err
= iwl_eeprom_check_version(priv
);
4410 goto out_free_eeprom
;
4412 /* extract MAC Address */
4413 iwl_eeprom_get_mac(priv
, priv
->addresses
[0].addr
);
4414 IWL_DEBUG_INFO(priv
, "MAC address: %pM\n", priv
->addresses
[0].addr
);
4415 priv
->hw
->wiphy
->addresses
= priv
->addresses
;
4416 priv
->hw
->wiphy
->n_addresses
= 1;
4417 num_mac
= iwl_eeprom_query16(priv
, EEPROM_NUM_MAC_ADDRESS
);
4419 memcpy(priv
->addresses
[1].addr
, priv
->addresses
[0].addr
,
4421 priv
->addresses
[1].addr
[5]++;
4422 priv
->hw
->wiphy
->n_addresses
++;
4425 /************************
4426 * 5. Setup HW constants
4427 ************************/
4428 if (iwl_set_hw_params(priv
)) {
4429 IWL_ERR(priv
, "failed to set hw parameters\n");
4430 goto out_free_eeprom
;
4433 /*******************
4435 *******************/
4437 err
= iwl_init_drv(priv
);
4439 goto out_free_eeprom
;
4440 /* At this point both hw and priv are initialized. */
4442 /********************
4444 ********************/
4445 spin_lock_irqsave(&priv
->lock
, flags
);
4446 iwl_disable_interrupts(priv
);
4447 spin_unlock_irqrestore(&priv
->lock
, flags
);
4449 pci_enable_msi(priv
->pci_dev
);
4451 iwl_alloc_isr_ict(priv
);
4452 err
= request_irq(priv
->pci_dev
->irq
, priv
->cfg
->ops
->lib
->isr
,
4453 IRQF_SHARED
, DRV_NAME
, priv
);
4455 IWL_ERR(priv
, "Error allocating IRQ %d\n", priv
->pci_dev
->irq
);
4456 goto out_disable_msi
;
4459 iwl_setup_deferred_work(priv
);
4460 iwl_setup_rx_handlers(priv
);
4462 /*********************************************
4463 * 8. Enable interrupts and read RFKILL state
4464 *********************************************/
4466 /* enable interrupts if needed: hw bug w/a */
4467 pci_read_config_word(priv
->pci_dev
, PCI_COMMAND
, &pci_cmd
);
4468 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
4469 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
4470 pci_write_config_word(priv
->pci_dev
, PCI_COMMAND
, pci_cmd
);
4473 iwl_enable_interrupts(priv
);
4475 /* If platform's RF_KILL switch is NOT set to KILL */
4476 if (iwl_read32(priv
, CSR_GP_CNTRL
) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
4477 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
4479 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
4481 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
,
4482 test_bit(STATUS_RF_KILL_HW
, &priv
->status
));
4484 iwl_power_initialize(priv
);
4485 iwl_tt_initialize(priv
);
4487 init_completion(&priv
->_agn
.firmware_loading_complete
);
4489 err
= iwl_request_firmware(priv
, true);
4491 goto out_destroy_workqueue
;
4495 out_destroy_workqueue
:
4496 destroy_workqueue(priv
->workqueue
);
4497 priv
->workqueue
= NULL
;
4498 free_irq(priv
->pci_dev
->irq
, priv
);
4499 iwl_free_isr_ict(priv
);
4501 pci_disable_msi(priv
->pci_dev
);
4502 iwl_uninit_drv(priv
);
4504 iwl_eeprom_free(priv
);
4506 pci_iounmap(pdev
, priv
->hw_base
);
4507 out_pci_release_regions
:
4508 pci_set_drvdata(pdev
, NULL
);
4509 pci_release_regions(pdev
);
4510 out_pci_disable_device
:
4511 pci_disable_device(pdev
);
4512 out_ieee80211_free_hw
:
4513 iwl_free_traffic_mem(priv
);
4514 ieee80211_free_hw(priv
->hw
);
4519 static void __devexit
iwl_pci_remove(struct pci_dev
*pdev
)
4521 struct iwl_priv
*priv
= pci_get_drvdata(pdev
);
4522 unsigned long flags
;
4527 wait_for_completion(&priv
->_agn
.firmware_loading_complete
);
4529 IWL_DEBUG_INFO(priv
, "*** UNLOAD DRIVER ***\n");
4531 iwl_dbgfs_unregister(priv
);
4532 sysfs_remove_group(&pdev
->dev
.kobj
, &iwl_attribute_group
);
4534 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4535 * to be called and iwl_down since we are removing the device
4536 * we need to set STATUS_EXIT_PENDING bit.
4538 set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
4539 if (priv
->mac80211_registered
) {
4540 ieee80211_unregister_hw(priv
->hw
);
4541 priv
->mac80211_registered
= 0;
4547 * Make sure device is reset to low power before unloading driver.
4548 * This may be redundant with iwl_down(), but there are paths to
4549 * run iwl_down() without calling apm_ops.stop(), and there are
4550 * paths to avoid running iwl_down() at all before leaving driver.
4551 * This (inexpensive) call *makes sure* device is reset.
4553 priv
->cfg
->ops
->lib
->apm_ops
.stop(priv
);
4557 /* make sure we flush any pending irq or
4558 * tasklet for the driver
4560 spin_lock_irqsave(&priv
->lock
, flags
);
4561 iwl_disable_interrupts(priv
);
4562 spin_unlock_irqrestore(&priv
->lock
, flags
);
4564 iwl_synchronize_irq(priv
);
4566 iwl_dealloc_ucode_pci(priv
);
4569 iwlagn_rx_queue_free(priv
, &priv
->rxq
);
4570 iwlagn_hw_txq_ctx_free(priv
);
4572 iwl_eeprom_free(priv
);
4575 /*netif_stop_queue(dev); */
4576 flush_workqueue(priv
->workqueue
);
4578 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4579 * priv->workqueue... so we can't take down the workqueue
4581 destroy_workqueue(priv
->workqueue
);
4582 priv
->workqueue
= NULL
;
4583 iwl_free_traffic_mem(priv
);
4585 free_irq(priv
->pci_dev
->irq
, priv
);
4586 pci_disable_msi(priv
->pci_dev
);
4587 pci_iounmap(pdev
, priv
->hw_base
);
4588 pci_release_regions(pdev
);
4589 pci_disable_device(pdev
);
4590 pci_set_drvdata(pdev
, NULL
);
4592 iwl_uninit_drv(priv
);
4594 iwl_free_isr_ict(priv
);
4596 if (priv
->ibss_beacon
)
4597 dev_kfree_skb(priv
->ibss_beacon
);
4599 ieee80211_free_hw(priv
->hw
);
4603 /*****************************************************************************
4605 * driver and module entry point
4607 *****************************************************************************/
4609 /* Hardware specific file defines the PCI IDs table for that hardware module */
4610 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids
) = {
4611 #ifdef CONFIG_IWL4965
4612 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID
, iwl4965_agn_cfg
)},
4613 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID
, iwl4965_agn_cfg
)},
4614 #endif /* CONFIG_IWL4965 */
4615 #ifdef CONFIG_IWL5000
4616 /* 5100 Series WiFi */
4617 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg
)}, /* Mini Card */
4618 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg
)}, /* Half Mini Card */
4619 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg
)}, /* Mini Card */
4620 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg
)}, /* Half Mini Card */
4621 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg
)}, /* Mini Card */
4622 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4623 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg
)}, /* Mini Card */
4624 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg
)}, /* Half Mini Card */
4625 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg
)}, /* Mini Card */
4626 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg
)}, /* Half Mini Card */
4627 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg
)}, /* Mini Card */
4628 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg
)}, /* Half Mini Card */
4629 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg
)}, /* Mini Card */
4630 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4631 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg
)}, /* Mini Card */
4632 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg
)}, /* Half Mini Card */
4633 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg
)}, /* Mini Card */
4634 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg
)}, /* Half Mini Card */
4635 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg
)}, /* Mini Card */
4636 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg
)}, /* Half Mini Card */
4637 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg
)}, /* Mini Card */
4638 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4639 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg
)}, /* Mini Card */
4640 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg
)}, /* Half Mini Card */
4642 /* 5300 Series WiFi */
4643 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg
)}, /* Mini Card */
4644 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg
)}, /* Half Mini Card */
4645 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg
)}, /* Mini Card */
4646 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg
)}, /* Half Mini Card */
4647 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg
)}, /* Mini Card */
4648 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg
)}, /* Half Mini Card */
4649 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg
)}, /* Mini Card */
4650 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg
)}, /* Half Mini Card */
4651 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg
)}, /* Mini Card */
4652 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg
)}, /* Half Mini Card */
4653 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg
)}, /* Mini Card */
4654 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg
)}, /* Half Mini Card */
4656 /* 5350 Series WiFi/WiMax */
4657 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg
)}, /* Mini Card */
4658 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg
)}, /* Mini Card */
4659 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg
)}, /* Mini Card */
4661 /* 5150 Series Wifi/WiMax */
4662 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg
)}, /* Mini Card */
4663 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg
)}, /* Half Mini Card */
4664 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg
)}, /* Mini Card */
4665 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg
)}, /* Half Mini Card */
4666 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg
)}, /* Mini Card */
4667 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg
)}, /* Half Mini Card */
4669 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg
)}, /* Mini Card */
4670 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg
)}, /* Half Mini Card */
4671 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg
)}, /* Mini Card */
4672 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg
)}, /* Half Mini Card */
4675 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg
)},
4676 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg
)},
4677 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg
)},
4678 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg
)},
4679 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg
)},
4680 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg
)},
4681 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg
)},
4682 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg
)},
4683 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg
)},
4684 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg
)},
4686 /* 6x00 Series Gen2a */
4687 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg
)},
4688 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg
)},
4689 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg
)},
4690 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg
)},
4691 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg
)},
4692 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg
)},
4693 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg
)},
4694 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg
)},
4695 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg
)},
4696 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg
)},
4697 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg
)},
4698 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg
)},
4699 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg
)},
4700 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg
)},
4702 /* 6x00 Series Gen2b */
4703 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg
)},
4704 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg
)},
4705 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg
)},
4706 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg
)},
4707 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg
)},
4708 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg
)},
4709 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg
)},
4710 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg
)},
4711 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg
)},
4712 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg
)},
4713 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg
)},
4714 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg
)},
4715 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg
)},
4716 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg
)},
4717 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg
)},
4718 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg
)},
4719 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg
)},
4720 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg
)},
4721 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg
)},
4722 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg
)},
4723 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg
)},
4724 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg
)},
4725 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg
)},
4726 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg
)},
4727 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg
)},
4728 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg
)},
4729 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg
)},
4730 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg
)},
4732 /* 6x50 WiFi/WiMax Series */
4733 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg
)},
4734 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg
)},
4735 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg
)},
4736 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg
)},
4737 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg
)},
4738 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg
)},
4740 /* 6x50 WiFi/WiMax Series Gen2 */
4741 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg
)},
4742 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg
)},
4743 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg
)},
4744 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg
)},
4745 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg
)},
4746 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg
)},
4748 /* 1000 Series WiFi */
4749 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg
)},
4750 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg
)},
4751 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg
)},
4752 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg
)},
4753 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg
)},
4754 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg
)},
4755 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg
)},
4756 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg
)},
4757 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg
)},
4758 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg
)},
4759 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg
)},
4760 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg
)},
4761 #endif /* CONFIG_IWL5000 */
4765 MODULE_DEVICE_TABLE(pci
, iwl_hw_card_ids
);
4767 static struct pci_driver iwl_driver
= {
4769 .id_table
= iwl_hw_card_ids
,
4770 .probe
= iwl_pci_probe
,
4771 .remove
= __devexit_p(iwl_pci_remove
),
4773 .suspend
= iwl_pci_suspend
,
4774 .resume
= iwl_pci_resume
,
4778 static int __init
iwl_init(void)
4782 pr_info(DRV_DESCRIPTION
", " DRV_VERSION
"\n");
4783 pr_info(DRV_COPYRIGHT
"\n");
4785 ret
= iwlagn_rate_control_register();
4787 pr_err("Unable to register rate control algorithm: %d\n", ret
);
4791 ret
= pci_register_driver(&iwl_driver
);
4793 pr_err("Unable to initialize PCI module\n");
4794 goto error_register
;
4800 iwlagn_rate_control_unregister();
4804 static void __exit
iwl_exit(void)
4806 pci_unregister_driver(&iwl_driver
);
4807 iwlagn_rate_control_unregister();
4810 module_exit(iwl_exit
);
4811 module_init(iwl_init
);
4813 #ifdef CONFIG_IWLWIFI_DEBUG
4814 module_param_named(debug50
, iwl_debug_level
, uint
, S_IRUGO
);
4815 MODULE_PARM_DESC(debug50
, "50XX debug output mask (deprecated)");
4816 module_param_named(debug
, iwl_debug_level
, uint
, S_IRUGO
| S_IWUSR
);
4817 MODULE_PARM_DESC(debug
, "debug output mask");
4820 module_param_named(swcrypto50
, iwlagn_mod_params
.sw_crypto
, bool, S_IRUGO
);
4821 MODULE_PARM_DESC(swcrypto50
,
4822 "using crypto in software (default 0 [hardware]) (deprecated)");
4823 module_param_named(swcrypto
, iwlagn_mod_params
.sw_crypto
, int, S_IRUGO
);
4824 MODULE_PARM_DESC(swcrypto
, "using crypto in software (default 0 [hardware])");
4825 module_param_named(queues_num50
,
4826 iwlagn_mod_params
.num_of_queues
, int, S_IRUGO
);
4827 MODULE_PARM_DESC(queues_num50
,
4828 "number of hw queues in 50xx series (deprecated)");
4829 module_param_named(queues_num
, iwlagn_mod_params
.num_of_queues
, int, S_IRUGO
);
4830 MODULE_PARM_DESC(queues_num
, "number of hw queues.");
4831 module_param_named(11n_disable50
, iwlagn_mod_params
.disable_11n
, int, S_IRUGO
);
4832 MODULE_PARM_DESC(11n_disable50
, "disable 50XX 11n functionality (deprecated)");
4833 module_param_named(11n_disable
, iwlagn_mod_params
.disable_11n
, int, S_IRUGO
);
4834 MODULE_PARM_DESC(11n_disable
, "disable 11n functionality");
4835 module_param_named(amsdu_size_8K50
, iwlagn_mod_params
.amsdu_size_8K
,
4837 MODULE_PARM_DESC(amsdu_size_8K50
,
4838 "enable 8K amsdu size in 50XX series (deprecated)");
4839 module_param_named(amsdu_size_8K
, iwlagn_mod_params
.amsdu_size_8K
,
4841 MODULE_PARM_DESC(amsdu_size_8K
, "enable 8K amsdu size");
4842 module_param_named(fw_restart50
, iwlagn_mod_params
.restart_fw
, int, S_IRUGO
);
4843 MODULE_PARM_DESC(fw_restart50
,
4844 "restart firmware in case of error (deprecated)");
4845 module_param_named(fw_restart
, iwlagn_mod_params
.restart_fw
, int, S_IRUGO
);
4846 MODULE_PARM_DESC(fw_restart
, "restart firmware in case of error");
4848 disable_hw_scan
, iwlagn_mod_params
.disable_hw_scan
, int, S_IRUGO
);
4849 MODULE_PARM_DESC(disable_hw_scan
, "disable hardware scanning (default 0)");
4851 module_param_named(ucode_alternative
, iwlagn_wanted_ucode_alternative
, int,
4853 MODULE_PARM_DESC(ucode_alternative
,
4854 "specify ucode alternative to use from ucode file");
4856 module_param_named(antenna_coupling
, iwlagn_ant_coupling
, int, S_IRUGO
);
4857 MODULE_PARM_DESC(antenna_coupling
,
4858 "specify antenna coupling in dB (defualt: 0 dB)");
4860 module_param_named(bt_ch_announce
, iwlagn_bt_ch_announce
, bool, S_IRUGO
);
4861 MODULE_PARM_DESC(bt_ch_announce
,
4862 "Enable BT channel announcement mode (default: enable)");