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ARM: JIVE: Update mach-jive to use gpiolib API
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / s2io.c
blob92ae8d3de39be642cccc50321696895bac745f1c
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4 *
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
56
57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
59 #include <linux/module.h>
60 #include <linux/types.h>
61 #include <linux/errno.h>
62 #include <linux/ioport.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/kernel.h>
66 #include <linux/netdevice.h>
67 #include <linux/etherdevice.h>
68 #include <linux/mdio.h>
69 #include <linux/skbuff.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/stddef.h>
73 #include <linux/ioctl.h>
74 #include <linux/timex.h>
75 #include <linux/ethtool.h>
76 #include <linux/workqueue.h>
77 #include <linux/if_vlan.h>
78 #include <linux/ip.h>
79 #include <linux/tcp.h>
80 #include <linux/uaccess.h>
81 #include <linux/io.h>
82 #include <linux/slab.h>
83 #include <net/tcp.h>
84
85 #include <asm/system.h>
86 #include <asm/div64.h>
87 #include <asm/irq.h>
88
89 /* local include */
90 #include "s2io.h"
91 #include "s2io-regs.h"
92
93 #define DRV_VERSION "2.0.26.25"
94
95 /* S2io Driver name & version. */
96 static char s2io_driver_name[] = "Neterion";
97 static char s2io_driver_version[] = DRV_VERSION;
98
99 static int rxd_size[2] = {32, 48};
100 static int rxd_count[2] = {127, 85};
101
102 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
103 {
104 int ret;
105
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
108
109 return ret;
110 }
111
112 /*
113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
116 */
117 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
121
122 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
124
125 static inline int is_s2io_card_up(const struct s2io_nic *sp)
126 {
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128 }
129
130 /* Ethtool related variables and Macros. */
131 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
137 };
138
139 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
140 {"tmac_frms"},
141 {"tmac_data_octets"},
142 {"tmac_drop_frms"},
143 {"tmac_mcst_frms"},
144 {"tmac_bcst_frms"},
145 {"tmac_pause_ctrl_frms"},
146 {"tmac_ttl_octets"},
147 {"tmac_ucst_frms"},
148 {"tmac_nucst_frms"},
149 {"tmac_any_err_frms"},
150 {"tmac_ttl_less_fb_octets"},
151 {"tmac_vld_ip_octets"},
152 {"tmac_vld_ip"},
153 {"tmac_drop_ip"},
154 {"tmac_icmp"},
155 {"tmac_rst_tcp"},
156 {"tmac_tcp"},
157 {"tmac_udp"},
158 {"rmac_vld_frms"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
161 {"rmac_drop_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
165 {"rmac_out_rng_len_err_frms"},
166 {"rmac_long_frms"},
167 {"rmac_pause_ctrl_frms"},
168 {"rmac_unsup_ctrl_frms"},
169 {"rmac_ttl_octets"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
172 {"rmac_discarded_frms"},
173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
175 {"rmac_ttl_frms"},
176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
178 {"rmac_frag_frms"},
179 {"rmac_jabber_frms"},
180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
186 {"rmac_ip"},
187 {"rmac_ip_octets"},
188 {"rmac_hdr_err_ip"},
189 {"rmac_drop_ip"},
190 {"rmac_icmp"},
191 {"rmac_tcp"},
192 {"rmac_udp"},
193 {"rmac_err_drp_udp"},
194 {"rmac_xgmii_err_sym"},
195 {"rmac_frms_q0"},
196 {"rmac_frms_q1"},
197 {"rmac_frms_q2"},
198 {"rmac_frms_q3"},
199 {"rmac_frms_q4"},
200 {"rmac_frms_q5"},
201 {"rmac_frms_q6"},
202 {"rmac_frms_q7"},
203 {"rmac_full_q0"},
204 {"rmac_full_q1"},
205 {"rmac_full_q2"},
206 {"rmac_full_q3"},
207 {"rmac_full_q4"},
208 {"rmac_full_q5"},
209 {"rmac_full_q6"},
210 {"rmac_full_q7"},
211 {"rmac_pause_cnt"},
212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
214 {"rmac_accepted_ip"},
215 {"rmac_err_tcp"},
216 {"rd_req_cnt"},
217 {"new_rd_req_cnt"},
218 {"new_rd_req_rtry_cnt"},
219 {"rd_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
221 {"wr_req_cnt"},
222 {"new_wr_req_cnt"},
223 {"new_wr_req_rtry_cnt"},
224 {"wr_rtry_cnt"},
225 {"wr_disc_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
227 {"txp_wr_cnt"},
228 {"txd_rd_cnt"},
229 {"txd_wr_cnt"},
230 {"rxd_rd_cnt"},
231 {"rxd_wr_cnt"},
232 {"txf_rd_cnt"},
233 {"rxf_wr_cnt"}
234 };
235
236 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
244 {"rmac_vlan_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
247 {"rmac_pf_discard"},
248 {"rmac_da_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
252 {"link_fault_cnt"}
253 };
254
255 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
259 {"parity_err_cnt"},
260 {"serious_err_cnt"},
261 {"soft_reset_cnt"},
262 {"fifo_full_cnt"},
263 {"ring_0_full_cnt"},
264 {"ring_1_full_cnt"},
265 {"ring_2_full_cnt"},
266 {"ring_3_full_cnt"},
267 {"ring_4_full_cnt"},
268 {"ring_5_full_cnt"},
269 {"ring_6_full_cnt"},
270 {"ring_7_full_cnt"},
271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
291 {"mem_allocated"},
292 {"mem_freed"},
293 {"link_up_cnt"},
294 {"link_down_cnt"},
295 {"link_up_time"},
296 {"link_down_time"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
311 {"tda_err_cnt"},
312 {"pfc_err_cnt"},
313 {"pcc_err_cnt"},
314 {"tti_err_cnt"},
315 {"tpa_err_cnt"},
316 {"sm_err_cnt"},
317 {"lso_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
322 {"rc_err_cnt"},
323 {"prc_pcix_err_cnt"},
324 {"rpa_err_cnt"},
325 {"rda_err_cnt"},
326 {"rti_err_cnt"},
327 {"mc_err_cnt"}
328 };
329
330 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
333
334 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
336
337 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
339
340 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
341 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
342
343 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
348
349 /* copy mac addr to def_mac_addr array */
350 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351 {
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358 }
359
360 /* Add the vlan */
361 static void s2io_vlan_rx_register(struct net_device *dev,
362 struct vlan_group *grp)
363 {
364 int i;
365 struct s2io_nic *nic = netdev_priv(dev);
366 unsigned long flags[MAX_TX_FIFOS];
367 struct config_param *config = &nic->config;
368 struct mac_info *mac_control = &nic->mac_control;
369
370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
372
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
374 }
375
376 nic->vlgrp = grp;
377
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
380
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 }
383 }
384
385 /* Unregister the vlan */
386 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
387 {
388 int i;
389 struct s2io_nic *nic = netdev_priv(dev);
390 unsigned long flags[MAX_TX_FIFOS];
391 struct config_param *config = &nic->config;
392 struct mac_info *mac_control = &nic->mac_control;
393
394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
396
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 }
399
400 if (nic->vlgrp)
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
402
403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
405
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
407 }
408 }
409
410 /*
411 * Constants to be programmed into the Xena's registers, to configure
412 * the XAUI.
413 */
414
415 #define END_SIGN 0x0
416 static const u64 herc_act_dtx_cfg[] = {
417 /* Set address */
418 0x8000051536750000ULL, 0x80000515367500E0ULL,
419 /* Write data */
420 0x8000051536750004ULL, 0x80000515367500E4ULL,
421 /* Set address */
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
423 /* Write data */
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
425 /* Set address */
426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
427 /* Write data */
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
429 /* Set address */
430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
431 /* Write data */
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
433 /* Done */
434 END_SIGN
435 };
436
437 static const u64 xena_dtx_cfg[] = {
438 /* Set address */
439 0x8000051500000000ULL, 0x80000515000000E0ULL,
440 /* Write data */
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
442 /* Set address */
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
444 /* Write data */
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
446 /* Set address */
447 0x8002051500000000ULL, 0x80020515000000E0ULL,
448 /* Write data */
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
450 END_SIGN
451 };
452
453 /*
454 * Constants for Fixing the MacAddress problem seen mostly on
455 * Alpha machines.
456 */
457 static const u64 fix_mac[] = {
458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
472 END_SIGN
473 };
474
475 MODULE_LICENSE("GPL");
476 MODULE_VERSION(DRV_VERSION);
477
478
479 /* Module Loadable parameters. */
480 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
481 S2IO_PARM_INT(rx_ring_num, 1);
482 S2IO_PARM_INT(multiq, 0);
483 S2IO_PARM_INT(rx_ring_mode, 1);
484 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485 S2IO_PARM_INT(rmac_pause_time, 0x100);
486 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488 S2IO_PARM_INT(shared_splits, 0);
489 S2IO_PARM_INT(tmac_util_period, 5);
490 S2IO_PARM_INT(rmac_util_period, 5);
491 S2IO_PARM_INT(l3l4hdr_size, 128);
492 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
494 /* Frequency of Rx desc syncs expressed as power of 2 */
495 S2IO_PARM_INT(rxsync_frequency, 3);
496 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
497 S2IO_PARM_INT(intr_type, 2);
498 /* Large receive offload feature */
499 static unsigned int lro_enable;
500 module_param_named(lro, lro_enable, uint, 0);
501
502 /* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
504 */
505 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
506 S2IO_PARM_INT(indicate_max_pkts, 0);
507
508 S2IO_PARM_INT(napi, 1);
509 S2IO_PARM_INT(ufo, 0);
510 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
511
512 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
513 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
514 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
515 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
516 static unsigned int rts_frm_len[MAX_RX_RINGS] =
517 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
518
519 module_param_array(tx_fifo_len, uint, NULL, 0);
520 module_param_array(rx_ring_sz, uint, NULL, 0);
521 module_param_array(rts_frm_len, uint, NULL, 0);
522
523 /*
524 * S2IO device table.
525 * This table lists all the devices that this driver supports.
526 */
527 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
536 {0,}
537 };
538
539 MODULE_DEVICE_TABLE(pci, s2io_tbl);
540
541 static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
545 };
546
547 static struct pci_driver s2io_driver = {
548 .name = "S2IO",
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
553 };
554
555 /* A simplifier macro used both by init and free shared_mem Fns(). */
556 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
557
558 /* netqueue manipulation helper functions */
559 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
560 {
561 if (!sp->config.multiq) {
562 int i;
563
564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
566 }
567 netif_tx_stop_all_queues(sp->dev);
568 }
569
570 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
571 {
572 if (!sp->config.multiq)
573 sp->mac_control.fifos[fifo_no].queue_state =
574 FIFO_QUEUE_STOP;
575
576 netif_tx_stop_all_queues(sp->dev);
577 }
578
579 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
580 {
581 if (!sp->config.multiq) {
582 int i;
583
584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
586 }
587 netif_tx_start_all_queues(sp->dev);
588 }
589
590 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
591 {
592 if (!sp->config.multiq)
593 sp->mac_control.fifos[fifo_no].queue_state =
594 FIFO_QUEUE_START;
595
596 netif_tx_start_all_queues(sp->dev);
597 }
598
599 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
600 {
601 if (!sp->config.multiq) {
602 int i;
603
604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
606 }
607 netif_tx_wake_all_queues(sp->dev);
608 }
609
610 static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
612 {
613
614 if (multiq) {
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
621 }
622 }
623 }
624
625 /**
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
630 * Rx descriptors and the statistics block.
631 */
632
633 static int init_shared_mem(struct s2io_nic *nic)
634 {
635 u32 size;
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
638 struct RxD_block *pre_rxd_blk = NULL;
639 int i, j, blk_cnt;
640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
642 unsigned long tmp;
643 struct buffAdd *ba;
644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
646 unsigned long long mem_allocated = 0;
647
648 /* Allocation and initialization of TXDLs in FIFOs */
649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
652
653 size += tx_cfg->fifo_len;
654 }
655 if (size > MAX_AVAILABLE_TXDS) {
656 DBG_PRINT(ERR_DBG,
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
659 return -EINVAL;
660 }
661
662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
673 i, size);
674 return -EINVAL;
675 }
676 }
677
678 lst_size = (sizeof(struct TxD) * config->max_txds);
679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
690 return -ENOMEM;
691 }
692 mem_allocated += list_holder_size;
693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
708
709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
716 DBG_PRINT(INFO_DBG,
717 "pci_alloc_consistent failed for TxDL\n");
718 return -ENOMEM;
719 }
720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
727 DBG_PRINT(INIT_DBG,
728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
730 dev->name, tmp_v);
731 tmp_v = pci_alloc_consistent(nic->pdev,
732 PAGE_SIZE, &tmp_p);
733 if (!tmp_v) {
734 DBG_PRINT(INFO_DBG,
735 "pci_alloc_consistent failed for TxDL\n");
736 return -ENOMEM;
737 }
738 mem_allocated += PAGE_SIZE;
739 }
740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
742 if (l == tx_cfg->fifo_len)
743 break;
744 fifo->list_info[l].list_virt_addr =
745 tmp_v + (k * lst_size);
746 fifo->list_info[l].list_phy_addr =
747 tmp_p + (k * lst_size);
748 k++;
749 }
750 }
751 }
752
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
756
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
760 return -ENOMEM;
761 mem_allocated += (size * sizeof(u64));
762 }
763
764 /* Allocation and initialization of RXDs in Rings */
765 size = 0;
766 for (i = 0; i < config->rx_ring_num; i++) {
767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
769
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
773 dev->name, i);
774 return FAILURE;
775 }
776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
778 (rxd_count[nic->rxd_mode] + 1);
779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
780 }
781 if (nic->rxd_mode == RXD_MODE_1)
782 size = (size * (sizeof(struct RxD1)));
783 else
784 size = (size * (sizeof(struct RxD3)));
785
786 for (i = 0; i < config->rx_ring_num; i++) {
787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
789
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->nic = nic;
797 ring->ring_no = i;
798 ring->lro = lro_enable;
799
800 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
801 /* Allocating all the Rx blocks */
802 for (j = 0; j < blk_cnt; j++) {
803 struct rx_block_info *rx_blocks;
804 int l;
805
806 rx_blocks = &ring->rx_blocks[j];
807 size = SIZE_OF_BLOCK; /* size is always page size */
808 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
809 &tmp_p_addr);
810 if (tmp_v_addr == NULL) {
811 /*
812 * In case of failure, free_shared_mem()
813 * is called, which should free any
814 * memory that was alloced till the
815 * failure happened.
816 */
817 rx_blocks->block_virt_addr = tmp_v_addr;
818 return -ENOMEM;
819 }
820 mem_allocated += size;
821 memset(tmp_v_addr, 0, size);
822
823 size = sizeof(struct rxd_info) *
824 rxd_count[nic->rxd_mode];
825 rx_blocks->block_virt_addr = tmp_v_addr;
826 rx_blocks->block_dma_addr = tmp_p_addr;
827 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
828 if (!rx_blocks->rxds)
829 return -ENOMEM;
830 mem_allocated += size;
831 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
832 rx_blocks->rxds[l].virt_addr =
833 rx_blocks->block_virt_addr +
834 (rxd_size[nic->rxd_mode] * l);
835 rx_blocks->rxds[l].dma_addr =
836 rx_blocks->block_dma_addr +
837 (rxd_size[nic->rxd_mode] * l);
838 }
839 }
840 /* Interlinking all Rx Blocks */
841 for (j = 0; j < blk_cnt; j++) {
842 int next = (j + 1) % blk_cnt;
843 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
844 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
845 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
846 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
847
848 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
849 pre_rxd_blk->reserved_2_pNext_RxD_block =
850 (unsigned long)tmp_v_addr_next;
851 pre_rxd_blk->pNext_RxD_Blk_physical =
852 (u64)tmp_p_addr_next;
853 }
854 }
855 if (nic->rxd_mode == RXD_MODE_3B) {
856 /*
857 * Allocation of Storages for buffer addresses in 2BUFF mode
858 * and the buffers as well.
859 */
860 for (i = 0; i < config->rx_ring_num; i++) {
861 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
862 struct ring_info *ring = &mac_control->rings[i];
863
864 blk_cnt = rx_cfg->num_rxd /
865 (rxd_count[nic->rxd_mode] + 1);
866 size = sizeof(struct buffAdd *) * blk_cnt;
867 ring->ba = kmalloc(size, GFP_KERNEL);
868 if (!ring->ba)
869 return -ENOMEM;
870 mem_allocated += size;
871 for (j = 0; j < blk_cnt; j++) {
872 int k = 0;
873
874 size = sizeof(struct buffAdd) *
875 (rxd_count[nic->rxd_mode] + 1);
876 ring->ba[j] = kmalloc(size, GFP_KERNEL);
877 if (!ring->ba[j])
878 return -ENOMEM;
879 mem_allocated += size;
880 while (k != rxd_count[nic->rxd_mode]) {
881 ba = &ring->ba[j][k];
882 size = BUF0_LEN + ALIGN_SIZE;
883 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
884 if (!ba->ba_0_org)
885 return -ENOMEM;
886 mem_allocated += size;
887 tmp = (unsigned long)ba->ba_0_org;
888 tmp += ALIGN_SIZE;
889 tmp &= ~((unsigned long)ALIGN_SIZE);
890 ba->ba_0 = (void *)tmp;
891
892 size = BUF1_LEN + ALIGN_SIZE;
893 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
894 if (!ba->ba_1_org)
895 return -ENOMEM;
896 mem_allocated += size;
897 tmp = (unsigned long)ba->ba_1_org;
898 tmp += ALIGN_SIZE;
899 tmp &= ~((unsigned long)ALIGN_SIZE);
900 ba->ba_1 = (void *)tmp;
901 k++;
902 }
903 }
904 }
905 }
906
907 /* Allocation and initialization of Statistics block */
908 size = sizeof(struct stat_block);
909 mac_control->stats_mem =
910 pci_alloc_consistent(nic->pdev, size,
911 &mac_control->stats_mem_phy);
912
913 if (!mac_control->stats_mem) {
914 /*
915 * In case of failure, free_shared_mem() is called, which
916 * should free any memory that was alloced till the
917 * failure happened.
918 */
919 return -ENOMEM;
920 }
921 mem_allocated += size;
922 mac_control->stats_mem_sz = size;
923
924 tmp_v_addr = mac_control->stats_mem;
925 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
926 memset(tmp_v_addr, 0, size);
927 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
928 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
929 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
930 return SUCCESS;
931 }
932
933 /**
934 * free_shared_mem - Free the allocated Memory
935 * @nic: Device private variable.
936 * Description: This function is to free all memory locations allocated by
937 * the init_shared_mem() function and return it to the kernel.
938 */
939
940 static void free_shared_mem(struct s2io_nic *nic)
941 {
942 int i, j, blk_cnt, size;
943 void *tmp_v_addr;
944 dma_addr_t tmp_p_addr;
945 int lst_size, lst_per_page;
946 struct net_device *dev;
947 int page_num = 0;
948 struct config_param *config;
949 struct mac_info *mac_control;
950 struct stat_block *stats;
951 struct swStat *swstats;
952
953 if (!nic)
954 return;
955
956 dev = nic->dev;
957
958 config = &nic->config;
959 mac_control = &nic->mac_control;
960 stats = mac_control->stats_info;
961 swstats = &stats->sw_stat;
962
963 lst_size = sizeof(struct TxD) * config->max_txds;
964 lst_per_page = PAGE_SIZE / lst_size;
965
966 for (i = 0; i < config->tx_fifo_num; i++) {
967 struct fifo_info *fifo = &mac_control->fifos[i];
968 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
969
970 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
971 for (j = 0; j < page_num; j++) {
972 int mem_blks = (j * lst_per_page);
973 struct list_info_hold *fli;
974
975 if (!fifo->list_info)
976 return;
977
978 fli = &fifo->list_info[mem_blks];
979 if (!fli->list_virt_addr)
980 break;
981 pci_free_consistent(nic->pdev, PAGE_SIZE,
982 fli->list_virt_addr,
983 fli->list_phy_addr);
984 swstats->mem_freed += PAGE_SIZE;
985 }
986 /* If we got a zero DMA address during allocation,
987 * free the page now
988 */
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
992 (dma_addr_t)0);
993 DBG_PRINT(INIT_DBG,
994 "%s: Freeing TxDL with zero DMA address. "
995 "Virtual address %p\n",
996 dev->name, mac_control->zerodma_virt_addr);
997 swstats->mem_freed += PAGE_SIZE;
998 }
999 kfree(fifo->list_info);
1000 swstats->mem_freed += tx_cfg->fifo_len *
1001 sizeof(struct list_info_hold);
1002 }
1003
1004 size = SIZE_OF_BLOCK;
1005 for (i = 0; i < config->rx_ring_num; i++) {
1006 struct ring_info *ring = &mac_control->rings[i];
1007
1008 blk_cnt = ring->block_count;
1009 for (j = 0; j < blk_cnt; j++) {
1010 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1011 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1012 if (tmp_v_addr == NULL)
1013 break;
1014 pci_free_consistent(nic->pdev, size,
1015 tmp_v_addr, tmp_p_addr);
1016 swstats->mem_freed += size;
1017 kfree(ring->rx_blocks[j].rxds);
1018 swstats->mem_freed += sizeof(struct rxd_info) *
1019 rxd_count[nic->rxd_mode];
1020 }
1021 }
1022
1023 if (nic->rxd_mode == RXD_MODE_3B) {
1024 /* Freeing buffer storage addresses in 2BUFF mode. */
1025 for (i = 0; i < config->rx_ring_num; i++) {
1026 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1027 struct ring_info *ring = &mac_control->rings[i];
1028
1029 blk_cnt = rx_cfg->num_rxd /
1030 (rxd_count[nic->rxd_mode] + 1);
1031 for (j = 0; j < blk_cnt; j++) {
1032 int k = 0;
1033 if (!ring->ba[j])
1034 continue;
1035 while (k != rxd_count[nic->rxd_mode]) {
1036 struct buffAdd *ba = &ring->ba[j][k];
1037 kfree(ba->ba_0_org);
1038 swstats->mem_freed +=
1039 BUF0_LEN + ALIGN_SIZE;
1040 kfree(ba->ba_1_org);
1041 swstats->mem_freed +=
1042 BUF1_LEN + ALIGN_SIZE;
1043 k++;
1044 }
1045 kfree(ring->ba[j]);
1046 swstats->mem_freed += sizeof(struct buffAdd) *
1047 (rxd_count[nic->rxd_mode] + 1);
1048 }
1049 kfree(ring->ba);
1050 swstats->mem_freed += sizeof(struct buffAdd *) *
1051 blk_cnt;
1052 }
1053 }
1054
1055 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1056 struct fifo_info *fifo = &mac_control->fifos[i];
1057 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1058
1059 if (fifo->ufo_in_band_v) {
1060 swstats->mem_freed += tx_cfg->fifo_len *
1061 sizeof(u64);
1062 kfree(fifo->ufo_in_band_v);
1063 }
1064 }
1065
1066 if (mac_control->stats_mem) {
1067 swstats->mem_freed += mac_control->stats_mem_sz;
1068 pci_free_consistent(nic->pdev,
1069 mac_control->stats_mem_sz,
1070 mac_control->stats_mem,
1071 mac_control->stats_mem_phy);
1072 }
1073 }
1074
1075 /**
1076 * s2io_verify_pci_mode -
1077 */
1078
1079 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1080 {
1081 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1082 register u64 val64 = 0;
1083 int mode;
1084
1085 val64 = readq(&bar0->pci_mode);
1086 mode = (u8)GET_PCI_MODE(val64);
1087
1088 if (val64 & PCI_MODE_UNKNOWN_MODE)
1089 return -1; /* Unknown PCI mode */
1090 return mode;
1091 }
1092
1093 #define NEC_VENID 0x1033
1094 #define NEC_DEVID 0x0125
1095 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1096 {
1097 struct pci_dev *tdev = NULL;
1098 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1099 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1100 if (tdev->bus == s2io_pdev->bus->parent) {
1101 pci_dev_put(tdev);
1102 return 1;
1103 }
1104 }
1105 }
1106 return 0;
1107 }
1108
1109 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1110 /**
1111 * s2io_print_pci_mode -
1112 */
1113 static int s2io_print_pci_mode(struct s2io_nic *nic)
1114 {
1115 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1116 register u64 val64 = 0;
1117 int mode;
1118 struct config_param *config = &nic->config;
1119 const char *pcimode;
1120
1121 val64 = readq(&bar0->pci_mode);
1122 mode = (u8)GET_PCI_MODE(val64);
1123
1124 if (val64 & PCI_MODE_UNKNOWN_MODE)
1125 return -1; /* Unknown PCI mode */
1126
1127 config->bus_speed = bus_speed[mode];
1128
1129 if (s2io_on_nec_bridge(nic->pdev)) {
1130 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1131 nic->dev->name);
1132 return mode;
1133 }
1134
1135 switch (mode) {
1136 case PCI_MODE_PCI_33:
1137 pcimode = "33MHz PCI bus";
1138 break;
1139 case PCI_MODE_PCI_66:
1140 pcimode = "66MHz PCI bus";
1141 break;
1142 case PCI_MODE_PCIX_M1_66:
1143 pcimode = "66MHz PCIX(M1) bus";
1144 break;
1145 case PCI_MODE_PCIX_M1_100:
1146 pcimode = "100MHz PCIX(M1) bus";
1147 break;
1148 case PCI_MODE_PCIX_M1_133:
1149 pcimode = "133MHz PCIX(M1) bus";
1150 break;
1151 case PCI_MODE_PCIX_M2_66:
1152 pcimode = "133MHz PCIX(M2) bus";
1153 break;
1154 case PCI_MODE_PCIX_M2_100:
1155 pcimode = "200MHz PCIX(M2) bus";
1156 break;
1157 case PCI_MODE_PCIX_M2_133:
1158 pcimode = "266MHz PCIX(M2) bus";
1159 break;
1160 default:
1161 pcimode = "unsupported bus!";
1162 mode = -1;
1163 }
1164
1165 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1166 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1167
1168 return mode;
1169 }
1170
1171 /**
1172 * init_tti - Initialization transmit traffic interrupt scheme
1173 * @nic: device private variable
1174 * @link: link status (UP/DOWN) used to enable/disable continuous
1175 * transmit interrupts
1176 * Description: The function configures transmit traffic interrupts
1177 * Return Value: SUCCESS on success and
1178 * '-1' on failure
1179 */
1180
1181 static int init_tti(struct s2io_nic *nic, int link)
1182 {
1183 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1184 register u64 val64 = 0;
1185 int i;
1186 struct config_param *config = &nic->config;
1187
1188 for (i = 0; i < config->tx_fifo_num; i++) {
1189 /*
1190 * TTI Initialization. Default Tx timer gets us about
1191 * 250 interrupts per sec. Continuous interrupts are enabled
1192 * by default.
1193 */
1194 if (nic->device_type == XFRAME_II_DEVICE) {
1195 int count = (nic->config.bus_speed * 125)/2;
1196 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1197 } else
1198 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1199
1200 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1201 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1202 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1203 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1204 if (i == 0)
1205 if (use_continuous_tx_intrs && (link == LINK_UP))
1206 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1207 writeq(val64, &bar0->tti_data1_mem);
1208
1209 if (nic->config.intr_type == MSI_X) {
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x300);
1214 } else {
1215 if ((nic->config.tx_steering_type ==
1216 TX_DEFAULT_STEERING) &&
1217 (config->tx_fifo_num > 1) &&
1218 (i >= nic->udp_fifo_idx) &&
1219 (i < (nic->udp_fifo_idx +
1220 nic->total_udp_fifos)))
1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x120);
1225 else
1226 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1227 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1228 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1229 TTI_DATA2_MEM_TX_UFC_D(0x80);
1230 }
1231
1232 writeq(val64, &bar0->tti_data2_mem);
1233
1234 val64 = TTI_CMD_MEM_WE |
1235 TTI_CMD_MEM_STROBE_NEW_CMD |
1236 TTI_CMD_MEM_OFFSET(i);
1237 writeq(val64, &bar0->tti_command_mem);
1238
1239 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1240 TTI_CMD_MEM_STROBE_NEW_CMD,
1241 S2IO_BIT_RESET) != SUCCESS)
1242 return FAILURE;
1243 }
1244
1245 return SUCCESS;
1246 }
1247
1248 /**
1249 * init_nic - Initialization of hardware
1250 * @nic: device private variable
1251 * Description: The function sequentially configures every block
1252 * of the H/W from their reset values.
1253 * Return Value: SUCCESS on success and
1254 * '-1' on failure (endian settings incorrect).
1255 */
1256
1257 static int init_nic(struct s2io_nic *nic)
1258 {
1259 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1260 struct net_device *dev = nic->dev;
1261 register u64 val64 = 0;
1262 void __iomem *add;
1263 u32 time;
1264 int i, j;
1265 int dtx_cnt = 0;
1266 unsigned long long mem_share;
1267 int mem_size;
1268 struct config_param *config = &nic->config;
1269 struct mac_info *mac_control = &nic->mac_control;
1270
1271 /* to set the swapper controle on the card */
1272 if (s2io_set_swapper(nic)) {
1273 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1274 return -EIO;
1275 }
1276
1277 /*
1278 * Herc requires EOI to be removed from reset before XGXS, so..
1279 */
1280 if (nic->device_type & XFRAME_II_DEVICE) {
1281 val64 = 0xA500000000ULL;
1282 writeq(val64, &bar0->sw_reset);
1283 msleep(500);
1284 val64 = readq(&bar0->sw_reset);
1285 }
1286
1287 /* Remove XGXS from reset state */
1288 val64 = 0;
1289 writeq(val64, &bar0->sw_reset);
1290 msleep(500);
1291 val64 = readq(&bar0->sw_reset);
1292
1293 /* Ensure that it's safe to access registers by checking
1294 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1295 */
1296 if (nic->device_type == XFRAME_II_DEVICE) {
1297 for (i = 0; i < 50; i++) {
1298 val64 = readq(&bar0->adapter_status);
1299 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1300 break;
1301 msleep(10);
1302 }
1303 if (i == 50)
1304 return -ENODEV;
1305 }
1306
1307 /* Enable Receiving broadcasts */
1308 add = &bar0->mac_cfg;
1309 val64 = readq(&bar0->mac_cfg);
1310 val64 |= MAC_RMAC_BCAST_ENABLE;
1311 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1312 writel((u32)val64, add);
1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314 writel((u32) (val64 >> 32), (add + 4));
1315
1316 /* Read registers in all blocks */
1317 val64 = readq(&bar0->mac_int_mask);
1318 val64 = readq(&bar0->mc_int_mask);
1319 val64 = readq(&bar0->xgxs_int_mask);
1320
1321 /* Set MTU */
1322 val64 = dev->mtu;
1323 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1324
1325 if (nic->device_type & XFRAME_II_DEVICE) {
1326 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1327 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1328 &bar0->dtx_control, UF);
1329 if (dtx_cnt & 0x1)
1330 msleep(1); /* Necessary!! */
1331 dtx_cnt++;
1332 }
1333 } else {
1334 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1335 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1336 &bar0->dtx_control, UF);
1337 val64 = readq(&bar0->dtx_control);
1338 dtx_cnt++;
1339 }
1340 }
1341
1342 /* Tx DMA Initialization */
1343 val64 = 0;
1344 writeq(val64, &bar0->tx_fifo_partition_0);
1345 writeq(val64, &bar0->tx_fifo_partition_1);
1346 writeq(val64, &bar0->tx_fifo_partition_2);
1347 writeq(val64, &bar0->tx_fifo_partition_3);
1348
1349 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1350 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1351
1352 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1353 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1354
1355 if (i == (config->tx_fifo_num - 1)) {
1356 if (i % 2 == 0)
1357 i++;
1358 }
1359
1360 switch (i) {
1361 case 1:
1362 writeq(val64, &bar0->tx_fifo_partition_0);
1363 val64 = 0;
1364 j = 0;
1365 break;
1366 case 3:
1367 writeq(val64, &bar0->tx_fifo_partition_1);
1368 val64 = 0;
1369 j = 0;
1370 break;
1371 case 5:
1372 writeq(val64, &bar0->tx_fifo_partition_2);
1373 val64 = 0;
1374 j = 0;
1375 break;
1376 case 7:
1377 writeq(val64, &bar0->tx_fifo_partition_3);
1378 val64 = 0;
1379 j = 0;
1380 break;
1381 default:
1382 j++;
1383 break;
1384 }
1385 }
1386
1387 /*
1388 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1389 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1390 */
1391 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1392 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1393
1394 val64 = readq(&bar0->tx_fifo_partition_0);
1395 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1396 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1397
1398 /*
1399 * Initialization of Tx_PA_CONFIG register to ignore packet
1400 * integrity checking.
1401 */
1402 val64 = readq(&bar0->tx_pa_cfg);
1403 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1404 TX_PA_CFG_IGNORE_SNAP_OUI |
1405 TX_PA_CFG_IGNORE_LLC_CTRL |
1406 TX_PA_CFG_IGNORE_L2_ERR;
1407 writeq(val64, &bar0->tx_pa_cfg);
1408
1409 /* Rx DMA intialization. */
1410 val64 = 0;
1411 for (i = 0; i < config->rx_ring_num; i++) {
1412 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1413
1414 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1415 }
1416 writeq(val64, &bar0->rx_queue_priority);
1417
1418 /*
1419 * Allocating equal share of memory to all the
1420 * configured Rings.
1421 */
1422 val64 = 0;
1423 if (nic->device_type & XFRAME_II_DEVICE)
1424 mem_size = 32;
1425 else
1426 mem_size = 64;
1427
1428 for (i = 0; i < config->rx_ring_num; i++) {
1429 switch (i) {
1430 case 0:
1431 mem_share = (mem_size / config->rx_ring_num +
1432 mem_size % config->rx_ring_num);
1433 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1434 continue;
1435 case 1:
1436 mem_share = (mem_size / config->rx_ring_num);
1437 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1438 continue;
1439 case 2:
1440 mem_share = (mem_size / config->rx_ring_num);
1441 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1442 continue;
1443 case 3:
1444 mem_share = (mem_size / config->rx_ring_num);
1445 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1446 continue;
1447 case 4:
1448 mem_share = (mem_size / config->rx_ring_num);
1449 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1450 continue;
1451 case 5:
1452 mem_share = (mem_size / config->rx_ring_num);
1453 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1454 continue;
1455 case 6:
1456 mem_share = (mem_size / config->rx_ring_num);
1457 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1458 continue;
1459 case 7:
1460 mem_share = (mem_size / config->rx_ring_num);
1461 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1462 continue;
1463 }
1464 }
1465 writeq(val64, &bar0->rx_queue_cfg);
1466
1467 /*
1468 * Filling Tx round robin registers
1469 * as per the number of FIFOs for equal scheduling priority
1470 */
1471 switch (config->tx_fifo_num) {
1472 case 1:
1473 val64 = 0x0;
1474 writeq(val64, &bar0->tx_w_round_robin_0);
1475 writeq(val64, &bar0->tx_w_round_robin_1);
1476 writeq(val64, &bar0->tx_w_round_robin_2);
1477 writeq(val64, &bar0->tx_w_round_robin_3);
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 2:
1481 val64 = 0x0001000100010001ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 writeq(val64, &bar0->tx_w_round_robin_2);
1485 writeq(val64, &bar0->tx_w_round_robin_3);
1486 val64 = 0x0001000100000000ULL;
1487 writeq(val64, &bar0->tx_w_round_robin_4);
1488 break;
1489 case 3:
1490 val64 = 0x0001020001020001ULL;
1491 writeq(val64, &bar0->tx_w_round_robin_0);
1492 val64 = 0x0200010200010200ULL;
1493 writeq(val64, &bar0->tx_w_round_robin_1);
1494 val64 = 0x0102000102000102ULL;
1495 writeq(val64, &bar0->tx_w_round_robin_2);
1496 val64 = 0x0001020001020001ULL;
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 val64 = 0x0200010200000000ULL;
1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 4:
1502 val64 = 0x0001020300010203ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_0);
1504 writeq(val64, &bar0->tx_w_round_robin_1);
1505 writeq(val64, &bar0->tx_w_round_robin_2);
1506 writeq(val64, &bar0->tx_w_round_robin_3);
1507 val64 = 0x0001020300000000ULL;
1508 writeq(val64, &bar0->tx_w_round_robin_4);
1509 break;
1510 case 5:
1511 val64 = 0x0001020304000102ULL;
1512 writeq(val64, &bar0->tx_w_round_robin_0);
1513 val64 = 0x0304000102030400ULL;
1514 writeq(val64, &bar0->tx_w_round_robin_1);
1515 val64 = 0x0102030400010203ULL;
1516 writeq(val64, &bar0->tx_w_round_robin_2);
1517 val64 = 0x0400010203040001ULL;
1518 writeq(val64, &bar0->tx_w_round_robin_3);
1519 val64 = 0x0203040000000000ULL;
1520 writeq(val64, &bar0->tx_w_round_robin_4);
1521 break;
1522 case 6:
1523 val64 = 0x0001020304050001ULL;
1524 writeq(val64, &bar0->tx_w_round_robin_0);
1525 val64 = 0x0203040500010203ULL;
1526 writeq(val64, &bar0->tx_w_round_robin_1);
1527 val64 = 0x0405000102030405ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_2);
1529 val64 = 0x0001020304050001ULL;
1530 writeq(val64, &bar0->tx_w_round_robin_3);
1531 val64 = 0x0203040500000000ULL;
1532 writeq(val64, &bar0->tx_w_round_robin_4);
1533 break;
1534 case 7:
1535 val64 = 0x0001020304050600ULL;
1536 writeq(val64, &bar0->tx_w_round_robin_0);
1537 val64 = 0x0102030405060001ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_1);
1539 val64 = 0x0203040506000102ULL;
1540 writeq(val64, &bar0->tx_w_round_robin_2);
1541 val64 = 0x0304050600010203ULL;
1542 writeq(val64, &bar0->tx_w_round_robin_3);
1543 val64 = 0x0405060000000000ULL;
1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 case 8:
1547 val64 = 0x0001020304050607ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_0);
1549 writeq(val64, &bar0->tx_w_round_robin_1);
1550 writeq(val64, &bar0->tx_w_round_robin_2);
1551 writeq(val64, &bar0->tx_w_round_robin_3);
1552 val64 = 0x0001020300000000ULL;
1553 writeq(val64, &bar0->tx_w_round_robin_4);
1554 break;
1555 }
1556
1557 /* Enable all configured Tx FIFO partitions */
1558 val64 = readq(&bar0->tx_fifo_partition_0);
1559 val64 |= (TX_FIFO_PARTITION_EN);
1560 writeq(val64, &bar0->tx_fifo_partition_0);
1561
1562 /* Filling the Rx round robin registers as per the
1563 * number of Rings and steering based on QoS with
1564 * equal priority.
1565 */
1566 switch (config->rx_ring_num) {
1567 case 1:
1568 val64 = 0x0;
1569 writeq(val64, &bar0->rx_w_round_robin_0);
1570 writeq(val64, &bar0->rx_w_round_robin_1);
1571 writeq(val64, &bar0->rx_w_round_robin_2);
1572 writeq(val64, &bar0->rx_w_round_robin_3);
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1574
1575 val64 = 0x8080808080808080ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1577 break;
1578 case 2:
1579 val64 = 0x0001000100010001ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_0);
1581 writeq(val64, &bar0->rx_w_round_robin_1);
1582 writeq(val64, &bar0->rx_w_round_robin_2);
1583 writeq(val64, &bar0->rx_w_round_robin_3);
1584 val64 = 0x0001000100000000ULL;
1585 writeq(val64, &bar0->rx_w_round_robin_4);
1586
1587 val64 = 0x8080808040404040ULL;
1588 writeq(val64, &bar0->rts_qos_steering);
1589 break;
1590 case 3:
1591 val64 = 0x0001020001020001ULL;
1592 writeq(val64, &bar0->rx_w_round_robin_0);
1593 val64 = 0x0200010200010200ULL;
1594 writeq(val64, &bar0->rx_w_round_robin_1);
1595 val64 = 0x0102000102000102ULL;
1596 writeq(val64, &bar0->rx_w_round_robin_2);
1597 val64 = 0x0001020001020001ULL;
1598 writeq(val64, &bar0->rx_w_round_robin_3);
1599 val64 = 0x0200010200000000ULL;
1600 writeq(val64, &bar0->rx_w_round_robin_4);
1601
1602 val64 = 0x8080804040402020ULL;
1603 writeq(val64, &bar0->rts_qos_steering);
1604 break;
1605 case 4:
1606 val64 = 0x0001020300010203ULL;
1607 writeq(val64, &bar0->rx_w_round_robin_0);
1608 writeq(val64, &bar0->rx_w_round_robin_1);
1609 writeq(val64, &bar0->rx_w_round_robin_2);
1610 writeq(val64, &bar0->rx_w_round_robin_3);
1611 val64 = 0x0001020300000000ULL;
1612 writeq(val64, &bar0->rx_w_round_robin_4);
1613
1614 val64 = 0x8080404020201010ULL;
1615 writeq(val64, &bar0->rts_qos_steering);
1616 break;
1617 case 5:
1618 val64 = 0x0001020304000102ULL;
1619 writeq(val64, &bar0->rx_w_round_robin_0);
1620 val64 = 0x0304000102030400ULL;
1621 writeq(val64, &bar0->rx_w_round_robin_1);
1622 val64 = 0x0102030400010203ULL;
1623 writeq(val64, &bar0->rx_w_round_robin_2);
1624 val64 = 0x0400010203040001ULL;
1625 writeq(val64, &bar0->rx_w_round_robin_3);
1626 val64 = 0x0203040000000000ULL;
1627 writeq(val64, &bar0->rx_w_round_robin_4);
1628
1629 val64 = 0x8080404020201008ULL;
1630 writeq(val64, &bar0->rts_qos_steering);
1631 break;
1632 case 6:
1633 val64 = 0x0001020304050001ULL;
1634 writeq(val64, &bar0->rx_w_round_robin_0);
1635 val64 = 0x0203040500010203ULL;
1636 writeq(val64, &bar0->rx_w_round_robin_1);
1637 val64 = 0x0405000102030405ULL;
1638 writeq(val64, &bar0->rx_w_round_robin_2);
1639 val64 = 0x0001020304050001ULL;
1640 writeq(val64, &bar0->rx_w_round_robin_3);
1641 val64 = 0x0203040500000000ULL;
1642 writeq(val64, &bar0->rx_w_round_robin_4);
1643
1644 val64 = 0x8080404020100804ULL;
1645 writeq(val64, &bar0->rts_qos_steering);
1646 break;
1647 case 7:
1648 val64 = 0x0001020304050600ULL;
1649 writeq(val64, &bar0->rx_w_round_robin_0);
1650 val64 = 0x0102030405060001ULL;
1651 writeq(val64, &bar0->rx_w_round_robin_1);
1652 val64 = 0x0203040506000102ULL;
1653 writeq(val64, &bar0->rx_w_round_robin_2);
1654 val64 = 0x0304050600010203ULL;
1655 writeq(val64, &bar0->rx_w_round_robin_3);
1656 val64 = 0x0405060000000000ULL;
1657 writeq(val64, &bar0->rx_w_round_robin_4);
1658
1659 val64 = 0x8080402010080402ULL;
1660 writeq(val64, &bar0->rts_qos_steering);
1661 break;
1662 case 8:
1663 val64 = 0x0001020304050607ULL;
1664 writeq(val64, &bar0->rx_w_round_robin_0);
1665 writeq(val64, &bar0->rx_w_round_robin_1);
1666 writeq(val64, &bar0->rx_w_round_robin_2);
1667 writeq(val64, &bar0->rx_w_round_robin_3);
1668 val64 = 0x0001020300000000ULL;
1669 writeq(val64, &bar0->rx_w_round_robin_4);
1670
1671 val64 = 0x8040201008040201ULL;
1672 writeq(val64, &bar0->rts_qos_steering);
1673 break;
1674 }
1675
1676 /* UDP Fix */
1677 val64 = 0;
1678 for (i = 0; i < 8; i++)
1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1680
1681 /* Set the default rts frame length for the rings configured */
1682 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1683 for (i = 0 ; i < config->rx_ring_num ; i++)
1684 writeq(val64, &bar0->rts_frm_len_n[i]);
1685
1686 /* Set the frame length for the configured rings
1687 * desired by the user
1688 */
1689 for (i = 0; i < config->rx_ring_num; i++) {
1690 /* If rts_frm_len[i] == 0 then it is assumed that user not
1691 * specified frame length steering.
1692 * If the user provides the frame length then program
1693 * the rts_frm_len register for those values or else
1694 * leave it as it is.
1695 */
1696 if (rts_frm_len[i] != 0) {
1697 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1698 &bar0->rts_frm_len_n[i]);
1699 }
1700 }
1701
1702 /* Disable differentiated services steering logic */
1703 for (i = 0; i < 64; i++) {
1704 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1705 DBG_PRINT(ERR_DBG,
1706 "%s: rts_ds_steer failed on codepoint %d\n",
1707 dev->name, i);
1708 return -ENODEV;
1709 }
1710 }
1711
1712 /* Program statistics memory */
1713 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1714
1715 if (nic->device_type == XFRAME_II_DEVICE) {
1716 val64 = STAT_BC(0x320);
1717 writeq(val64, &bar0->stat_byte_cnt);
1718 }
1719
1720 /*
1721 * Initializing the sampling rate for the device to calculate the
1722 * bandwidth utilization.
1723 */
1724 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1725 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1726 writeq(val64, &bar0->mac_link_util);
1727
1728 /*
1729 * Initializing the Transmit and Receive Traffic Interrupt
1730 * Scheme.
1731 */
1732
1733 /* Initialize TTI */
1734 if (SUCCESS != init_tti(nic, nic->last_link_state))
1735 return -ENODEV;
1736
1737 /* RTI Initialization */
1738 if (nic->device_type == XFRAME_II_DEVICE) {
1739 /*
1740 * Programmed to generate Apprx 500 Intrs per
1741 * second
1742 */
1743 int count = (nic->config.bus_speed * 125)/4;
1744 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1745 } else
1746 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1747 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1748 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1749 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1750 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1751
1752 writeq(val64, &bar0->rti_data1_mem);
1753
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
1759 else
1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
1762 writeq(val64, &bar0->rti_data2_mem);
1763
1764 for (i = 0; i < config->rx_ring_num; i++) {
1765 val64 = RTI_CMD_MEM_WE |
1766 RTI_CMD_MEM_STROBE_NEW_CMD |
1767 RTI_CMD_MEM_OFFSET(i);
1768 writeq(val64, &bar0->rti_command_mem);
1769
1770 /*
1771 * Once the operation completes, the Strobe bit of the
1772 * command register will be reset. We poll for this
1773 * particular condition. We wait for a maximum of 500ms
1774 * for the operation to complete, if it's not complete
1775 * by then we return error.
1776 */
1777 time = 0;
1778 while (true) {
1779 val64 = readq(&bar0->rti_command_mem);
1780 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1781 break;
1782
1783 if (time > 10) {
1784 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1785 dev->name);
1786 return -ENODEV;
1787 }
1788 time++;
1789 msleep(50);
1790 }
1791 }
1792
1793 /*
1794 * Initializing proper values as Pause threshold into all
1795 * the 8 Queues on Rx side.
1796 */
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1798 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1799
1800 /* Disable RMAC PAD STRIPPING */
1801 add = &bar0->mac_cfg;
1802 val64 = readq(&bar0->mac_cfg);
1803 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1804 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1805 writel((u32) (val64), add);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64 >> 32), (add + 4));
1808 val64 = readq(&bar0->mac_cfg);
1809
1810 /* Enable FCS stripping by adapter */
1811 add = &bar0->mac_cfg;
1812 val64 = readq(&bar0->mac_cfg);
1813 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1814 if (nic->device_type == XFRAME_II_DEVICE)
1815 writeq(val64, &bar0->mac_cfg);
1816 else {
1817 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writel((u32) (val64), add);
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64 >> 32), (add + 4));
1821 }
1822
1823 /*
1824 * Set the time value to be inserted in the pause frame
1825 * generated by xena.
1826 */
1827 val64 = readq(&bar0->rmac_pause_cfg);
1828 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1829 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1830 writeq(val64, &bar0->rmac_pause_cfg);
1831
1832 /*
1833 * Set the Threshold Limit for Generating the pause frame
1834 * If the amount of data in any Queue exceeds ratio of
1835 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1836 * pause frame is generated
1837 */
1838 val64 = 0;
1839 for (i = 0; i < 4; i++) {
1840 val64 |= (((u64)0xFF00 |
1841 nic->mac_control.mc_pause_threshold_q0q3)
1842 << (i * 2 * 8));
1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1845
1846 val64 = 0;
1847 for (i = 0; i < 4; i++) {
1848 val64 |= (((u64)0xFF00 |
1849 nic->mac_control.mc_pause_threshold_q4q7)
1850 << (i * 2 * 8));
1851 }
1852 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1853
1854 /*
1855 * TxDMA will stop Read request if the number of read split has
1856 * exceeded the limit pointed by shared_splits
1857 */
1858 val64 = readq(&bar0->pic_control);
1859 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1860 writeq(val64, &bar0->pic_control);
1861
1862 if (nic->config.bus_speed == 266) {
1863 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1864 writeq(0x0, &bar0->read_retry_delay);
1865 writeq(0x0, &bar0->write_retry_delay);
1866 }
1867
1868 /*
1869 * Programming the Herc to split every write transaction
1870 * that does not start on an ADB to reduce disconnects.
1871 */
1872 if (nic->device_type == XFRAME_II_DEVICE) {
1873 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1874 MISC_LINK_STABILITY_PRD(3);
1875 writeq(val64, &bar0->misc_control);
1876 val64 = readq(&bar0->pic_control2);
1877 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1878 writeq(val64, &bar0->pic_control2);
1879 }
1880 if (strstr(nic->product_name, "CX4")) {
1881 val64 = TMAC_AVG_IPG(0x17);
1882 writeq(val64, &bar0->tmac_avg_ipg);
1883 }
1884
1885 return SUCCESS;
1886 }
1887 #define LINK_UP_DOWN_INTERRUPT 1
1888 #define MAC_RMAC_ERR_TIMER 2
1889
1890 static int s2io_link_fault_indication(struct s2io_nic *nic)
1891 {
1892 if (nic->device_type == XFRAME_II_DEVICE)
1893 return LINK_UP_DOWN_INTERRUPT;
1894 else
1895 return MAC_RMAC_ERR_TIMER;
1896 }
1897
1898 /**
1899 * do_s2io_write_bits - update alarm bits in alarm register
1900 * @value: alarm bits
1901 * @flag: interrupt status
1902 * @addr: address value
1903 * Description: update alarm bits in alarm register
1904 * Return Value:
1905 * NONE.
1906 */
1907 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1908 {
1909 u64 temp64;
1910
1911 temp64 = readq(addr);
1912
1913 if (flag == ENABLE_INTRS)
1914 temp64 &= ~((u64)value);
1915 else
1916 temp64 |= ((u64)value);
1917 writeq(temp64, addr);
1918 }
1919
1920 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1921 {
1922 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923 register u64 gen_int_mask = 0;
1924 u64 interruptible;
1925
1926 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1927 if (mask & TX_DMA_INTR) {
1928 gen_int_mask |= TXDMA_INT_M;
1929
1930 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1931 TXDMA_PCC_INT | TXDMA_TTI_INT |
1932 TXDMA_LSO_INT | TXDMA_TPA_INT |
1933 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1934
1935 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1936 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1937 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1938 &bar0->pfc_err_mask);
1939
1940 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1941 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1942 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1943
1944 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1945 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1946 PCC_N_SERR | PCC_6_COF_OV_ERR |
1947 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1948 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1949 PCC_TXB_ECC_SG_ERR,
1950 flag, &bar0->pcc_err_mask);
1951
1952 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1953 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1954
1955 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1956 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1957 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1958 flag, &bar0->lso_err_mask);
1959
1960 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1961 flag, &bar0->tpa_err_mask);
1962
1963 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1964 }
1965
1966 if (mask & TX_MAC_INTR) {
1967 gen_int_mask |= TXMAC_INT_M;
1968 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1969 &bar0->mac_int_mask);
1970 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1971 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1972 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1973 flag, &bar0->mac_tmac_err_mask);
1974 }
1975
1976 if (mask & TX_XGXS_INTR) {
1977 gen_int_mask |= TXXGXS_INT_M;
1978 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1979 &bar0->xgxs_int_mask);
1980 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1981 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1982 flag, &bar0->xgxs_txgxs_err_mask);
1983 }
1984
1985 if (mask & RX_DMA_INTR) {
1986 gen_int_mask |= RXDMA_INT_M;
1987 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1988 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1989 flag, &bar0->rxdma_int_mask);
1990 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1991 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1992 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1993 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1994 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1995 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1996 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1997 &bar0->prc_pcix_err_mask);
1998 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1999 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2000 &bar0->rpa_err_mask);
2001 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2002 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2003 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2004 RDA_FRM_ECC_SG_ERR |
2005 RDA_MISC_ERR|RDA_PCIX_ERR,
2006 flag, &bar0->rda_err_mask);
2007 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2008 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2009 flag, &bar0->rti_err_mask);
2010 }
2011
2012 if (mask & RX_MAC_INTR) {
2013 gen_int_mask |= RXMAC_INT_M;
2014 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2015 &bar0->mac_int_mask);
2016 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2017 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2018 RMAC_DOUBLE_ECC_ERR);
2019 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2020 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2021 do_s2io_write_bits(interruptible,
2022 flag, &bar0->mac_rmac_err_mask);
2023 }
2024
2025 if (mask & RX_XGXS_INTR) {
2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2028 &bar0->xgxs_int_mask);
2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2030 &bar0->xgxs_rxgxs_err_mask);
2031 }
2032
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
2035 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2036 flag, &bar0->mc_int_mask);
2037 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2038 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2039 &bar0->mc_err_mask);
2040 }
2041 nic->general_int_mask = gen_int_mask;
2042
2043 /* Remove this line when alarm interrupts are enabled */
2044 nic->general_int_mask = 0;
2045 }
2046
2047 /**
2048 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2049 * @nic: device private variable,
2050 * @mask: A mask indicating which Intr block must be modified and,
2051 * @flag: A flag indicating whether to enable or disable the Intrs.
2052 * Description: This function will either disable or enable the interrupts
2053 * depending on the flag argument. The mask argument can be used to
2054 * enable/disable any Intr block.
2055 * Return Value: NONE.
2056 */
2057
2058 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2059 {
2060 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2061 register u64 temp64 = 0, intr_mask = 0;
2062
2063 intr_mask = nic->general_int_mask;
2064
2065 /* Top level interrupt classification */
2066 /* PIC Interrupts */
2067 if (mask & TX_PIC_INTR) {
2068 /* Enable PIC Intrs in the general intr mask register */
2069 intr_mask |= TXPIC_INT_M;
2070 if (flag == ENABLE_INTRS) {
2071 /*
2072 * If Hercules adapter enable GPIO otherwise
2073 * disable all PCIX, Flash, MDIO, IIC and GPIO
2074 * interrupts for now.
2075 * TODO
2076 */
2077 if (s2io_link_fault_indication(nic) ==
2078 LINK_UP_DOWN_INTERRUPT) {
2079 do_s2io_write_bits(PIC_INT_GPIO, flag,
2080 &bar0->pic_int_mask);
2081 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2082 &bar0->gpio_int_mask);
2083 } else
2084 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2085 } else if (flag == DISABLE_INTRS) {
2086 /*
2087 * Disable PIC Intrs in the general
2088 * intr mask register
2089 */
2090 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2091 }
2092 }
2093
2094 /* Tx traffic interrupts */
2095 if (mask & TX_TRAFFIC_INTR) {
2096 intr_mask |= TXTRAFFIC_INT_M;
2097 if (flag == ENABLE_INTRS) {
2098 /*
2099 * Enable all the Tx side interrupts
2100 * writing 0 Enables all 64 TX interrupt levels
2101 */
2102 writeq(0x0, &bar0->tx_traffic_mask);
2103 } else if (flag == DISABLE_INTRS) {
2104 /*
2105 * Disable Tx Traffic Intrs in the general intr mask
2106 * register.
2107 */
2108 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2109 }
2110 }
2111
2112 /* Rx traffic interrupts */
2113 if (mask & RX_TRAFFIC_INTR) {
2114 intr_mask |= RXTRAFFIC_INT_M;
2115 if (flag == ENABLE_INTRS) {
2116 /* writing 0 Enables all 8 RX interrupt levels */
2117 writeq(0x0, &bar0->rx_traffic_mask);
2118 } else if (flag == DISABLE_INTRS) {
2119 /*
2120 * Disable Rx Traffic Intrs in the general intr mask
2121 * register.
2122 */
2123 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2124 }
2125 }
2126
2127 temp64 = readq(&bar0->general_int_mask);
2128 if (flag == ENABLE_INTRS)
2129 temp64 &= ~((u64)intr_mask);
2130 else
2131 temp64 = DISABLE_ALL_INTRS;
2132 writeq(temp64, &bar0->general_int_mask);
2133
2134 nic->general_int_mask = readq(&bar0->general_int_mask);
2135 }
2136
2137 /**
2138 * verify_pcc_quiescent- Checks for PCC quiescent state
2139 * Return: 1 If PCC is quiescence
2140 * 0 If PCC is not quiescence
2141 */
2142 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2143 {
2144 int ret = 0, herc;
2145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2146 u64 val64 = readq(&bar0->adapter_status);
2147
2148 herc = (sp->device_type == XFRAME_II_DEVICE);
2149
2150 if (flag == false) {
2151 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2152 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2153 ret = 1;
2154 } else {
2155 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2156 ret = 1;
2157 }
2158 } else {
2159 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2161 ADAPTER_STATUS_RMAC_PCC_IDLE))
2162 ret = 1;
2163 } else {
2164 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2165 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2166 ret = 1;
2167 }
2168 }
2169
2170 return ret;
2171 }
2172 /**
2173 * verify_xena_quiescence - Checks whether the H/W is ready
2174 * Description: Returns whether the H/W is ready to go or not. Depending
2175 * on whether adapter enable bit was written or not the comparison
2176 * differs and the calling function passes the input argument flag to
2177 * indicate this.
2178 * Return: 1 If xena is quiescence
2179 * 0 If Xena is not quiescence
2180 */
2181
2182 static int verify_xena_quiescence(struct s2io_nic *sp)
2183 {
2184 int mode;
2185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2186 u64 val64 = readq(&bar0->adapter_status);
2187 mode = s2io_verify_pci_mode(sp);
2188
2189 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2190 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2191 return 0;
2192 }
2193 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2194 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2195 return 0;
2196 }
2197 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2198 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2199 return 0;
2200 }
2201 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2202 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2206 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2210 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2214 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2215 return 0;
2216 }
2217 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2218 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2219 return 0;
2220 }
2221
2222 /*
2223 * In PCI 33 mode, the P_PLL is not used, and therefore,
2224 * the the P_PLL_LOCK bit in the adapter_status register will
2225 * not be asserted.
2226 */
2227 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2228 sp->device_type == XFRAME_II_DEVICE &&
2229 mode != PCI_MODE_PCI_33) {
2230 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2231 return 0;
2232 }
2233 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2234 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2235 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2236 return 0;
2237 }
2238 return 1;
2239 }
2240
2241 /**
2242 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2243 * @sp: Pointer to device specifc structure
2244 * Description :
2245 * New procedure to clear mac address reading problems on Alpha platforms
2246 *
2247 */
2248
2249 static void fix_mac_address(struct s2io_nic *sp)
2250 {
2251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2252 u64 val64;
2253 int i = 0;
2254
2255 while (fix_mac[i] != END_SIGN) {
2256 writeq(fix_mac[i++], &bar0->gpio_control);
2257 udelay(10);
2258 val64 = readq(&bar0->gpio_control);
2259 }
2260 }
2261
2262 /**
2263 * start_nic - Turns the device on
2264 * @nic : device private variable.
2265 * Description:
2266 * This function actually turns the device on. Before this function is
2267 * called,all Registers are configured from their reset states
2268 * and shared memory is allocated but the NIC is still quiescent. On
2269 * calling this function, the device interrupts are cleared and the NIC is
2270 * literally switched on by writing into the adapter control register.
2271 * Return Value:
2272 * SUCCESS on success and -1 on failure.
2273 */
2274
2275 static int start_nic(struct s2io_nic *nic)
2276 {
2277 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2278 struct net_device *dev = nic->dev;
2279 register u64 val64 = 0;
2280 u16 subid, i;
2281 struct config_param *config = &nic->config;
2282 struct mac_info *mac_control = &nic->mac_control;
2283
2284 /* PRC Initialization and configuration */
2285 for (i = 0; i < config->rx_ring_num; i++) {
2286 struct ring_info *ring = &mac_control->rings[i];
2287
2288 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2289 &bar0->prc_rxd0_n[i]);
2290
2291 val64 = readq(&bar0->prc_ctrl_n[i]);
2292 if (nic->rxd_mode == RXD_MODE_1)
2293 val64 |= PRC_CTRL_RC_ENABLED;
2294 else
2295 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2296 if (nic->device_type == XFRAME_II_DEVICE)
2297 val64 |= PRC_CTRL_GROUP_READS;
2298 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2299 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2300 writeq(val64, &bar0->prc_ctrl_n[i]);
2301 }
2302
2303 if (nic->rxd_mode == RXD_MODE_3B) {
2304 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2305 val64 = readq(&bar0->rx_pa_cfg);
2306 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2307 writeq(val64, &bar0->rx_pa_cfg);
2308 }
2309
2310 if (vlan_tag_strip == 0) {
2311 val64 = readq(&bar0->rx_pa_cfg);
2312 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2313 writeq(val64, &bar0->rx_pa_cfg);
2314 nic->vlan_strip_flag = 0;
2315 }
2316
2317 /*
2318 * Enabling MC-RLDRAM. After enabling the device, we timeout
2319 * for around 100ms, which is approximately the time required
2320 * for the device to be ready for operation.
2321 */
2322 val64 = readq(&bar0->mc_rldram_mrs);
2323 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2324 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2325 val64 = readq(&bar0->mc_rldram_mrs);
2326
2327 msleep(100); /* Delay by around 100 ms. */
2328
2329 /* Enabling ECC Protection. */
2330 val64 = readq(&bar0->adapter_control);
2331 val64 &= ~ADAPTER_ECC_EN;
2332 writeq(val64, &bar0->adapter_control);
2333
2334 /*
2335 * Verify if the device is ready to be enabled, if so enable
2336 * it.
2337 */
2338 val64 = readq(&bar0->adapter_status);
2339 if (!verify_xena_quiescence(nic)) {
2340 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2341 "Adapter status reads: 0x%llx\n",
2342 dev->name, (unsigned long long)val64);
2343 return FAILURE;
2344 }
2345
2346 /*
2347 * With some switches, link might be already up at this point.
2348 * Because of this weird behavior, when we enable laser,
2349 * we may not get link. We need to handle this. We cannot
2350 * figure out which switch is misbehaving. So we are forced to
2351 * make a global change.
2352 */
2353
2354 /* Enabling Laser. */
2355 val64 = readq(&bar0->adapter_control);
2356 val64 |= ADAPTER_EOI_TX_ON;
2357 writeq(val64, &bar0->adapter_control);
2358
2359 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2360 /*
2361 * Dont see link state interrupts initally on some switches,
2362 * so directly scheduling the link state task here.
2363 */
2364 schedule_work(&nic->set_link_task);
2365 }
2366 /* SXE-002: Initialize link and activity LED */
2367 subid = nic->pdev->subsystem_device;
2368 if (((subid & 0xFF) >= 0x07) &&
2369 (nic->device_type == XFRAME_I_DEVICE)) {
2370 val64 = readq(&bar0->gpio_control);
2371 val64 |= 0x0000800000000000ULL;
2372 writeq(val64, &bar0->gpio_control);
2373 val64 = 0x0411040400000000ULL;
2374 writeq(val64, (void __iomem *)bar0 + 0x2700);
2375 }
2376
2377 return SUCCESS;
2378 }
2379 /**
2380 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2381 */
2382 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2383 struct TxD *txdlp, int get_off)
2384 {
2385 struct s2io_nic *nic = fifo_data->nic;
2386 struct sk_buff *skb;
2387 struct TxD *txds;
2388 u16 j, frg_cnt;
2389
2390 txds = txdlp;
2391 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2392 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2393 sizeof(u64), PCI_DMA_TODEVICE);
2394 txds++;
2395 }
2396
2397 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2398 if (!skb) {
2399 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2400 return NULL;
2401 }
2402 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2403 skb->len - skb->data_len, PCI_DMA_TODEVICE);
2404 frg_cnt = skb_shinfo(skb)->nr_frags;
2405 if (frg_cnt) {
2406 txds++;
2407 for (j = 0; j < frg_cnt; j++, txds++) {
2408 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2409 if (!txds->Buffer_Pointer)
2410 break;
2411 pci_unmap_page(nic->pdev,
2412 (dma_addr_t)txds->Buffer_Pointer,
2413 frag->size, PCI_DMA_TODEVICE);
2414 }
2415 }
2416 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2417 return skb;
2418 }
2419
2420 /**
2421 * free_tx_buffers - Free all queued Tx buffers
2422 * @nic : device private variable.
2423 * Description:
2424 * Free all queued Tx buffers.
2425 * Return Value: void
2426 */
2427
2428 static void free_tx_buffers(struct s2io_nic *nic)
2429 {
2430 struct net_device *dev = nic->dev;
2431 struct sk_buff *skb;
2432 struct TxD *txdp;
2433 int i, j;
2434 int cnt = 0;
2435 struct config_param *config = &nic->config;
2436 struct mac_info *mac_control = &nic->mac_control;
2437 struct stat_block *stats = mac_control->stats_info;
2438 struct swStat *swstats = &stats->sw_stat;
2439
2440 for (i = 0; i < config->tx_fifo_num; i++) {
2441 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2442 struct fifo_info *fifo = &mac_control->fifos[i];
2443 unsigned long flags;
2444
2445 spin_lock_irqsave(&fifo->tx_lock, flags);
2446 for (j = 0; j < tx_cfg->fifo_len; j++) {
2447 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2448 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2449 if (skb) {
2450 swstats->mem_freed += skb->truesize;
2451 dev_kfree_skb(skb);
2452 cnt++;
2453 }
2454 }
2455 DBG_PRINT(INTR_DBG,
2456 "%s: forcibly freeing %d skbs on FIFO%d\n",
2457 dev->name, cnt, i);
2458 fifo->tx_curr_get_info.offset = 0;
2459 fifo->tx_curr_put_info.offset = 0;
2460 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2461 }
2462 }
2463
2464 /**
2465 * stop_nic - To stop the nic
2466 * @nic ; device private variable.
2467 * Description:
2468 * This function does exactly the opposite of what the start_nic()
2469 * function does. This function is called to stop the device.
2470 * Return Value:
2471 * void.
2472 */
2473
2474 static void stop_nic(struct s2io_nic *nic)
2475 {
2476 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2477 register u64 val64 = 0;
2478 u16 interruptible;
2479
2480 /* Disable all interrupts */
2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2483 interruptible |= TX_PIC_INTR;
2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485
2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
2490 }
2491
2492 /**
2493 * fill_rx_buffers - Allocates the Rx side skbs
2494 * @ring_info: per ring structure
2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
2498 * Description:
2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2503 * 1. single buffer,
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2510 * supported.
2511 * Return Value:
2512 * SUCCESS on success or an appropriate -ve value on failure.
2513 */
2514 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2515 int from_card_up)
2516 {
2517 struct sk_buff *skb;
2518 struct RxD_t *rxdp;
2519 int off, size, block_no, block_no1;
2520 u32 alloc_tab = 0;
2521 u32 alloc_cnt;
2522 u64 tmp;
2523 struct buffAdd *ba;
2524 struct RxD_t *first_rxdp = NULL;
2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2526 int rxd_index = 0;
2527 struct RxD1 *rxdp1;
2528 struct RxD3 *rxdp3;
2529 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2530
2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2532
2533 block_no1 = ring->rx_curr_get_info.block_index;
2534 while (alloc_tab < alloc_cnt) {
2535 block_no = ring->rx_curr_put_info.block_index;
2536
2537 off = ring->rx_curr_put_info.offset;
2538
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540
2541 rxd_index = off + 1;
2542 if (block_no)
2543 rxd_index += (block_no * ring->rxd_count);
2544
2545 if ((block_no == block_no1) &&
2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
2548 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2549 ring->dev->name);
2550 goto end;
2551 }
2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
2555 ring->block_count)
2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2558 off = 0;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2562 ring->dev->name, rxdp);
2563
2564 }
2565
2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
2569 ring->rx_curr_put_info.offset = off;
2570 goto end;
2571 }
2572 /* calculate size of skb based on ring mode */
2573 size = ring->mtu +
2574 HEADER_ETHERNET_II_802_3_SIZE +
2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2576 if (ring->rxd_mode == RXD_MODE_1)
2577 size += NET_IP_ALIGN;
2578 else
2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2580
2581 /* allocate skb */
2582 skb = dev_alloc_skb(size);
2583 if (!skb) {
2584 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2585 ring->dev->name);
2586 if (first_rxdp) {
2587 wmb();
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 }
2590 swstats->mem_alloc_fail_cnt++;
2591
2592 return -ENOMEM ;
2593 }
2594 swstats->mem_allocated += skb->truesize;
2595
2596 if (ring->rxd_mode == RXD_MODE_1) {
2597 /* 1 buffer mode - normal operation mode */
2598 rxdp1 = (struct RxD1 *)rxdp;
2599 memset(rxdp, 0, sizeof(struct RxD1));
2600 skb_reserve(skb, NET_IP_ALIGN);
2601 rxdp1->Buffer0_ptr =
2602 pci_map_single(ring->pdev, skb->data,
2603 size - NET_IP_ALIGN,
2604 PCI_DMA_FROMDEVICE);
2605 if (pci_dma_mapping_error(nic->pdev,
2606 rxdp1->Buffer0_ptr))
2607 goto pci_map_failed;
2608
2609 rxdp->Control_2 =
2610 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2611 rxdp->Host_Control = (unsigned long)skb;
2612 } else if (ring->rxd_mode == RXD_MODE_3B) {
2613 /*
2614 * 2 buffer mode -
2615 * 2 buffer mode provides 128
2616 * byte aligned receive buffers.
2617 */
2618
2619 rxdp3 = (struct RxD3 *)rxdp;
2620 /* save buffer pointers to avoid frequent dma mapping */
2621 Buffer0_ptr = rxdp3->Buffer0_ptr;
2622 Buffer1_ptr = rxdp3->Buffer1_ptr;
2623 memset(rxdp, 0, sizeof(struct RxD3));
2624 /* restore the buffer pointers for dma sync*/
2625 rxdp3->Buffer0_ptr = Buffer0_ptr;
2626 rxdp3->Buffer1_ptr = Buffer1_ptr;
2627
2628 ba = &ring->ba[block_no][off];
2629 skb_reserve(skb, BUF0_LEN);
2630 tmp = (u64)(unsigned long)skb->data;
2631 tmp += ALIGN_SIZE;
2632 tmp &= ~ALIGN_SIZE;
2633 skb->data = (void *) (unsigned long)tmp;
2634 skb_reset_tail_pointer(skb);
2635
2636 if (from_card_up) {
2637 rxdp3->Buffer0_ptr =
2638 pci_map_single(ring->pdev, ba->ba_0,
2639 BUF0_LEN,
2640 PCI_DMA_FROMDEVICE);
2641 if (pci_dma_mapping_error(nic->pdev,
2642 rxdp3->Buffer0_ptr))
2643 goto pci_map_failed;
2644 } else
2645 pci_dma_sync_single_for_device(ring->pdev,
2646 (dma_addr_t)rxdp3->Buffer0_ptr,
2647 BUF0_LEN,
2648 PCI_DMA_FROMDEVICE);
2649
2650 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2651 if (ring->rxd_mode == RXD_MODE_3B) {
2652 /* Two buffer mode */
2653
2654 /*
2655 * Buffer2 will have L3/L4 header plus
2656 * L4 payload
2657 */
2658 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2659 skb->data,
2660 ring->mtu + 4,
2661 PCI_DMA_FROMDEVICE);
2662
2663 if (pci_dma_mapping_error(nic->pdev,
2664 rxdp3->Buffer2_ptr))
2665 goto pci_map_failed;
2666
2667 if (from_card_up) {
2668 rxdp3->Buffer1_ptr =
2669 pci_map_single(ring->pdev,
2670 ba->ba_1,
2671 BUF1_LEN,
2672 PCI_DMA_FROMDEVICE);
2673
2674 if (pci_dma_mapping_error(nic->pdev,
2675 rxdp3->Buffer1_ptr)) {
2676 pci_unmap_single(ring->pdev,
2677 (dma_addr_t)(unsigned long)
2678 skb->data,
2679 ring->mtu + 4,
2680 PCI_DMA_FROMDEVICE);
2681 goto pci_map_failed;
2682 }
2683 }
2684 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2685 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2686 (ring->mtu + 4);
2687 }
2688 rxdp->Control_2 |= s2BIT(0);
2689 rxdp->Host_Control = (unsigned long) (skb);
2690 }
2691 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2692 rxdp->Control_1 |= RXD_OWN_XENA;
2693 off++;
2694 if (off == (ring->rxd_count + 1))
2695 off = 0;
2696 ring->rx_curr_put_info.offset = off;
2697
2698 rxdp->Control_2 |= SET_RXD_MARKER;
2699 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2700 if (first_rxdp) {
2701 wmb();
2702 first_rxdp->Control_1 |= RXD_OWN_XENA;
2703 }
2704 first_rxdp = rxdp;
2705 }
2706 ring->rx_bufs_left += 1;
2707 alloc_tab++;
2708 }
2709
2710 end:
2711 /* Transfer ownership of first descriptor to adapter just before
2712 * exiting. Before that, use memory barrier so that ownership
2713 * and other fields are seen by adapter correctly.
2714 */
2715 if (first_rxdp) {
2716 wmb();
2717 first_rxdp->Control_1 |= RXD_OWN_XENA;
2718 }
2719
2720 return SUCCESS;
2721
2722 pci_map_failed:
2723 swstats->pci_map_fail_cnt++;
2724 swstats->mem_freed += skb->truesize;
2725 dev_kfree_skb_irq(skb);
2726 return -ENOMEM;
2727 }
2728
2729 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2730 {
2731 struct net_device *dev = sp->dev;
2732 int j;
2733 struct sk_buff *skb;
2734 struct RxD_t *rxdp;
2735 struct buffAdd *ba;
2736 struct RxD1 *rxdp1;
2737 struct RxD3 *rxdp3;
2738 struct mac_info *mac_control = &sp->mac_control;
2739 struct stat_block *stats = mac_control->stats_info;
2740 struct swStat *swstats = &stats->sw_stat;
2741
2742 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2743 rxdp = mac_control->rings[ring_no].
2744 rx_blocks[blk].rxds[j].virt_addr;
2745 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2746 if (!skb)
2747 continue;
2748 if (sp->rxd_mode == RXD_MODE_1) {
2749 rxdp1 = (struct RxD1 *)rxdp;
2750 pci_unmap_single(sp->pdev,
2751 (dma_addr_t)rxdp1->Buffer0_ptr,
2752 dev->mtu +
2753 HEADER_ETHERNET_II_802_3_SIZE +
2754 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2755 PCI_DMA_FROMDEVICE);
2756 memset(rxdp, 0, sizeof(struct RxD1));
2757 } else if (sp->rxd_mode == RXD_MODE_3B) {
2758 rxdp3 = (struct RxD3 *)rxdp;
2759 ba = &mac_control->rings[ring_no].ba[blk][j];
2760 pci_unmap_single(sp->pdev,
2761 (dma_addr_t)rxdp3->Buffer0_ptr,
2762 BUF0_LEN,
2763 PCI_DMA_FROMDEVICE);
2764 pci_unmap_single(sp->pdev,
2765 (dma_addr_t)rxdp3->Buffer1_ptr,
2766 BUF1_LEN,
2767 PCI_DMA_FROMDEVICE);
2768 pci_unmap_single(sp->pdev,
2769 (dma_addr_t)rxdp3->Buffer2_ptr,
2770 dev->mtu + 4,
2771 PCI_DMA_FROMDEVICE);
2772 memset(rxdp, 0, sizeof(struct RxD3));
2773 }
2774 swstats->mem_freed += skb->truesize;
2775 dev_kfree_skb(skb);
2776 mac_control->rings[ring_no].rx_bufs_left -= 1;
2777 }
2778 }
2779
2780 /**
2781 * free_rx_buffers - Frees all Rx buffers
2782 * @sp: device private variable.
2783 * Description:
2784 * This function will free all Rx buffers allocated by host.
2785 * Return Value:
2786 * NONE.
2787 */
2788
2789 static void free_rx_buffers(struct s2io_nic *sp)
2790 {
2791 struct net_device *dev = sp->dev;
2792 int i, blk = 0, buf_cnt = 0;
2793 struct config_param *config = &sp->config;
2794 struct mac_info *mac_control = &sp->mac_control;
2795
2796 for (i = 0; i < config->rx_ring_num; i++) {
2797 struct ring_info *ring = &mac_control->rings[i];
2798
2799 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2800 free_rxd_blk(sp, i, blk);
2801
2802 ring->rx_curr_put_info.block_index = 0;
2803 ring->rx_curr_get_info.block_index = 0;
2804 ring->rx_curr_put_info.offset = 0;
2805 ring->rx_curr_get_info.offset = 0;
2806 ring->rx_bufs_left = 0;
2807 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2808 dev->name, buf_cnt, i);
2809 }
2810 }
2811
2812 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2813 {
2814 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2815 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2816 ring->dev->name);
2817 }
2818 return 0;
2819 }
2820
2821 /**
2822 * s2io_poll - Rx interrupt handler for NAPI support
2823 * @napi : pointer to the napi structure.
2824 * @budget : The number of packets that were budgeted to be processed
2825 * during one pass through the 'Poll" function.
2826 * Description:
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2830 * Return value:
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2832 */
2833
2834 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2835 {
2836 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2837 struct net_device *dev = ring->dev;
2838 int pkts_processed = 0;
2839 u8 __iomem *addr = NULL;
2840 u8 val8 = 0;
2841 struct s2io_nic *nic = netdev_priv(dev);
2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843 int budget_org = budget;
2844
2845 if (unlikely(!is_s2io_card_up(nic)))
2846 return 0;
2847
2848 pkts_processed = rx_intr_handler(ring, budget);
2849 s2io_chk_rx_buffers(nic, ring);
2850
2851 if (pkts_processed < budget_org) {
2852 napi_complete(napi);
2853 /*Re Enable MSI-Rx Vector*/
2854 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2855 addr += 7 - ring->ring_no;
2856 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2857 writeb(val8, addr);
2858 val8 = readb(addr);
2859 }
2860 return pkts_processed;
2861 }
2862
2863 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2864 {
2865 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2866 int pkts_processed = 0;
2867 int ring_pkts_processed, i;
2868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2869 int budget_org = budget;
2870 struct config_param *config = &nic->config;
2871 struct mac_info *mac_control = &nic->mac_control;
2872
2873 if (unlikely(!is_s2io_card_up(nic)))
2874 return 0;
2875
2876 for (i = 0; i < config->rx_ring_num; i++) {
2877 struct ring_info *ring = &mac_control->rings[i];
2878 ring_pkts_processed = rx_intr_handler(ring, budget);
2879 s2io_chk_rx_buffers(nic, ring);
2880 pkts_processed += ring_pkts_processed;
2881 budget -= ring_pkts_processed;
2882 if (budget <= 0)
2883 break;
2884 }
2885 if (pkts_processed < budget_org) {
2886 napi_complete(napi);
2887 /* Re enable the Rx interrupts for the ring */
2888 writeq(0, &bar0->rx_traffic_mask);
2889 readl(&bar0->rx_traffic_mask);
2890 }
2891 return pkts_processed;
2892 }
2893
2894 #ifdef CONFIG_NET_POLL_CONTROLLER
2895 /**
2896 * s2io_netpoll - netpoll event handler entry point
2897 * @dev : pointer to the device structure.
2898 * Description:
2899 * This function will be called by upper layer to check for events on the
2900 * interface in situations where interrupts are disabled. It is used for
2901 * specific in-kernel networking tasks, such as remote consoles and kernel
2902 * debugging over the network (example netdump in RedHat).
2903 */
2904 static void s2io_netpoll(struct net_device *dev)
2905 {
2906 struct s2io_nic *nic = netdev_priv(dev);
2907 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2908 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2909 int i;
2910 struct config_param *config = &nic->config;
2911 struct mac_info *mac_control = &nic->mac_control;
2912
2913 if (pci_channel_offline(nic->pdev))
2914 return;
2915
2916 disable_irq(dev->irq);
2917
2918 writeq(val64, &bar0->rx_traffic_int);
2919 writeq(val64, &bar0->tx_traffic_int);
2920
2921 /* we need to free up the transmitted skbufs or else netpoll will
2922 * run out of skbs and will fail and eventually netpoll application such
2923 * as netdump will fail.
2924 */
2925 for (i = 0; i < config->tx_fifo_num; i++)
2926 tx_intr_handler(&mac_control->fifos[i]);
2927
2928 /* check for received packet and indicate up to network */
2929 for (i = 0; i < config->rx_ring_num; i++) {
2930 struct ring_info *ring = &mac_control->rings[i];
2931
2932 rx_intr_handler(ring, 0);
2933 }
2934
2935 for (i = 0; i < config->rx_ring_num; i++) {
2936 struct ring_info *ring = &mac_control->rings[i];
2937
2938 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2939 DBG_PRINT(INFO_DBG,
2940 "%s: Out of memory in Rx Netpoll!!\n",
2941 dev->name);
2942 break;
2943 }
2944 }
2945 enable_irq(dev->irq);
2946 return;
2947 }
2948 #endif
2949
2950 /**
2951 * rx_intr_handler - Rx interrupt handler
2952 * @ring_info: per ring structure.
2953 * @budget: budget for napi processing.
2954 * Description:
2955 * If the interrupt is because of a received frame or if the
2956 * receive ring contains fresh as yet un-processed frames,this function is
2957 * called. It picks out the RxD at which place the last Rx processing had
2958 * stopped and sends the skb to the OSM's Rx handler and then increments
2959 * the offset.
2960 * Return Value:
2961 * No. of napi packets processed.
2962 */
2963 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2964 {
2965 int get_block, put_block;
2966 struct rx_curr_get_info get_info, put_info;
2967 struct RxD_t *rxdp;
2968 struct sk_buff *skb;
2969 int pkt_cnt = 0, napi_pkts = 0;
2970 int i;
2971 struct RxD1 *rxdp1;
2972 struct RxD3 *rxdp3;
2973
2974 get_info = ring_data->rx_curr_get_info;
2975 get_block = get_info.block_index;
2976 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2977 put_block = put_info.block_index;
2978 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2979
2980 while (RXD_IS_UP2DT(rxdp)) {
2981 /*
2982 * If your are next to put index then it's
2983 * FIFO full condition
2984 */
2985 if ((get_block == put_block) &&
2986 (get_info.offset + 1) == put_info.offset) {
2987 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2988 ring_data->dev->name);
2989 break;
2990 }
2991 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2992 if (skb == NULL) {
2993 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2994 ring_data->dev->name);
2995 return 0;
2996 }
2997 if (ring_data->rxd_mode == RXD_MODE_1) {
2998 rxdp1 = (struct RxD1 *)rxdp;
2999 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3000 rxdp1->Buffer0_ptr,
3001 ring_data->mtu +
3002 HEADER_ETHERNET_II_802_3_SIZE +
3003 HEADER_802_2_SIZE +
3004 HEADER_SNAP_SIZE,
3005 PCI_DMA_FROMDEVICE);
3006 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3007 rxdp3 = (struct RxD3 *)rxdp;
3008 pci_dma_sync_single_for_cpu(ring_data->pdev,
3009 (dma_addr_t)rxdp3->Buffer0_ptr,
3010 BUF0_LEN,
3011 PCI_DMA_FROMDEVICE);
3012 pci_unmap_single(ring_data->pdev,
3013 (dma_addr_t)rxdp3->Buffer2_ptr,
3014 ring_data->mtu + 4,
3015 PCI_DMA_FROMDEVICE);
3016 }
3017 prefetch(skb->data);
3018 rx_osm_handler(ring_data, rxdp);
3019 get_info.offset++;
3020 ring_data->rx_curr_get_info.offset = get_info.offset;
3021 rxdp = ring_data->rx_blocks[get_block].
3022 rxds[get_info.offset].virt_addr;
3023 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3024 get_info.offset = 0;
3025 ring_data->rx_curr_get_info.offset = get_info.offset;
3026 get_block++;
3027 if (get_block == ring_data->block_count)
3028 get_block = 0;
3029 ring_data->rx_curr_get_info.block_index = get_block;
3030 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3031 }
3032
3033 if (ring_data->nic->config.napi) {
3034 budget--;
3035 napi_pkts++;
3036 if (!budget)
3037 break;
3038 }
3039 pkt_cnt++;
3040 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3041 break;
3042 }
3043 if (ring_data->lro) {
3044 /* Clear all LRO sessions before exiting */
3045 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3046 struct lro *lro = &ring_data->lro0_n[i];
3047 if (lro->in_use) {
3048 update_L3L4_header(ring_data->nic, lro);
3049 queue_rx_frame(lro->parent, lro->vlan_tag);
3050 clear_lro_session(lro);
3051 }
3052 }
3053 }
3054 return napi_pkts;
3055 }
3056
3057 /**
3058 * tx_intr_handler - Transmit interrupt handler
3059 * @nic : device private variable
3060 * Description:
3061 * If an interrupt was raised to indicate DMA complete of the
3062 * Tx packet, this function is called. It identifies the last TxD
3063 * whose buffer was freed and frees all skbs whose data have already
3064 * DMA'ed into the NICs internal memory.
3065 * Return Value:
3066 * NONE
3067 */
3068
3069 static void tx_intr_handler(struct fifo_info *fifo_data)
3070 {
3071 struct s2io_nic *nic = fifo_data->nic;
3072 struct tx_curr_get_info get_info, put_info;
3073 struct sk_buff *skb = NULL;
3074 struct TxD *txdlp;
3075 int pkt_cnt = 0;
3076 unsigned long flags = 0;
3077 u8 err_mask;
3078 struct stat_block *stats = nic->mac_control.stats_info;
3079 struct swStat *swstats = &stats->sw_stat;
3080
3081 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3082 return;
3083
3084 get_info = fifo_data->tx_curr_get_info;
3085 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3086 txdlp = (struct TxD *)
3087 fifo_data->list_info[get_info.offset].list_virt_addr;
3088 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3089 (get_info.offset != put_info.offset) &&
3090 (txdlp->Host_Control)) {
3091 /* Check for TxD errors */
3092 if (txdlp->Control_1 & TXD_T_CODE) {
3093 unsigned long long err;
3094 err = txdlp->Control_1 & TXD_T_CODE;
3095 if (err & 0x1) {
3096 swstats->parity_err_cnt++;
3097 }
3098
3099 /* update t_code statistics */
3100 err_mask = err >> 48;
3101 switch (err_mask) {
3102 case 2:
3103 swstats->tx_buf_abort_cnt++;
3104 break;
3105
3106 case 3:
3107 swstats->tx_desc_abort_cnt++;
3108 break;
3109
3110 case 7:
3111 swstats->tx_parity_err_cnt++;
3112 break;
3113
3114 case 10:
3115 swstats->tx_link_loss_cnt++;
3116 break;
3117
3118 case 15:
3119 swstats->tx_list_proc_err_cnt++;
3120 break;
3121 }
3122 }
3123
3124 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3125 if (skb == NULL) {
3126 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3127 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3128 __func__);
3129 return;
3130 }
3131 pkt_cnt++;
3132
3133 /* Updating the statistics block */
3134 nic->dev->stats.tx_bytes += skb->len;
3135 swstats->mem_freed += skb->truesize;
3136 dev_kfree_skb_irq(skb);
3137
3138 get_info.offset++;
3139 if (get_info.offset == get_info.fifo_len + 1)
3140 get_info.offset = 0;
3141 txdlp = (struct TxD *)
3142 fifo_data->list_info[get_info.offset].list_virt_addr;
3143 fifo_data->tx_curr_get_info.offset = get_info.offset;
3144 }
3145
3146 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3147
3148 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3149 }
3150
3151 /**
3152 * s2io_mdio_write - Function to write in to MDIO registers
3153 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3154 * @addr : address value
3155 * @value : data value
3156 * @dev : pointer to net_device structure
3157 * Description:
3158 * This function is used to write values to the MDIO registers
3159 * NONE
3160 */
3161 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3162 struct net_device *dev)
3163 {
3164 u64 val64;
3165 struct s2io_nic *sp = netdev_priv(dev);
3166 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3167
3168 /* address transaction */
3169 val64 = MDIO_MMD_INDX_ADDR(addr) |
3170 MDIO_MMD_DEV_ADDR(mmd_type) |
3171 MDIO_MMS_PRT_ADDR(0x0);
3172 writeq(val64, &bar0->mdio_control);
3173 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3174 writeq(val64, &bar0->mdio_control);
3175 udelay(100);
3176
3177 /* Data transaction */
3178 val64 = MDIO_MMD_INDX_ADDR(addr) |
3179 MDIO_MMD_DEV_ADDR(mmd_type) |
3180 MDIO_MMS_PRT_ADDR(0x0) |
3181 MDIO_MDIO_DATA(value) |
3182 MDIO_OP(MDIO_OP_WRITE_TRANS);
3183 writeq(val64, &bar0->mdio_control);
3184 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3185 writeq(val64, &bar0->mdio_control);
3186 udelay(100);
3187
3188 val64 = MDIO_MMD_INDX_ADDR(addr) |
3189 MDIO_MMD_DEV_ADDR(mmd_type) |
3190 MDIO_MMS_PRT_ADDR(0x0) |
3191 MDIO_OP(MDIO_OP_READ_TRANS);
3192 writeq(val64, &bar0->mdio_control);
3193 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3194 writeq(val64, &bar0->mdio_control);
3195 udelay(100);
3196 }
3197
3198 /**
3199 * s2io_mdio_read - Function to write in to MDIO registers
3200 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3201 * @addr : address value
3202 * @dev : pointer to net_device structure
3203 * Description:
3204 * This function is used to read values to the MDIO registers
3205 * NONE
3206 */
3207 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3208 {
3209 u64 val64 = 0x0;
3210 u64 rval64 = 0x0;
3211 struct s2io_nic *sp = netdev_priv(dev);
3212 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3213
3214 /* address transaction */
3215 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3216 | MDIO_MMD_DEV_ADDR(mmd_type)
3217 | MDIO_MMS_PRT_ADDR(0x0));
3218 writeq(val64, &bar0->mdio_control);
3219 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3220 writeq(val64, &bar0->mdio_control);
3221 udelay(100);
3222
3223 /* Data transaction */
3224 val64 = MDIO_MMD_INDX_ADDR(addr) |
3225 MDIO_MMD_DEV_ADDR(mmd_type) |
3226 MDIO_MMS_PRT_ADDR(0x0) |
3227 MDIO_OP(MDIO_OP_READ_TRANS);
3228 writeq(val64, &bar0->mdio_control);
3229 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3230 writeq(val64, &bar0->mdio_control);
3231 udelay(100);
3232
3233 /* Read the value from regs */
3234 rval64 = readq(&bar0->mdio_control);
3235 rval64 = rval64 & 0xFFFF0000;
3236 rval64 = rval64 >> 16;
3237 return rval64;
3238 }
3239
3240 /**
3241 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3242 * @counter : counter value to be updated
3243 * @flag : flag to indicate the status
3244 * @type : counter type
3245 * Description:
3246 * This function is to check the status of the xpak counters value
3247 * NONE
3248 */
3249
3250 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3251 u16 flag, u16 type)
3252 {
3253 u64 mask = 0x3;
3254 u64 val64;
3255 int i;
3256 for (i = 0; i < index; i++)
3257 mask = mask << 0x2;
3258
3259 if (flag > 0) {
3260 *counter = *counter + 1;
3261 val64 = *regs_stat & mask;
3262 val64 = val64 >> (index * 0x2);
3263 val64 = val64 + 1;
3264 if (val64 == 3) {
3265 switch (type) {
3266 case 1:
3267 DBG_PRINT(ERR_DBG,
3268 "Take Xframe NIC out of service.\n");
3269 DBG_PRINT(ERR_DBG,
3270 "Excessive temperatures may result in premature transceiver failure.\n");
3271 break;
3272 case 2:
3273 DBG_PRINT(ERR_DBG,
3274 "Take Xframe NIC out of service.\n");
3275 DBG_PRINT(ERR_DBG,
3276 "Excessive bias currents may indicate imminent laser diode failure.\n");
3277 break;
3278 case 3:
3279 DBG_PRINT(ERR_DBG,
3280 "Take Xframe NIC out of service.\n");
3281 DBG_PRINT(ERR_DBG,
3282 "Excessive laser output power may saturate far-end receiver.\n");
3283 break;
3284 default:
3285 DBG_PRINT(ERR_DBG,
3286 "Incorrect XPAK Alarm type\n");
3287 }
3288 val64 = 0x0;
3289 }
3290 val64 = val64 << (index * 0x2);
3291 *regs_stat = (*regs_stat & (~mask)) | (val64);
3292
3293 } else {
3294 *regs_stat = *regs_stat & (~mask);
3295 }
3296 }
3297
3298 /**
3299 * s2io_updt_xpak_counter - Function to update the xpak counters
3300 * @dev : pointer to net_device struct
3301 * Description:
3302 * This function is to upate the status of the xpak counters value
3303 * NONE
3304 */
3305 static void s2io_updt_xpak_counter(struct net_device *dev)
3306 {
3307 u16 flag = 0x0;
3308 u16 type = 0x0;
3309 u16 val16 = 0x0;
3310 u64 val64 = 0x0;
3311 u64 addr = 0x0;
3312
3313 struct s2io_nic *sp = netdev_priv(dev);
3314 struct stat_block *stats = sp->mac_control.stats_info;
3315 struct xpakStat *xstats = &stats->xpak_stat;
3316
3317 /* Check the communication with the MDIO slave */
3318 addr = MDIO_CTRL1;
3319 val64 = 0x0;
3320 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3321 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3322 DBG_PRINT(ERR_DBG,
3323 "ERR: MDIO slave access failed - Returned %llx\n",
3324 (unsigned long long)val64);
3325 return;
3326 }
3327
3328 /* Check for the expected value of control reg 1 */
3329 if (val64 != MDIO_CTRL1_SPEED10G) {
3330 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3331 "Returned: %llx- Expected: 0x%x\n",
3332 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3333 return;
3334 }
3335
3336 /* Loading the DOM register to MDIO register */
3337 addr = 0xA100;
3338 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3339 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3340
3341 /* Reading the Alarm flags */
3342 addr = 0xA070;
3343 val64 = 0x0;
3344 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3345
3346 flag = CHECKBIT(val64, 0x7);
3347 type = 1;
3348 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3349 &xstats->xpak_regs_stat,
3350 0x0, flag, type);
3351
3352 if (CHECKBIT(val64, 0x6))
3353 xstats->alarm_transceiver_temp_low++;
3354
3355 flag = CHECKBIT(val64, 0x3);
3356 type = 2;
3357 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3358 &xstats->xpak_regs_stat,
3359 0x2, flag, type);
3360
3361 if (CHECKBIT(val64, 0x2))
3362 xstats->alarm_laser_bias_current_low++;
3363
3364 flag = CHECKBIT(val64, 0x1);
3365 type = 3;
3366 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3367 &xstats->xpak_regs_stat,
3368 0x4, flag, type);
3369
3370 if (CHECKBIT(val64, 0x0))
3371 xstats->alarm_laser_output_power_low++;
3372
3373 /* Reading the Warning flags */
3374 addr = 0xA074;
3375 val64 = 0x0;
3376 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3377
3378 if (CHECKBIT(val64, 0x7))
3379 xstats->warn_transceiver_temp_high++;
3380
3381 if (CHECKBIT(val64, 0x6))
3382 xstats->warn_transceiver_temp_low++;
3383
3384 if (CHECKBIT(val64, 0x3))
3385 xstats->warn_laser_bias_current_high++;
3386
3387 if (CHECKBIT(val64, 0x2))
3388 xstats->warn_laser_bias_current_low++;
3389
3390 if (CHECKBIT(val64, 0x1))
3391 xstats->warn_laser_output_power_high++;
3392
3393 if (CHECKBIT(val64, 0x0))
3394 xstats->warn_laser_output_power_low++;
3395 }
3396
3397 /**
3398 * wait_for_cmd_complete - waits for a command to complete.
3399 * @sp : private member of the device structure, which is a pointer to the
3400 * s2io_nic structure.
3401 * Description: Function that waits for a command to Write into RMAC
3402 * ADDR DATA registers to be completed and returns either success or
3403 * error depending on whether the command was complete or not.
3404 * Return value:
3405 * SUCCESS on success and FAILURE on failure.
3406 */
3407
3408 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3409 int bit_state)
3410 {
3411 int ret = FAILURE, cnt = 0, delay = 1;
3412 u64 val64;
3413
3414 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3415 return FAILURE;
3416
3417 do {
3418 val64 = readq(addr);
3419 if (bit_state == S2IO_BIT_RESET) {
3420 if (!(val64 & busy_bit)) {
3421 ret = SUCCESS;
3422 break;
3423 }
3424 } else {
3425 if (val64 & busy_bit) {
3426 ret = SUCCESS;
3427 break;
3428 }
3429 }
3430
3431 if (in_interrupt())
3432 mdelay(delay);
3433 else
3434 msleep(delay);
3435
3436 if (++cnt >= 10)
3437 delay = 50;
3438 } while (cnt < 20);
3439 return ret;
3440 }
3441 /*
3442 * check_pci_device_id - Checks if the device id is supported
3443 * @id : device id
3444 * Description: Function to check if the pci device id is supported by driver.
3445 * Return value: Actual device id if supported else PCI_ANY_ID
3446 */
3447 static u16 check_pci_device_id(u16 id)
3448 {
3449 switch (id) {
3450 case PCI_DEVICE_ID_HERC_WIN:
3451 case PCI_DEVICE_ID_HERC_UNI:
3452 return XFRAME_II_DEVICE;
3453 case PCI_DEVICE_ID_S2IO_UNI:
3454 case PCI_DEVICE_ID_S2IO_WIN:
3455 return XFRAME_I_DEVICE;
3456 default:
3457 return PCI_ANY_ID;
3458 }
3459 }
3460
3461 /**
3462 * s2io_reset - Resets the card.
3463 * @sp : private member of the device structure.
3464 * Description: Function to Reset the card. This function then also
3465 * restores the previously saved PCI configuration space registers as
3466 * the card reset also resets the configuration space.
3467 * Return value:
3468 * void.
3469 */
3470
3471 static void s2io_reset(struct s2io_nic *sp)
3472 {
3473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3474 u64 val64;
3475 u16 subid, pci_cmd;
3476 int i;
3477 u16 val16;
3478 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3479 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3480 struct stat_block *stats;
3481 struct swStat *swstats;
3482
3483 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3484 __func__, pci_name(sp->pdev));
3485
3486 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3487 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3488
3489 val64 = SW_RESET_ALL;
3490 writeq(val64, &bar0->sw_reset);
3491 if (strstr(sp->product_name, "CX4"))
3492 msleep(750);
3493 msleep(250);
3494 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3495
3496 /* Restore the PCI state saved during initialization. */
3497 pci_restore_state(sp->pdev);
3498 pci_save_state(sp->pdev);
3499 pci_read_config_word(sp->pdev, 0x2, &val16);
3500 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3501 break;
3502 msleep(200);
3503 }
3504
3505 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3506 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3507
3508 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3509
3510 s2io_init_pci(sp);
3511
3512 /* Set swapper to enable I/O register access */
3513 s2io_set_swapper(sp);
3514
3515 /* restore mac_addr entries */
3516 do_s2io_restore_unicast_mc(sp);
3517
3518 /* Restore the MSIX table entries from local variables */
3519 restore_xmsi_data(sp);
3520
3521 /* Clear certain PCI/PCI-X fields after reset */
3522 if (sp->device_type == XFRAME_II_DEVICE) {
3523 /* Clear "detected parity error" bit */
3524 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3525
3526 /* Clearing PCIX Ecc status register */
3527 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3528
3529 /* Clearing PCI_STATUS error reflected here */
3530 writeq(s2BIT(62), &bar0->txpic_int_reg);
3531 }
3532
3533 /* Reset device statistics maintained by OS */
3534 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3535
3536 stats = sp->mac_control.stats_info;
3537 swstats = &stats->sw_stat;
3538
3539 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3540 up_cnt = swstats->link_up_cnt;
3541 down_cnt = swstats->link_down_cnt;
3542 up_time = swstats->link_up_time;
3543 down_time = swstats->link_down_time;
3544 reset_cnt = swstats->soft_reset_cnt;
3545 mem_alloc_cnt = swstats->mem_allocated;
3546 mem_free_cnt = swstats->mem_freed;
3547 watchdog_cnt = swstats->watchdog_timer_cnt;
3548
3549 memset(stats, 0, sizeof(struct stat_block));
3550
3551 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3552 swstats->link_up_cnt = up_cnt;
3553 swstats->link_down_cnt = down_cnt;
3554 swstats->link_up_time = up_time;
3555 swstats->link_down_time = down_time;
3556 swstats->soft_reset_cnt = reset_cnt;
3557 swstats->mem_allocated = mem_alloc_cnt;
3558 swstats->mem_freed = mem_free_cnt;
3559 swstats->watchdog_timer_cnt = watchdog_cnt;
3560
3561 /* SXE-002: Configure link and activity LED to turn it off */
3562 subid = sp->pdev->subsystem_device;
3563 if (((subid & 0xFF) >= 0x07) &&
3564 (sp->device_type == XFRAME_I_DEVICE)) {
3565 val64 = readq(&bar0->gpio_control);
3566 val64 |= 0x0000800000000000ULL;
3567 writeq(val64, &bar0->gpio_control);
3568 val64 = 0x0411040400000000ULL;
3569 writeq(val64, (void __iomem *)bar0 + 0x2700);
3570 }
3571
3572 /*
3573 * Clear spurious ECC interrupts that would have occured on
3574 * XFRAME II cards after reset.
3575 */
3576 if (sp->device_type == XFRAME_II_DEVICE) {
3577 val64 = readq(&bar0->pcc_err_reg);
3578 writeq(val64, &bar0->pcc_err_reg);
3579 }
3580
3581 sp->device_enabled_once = false;
3582 }
3583
3584 /**
3585 * s2io_set_swapper - to set the swapper controle on the card
3586 * @sp : private member of the device structure,
3587 * pointer to the s2io_nic structure.
3588 * Description: Function to set the swapper control on the card
3589 * correctly depending on the 'endianness' of the system.
3590 * Return value:
3591 * SUCCESS on success and FAILURE on failure.
3592 */
3593
3594 static int s2io_set_swapper(struct s2io_nic *sp)
3595 {
3596 struct net_device *dev = sp->dev;
3597 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3598 u64 val64, valt, valr;
3599
3600 /*
3601 * Set proper endian settings and verify the same by reading
3602 * the PIF Feed-back register.
3603 */
3604
3605 val64 = readq(&bar0->pif_rd_swapper_fb);
3606 if (val64 != 0x0123456789ABCDEFULL) {
3607 int i = 0;
3608 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3609 0x8100008181000081ULL, /* FE=1, SE=0 */
3610 0x4200004242000042ULL, /* FE=0, SE=1 */
3611 0}; /* FE=0, SE=0 */
3612
3613 while (i < 4) {
3614 writeq(value[i], &bar0->swapper_ctrl);
3615 val64 = readq(&bar0->pif_rd_swapper_fb);
3616 if (val64 == 0x0123456789ABCDEFULL)
3617 break;
3618 i++;
3619 }
3620 if (i == 4) {
3621 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3622 "feedback read %llx\n",
3623 dev->name, (unsigned long long)val64);
3624 return FAILURE;
3625 }
3626 valr = value[i];
3627 } else {
3628 valr = readq(&bar0->swapper_ctrl);
3629 }
3630
3631 valt = 0x0123456789ABCDEFULL;
3632 writeq(valt, &bar0->xmsi_address);
3633 val64 = readq(&bar0->xmsi_address);
3634
3635 if (val64 != valt) {
3636 int i = 0;
3637 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3638 0x0081810000818100ULL, /* FE=1, SE=0 */
3639 0x0042420000424200ULL, /* FE=0, SE=1 */
3640 0}; /* FE=0, SE=0 */
3641
3642 while (i < 4) {
3643 writeq((value[i] | valr), &bar0->swapper_ctrl);
3644 writeq(valt, &bar0->xmsi_address);
3645 val64 = readq(&bar0->xmsi_address);
3646 if (val64 == valt)
3647 break;
3648 i++;
3649 }
3650 if (i == 4) {
3651 unsigned long long x = val64;
3652 DBG_PRINT(ERR_DBG,
3653 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3654 return FAILURE;
3655 }
3656 }
3657 val64 = readq(&bar0->swapper_ctrl);
3658 val64 &= 0xFFFF000000000000ULL;
3659
3660 #ifdef __BIG_ENDIAN
3661 /*
3662 * The device by default set to a big endian format, so a
3663 * big endian driver need not set anything.
3664 */
3665 val64 |= (SWAPPER_CTRL_TXP_FE |
3666 SWAPPER_CTRL_TXP_SE |
3667 SWAPPER_CTRL_TXD_R_FE |
3668 SWAPPER_CTRL_TXD_W_FE |
3669 SWAPPER_CTRL_TXF_R_FE |
3670 SWAPPER_CTRL_RXD_R_FE |
3671 SWAPPER_CTRL_RXD_W_FE |
3672 SWAPPER_CTRL_RXF_W_FE |
3673 SWAPPER_CTRL_XMSI_FE |
3674 SWAPPER_CTRL_STATS_FE |
3675 SWAPPER_CTRL_STATS_SE);
3676 if (sp->config.intr_type == INTA)
3677 val64 |= SWAPPER_CTRL_XMSI_SE;
3678 writeq(val64, &bar0->swapper_ctrl);
3679 #else
3680 /*
3681 * Initially we enable all bits to make it accessible by the
3682 * driver, then we selectively enable only those bits that
3683 * we want to set.
3684 */
3685 val64 |= (SWAPPER_CTRL_TXP_FE |
3686 SWAPPER_CTRL_TXP_SE |
3687 SWAPPER_CTRL_TXD_R_FE |
3688 SWAPPER_CTRL_TXD_R_SE |
3689 SWAPPER_CTRL_TXD_W_FE |
3690 SWAPPER_CTRL_TXD_W_SE |
3691 SWAPPER_CTRL_TXF_R_FE |
3692 SWAPPER_CTRL_RXD_R_FE |
3693 SWAPPER_CTRL_RXD_R_SE |
3694 SWAPPER_CTRL_RXD_W_FE |
3695 SWAPPER_CTRL_RXD_W_SE |
3696 SWAPPER_CTRL_RXF_W_FE |
3697 SWAPPER_CTRL_XMSI_FE |
3698 SWAPPER_CTRL_STATS_FE |
3699 SWAPPER_CTRL_STATS_SE);
3700 if (sp->config.intr_type == INTA)
3701 val64 |= SWAPPER_CTRL_XMSI_SE;
3702 writeq(val64, &bar0->swapper_ctrl);
3703 #endif
3704 val64 = readq(&bar0->swapper_ctrl);
3705
3706 /*
3707 * Verifying if endian settings are accurate by reading a
3708 * feedback register.
3709 */
3710 val64 = readq(&bar0->pif_rd_swapper_fb);
3711 if (val64 != 0x0123456789ABCDEFULL) {
3712 /* Endian settings are incorrect, calls for another dekko. */
3713 DBG_PRINT(ERR_DBG,
3714 "%s: Endian settings are wrong, feedback read %llx\n",
3715 dev->name, (unsigned long long)val64);
3716 return FAILURE;
3717 }
3718
3719 return SUCCESS;
3720 }
3721
3722 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3723 {
3724 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3725 u64 val64;
3726 int ret = 0, cnt = 0;
3727
3728 do {
3729 val64 = readq(&bar0->xmsi_access);
3730 if (!(val64 & s2BIT(15)))
3731 break;
3732 mdelay(1);
3733 cnt++;
3734 } while (cnt < 5);
3735 if (cnt == 5) {
3736 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3737 ret = 1;
3738 }
3739
3740 return ret;
3741 }
3742
3743 static void restore_xmsi_data(struct s2io_nic *nic)
3744 {
3745 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3746 u64 val64;
3747 int i, msix_index;
3748
3749 if (nic->device_type == XFRAME_I_DEVICE)
3750 return;
3751
3752 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3753 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3754 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3755 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3756 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3757 writeq(val64, &bar0->xmsi_access);
3758 if (wait_for_msix_trans(nic, msix_index)) {
3759 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3760 __func__, msix_index);
3761 continue;
3762 }
3763 }
3764 }
3765
3766 static void store_xmsi_data(struct s2io_nic *nic)
3767 {
3768 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3769 u64 val64, addr, data;
3770 int i, msix_index;
3771
3772 if (nic->device_type == XFRAME_I_DEVICE)
3773 return;
3774
3775 /* Store and display */
3776 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3777 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3778 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3779 writeq(val64, &bar0->xmsi_access);
3780 if (wait_for_msix_trans(nic, msix_index)) {
3781 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3782 __func__, msix_index);
3783 continue;
3784 }
3785 addr = readq(&bar0->xmsi_address);
3786 data = readq(&bar0->xmsi_data);
3787 if (addr && data) {
3788 nic->msix_info[i].addr = addr;
3789 nic->msix_info[i].data = data;
3790 }
3791 }
3792 }
3793
3794 static int s2io_enable_msi_x(struct s2io_nic *nic)
3795 {
3796 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3797 u64 rx_mat;
3798 u16 msi_control; /* Temp variable */
3799 int ret, i, j, msix_indx = 1;
3800 int size;
3801 struct stat_block *stats = nic->mac_control.stats_info;
3802 struct swStat *swstats = &stats->sw_stat;
3803
3804 size = nic->num_entries * sizeof(struct msix_entry);
3805 nic->entries = kzalloc(size, GFP_KERNEL);
3806 if (!nic->entries) {
3807 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3808 __func__);
3809 swstats->mem_alloc_fail_cnt++;
3810 return -ENOMEM;
3811 }
3812 swstats->mem_allocated += size;
3813
3814 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3815 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3816 if (!nic->s2io_entries) {
3817 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3818 __func__);
3819 swstats->mem_alloc_fail_cnt++;
3820 kfree(nic->entries);
3821 swstats->mem_freed
3822 += (nic->num_entries * sizeof(struct msix_entry));
3823 return -ENOMEM;
3824 }
3825 swstats->mem_allocated += size;
3826
3827 nic->entries[0].entry = 0;
3828 nic->s2io_entries[0].entry = 0;
3829 nic->s2io_entries[0].in_use = MSIX_FLG;
3830 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3831 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3832
3833 for (i = 1; i < nic->num_entries; i++) {
3834 nic->entries[i].entry = ((i - 1) * 8) + 1;
3835 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3836 nic->s2io_entries[i].arg = NULL;
3837 nic->s2io_entries[i].in_use = 0;
3838 }
3839
3840 rx_mat = readq(&bar0->rx_mat);
3841 for (j = 0; j < nic->config.rx_ring_num; j++) {
3842 rx_mat |= RX_MAT_SET(j, msix_indx);
3843 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3844 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3845 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3846 msix_indx += 8;
3847 }
3848 writeq(rx_mat, &bar0->rx_mat);
3849 readq(&bar0->rx_mat);
3850
3851 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3852 /* We fail init if error or we get less vectors than min required */
3853 if (ret) {
3854 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3855 kfree(nic->entries);
3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct msix_entry);
3858 kfree(nic->s2io_entries);
3859 swstats->mem_freed += nic->num_entries *
3860 sizeof(struct s2io_msix_entry);
3861 nic->entries = NULL;
3862 nic->s2io_entries = NULL;
3863 return -ENOMEM;
3864 }
3865
3866 /*
3867 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3868 * in the herc NIC. (Temp change, needs to be removed later)
3869 */
3870 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3871 msi_control |= 0x1; /* Enable MSI */
3872 pci_write_config_word(nic->pdev, 0x42, msi_control);
3873
3874 return 0;
3875 }
3876
3877 /* Handle software interrupt used during MSI(X) test */
3878 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3879 {
3880 struct s2io_nic *sp = dev_id;
3881
3882 sp->msi_detected = 1;
3883 wake_up(&sp->msi_wait);
3884
3885 return IRQ_HANDLED;
3886 }
3887
3888 /* Test interrupt path by forcing a a software IRQ */
3889 static int s2io_test_msi(struct s2io_nic *sp)
3890 {
3891 struct pci_dev *pdev = sp->pdev;
3892 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3893 int err;
3894 u64 val64, saved64;
3895
3896 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3897 sp->name, sp);
3898 if (err) {
3899 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3900 sp->dev->name, pci_name(pdev), pdev->irq);
3901 return err;
3902 }
3903
3904 init_waitqueue_head(&sp->msi_wait);
3905 sp->msi_detected = 0;
3906
3907 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3908 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3909 val64 |= SCHED_INT_CTRL_TIMER_EN;
3910 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3911 writeq(val64, &bar0->scheduled_int_ctrl);
3912
3913 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3914
3915 if (!sp->msi_detected) {
3916 /* MSI(X) test failed, go back to INTx mode */
3917 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3918 "using MSI(X) during test\n",
3919 sp->dev->name, pci_name(pdev));
3920
3921 err = -EOPNOTSUPP;
3922 }
3923
3924 free_irq(sp->entries[1].vector, sp);
3925
3926 writeq(saved64, &bar0->scheduled_int_ctrl);
3927
3928 return err;
3929 }
3930
3931 static void remove_msix_isr(struct s2io_nic *sp)
3932 {
3933 int i;
3934 u16 msi_control;
3935
3936 for (i = 0; i < sp->num_entries; i++) {
3937 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3938 int vector = sp->entries[i].vector;
3939 void *arg = sp->s2io_entries[i].arg;
3940 free_irq(vector, arg);
3941 }
3942 }
3943
3944 kfree(sp->entries);
3945 kfree(sp->s2io_entries);
3946 sp->entries = NULL;
3947 sp->s2io_entries = NULL;
3948
3949 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3950 msi_control &= 0xFFFE; /* Disable MSI */
3951 pci_write_config_word(sp->pdev, 0x42, msi_control);
3952
3953 pci_disable_msix(sp->pdev);
3954 }
3955
3956 static void remove_inta_isr(struct s2io_nic *sp)
3957 {
3958 struct net_device *dev = sp->dev;
3959
3960 free_irq(sp->pdev->irq, dev);
3961 }
3962
3963 /* ********************************************************* *
3964 * Functions defined below concern the OS part of the driver *
3965 * ********************************************************* */
3966
3967 /**
3968 * s2io_open - open entry point of the driver
3969 * @dev : pointer to the device structure.
3970 * Description:
3971 * This function is the open entry point of the driver. It mainly calls a
3972 * function to allocate Rx buffers and inserts them into the buffer
3973 * descriptors and then enables the Rx part of the NIC.
3974 * Return value:
3975 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3976 * file on failure.
3977 */
3978
3979 static int s2io_open(struct net_device *dev)
3980 {
3981 struct s2io_nic *sp = netdev_priv(dev);
3982 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3983 int err = 0;
3984
3985 /*
3986 * Make sure you have link off by default every time
3987 * Nic is initialized
3988 */
3989 netif_carrier_off(dev);
3990 sp->last_link_state = 0;
3991
3992 /* Initialize H/W and enable interrupts */
3993 err = s2io_card_up(sp);
3994 if (err) {
3995 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3996 dev->name);
3997 goto hw_init_failed;
3998 }
3999
4000 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4001 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4002 s2io_card_down(sp);
4003 err = -ENODEV;
4004 goto hw_init_failed;
4005 }
4006 s2io_start_all_tx_queue(sp);
4007 return 0;
4008
4009 hw_init_failed:
4010 if (sp->config.intr_type == MSI_X) {
4011 if (sp->entries) {
4012 kfree(sp->entries);
4013 swstats->mem_freed += sp->num_entries *
4014 sizeof(struct msix_entry);
4015 }
4016 if (sp->s2io_entries) {
4017 kfree(sp->s2io_entries);
4018 swstats->mem_freed += sp->num_entries *
4019 sizeof(struct s2io_msix_entry);
4020 }
4021 }
4022 return err;
4023 }
4024
4025 /**
4026 * s2io_close -close entry point of the driver
4027 * @dev : device pointer.
4028 * Description:
4029 * This is the stop entry point of the driver. It needs to undo exactly
4030 * whatever was done by the open entry point,thus it's usually referred to
4031 * as the close function.Among other things this function mainly stops the
4032 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4033 * Return value:
4034 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4035 * file on failure.
4036 */
4037
4038 static int s2io_close(struct net_device *dev)
4039 {
4040 struct s2io_nic *sp = netdev_priv(dev);
4041 struct config_param *config = &sp->config;
4042 u64 tmp64;
4043 int offset;
4044
4045 /* Return if the device is already closed *
4046 * Can happen when s2io_card_up failed in change_mtu *
4047 */
4048 if (!is_s2io_card_up(sp))
4049 return 0;
4050
4051 s2io_stop_all_tx_queue(sp);
4052 /* delete all populated mac entries */
4053 for (offset = 1; offset < config->max_mc_addr; offset++) {
4054 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4055 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4056 do_s2io_delete_unicast_mc(sp, tmp64);
4057 }
4058
4059 s2io_card_down(sp);
4060
4061 return 0;
4062 }
4063
4064 /**
4065 * s2io_xmit - Tx entry point of te driver
4066 * @skb : the socket buffer containing the Tx data.
4067 * @dev : device pointer.
4068 * Description :
4069 * This function is the Tx entry point of the driver. S2IO NIC supports
4070 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4071 * NOTE: when device cant queue the pkt,just the trans_start variable will
4072 * not be upadted.
4073 * Return value:
4074 * 0 on success & 1 on failure.
4075 */
4076
4077 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4078 {
4079 struct s2io_nic *sp = netdev_priv(dev);
4080 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4081 register u64 val64;
4082 struct TxD *txdp;
4083 struct TxFIFO_element __iomem *tx_fifo;
4084 unsigned long flags = 0;
4085 u16 vlan_tag = 0;
4086 struct fifo_info *fifo = NULL;
4087 int do_spin_lock = 1;
4088 int offload_type;
4089 int enable_per_list_interrupt = 0;
4090 struct config_param *config = &sp->config;
4091 struct mac_info *mac_control = &sp->mac_control;
4092 struct stat_block *stats = mac_control->stats_info;
4093 struct swStat *swstats = &stats->sw_stat;
4094
4095 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4096
4097 if (unlikely(skb->len <= 0)) {
4098 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4099 dev_kfree_skb_any(skb);
4100 return NETDEV_TX_OK;
4101 }
4102
4103 if (!is_s2io_card_up(sp)) {
4104 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4105 dev->name);
4106 dev_kfree_skb(skb);
4107 return NETDEV_TX_OK;
4108 }
4109
4110 queue = 0;
4111 if (sp->vlgrp && vlan_tx_tag_present(skb))
4112 vlan_tag = vlan_tx_tag_get(skb);
4113 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4114 if (skb->protocol == htons(ETH_P_IP)) {
4115 struct iphdr *ip;
4116 struct tcphdr *th;
4117 ip = ip_hdr(skb);
4118
4119 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4120 th = (struct tcphdr *)(((unsigned char *)ip) +
4121 ip->ihl*4);
4122
4123 if (ip->protocol == IPPROTO_TCP) {
4124 queue_len = sp->total_tcp_fifos;
4125 queue = (ntohs(th->source) +
4126 ntohs(th->dest)) &
4127 sp->fifo_selector[queue_len - 1];
4128 if (queue >= queue_len)
4129 queue = queue_len - 1;
4130 } else if (ip->protocol == IPPROTO_UDP) {
4131 queue_len = sp->total_udp_fifos;
4132 queue = (ntohs(th->source) +
4133 ntohs(th->dest)) &
4134 sp->fifo_selector[queue_len - 1];
4135 if (queue >= queue_len)
4136 queue = queue_len - 1;
4137 queue += sp->udp_fifo_idx;
4138 if (skb->len > 1024)
4139 enable_per_list_interrupt = 1;
4140 do_spin_lock = 0;
4141 }
4142 }
4143 }
4144 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4145 /* get fifo number based on skb->priority value */
4146 queue = config->fifo_mapping
4147 [skb->priority & (MAX_TX_FIFOS - 1)];
4148 fifo = &mac_control->fifos[queue];
4149
4150 if (do_spin_lock)
4151 spin_lock_irqsave(&fifo->tx_lock, flags);
4152 else {
4153 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4154 return NETDEV_TX_LOCKED;
4155 }
4156
4157 if (sp->config.multiq) {
4158 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4159 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4160 return NETDEV_TX_BUSY;
4161 }
4162 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4163 if (netif_queue_stopped(dev)) {
4164 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4165 return NETDEV_TX_BUSY;
4166 }
4167 }
4168
4169 put_off = (u16)fifo->tx_curr_put_info.offset;
4170 get_off = (u16)fifo->tx_curr_get_info.offset;
4171 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4172
4173 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4174 /* Avoid "put" pointer going beyond "get" pointer */
4175 if (txdp->Host_Control ||
4176 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4177 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4178 s2io_stop_tx_queue(sp, fifo->fifo_no);
4179 dev_kfree_skb(skb);
4180 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4181 return NETDEV_TX_OK;
4182 }
4183
4184 offload_type = s2io_offload_type(skb);
4185 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4186 txdp->Control_1 |= TXD_TCP_LSO_EN;
4187 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4188 }
4189 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4190 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4191 TXD_TX_CKO_TCP_EN |
4192 TXD_TX_CKO_UDP_EN);
4193 }
4194 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4195 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4196 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4197 if (enable_per_list_interrupt)
4198 if (put_off & (queue_len >> 5))
4199 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4200 if (vlan_tag) {
4201 txdp->Control_2 |= TXD_VLAN_ENABLE;
4202 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4203 }
4204
4205 frg_len = skb->len - skb->data_len;
4206 if (offload_type == SKB_GSO_UDP) {
4207 int ufo_size;
4208
4209 ufo_size = s2io_udp_mss(skb);
4210 ufo_size &= ~7;
4211 txdp->Control_1 |= TXD_UFO_EN;
4212 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4213 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4214 #ifdef __BIG_ENDIAN
4215 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4216 fifo->ufo_in_band_v[put_off] =
4217 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4218 #else
4219 fifo->ufo_in_band_v[put_off] =
4220 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4221 #endif
4222 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4223 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4224 fifo->ufo_in_band_v,
4225 sizeof(u64),
4226 PCI_DMA_TODEVICE);
4227 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4228 goto pci_map_failed;
4229 txdp++;
4230 }
4231
4232 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4233 frg_len, PCI_DMA_TODEVICE);
4234 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4235 goto pci_map_failed;
4236
4237 txdp->Host_Control = (unsigned long)skb;
4238 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4239 if (offload_type == SKB_GSO_UDP)
4240 txdp->Control_1 |= TXD_UFO_EN;
4241
4242 frg_cnt = skb_shinfo(skb)->nr_frags;
4243 /* For fragmented SKB. */
4244 for (i = 0; i < frg_cnt; i++) {
4245 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4246 /* A '0' length fragment will be ignored */
4247 if (!frag->size)
4248 continue;
4249 txdp++;
4250 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4251 frag->page_offset,
4252 frag->size,
4253 PCI_DMA_TODEVICE);
4254 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4255 if (offload_type == SKB_GSO_UDP)
4256 txdp->Control_1 |= TXD_UFO_EN;
4257 }
4258 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4259
4260 if (offload_type == SKB_GSO_UDP)
4261 frg_cnt++; /* as Txd0 was used for inband header */
4262
4263 tx_fifo = mac_control->tx_FIFO_start[queue];
4264 val64 = fifo->list_info[put_off].list_phy_addr;
4265 writeq(val64, &tx_fifo->TxDL_Pointer);
4266
4267 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4268 TX_FIFO_LAST_LIST);
4269 if (offload_type)
4270 val64 |= TX_FIFO_SPECIAL_FUNC;
4271
4272 writeq(val64, &tx_fifo->List_Control);
4273
4274 mmiowb();
4275
4276 put_off++;
4277 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4278 put_off = 0;
4279 fifo->tx_curr_put_info.offset = put_off;
4280
4281 /* Avoid "put" pointer going beyond "get" pointer */
4282 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4283 swstats->fifo_full_cnt++;
4284 DBG_PRINT(TX_DBG,
4285 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4286 put_off, get_off);
4287 s2io_stop_tx_queue(sp, fifo->fifo_no);
4288 }
4289 swstats->mem_allocated += skb->truesize;
4290 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4291
4292 if (sp->config.intr_type == MSI_X)
4293 tx_intr_handler(fifo);
4294
4295 return NETDEV_TX_OK;
4296
4297 pci_map_failed:
4298 swstats->pci_map_fail_cnt++;
4299 s2io_stop_tx_queue(sp, fifo->fifo_no);
4300 swstats->mem_freed += skb->truesize;
4301 dev_kfree_skb(skb);
4302 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4303 return NETDEV_TX_OK;
4304 }
4305
4306 static void
4307 s2io_alarm_handle(unsigned long data)
4308 {
4309 struct s2io_nic *sp = (struct s2io_nic *)data;
4310 struct net_device *dev = sp->dev;
4311
4312 s2io_handle_errors(dev);
4313 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4314 }
4315
4316 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4317 {
4318 struct ring_info *ring = (struct ring_info *)dev_id;
4319 struct s2io_nic *sp = ring->nic;
4320 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4321
4322 if (unlikely(!is_s2io_card_up(sp)))
4323 return IRQ_HANDLED;
4324
4325 if (sp->config.napi) {
4326 u8 __iomem *addr = NULL;
4327 u8 val8 = 0;
4328
4329 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4330 addr += (7 - ring->ring_no);
4331 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4332 writeb(val8, addr);
4333 val8 = readb(addr);
4334 napi_schedule(&ring->napi);
4335 } else {
4336 rx_intr_handler(ring, 0);
4337 s2io_chk_rx_buffers(sp, ring);
4338 }
4339
4340 return IRQ_HANDLED;
4341 }
4342
4343 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4344 {
4345 int i;
4346 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4347 struct s2io_nic *sp = fifos->nic;
4348 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4349 struct config_param *config = &sp->config;
4350 u64 reason;
4351
4352 if (unlikely(!is_s2io_card_up(sp)))
4353 return IRQ_NONE;
4354
4355 reason = readq(&bar0->general_int_status);
4356 if (unlikely(reason == S2IO_MINUS_ONE))
4357 /* Nothing much can be done. Get out */
4358 return IRQ_HANDLED;
4359
4360 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4361 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4362
4363 if (reason & GEN_INTR_TXPIC)
4364 s2io_txpic_intr_handle(sp);
4365
4366 if (reason & GEN_INTR_TXTRAFFIC)
4367 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4368
4369 for (i = 0; i < config->tx_fifo_num; i++)
4370 tx_intr_handler(&fifos[i]);
4371
4372 writeq(sp->general_int_mask, &bar0->general_int_mask);
4373 readl(&bar0->general_int_status);
4374 return IRQ_HANDLED;
4375 }
4376 /* The interrupt was not raised by us */
4377 return IRQ_NONE;
4378 }
4379
4380 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4381 {
4382 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4383 u64 val64;
4384
4385 val64 = readq(&bar0->pic_int_status);
4386 if (val64 & PIC_INT_GPIO) {
4387 val64 = readq(&bar0->gpio_int_reg);
4388 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4389 (val64 & GPIO_INT_REG_LINK_UP)) {
4390 /*
4391 * This is unstable state so clear both up/down
4392 * interrupt and adapter to re-evaluate the link state.
4393 */
4394 val64 |= GPIO_INT_REG_LINK_DOWN;
4395 val64 |= GPIO_INT_REG_LINK_UP;
4396 writeq(val64, &bar0->gpio_int_reg);
4397 val64 = readq(&bar0->gpio_int_mask);
4398 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4399 GPIO_INT_MASK_LINK_DOWN);
4400 writeq(val64, &bar0->gpio_int_mask);
4401 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4402 val64 = readq(&bar0->adapter_status);
4403 /* Enable Adapter */
4404 val64 = readq(&bar0->adapter_control);
4405 val64 |= ADAPTER_CNTL_EN;
4406 writeq(val64, &bar0->adapter_control);
4407 val64 |= ADAPTER_LED_ON;
4408 writeq(val64, &bar0->adapter_control);
4409 if (!sp->device_enabled_once)
4410 sp->device_enabled_once = 1;
4411
4412 s2io_link(sp, LINK_UP);
4413 /*
4414 * unmask link down interrupt and mask link-up
4415 * intr
4416 */
4417 val64 = readq(&bar0->gpio_int_mask);
4418 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4419 val64 |= GPIO_INT_MASK_LINK_UP;
4420 writeq(val64, &bar0->gpio_int_mask);
4421
4422 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4423 val64 = readq(&bar0->adapter_status);
4424 s2io_link(sp, LINK_DOWN);
4425 /* Link is down so unmaks link up interrupt */
4426 val64 = readq(&bar0->gpio_int_mask);
4427 val64 &= ~GPIO_INT_MASK_LINK_UP;
4428 val64 |= GPIO_INT_MASK_LINK_DOWN;
4429 writeq(val64, &bar0->gpio_int_mask);
4430
4431 /* turn off LED */
4432 val64 = readq(&bar0->adapter_control);
4433 val64 = val64 & (~ADAPTER_LED_ON);
4434 writeq(val64, &bar0->adapter_control);
4435 }
4436 }
4437 val64 = readq(&bar0->gpio_int_mask);
4438 }
4439
4440 /**
4441 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4442 * @value: alarm bits
4443 * @addr: address value
4444 * @cnt: counter variable
4445 * Description: Check for alarm and increment the counter
4446 * Return Value:
4447 * 1 - if alarm bit set
4448 * 0 - if alarm bit is not set
4449 */
4450 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4451 unsigned long long *cnt)
4452 {
4453 u64 val64;
4454 val64 = readq(addr);
4455 if (val64 & value) {
4456 writeq(val64, addr);
4457 (*cnt)++;
4458 return 1;
4459 }
4460 return 0;
4461
4462 }
4463
4464 /**
4465 * s2io_handle_errors - Xframe error indication handler
4466 * @nic: device private variable
4467 * Description: Handle alarms such as loss of link, single or
4468 * double ECC errors, critical and serious errors.
4469 * Return Value:
4470 * NONE
4471 */
4472 static void s2io_handle_errors(void *dev_id)
4473 {
4474 struct net_device *dev = (struct net_device *)dev_id;
4475 struct s2io_nic *sp = netdev_priv(dev);
4476 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4477 u64 temp64 = 0, val64 = 0;
4478 int i = 0;
4479
4480 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4481 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4482
4483 if (!is_s2io_card_up(sp))
4484 return;
4485
4486 if (pci_channel_offline(sp->pdev))
4487 return;
4488
4489 memset(&sw_stat->ring_full_cnt, 0,
4490 sizeof(sw_stat->ring_full_cnt));
4491
4492 /* Handling the XPAK counters update */
4493 if (stats->xpak_timer_count < 72000) {
4494 /* waiting for an hour */
4495 stats->xpak_timer_count++;
4496 } else {
4497 s2io_updt_xpak_counter(dev);
4498 /* reset the count to zero */
4499 stats->xpak_timer_count = 0;
4500 }
4501
4502 /* Handling link status change error Intr */
4503 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4504 val64 = readq(&bar0->mac_rmac_err_reg);
4505 writeq(val64, &bar0->mac_rmac_err_reg);
4506 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4507 schedule_work(&sp->set_link_task);
4508 }
4509
4510 /* In case of a serious error, the device will be Reset. */
4511 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4512 &sw_stat->serious_err_cnt))
4513 goto reset;
4514
4515 /* Check for data parity error */
4516 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4517 &sw_stat->parity_err_cnt))
4518 goto reset;
4519
4520 /* Check for ring full counter */
4521 if (sp->device_type == XFRAME_II_DEVICE) {
4522 val64 = readq(&bar0->ring_bump_counter1);
4523 for (i = 0; i < 4; i++) {
4524 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4525 temp64 >>= 64 - ((i+1)*16);
4526 sw_stat->ring_full_cnt[i] += temp64;
4527 }
4528
4529 val64 = readq(&bar0->ring_bump_counter2);
4530 for (i = 0; i < 4; i++) {
4531 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4532 temp64 >>= 64 - ((i+1)*16);
4533 sw_stat->ring_full_cnt[i+4] += temp64;
4534 }
4535 }
4536
4537 val64 = readq(&bar0->txdma_int_status);
4538 /*check for pfc_err*/
4539 if (val64 & TXDMA_PFC_INT) {
4540 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4541 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4542 PFC_PCIX_ERR,
4543 &bar0->pfc_err_reg,
4544 &sw_stat->pfc_err_cnt))
4545 goto reset;
4546 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4547 &bar0->pfc_err_reg,
4548 &sw_stat->pfc_err_cnt);
4549 }
4550
4551 /*check for tda_err*/
4552 if (val64 & TXDMA_TDA_INT) {
4553 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4554 TDA_SM0_ERR_ALARM |
4555 TDA_SM1_ERR_ALARM,
4556 &bar0->tda_err_reg,
4557 &sw_stat->tda_err_cnt))
4558 goto reset;
4559 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4560 &bar0->tda_err_reg,
4561 &sw_stat->tda_err_cnt);
4562 }
4563 /*check for pcc_err*/
4564 if (val64 & TXDMA_PCC_INT) {
4565 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4566 PCC_N_SERR | PCC_6_COF_OV_ERR |
4567 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4568 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4569 PCC_TXB_ECC_DB_ERR,
4570 &bar0->pcc_err_reg,
4571 &sw_stat->pcc_err_cnt))
4572 goto reset;
4573 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4574 &bar0->pcc_err_reg,
4575 &sw_stat->pcc_err_cnt);
4576 }
4577
4578 /*check for tti_err*/
4579 if (val64 & TXDMA_TTI_INT) {
4580 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4581 &bar0->tti_err_reg,
4582 &sw_stat->tti_err_cnt))
4583 goto reset;
4584 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4585 &bar0->tti_err_reg,
4586 &sw_stat->tti_err_cnt);
4587 }
4588
4589 /*check for lso_err*/
4590 if (val64 & TXDMA_LSO_INT) {
4591 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4592 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4593 &bar0->lso_err_reg,
4594 &sw_stat->lso_err_cnt))
4595 goto reset;
4596 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4597 &bar0->lso_err_reg,
4598 &sw_stat->lso_err_cnt);
4599 }
4600
4601 /*check for tpa_err*/
4602 if (val64 & TXDMA_TPA_INT) {
4603 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4604 &bar0->tpa_err_reg,
4605 &sw_stat->tpa_err_cnt))
4606 goto reset;
4607 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4608 &bar0->tpa_err_reg,
4609 &sw_stat->tpa_err_cnt);
4610 }
4611
4612 /*check for sm_err*/
4613 if (val64 & TXDMA_SM_INT) {
4614 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4615 &bar0->sm_err_reg,
4616 &sw_stat->sm_err_cnt))
4617 goto reset;
4618 }
4619
4620 val64 = readq(&bar0->mac_int_status);
4621 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4622 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4623 &bar0->mac_tmac_err_reg,
4624 &sw_stat->mac_tmac_err_cnt))
4625 goto reset;
4626 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4627 TMAC_DESC_ECC_SG_ERR |
4628 TMAC_DESC_ECC_DB_ERR,
4629 &bar0->mac_tmac_err_reg,
4630 &sw_stat->mac_tmac_err_cnt);
4631 }
4632
4633 val64 = readq(&bar0->xgxs_int_status);
4634 if (val64 & XGXS_INT_STATUS_TXGXS) {
4635 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4636 &bar0->xgxs_txgxs_err_reg,
4637 &sw_stat->xgxs_txgxs_err_cnt))
4638 goto reset;
4639 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4640 &bar0->xgxs_txgxs_err_reg,
4641 &sw_stat->xgxs_txgxs_err_cnt);
4642 }
4643
4644 val64 = readq(&bar0->rxdma_int_status);
4645 if (val64 & RXDMA_INT_RC_INT_M) {
4646 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4647 RC_FTC_ECC_DB_ERR |
4648 RC_PRCn_SM_ERR_ALARM |
4649 RC_FTC_SM_ERR_ALARM,
4650 &bar0->rc_err_reg,
4651 &sw_stat->rc_err_cnt))
4652 goto reset;
4653 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4654 RC_FTC_ECC_SG_ERR |
4655 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4656 &sw_stat->rc_err_cnt);
4657 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4658 PRC_PCI_AB_WR_Rn |
4659 PRC_PCI_AB_F_WR_Rn,
4660 &bar0->prc_pcix_err_reg,
4661 &sw_stat->prc_pcix_err_cnt))
4662 goto reset;
4663 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4664 PRC_PCI_DP_WR_Rn |
4665 PRC_PCI_DP_F_WR_Rn,
4666 &bar0->prc_pcix_err_reg,
4667 &sw_stat->prc_pcix_err_cnt);
4668 }
4669
4670 if (val64 & RXDMA_INT_RPA_INT_M) {
4671 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4672 &bar0->rpa_err_reg,
4673 &sw_stat->rpa_err_cnt))
4674 goto reset;
4675 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4676 &bar0->rpa_err_reg,
4677 &sw_stat->rpa_err_cnt);
4678 }
4679
4680 if (val64 & RXDMA_INT_RDA_INT_M) {
4681 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4682 RDA_FRM_ECC_DB_N_AERR |
4683 RDA_SM1_ERR_ALARM |
4684 RDA_SM0_ERR_ALARM |
4685 RDA_RXD_ECC_DB_SERR,
4686 &bar0->rda_err_reg,
4687 &sw_stat->rda_err_cnt))
4688 goto reset;
4689 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4690 RDA_FRM_ECC_SG_ERR |
4691 RDA_MISC_ERR |
4692 RDA_PCIX_ERR,
4693 &bar0->rda_err_reg,
4694 &sw_stat->rda_err_cnt);
4695 }
4696
4697 if (val64 & RXDMA_INT_RTI_INT_M) {
4698 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4699 &bar0->rti_err_reg,
4700 &sw_stat->rti_err_cnt))
4701 goto reset;
4702 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4703 &bar0->rti_err_reg,
4704 &sw_stat->rti_err_cnt);
4705 }
4706
4707 val64 = readq(&bar0->mac_int_status);
4708 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4709 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4710 &bar0->mac_rmac_err_reg,
4711 &sw_stat->mac_rmac_err_cnt))
4712 goto reset;
4713 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4714 RMAC_SINGLE_ECC_ERR |
4715 RMAC_DOUBLE_ECC_ERR,
4716 &bar0->mac_rmac_err_reg,
4717 &sw_stat->mac_rmac_err_cnt);
4718 }
4719
4720 val64 = readq(&bar0->xgxs_int_status);
4721 if (val64 & XGXS_INT_STATUS_RXGXS) {
4722 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4723 &bar0->xgxs_rxgxs_err_reg,
4724 &sw_stat->xgxs_rxgxs_err_cnt))
4725 goto reset;
4726 }
4727
4728 val64 = readq(&bar0->mc_int_status);
4729 if (val64 & MC_INT_STATUS_MC_INT) {
4730 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4731 &bar0->mc_err_reg,
4732 &sw_stat->mc_err_cnt))
4733 goto reset;
4734
4735 /* Handling Ecc errors */
4736 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4737 writeq(val64, &bar0->mc_err_reg);
4738 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4739 sw_stat->double_ecc_errs++;
4740 if (sp->device_type != XFRAME_II_DEVICE) {
4741 /*
4742 * Reset XframeI only if critical error
4743 */
4744 if (val64 &
4745 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4746 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4747 goto reset;
4748 }
4749 } else
4750 sw_stat->single_ecc_errs++;
4751 }
4752 }
4753 return;
4754
4755 reset:
4756 s2io_stop_all_tx_queue(sp);
4757 schedule_work(&sp->rst_timer_task);
4758 sw_stat->soft_reset_cnt++;
4759 return;
4760 }
4761
4762 /**
4763 * s2io_isr - ISR handler of the device .
4764 * @irq: the irq of the device.
4765 * @dev_id: a void pointer to the dev structure of the NIC.
4766 * Description: This function is the ISR handler of the device. It
4767 * identifies the reason for the interrupt and calls the relevant
4768 * service routines. As a contongency measure, this ISR allocates the
4769 * recv buffers, if their numbers are below the panic value which is
4770 * presently set to 25% of the original number of rcv buffers allocated.
4771 * Return value:
4772 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4773 * IRQ_NONE: will be returned if interrupt is not from our device
4774 */
4775 static irqreturn_t s2io_isr(int irq, void *dev_id)
4776 {
4777 struct net_device *dev = (struct net_device *)dev_id;
4778 struct s2io_nic *sp = netdev_priv(dev);
4779 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4780 int i;
4781 u64 reason = 0;
4782 struct mac_info *mac_control;
4783 struct config_param *config;
4784
4785 /* Pretend we handled any irq's from a disconnected card */
4786 if (pci_channel_offline(sp->pdev))
4787 return IRQ_NONE;
4788
4789 if (!is_s2io_card_up(sp))
4790 return IRQ_NONE;
4791
4792 config = &sp->config;
4793 mac_control = &sp->mac_control;
4794
4795 /*
4796 * Identify the cause for interrupt and call the appropriate
4797 * interrupt handler. Causes for the interrupt could be;
4798 * 1. Rx of packet.
4799 * 2. Tx complete.
4800 * 3. Link down.
4801 */
4802 reason = readq(&bar0->general_int_status);
4803
4804 if (unlikely(reason == S2IO_MINUS_ONE))
4805 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4806
4807 if (reason &
4808 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4809 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4810
4811 if (config->napi) {
4812 if (reason & GEN_INTR_RXTRAFFIC) {
4813 napi_schedule(&sp->napi);
4814 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4815 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4816 readl(&bar0->rx_traffic_int);
4817 }
4818 } else {
4819 /*
4820 * rx_traffic_int reg is an R1 register, writing all 1's
4821 * will ensure that the actual interrupt causing bit
4822 * get's cleared and hence a read can be avoided.
4823 */
4824 if (reason & GEN_INTR_RXTRAFFIC)
4825 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4826
4827 for (i = 0; i < config->rx_ring_num; i++) {
4828 struct ring_info *ring = &mac_control->rings[i];
4829
4830 rx_intr_handler(ring, 0);
4831 }
4832 }
4833
4834 /*
4835 * tx_traffic_int reg is an R1 register, writing all 1's
4836 * will ensure that the actual interrupt causing bit get's
4837 * cleared and hence a read can be avoided.
4838 */
4839 if (reason & GEN_INTR_TXTRAFFIC)
4840 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4841
4842 for (i = 0; i < config->tx_fifo_num; i++)
4843 tx_intr_handler(&mac_control->fifos[i]);
4844
4845 if (reason & GEN_INTR_TXPIC)
4846 s2io_txpic_intr_handle(sp);
4847
4848 /*
4849 * Reallocate the buffers from the interrupt handler itself.
4850 */
4851 if (!config->napi) {
4852 for (i = 0; i < config->rx_ring_num; i++) {
4853 struct ring_info *ring = &mac_control->rings[i];
4854
4855 s2io_chk_rx_buffers(sp, ring);
4856 }
4857 }
4858 writeq(sp->general_int_mask, &bar0->general_int_mask);
4859 readl(&bar0->general_int_status);
4860
4861 return IRQ_HANDLED;
4862
4863 } else if (!reason) {
4864 /* The interrupt was not raised by us */
4865 return IRQ_NONE;
4866 }
4867
4868 return IRQ_HANDLED;
4869 }
4870
4871 /**
4872 * s2io_updt_stats -
4873 */
4874 static void s2io_updt_stats(struct s2io_nic *sp)
4875 {
4876 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4877 u64 val64;
4878 int cnt = 0;
4879
4880 if (is_s2io_card_up(sp)) {
4881 /* Apprx 30us on a 133 MHz bus */
4882 val64 = SET_UPDT_CLICKS(10) |
4883 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4884 writeq(val64, &bar0->stat_cfg);
4885 do {
4886 udelay(100);
4887 val64 = readq(&bar0->stat_cfg);
4888 if (!(val64 & s2BIT(0)))
4889 break;
4890 cnt++;
4891 if (cnt == 5)
4892 break; /* Updt failed */
4893 } while (1);
4894 }
4895 }
4896
4897 /**
4898 * s2io_get_stats - Updates the device statistics structure.
4899 * @dev : pointer to the device structure.
4900 * Description:
4901 * This function updates the device statistics structure in the s2io_nic
4902 * structure and returns a pointer to the same.
4903 * Return value:
4904 * pointer to the updated net_device_stats structure.
4905 */
4906
4907 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4908 {
4909 struct s2io_nic *sp = netdev_priv(dev);
4910 struct config_param *config = &sp->config;
4911 struct mac_info *mac_control = &sp->mac_control;
4912 struct stat_block *stats = mac_control->stats_info;
4913 int i;
4914
4915 /* Configure Stats for immediate updt */
4916 s2io_updt_stats(sp);
4917
4918 /* Using sp->stats as a staging area, because reset (due to mtu
4919 change, for example) will clear some hardware counters */
4920 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
4921 sp->stats.tx_packets;
4922 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4923
4924 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
4925 sp->stats.tx_errors;
4926 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4927
4928 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
4929 sp->stats.rx_errors;
4930 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4931
4932 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
4933 sp->stats.multicast;
4934 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4935
4936 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
4937 sp->stats.rx_length_errors;
4938 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
4939
4940 /* collect per-ring rx_packets and rx_bytes */
4941 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4942 for (i = 0; i < config->rx_ring_num; i++) {
4943 struct ring_info *ring = &mac_control->rings[i];
4944
4945 dev->stats.rx_packets += ring->rx_packets;
4946 dev->stats.rx_bytes += ring->rx_bytes;
4947 }
4948
4949 return &dev->stats;
4950 }
4951
4952 /**
4953 * s2io_set_multicast - entry point for multicast address enable/disable.
4954 * @dev : pointer to the device structure
4955 * Description:
4956 * This function is a driver entry point which gets called by the kernel
4957 * whenever multicast addresses must be enabled/disabled. This also gets
4958 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4959 * determine, if multicast address must be enabled or if promiscuous mode
4960 * is to be disabled etc.
4961 * Return value:
4962 * void.
4963 */
4964
4965 static void s2io_set_multicast(struct net_device *dev)
4966 {
4967 int i, j, prev_cnt;
4968 struct dev_mc_list *mclist;
4969 struct s2io_nic *sp = netdev_priv(dev);
4970 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4971 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4972 0xfeffffffffffULL;
4973 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4974 void __iomem *add;
4975 struct config_param *config = &sp->config;
4976
4977 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4978 /* Enable all Multicast addresses */
4979 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4980 &bar0->rmac_addr_data0_mem);
4981 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4982 &bar0->rmac_addr_data1_mem);
4983 val64 = RMAC_ADDR_CMD_MEM_WE |
4984 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4985 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4986 writeq(val64, &bar0->rmac_addr_cmd_mem);
4987 /* Wait till command completes */
4988 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4989 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4990 S2IO_BIT_RESET);
4991
4992 sp->m_cast_flg = 1;
4993 sp->all_multi_pos = config->max_mc_addr - 1;
4994 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4995 /* Disable all Multicast addresses */
4996 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4997 &bar0->rmac_addr_data0_mem);
4998 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4999 &bar0->rmac_addr_data1_mem);
5000 val64 = RMAC_ADDR_CMD_MEM_WE |
5001 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5002 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5003 writeq(val64, &bar0->rmac_addr_cmd_mem);
5004 /* Wait till command completes */
5005 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5006 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5007 S2IO_BIT_RESET);
5008
5009 sp->m_cast_flg = 0;
5010 sp->all_multi_pos = 0;
5011 }
5012
5013 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5014 /* Put the NIC into promiscuous mode */
5015 add = &bar0->mac_cfg;
5016 val64 = readq(&bar0->mac_cfg);
5017 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5018
5019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020 writel((u32)val64, add);
5021 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5022 writel((u32) (val64 >> 32), (add + 4));
5023
5024 if (vlan_tag_strip != 1) {
5025 val64 = readq(&bar0->rx_pa_cfg);
5026 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5027 writeq(val64, &bar0->rx_pa_cfg);
5028 sp->vlan_strip_flag = 0;
5029 }
5030
5031 val64 = readq(&bar0->mac_cfg);
5032 sp->promisc_flg = 1;
5033 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5034 dev->name);
5035 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5036 /* Remove the NIC from promiscuous mode */
5037 add = &bar0->mac_cfg;
5038 val64 = readq(&bar0->mac_cfg);
5039 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5040
5041 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5042 writel((u32)val64, add);
5043 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5044 writel((u32) (val64 >> 32), (add + 4));
5045
5046 if (vlan_tag_strip != 0) {
5047 val64 = readq(&bar0->rx_pa_cfg);
5048 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5049 writeq(val64, &bar0->rx_pa_cfg);
5050 sp->vlan_strip_flag = 1;
5051 }
5052
5053 val64 = readq(&bar0->mac_cfg);
5054 sp->promisc_flg = 0;
5055 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5056 }
5057
5058 /* Update individual M_CAST address list */
5059 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5060 if (netdev_mc_count(dev) >
5061 (config->max_mc_addr - config->max_mac_addr)) {
5062 DBG_PRINT(ERR_DBG,
5063 "%s: No more Rx filters can be added - "
5064 "please enable ALL_MULTI instead\n",
5065 dev->name);
5066 return;
5067 }
5068
5069 prev_cnt = sp->mc_addr_count;
5070 sp->mc_addr_count = netdev_mc_count(dev);
5071
5072 /* Clear out the previous list of Mc in the H/W. */
5073 for (i = 0; i < prev_cnt; i++) {
5074 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5075 &bar0->rmac_addr_data0_mem);
5076 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5077 &bar0->rmac_addr_data1_mem);
5078 val64 = RMAC_ADDR_CMD_MEM_WE |
5079 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5080 RMAC_ADDR_CMD_MEM_OFFSET
5081 (config->mc_start_offset + i);
5082 writeq(val64, &bar0->rmac_addr_cmd_mem);
5083
5084 /* Wait for command completes */
5085 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5086 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5087 S2IO_BIT_RESET)) {
5088 DBG_PRINT(ERR_DBG,
5089 "%s: Adding Multicasts failed\n",
5090 dev->name);
5091 return;
5092 }
5093 }
5094
5095 /* Create the new Rx filter list and update the same in H/W. */
5096 i = 0;
5097 netdev_for_each_mc_addr(mclist, dev) {
5098 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5099 ETH_ALEN);
5100 mac_addr = 0;
5101 for (j = 0; j < ETH_ALEN; j++) {
5102 mac_addr |= mclist->dmi_addr[j];
5103 mac_addr <<= 8;
5104 }
5105 mac_addr >>= 8;
5106 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5107 &bar0->rmac_addr_data0_mem);
5108 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5109 &bar0->rmac_addr_data1_mem);
5110 val64 = RMAC_ADDR_CMD_MEM_WE |
5111 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5112 RMAC_ADDR_CMD_MEM_OFFSET
5113 (i + config->mc_start_offset);
5114 writeq(val64, &bar0->rmac_addr_cmd_mem);
5115
5116 /* Wait for command completes */
5117 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5118 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5119 S2IO_BIT_RESET)) {
5120 DBG_PRINT(ERR_DBG,
5121 "%s: Adding Multicasts failed\n",
5122 dev->name);
5123 return;
5124 }
5125 i++;
5126 }
5127 }
5128 }
5129
5130 /* read from CAM unicast & multicast addresses and store it in
5131 * def_mac_addr structure
5132 */
5133 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5134 {
5135 int offset;
5136 u64 mac_addr = 0x0;
5137 struct config_param *config = &sp->config;
5138
5139 /* store unicast & multicast mac addresses */
5140 for (offset = 0; offset < config->max_mc_addr; offset++) {
5141 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5142 /* if read fails disable the entry */
5143 if (mac_addr == FAILURE)
5144 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5145 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5146 }
5147 }
5148
5149 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5150 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5151 {
5152 int offset;
5153 struct config_param *config = &sp->config;
5154 /* restore unicast mac address */
5155 for (offset = 0; offset < config->max_mac_addr; offset++)
5156 do_s2io_prog_unicast(sp->dev,
5157 sp->def_mac_addr[offset].mac_addr);
5158
5159 /* restore multicast mac address */
5160 for (offset = config->mc_start_offset;
5161 offset < config->max_mc_addr; offset++)
5162 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5163 }
5164
5165 /* add a multicast MAC address to CAM */
5166 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5167 {
5168 int i;
5169 u64 mac_addr = 0;
5170 struct config_param *config = &sp->config;
5171
5172 for (i = 0; i < ETH_ALEN; i++) {
5173 mac_addr <<= 8;
5174 mac_addr |= addr[i];
5175 }
5176 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5177 return SUCCESS;
5178
5179 /* check if the multicast mac already preset in CAM */
5180 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5181 u64 tmp64;
5182 tmp64 = do_s2io_read_unicast_mc(sp, i);
5183 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5184 break;
5185
5186 if (tmp64 == mac_addr)
5187 return SUCCESS;
5188 }
5189 if (i == config->max_mc_addr) {
5190 DBG_PRINT(ERR_DBG,
5191 "CAM full no space left for multicast MAC\n");
5192 return FAILURE;
5193 }
5194 /* Update the internal structure with this new mac address */
5195 do_s2io_copy_mac_addr(sp, i, mac_addr);
5196
5197 return do_s2io_add_mac(sp, mac_addr, i);
5198 }
5199
5200 /* add MAC address to CAM */
5201 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5202 {
5203 u64 val64;
5204 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5205
5206 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5207 &bar0->rmac_addr_data0_mem);
5208
5209 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5210 RMAC_ADDR_CMD_MEM_OFFSET(off);
5211 writeq(val64, &bar0->rmac_addr_cmd_mem);
5212
5213 /* Wait till command completes */
5214 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5215 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5216 S2IO_BIT_RESET)) {
5217 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5218 return FAILURE;
5219 }
5220 return SUCCESS;
5221 }
5222 /* deletes a specified unicast/multicast mac entry from CAM */
5223 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5224 {
5225 int offset;
5226 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5227 struct config_param *config = &sp->config;
5228
5229 for (offset = 1;
5230 offset < config->max_mc_addr; offset++) {
5231 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5232 if (tmp64 == addr) {
5233 /* disable the entry by writing 0xffffffffffffULL */
5234 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5235 return FAILURE;
5236 /* store the new mac list from CAM */
5237 do_s2io_store_unicast_mc(sp);
5238 return SUCCESS;
5239 }
5240 }
5241 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5242 (unsigned long long)addr);
5243 return FAILURE;
5244 }
5245
5246 /* read mac entries from CAM */
5247 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5248 {
5249 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5251
5252 /* read mac addr */
5253 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5254 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5255 writeq(val64, &bar0->rmac_addr_cmd_mem);
5256
5257 /* Wait till command completes */
5258 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5259 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5260 S2IO_BIT_RESET)) {
5261 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5262 return FAILURE;
5263 }
5264 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5265
5266 return tmp64 >> 16;
5267 }
5268
5269 /**
5270 * s2io_set_mac_addr driver entry point
5271 */
5272
5273 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5274 {
5275 struct sockaddr *addr = p;
5276
5277 if (!is_valid_ether_addr(addr->sa_data))
5278 return -EINVAL;
5279
5280 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5281
5282 /* store the MAC address in CAM */
5283 return do_s2io_prog_unicast(dev, dev->dev_addr);
5284 }
5285 /**
5286 * do_s2io_prog_unicast - Programs the Xframe mac address
5287 * @dev : pointer to the device structure.
5288 * @addr: a uchar pointer to the new mac address which is to be set.
5289 * Description : This procedure will program the Xframe to receive
5290 * frames with new Mac Address
5291 * Return value: SUCCESS on success and an appropriate (-)ve integer
5292 * as defined in errno.h file on failure.
5293 */
5294
5295 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5296 {
5297 struct s2io_nic *sp = netdev_priv(dev);
5298 register u64 mac_addr = 0, perm_addr = 0;
5299 int i;
5300 u64 tmp64;
5301 struct config_param *config = &sp->config;
5302
5303 /*
5304 * Set the new MAC address as the new unicast filter and reflect this
5305 * change on the device address registered with the OS. It will be
5306 * at offset 0.
5307 */
5308 for (i = 0; i < ETH_ALEN; i++) {
5309 mac_addr <<= 8;
5310 mac_addr |= addr[i];
5311 perm_addr <<= 8;
5312 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5313 }
5314
5315 /* check if the dev_addr is different than perm_addr */
5316 if (mac_addr == perm_addr)
5317 return SUCCESS;
5318
5319 /* check if the mac already preset in CAM */
5320 for (i = 1; i < config->max_mac_addr; i++) {
5321 tmp64 = do_s2io_read_unicast_mc(sp, i);
5322 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5323 break;
5324
5325 if (tmp64 == mac_addr) {
5326 DBG_PRINT(INFO_DBG,
5327 "MAC addr:0x%llx already present in CAM\n",
5328 (unsigned long long)mac_addr);
5329 return SUCCESS;
5330 }
5331 }
5332 if (i == config->max_mac_addr) {
5333 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5334 return FAILURE;
5335 }
5336 /* Update the internal structure with this new mac address */
5337 do_s2io_copy_mac_addr(sp, i, mac_addr);
5338
5339 return do_s2io_add_mac(sp, mac_addr, i);
5340 }
5341
5342 /**
5343 * s2io_ethtool_sset - Sets different link parameters.
5344 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5345 * @info: pointer to the structure with parameters given by ethtool to set
5346 * link information.
5347 * Description:
5348 * The function sets different link parameters provided by the user onto
5349 * the NIC.
5350 * Return value:
5351 * 0 on success.
5352 */
5353
5354 static int s2io_ethtool_sset(struct net_device *dev,
5355 struct ethtool_cmd *info)
5356 {
5357 struct s2io_nic *sp = netdev_priv(dev);
5358 if ((info->autoneg == AUTONEG_ENABLE) ||
5359 (info->speed != SPEED_10000) ||
5360 (info->duplex != DUPLEX_FULL))
5361 return -EINVAL;
5362 else {
5363 s2io_close(sp->dev);
5364 s2io_open(sp->dev);
5365 }
5366
5367 return 0;
5368 }
5369
5370 /**
5371 * s2io_ethtol_gset - Return link specific information.
5372 * @sp : private member of the device structure, pointer to the
5373 * s2io_nic structure.
5374 * @info : pointer to the structure with parameters given by ethtool
5375 * to return link information.
5376 * Description:
5377 * Returns link specific information like speed, duplex etc.. to ethtool.
5378 * Return value :
5379 * return 0 on success.
5380 */
5381
5382 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5383 {
5384 struct s2io_nic *sp = netdev_priv(dev);
5385 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5386 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5387 info->port = PORT_FIBRE;
5388
5389 /* info->transceiver */
5390 info->transceiver = XCVR_EXTERNAL;
5391
5392 if (netif_carrier_ok(sp->dev)) {
5393 info->speed = 10000;
5394 info->duplex = DUPLEX_FULL;
5395 } else {
5396 info->speed = -1;
5397 info->duplex = -1;
5398 }
5399
5400 info->autoneg = AUTONEG_DISABLE;
5401 return 0;
5402 }
5403
5404 /**
5405 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5406 * @sp : private member of the device structure, which is a pointer to the
5407 * s2io_nic structure.
5408 * @info : pointer to the structure with parameters given by ethtool to
5409 * return driver information.
5410 * Description:
5411 * Returns driver specefic information like name, version etc.. to ethtool.
5412 * Return value:
5413 * void
5414 */
5415
5416 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5417 struct ethtool_drvinfo *info)
5418 {
5419 struct s2io_nic *sp = netdev_priv(dev);
5420
5421 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5422 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5423 strncpy(info->fw_version, "", sizeof(info->fw_version));
5424 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5425 info->regdump_len = XENA_REG_SPACE;
5426 info->eedump_len = XENA_EEPROM_SPACE;
5427 }
5428
5429 /**
5430 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5431 * @sp: private member of the device structure, which is a pointer to the
5432 * s2io_nic structure.
5433 * @regs : pointer to the structure with parameters given by ethtool for
5434 * dumping the registers.
5435 * @reg_space: The input argumnet into which all the registers are dumped.
5436 * Description:
5437 * Dumps the entire register space of xFrame NIC into the user given
5438 * buffer area.
5439 * Return value :
5440 * void .
5441 */
5442
5443 static void s2io_ethtool_gregs(struct net_device *dev,
5444 struct ethtool_regs *regs, void *space)
5445 {
5446 int i;
5447 u64 reg;
5448 u8 *reg_space = (u8 *)space;
5449 struct s2io_nic *sp = netdev_priv(dev);
5450
5451 regs->len = XENA_REG_SPACE;
5452 regs->version = sp->pdev->subsystem_device;
5453
5454 for (i = 0; i < regs->len; i += 8) {
5455 reg = readq(sp->bar0 + i);
5456 memcpy((reg_space + i), &reg, 8);
5457 }
5458 }
5459
5460 /**
5461 * s2io_phy_id - timer function that alternates adapter LED.
5462 * @data : address of the private member of the device structure, which
5463 * is a pointer to the s2io_nic structure, provided as an u32.
5464 * Description: This is actually the timer function that alternates the
5465 * adapter LED bit of the adapter control bit to set/reset every time on
5466 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5467 * once every second.
5468 */
5469 static void s2io_phy_id(unsigned long data)
5470 {
5471 struct s2io_nic *sp = (struct s2io_nic *)data;
5472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5473 u64 val64 = 0;
5474 u16 subid;
5475
5476 subid = sp->pdev->subsystem_device;
5477 if ((sp->device_type == XFRAME_II_DEVICE) ||
5478 ((subid & 0xFF) >= 0x07)) {
5479 val64 = readq(&bar0->gpio_control);
5480 val64 ^= GPIO_CTRL_GPIO_0;
5481 writeq(val64, &bar0->gpio_control);
5482 } else {
5483 val64 = readq(&bar0->adapter_control);
5484 val64 ^= ADAPTER_LED_ON;
5485 writeq(val64, &bar0->adapter_control);
5486 }
5487
5488 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5489 }
5490
5491 /**
5492 * s2io_ethtool_idnic - To physically identify the nic on the system.
5493 * @sp : private member of the device structure, which is a pointer to the
5494 * s2io_nic structure.
5495 * @id : pointer to the structure with identification parameters given by
5496 * ethtool.
5497 * Description: Used to physically identify the NIC on the system.
5498 * The Link LED will blink for a time specified by the user for
5499 * identification.
5500 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5501 * identification is possible only if it's link is up.
5502 * Return value:
5503 * int , returns 0 on success
5504 */
5505
5506 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5507 {
5508 u64 val64 = 0, last_gpio_ctrl_val;
5509 struct s2io_nic *sp = netdev_priv(dev);
5510 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5511 u16 subid;
5512
5513 subid = sp->pdev->subsystem_device;
5514 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5515 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5516 val64 = readq(&bar0->adapter_control);
5517 if (!(val64 & ADAPTER_CNTL_EN)) {
5518 pr_err("Adapter Link down, cannot blink LED\n");
5519 return -EFAULT;
5520 }
5521 }
5522 if (sp->id_timer.function == NULL) {
5523 init_timer(&sp->id_timer);
5524 sp->id_timer.function = s2io_phy_id;
5525 sp->id_timer.data = (unsigned long)sp;
5526 }
5527 mod_timer(&sp->id_timer, jiffies);
5528 if (data)
5529 msleep_interruptible(data * HZ);
5530 else
5531 msleep_interruptible(MAX_FLICKER_TIME);
5532 del_timer_sync(&sp->id_timer);
5533
5534 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5535 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5536 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5537 }
5538
5539 return 0;
5540 }
5541
5542 static void s2io_ethtool_gringparam(struct net_device *dev,
5543 struct ethtool_ringparam *ering)
5544 {
5545 struct s2io_nic *sp = netdev_priv(dev);
5546 int i, tx_desc_count = 0, rx_desc_count = 0;
5547
5548 if (sp->rxd_mode == RXD_MODE_1)
5549 ering->rx_max_pending = MAX_RX_DESC_1;
5550 else if (sp->rxd_mode == RXD_MODE_3B)
5551 ering->rx_max_pending = MAX_RX_DESC_2;
5552
5553 ering->tx_max_pending = MAX_TX_DESC;
5554 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5555 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5556
5557 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5558 ering->tx_pending = tx_desc_count;
5559 rx_desc_count = 0;
5560 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5561 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5562
5563 ering->rx_pending = rx_desc_count;
5564
5565 ering->rx_mini_max_pending = 0;
5566 ering->rx_mini_pending = 0;
5567 if (sp->rxd_mode == RXD_MODE_1)
5568 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5569 else if (sp->rxd_mode == RXD_MODE_3B)
5570 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5571 ering->rx_jumbo_pending = rx_desc_count;
5572 }
5573
5574 /**
5575 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5576 * @sp : private member of the device structure, which is a pointer to the
5577 * s2io_nic structure.
5578 * @ep : pointer to the structure with pause parameters given by ethtool.
5579 * Description:
5580 * Returns the Pause frame generation and reception capability of the NIC.
5581 * Return value:
5582 * void
5583 */
5584 static void s2io_ethtool_getpause_data(struct net_device *dev,
5585 struct ethtool_pauseparam *ep)
5586 {
5587 u64 val64;
5588 struct s2io_nic *sp = netdev_priv(dev);
5589 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5590
5591 val64 = readq(&bar0->rmac_pause_cfg);
5592 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5593 ep->tx_pause = true;
5594 if (val64 & RMAC_PAUSE_RX_ENABLE)
5595 ep->rx_pause = true;
5596 ep->autoneg = false;
5597 }
5598
5599 /**
5600 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5601 * @sp : private member of the device structure, which is a pointer to the
5602 * s2io_nic structure.
5603 * @ep : pointer to the structure with pause parameters given by ethtool.
5604 * Description:
5605 * It can be used to set or reset Pause frame generation or reception
5606 * support of the NIC.
5607 * Return value:
5608 * int, returns 0 on Success
5609 */
5610
5611 static int s2io_ethtool_setpause_data(struct net_device *dev,
5612 struct ethtool_pauseparam *ep)
5613 {
5614 u64 val64;
5615 struct s2io_nic *sp = netdev_priv(dev);
5616 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5617
5618 val64 = readq(&bar0->rmac_pause_cfg);
5619 if (ep->tx_pause)
5620 val64 |= RMAC_PAUSE_GEN_ENABLE;
5621 else
5622 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5623 if (ep->rx_pause)
5624 val64 |= RMAC_PAUSE_RX_ENABLE;
5625 else
5626 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5627 writeq(val64, &bar0->rmac_pause_cfg);
5628 return 0;
5629 }
5630
5631 /**
5632 * read_eeprom - reads 4 bytes of data from user given offset.
5633 * @sp : private member of the device structure, which is a pointer to the
5634 * s2io_nic structure.
5635 * @off : offset at which the data must be written
5636 * @data : Its an output parameter where the data read at the given
5637 * offset is stored.
5638 * Description:
5639 * Will read 4 bytes of data from the user given offset and return the
5640 * read data.
5641 * NOTE: Will allow to read only part of the EEPROM visible through the
5642 * I2C bus.
5643 * Return value:
5644 * -1 on failure and 0 on success.
5645 */
5646
5647 #define S2IO_DEV_ID 5
5648 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5649 {
5650 int ret = -1;
5651 u32 exit_cnt = 0;
5652 u64 val64;
5653 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5654
5655 if (sp->device_type == XFRAME_I_DEVICE) {
5656 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5657 I2C_CONTROL_ADDR(off) |
5658 I2C_CONTROL_BYTE_CNT(0x3) |
5659 I2C_CONTROL_READ |
5660 I2C_CONTROL_CNTL_START;
5661 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5662
5663 while (exit_cnt < 5) {
5664 val64 = readq(&bar0->i2c_control);
5665 if (I2C_CONTROL_CNTL_END(val64)) {
5666 *data = I2C_CONTROL_GET_DATA(val64);
5667 ret = 0;
5668 break;
5669 }
5670 msleep(50);
5671 exit_cnt++;
5672 }
5673 }
5674
5675 if (sp->device_type == XFRAME_II_DEVICE) {
5676 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5677 SPI_CONTROL_BYTECNT(0x3) |
5678 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5679 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5680 val64 |= SPI_CONTROL_REQ;
5681 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5682 while (exit_cnt < 5) {
5683 val64 = readq(&bar0->spi_control);
5684 if (val64 & SPI_CONTROL_NACK) {
5685 ret = 1;
5686 break;
5687 } else if (val64 & SPI_CONTROL_DONE) {
5688 *data = readq(&bar0->spi_data);
5689 *data &= 0xffffff;
5690 ret = 0;
5691 break;
5692 }
5693 msleep(50);
5694 exit_cnt++;
5695 }
5696 }
5697 return ret;
5698 }
5699
5700 /**
5701 * write_eeprom - actually writes the relevant part of the data value.
5702 * @sp : private member of the device structure, which is a pointer to the
5703 * s2io_nic structure.
5704 * @off : offset at which the data must be written
5705 * @data : The data that is to be written
5706 * @cnt : Number of bytes of the data that are actually to be written into
5707 * the Eeprom. (max of 3)
5708 * Description:
5709 * Actually writes the relevant part of the data value into the Eeprom
5710 * through the I2C bus.
5711 * Return value:
5712 * 0 on success, -1 on failure.
5713 */
5714
5715 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5716 {
5717 int exit_cnt = 0, ret = -1;
5718 u64 val64;
5719 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5720
5721 if (sp->device_type == XFRAME_I_DEVICE) {
5722 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5723 I2C_CONTROL_ADDR(off) |
5724 I2C_CONTROL_BYTE_CNT(cnt) |
5725 I2C_CONTROL_SET_DATA((u32)data) |
5726 I2C_CONTROL_CNTL_START;
5727 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5728
5729 while (exit_cnt < 5) {
5730 val64 = readq(&bar0->i2c_control);
5731 if (I2C_CONTROL_CNTL_END(val64)) {
5732 if (!(val64 & I2C_CONTROL_NACK))
5733 ret = 0;
5734 break;
5735 }
5736 msleep(50);
5737 exit_cnt++;
5738 }
5739 }
5740
5741 if (sp->device_type == XFRAME_II_DEVICE) {
5742 int write_cnt = (cnt == 8) ? 0 : cnt;
5743 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5744
5745 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5746 SPI_CONTROL_BYTECNT(write_cnt) |
5747 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5748 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5749 val64 |= SPI_CONTROL_REQ;
5750 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5751 while (exit_cnt < 5) {
5752 val64 = readq(&bar0->spi_control);
5753 if (val64 & SPI_CONTROL_NACK) {
5754 ret = 1;
5755 break;
5756 } else if (val64 & SPI_CONTROL_DONE) {
5757 ret = 0;
5758 break;
5759 }
5760 msleep(50);
5761 exit_cnt++;
5762 }
5763 }
5764 return ret;
5765 }
5766 static void s2io_vpd_read(struct s2io_nic *nic)
5767 {
5768 u8 *vpd_data;
5769 u8 data;
5770 int i = 0, cnt, fail = 0;
5771 int vpd_addr = 0x80;
5772 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5773
5774 if (nic->device_type == XFRAME_II_DEVICE) {
5775 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5776 vpd_addr = 0x80;
5777 } else {
5778 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5779 vpd_addr = 0x50;
5780 }
5781 strcpy(nic->serial_num, "NOT AVAILABLE");
5782
5783 vpd_data = kmalloc(256, GFP_KERNEL);
5784 if (!vpd_data) {
5785 swstats->mem_alloc_fail_cnt++;
5786 return;
5787 }
5788 swstats->mem_allocated += 256;
5789
5790 for (i = 0; i < 256; i += 4) {
5791 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5792 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5793 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5794 for (cnt = 0; cnt < 5; cnt++) {
5795 msleep(2);
5796 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5797 if (data == 0x80)
5798 break;
5799 }
5800 if (cnt >= 5) {
5801 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5802 fail = 1;
5803 break;
5804 }
5805 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5806 (u32 *)&vpd_data[i]);
5807 }
5808
5809 if (!fail) {
5810 /* read serial number of adapter */
5811 for (cnt = 0; cnt < 256; cnt++) {
5812 if ((vpd_data[cnt] == 'S') &&
5813 (vpd_data[cnt+1] == 'N') &&
5814 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5815 memset(nic->serial_num, 0, VPD_STRING_LEN);
5816 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5817 vpd_data[cnt+2]);
5818 break;
5819 }
5820 }
5821 }
5822
5823 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
5824 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5825 kfree(vpd_data);
5826 swstats->mem_freed += 256;
5827 }
5828
5829 /**
5830 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5831 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5832 * @eeprom : pointer to the user level structure provided by ethtool,
5833 * containing all relevant information.
5834 * @data_buf : user defined value to be written into Eeprom.
5835 * Description: Reads the values stored in the Eeprom at given offset
5836 * for a given length. Stores these values int the input argument data
5837 * buffer 'data_buf' and returns these to the caller (ethtool.)
5838 * Return value:
5839 * int 0 on success
5840 */
5841
5842 static int s2io_ethtool_geeprom(struct net_device *dev,
5843 struct ethtool_eeprom *eeprom, u8 * data_buf)
5844 {
5845 u32 i, valid;
5846 u64 data;
5847 struct s2io_nic *sp = netdev_priv(dev);
5848
5849 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5850
5851 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5852 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5853
5854 for (i = 0; i < eeprom->len; i += 4) {
5855 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5856 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5857 return -EFAULT;
5858 }
5859 valid = INV(data);
5860 memcpy((data_buf + i), &valid, 4);
5861 }
5862 return 0;
5863 }
5864
5865 /**
5866 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5867 * @sp : private member of the device structure, which is a pointer to the
5868 * s2io_nic structure.
5869 * @eeprom : pointer to the user level structure provided by ethtool,
5870 * containing all relevant information.
5871 * @data_buf ; user defined value to be written into Eeprom.
5872 * Description:
5873 * Tries to write the user provided value in the Eeprom, at the offset
5874 * given by the user.
5875 * Return value:
5876 * 0 on success, -EFAULT on failure.
5877 */
5878
5879 static int s2io_ethtool_seeprom(struct net_device *dev,
5880 struct ethtool_eeprom *eeprom,
5881 u8 *data_buf)
5882 {
5883 int len = eeprom->len, cnt = 0;
5884 u64 valid = 0, data;
5885 struct s2io_nic *sp = netdev_priv(dev);
5886
5887 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5888 DBG_PRINT(ERR_DBG,
5889 "ETHTOOL_WRITE_EEPROM Err: "
5890 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5891 (sp->pdev->vendor | (sp->pdev->device << 16)),
5892 eeprom->magic);
5893 return -EFAULT;
5894 }
5895
5896 while (len) {
5897 data = (u32)data_buf[cnt] & 0x000000FF;
5898 if (data)
5899 valid = (u32)(data << 24);
5900 else
5901 valid = data;
5902
5903 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5904 DBG_PRINT(ERR_DBG,
5905 "ETHTOOL_WRITE_EEPROM Err: "
5906 "Cannot write into the specified offset\n");
5907 return -EFAULT;
5908 }
5909 cnt++;
5910 len--;
5911 }
5912
5913 return 0;
5914 }
5915
5916 /**
5917 * s2io_register_test - reads and writes into all clock domains.
5918 * @sp : private member of the device structure, which is a pointer to the
5919 * s2io_nic structure.
5920 * @data : variable that returns the result of each of the test conducted b
5921 * by the driver.
5922 * Description:
5923 * Read and write into all clock domains. The NIC has 3 clock domains,
5924 * see that registers in all the three regions are accessible.
5925 * Return value:
5926 * 0 on success.
5927 */
5928
5929 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5930 {
5931 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5932 u64 val64 = 0, exp_val;
5933 int fail = 0;
5934
5935 val64 = readq(&bar0->pif_rd_swapper_fb);
5936 if (val64 != 0x123456789abcdefULL) {
5937 fail = 1;
5938 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5939 }
5940
5941 val64 = readq(&bar0->rmac_pause_cfg);
5942 if (val64 != 0xc000ffff00000000ULL) {
5943 fail = 1;
5944 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5945 }
5946
5947 val64 = readq(&bar0->rx_queue_cfg);
5948 if (sp->device_type == XFRAME_II_DEVICE)
5949 exp_val = 0x0404040404040404ULL;
5950 else
5951 exp_val = 0x0808080808080808ULL;
5952 if (val64 != exp_val) {
5953 fail = 1;
5954 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5955 }
5956
5957 val64 = readq(&bar0->xgxs_efifo_cfg);
5958 if (val64 != 0x000000001923141EULL) {
5959 fail = 1;
5960 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5961 }
5962
5963 val64 = 0x5A5A5A5A5A5A5A5AULL;
5964 writeq(val64, &bar0->xmsi_data);
5965 val64 = readq(&bar0->xmsi_data);
5966 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5967 fail = 1;
5968 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5969 }
5970
5971 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5972 writeq(val64, &bar0->xmsi_data);
5973 val64 = readq(&bar0->xmsi_data);
5974 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5975 fail = 1;
5976 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5977 }
5978
5979 *data = fail;
5980 return fail;
5981 }
5982
5983 /**
5984 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5985 * @sp : private member of the device structure, which is a pointer to the
5986 * s2io_nic structure.
5987 * @data:variable that returns the result of each of the test conducted by
5988 * the driver.
5989 * Description:
5990 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5991 * register.
5992 * Return value:
5993 * 0 on success.
5994 */
5995
5996 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5997 {
5998 int fail = 0;
5999 u64 ret_data, org_4F0, org_7F0;
6000 u8 saved_4F0 = 0, saved_7F0 = 0;
6001 struct net_device *dev = sp->dev;
6002
6003 /* Test Write Error at offset 0 */
6004 /* Note that SPI interface allows write access to all areas
6005 * of EEPROM. Hence doing all negative testing only for Xframe I.
6006 */
6007 if (sp->device_type == XFRAME_I_DEVICE)
6008 if (!write_eeprom(sp, 0, 0, 3))
6009 fail = 1;
6010
6011 /* Save current values at offsets 0x4F0 and 0x7F0 */
6012 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6013 saved_4F0 = 1;
6014 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6015 saved_7F0 = 1;
6016
6017 /* Test Write at offset 4f0 */
6018 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6019 fail = 1;
6020 if (read_eeprom(sp, 0x4F0, &ret_data))
6021 fail = 1;
6022
6023 if (ret_data != 0x012345) {
6024 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6025 "Data written %llx Data read %llx\n",
6026 dev->name, (unsigned long long)0x12345,
6027 (unsigned long long)ret_data);
6028 fail = 1;
6029 }
6030
6031 /* Reset the EEPROM data go FFFF */
6032 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6033
6034 /* Test Write Request Error at offset 0x7c */
6035 if (sp->device_type == XFRAME_I_DEVICE)
6036 if (!write_eeprom(sp, 0x07C, 0, 3))
6037 fail = 1;
6038
6039 /* Test Write Request at offset 0x7f0 */
6040 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6041 fail = 1;
6042 if (read_eeprom(sp, 0x7F0, &ret_data))
6043 fail = 1;
6044
6045 if (ret_data != 0x012345) {
6046 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6047 "Data written %llx Data read %llx\n",
6048 dev->name, (unsigned long long)0x12345,
6049 (unsigned long long)ret_data);
6050 fail = 1;
6051 }
6052
6053 /* Reset the EEPROM data go FFFF */
6054 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6055
6056 if (sp->device_type == XFRAME_I_DEVICE) {
6057 /* Test Write Error at offset 0x80 */
6058 if (!write_eeprom(sp, 0x080, 0, 3))
6059 fail = 1;
6060
6061 /* Test Write Error at offset 0xfc */
6062 if (!write_eeprom(sp, 0x0FC, 0, 3))
6063 fail = 1;
6064
6065 /* Test Write Error at offset 0x100 */
6066 if (!write_eeprom(sp, 0x100, 0, 3))
6067 fail = 1;
6068
6069 /* Test Write Error at offset 4ec */
6070 if (!write_eeprom(sp, 0x4EC, 0, 3))
6071 fail = 1;
6072 }
6073
6074 /* Restore values at offsets 0x4F0 and 0x7F0 */
6075 if (saved_4F0)
6076 write_eeprom(sp, 0x4F0, org_4F0, 3);
6077 if (saved_7F0)
6078 write_eeprom(sp, 0x7F0, org_7F0, 3);
6079
6080 *data = fail;
6081 return fail;
6082 }
6083
6084 /**
6085 * s2io_bist_test - invokes the MemBist test of the card .
6086 * @sp : private member of the device structure, which is a pointer to the
6087 * s2io_nic structure.
6088 * @data:variable that returns the result of each of the test conducted by
6089 * the driver.
6090 * Description:
6091 * This invokes the MemBist test of the card. We give around
6092 * 2 secs time for the Test to complete. If it's still not complete
6093 * within this peiod, we consider that the test failed.
6094 * Return value:
6095 * 0 on success and -1 on failure.
6096 */
6097
6098 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6099 {
6100 u8 bist = 0;
6101 int cnt = 0, ret = -1;
6102
6103 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6104 bist |= PCI_BIST_START;
6105 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6106
6107 while (cnt < 20) {
6108 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6109 if (!(bist & PCI_BIST_START)) {
6110 *data = (bist & PCI_BIST_CODE_MASK);
6111 ret = 0;
6112 break;
6113 }
6114 msleep(100);
6115 cnt++;
6116 }
6117
6118 return ret;
6119 }
6120
6121 /**
6122 * s2io-link_test - verifies the link state of the nic
6123 * @sp ; private member of the device structure, which is a pointer to the
6124 * s2io_nic structure.
6125 * @data: variable that returns the result of each of the test conducted by
6126 * the driver.
6127 * Description:
6128 * The function verifies the link state of the NIC and updates the input
6129 * argument 'data' appropriately.
6130 * Return value:
6131 * 0 on success.
6132 */
6133
6134 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6135 {
6136 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6137 u64 val64;
6138
6139 val64 = readq(&bar0->adapter_status);
6140 if (!(LINK_IS_UP(val64)))
6141 *data = 1;
6142 else
6143 *data = 0;
6144
6145 return *data;
6146 }
6147
6148 /**
6149 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6150 * @sp - private member of the device structure, which is a pointer to the
6151 * s2io_nic structure.
6152 * @data - variable that returns the result of each of the test
6153 * conducted by the driver.
6154 * Description:
6155 * This is one of the offline test that tests the read and write
6156 * access to the RldRam chip on the NIC.
6157 * Return value:
6158 * 0 on success.
6159 */
6160
6161 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6162 {
6163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6164 u64 val64;
6165 int cnt, iteration = 0, test_fail = 0;
6166
6167 val64 = readq(&bar0->adapter_control);
6168 val64 &= ~ADAPTER_ECC_EN;
6169 writeq(val64, &bar0->adapter_control);
6170
6171 val64 = readq(&bar0->mc_rldram_test_ctrl);
6172 val64 |= MC_RLDRAM_TEST_MODE;
6173 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6174
6175 val64 = readq(&bar0->mc_rldram_mrs);
6176 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6177 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6178
6179 val64 |= MC_RLDRAM_MRS_ENABLE;
6180 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6181
6182 while (iteration < 2) {
6183 val64 = 0x55555555aaaa0000ULL;
6184 if (iteration == 1)
6185 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6186 writeq(val64, &bar0->mc_rldram_test_d0);
6187
6188 val64 = 0xaaaa5a5555550000ULL;
6189 if (iteration == 1)
6190 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6191 writeq(val64, &bar0->mc_rldram_test_d1);
6192
6193 val64 = 0x55aaaaaaaa5a0000ULL;
6194 if (iteration == 1)
6195 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6196 writeq(val64, &bar0->mc_rldram_test_d2);
6197
6198 val64 = (u64) (0x0000003ffffe0100ULL);
6199 writeq(val64, &bar0->mc_rldram_test_add);
6200
6201 val64 = MC_RLDRAM_TEST_MODE |
6202 MC_RLDRAM_TEST_WRITE |
6203 MC_RLDRAM_TEST_GO;
6204 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6205
6206 for (cnt = 0; cnt < 5; cnt++) {
6207 val64 = readq(&bar0->mc_rldram_test_ctrl);
6208 if (val64 & MC_RLDRAM_TEST_DONE)
6209 break;
6210 msleep(200);
6211 }
6212
6213 if (cnt == 5)
6214 break;
6215
6216 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6217 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6218
6219 for (cnt = 0; cnt < 5; cnt++) {
6220 val64 = readq(&bar0->mc_rldram_test_ctrl);
6221 if (val64 & MC_RLDRAM_TEST_DONE)
6222 break;
6223 msleep(500);
6224 }
6225
6226 if (cnt == 5)
6227 break;
6228
6229 val64 = readq(&bar0->mc_rldram_test_ctrl);
6230 if (!(val64 & MC_RLDRAM_TEST_PASS))
6231 test_fail = 1;
6232
6233 iteration++;
6234 }
6235
6236 *data = test_fail;
6237
6238 /* Bring the adapter out of test mode */
6239 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6240
6241 return test_fail;
6242 }
6243
6244 /**
6245 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6246 * @sp : private member of the device structure, which is a pointer to the
6247 * s2io_nic structure.
6248 * @ethtest : pointer to a ethtool command specific structure that will be
6249 * returned to the user.
6250 * @data : variable that returns the result of each of the test
6251 * conducted by the driver.
6252 * Description:
6253 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6254 * the health of the card.
6255 * Return value:
6256 * void
6257 */
6258
6259 static void s2io_ethtool_test(struct net_device *dev,
6260 struct ethtool_test *ethtest,
6261 uint64_t *data)
6262 {
6263 struct s2io_nic *sp = netdev_priv(dev);
6264 int orig_state = netif_running(sp->dev);
6265
6266 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6267 /* Offline Tests. */
6268 if (orig_state)
6269 s2io_close(sp->dev);
6270
6271 if (s2io_register_test(sp, &data[0]))
6272 ethtest->flags |= ETH_TEST_FL_FAILED;
6273
6274 s2io_reset(sp);
6275
6276 if (s2io_rldram_test(sp, &data[3]))
6277 ethtest->flags |= ETH_TEST_FL_FAILED;
6278
6279 s2io_reset(sp);
6280
6281 if (s2io_eeprom_test(sp, &data[1]))
6282 ethtest->flags |= ETH_TEST_FL_FAILED;
6283
6284 if (s2io_bist_test(sp, &data[4]))
6285 ethtest->flags |= ETH_TEST_FL_FAILED;
6286
6287 if (orig_state)
6288 s2io_open(sp->dev);
6289
6290 data[2] = 0;
6291 } else {
6292 /* Online Tests. */
6293 if (!orig_state) {
6294 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6295 dev->name);
6296 data[0] = -1;
6297 data[1] = -1;
6298 data[2] = -1;
6299 data[3] = -1;
6300 data[4] = -1;
6301 }
6302
6303 if (s2io_link_test(sp, &data[2]))
6304 ethtest->flags |= ETH_TEST_FL_FAILED;
6305
6306 data[0] = 0;
6307 data[1] = 0;
6308 data[3] = 0;
6309 data[4] = 0;
6310 }
6311 }
6312
6313 static void s2io_get_ethtool_stats(struct net_device *dev,
6314 struct ethtool_stats *estats,
6315 u64 *tmp_stats)
6316 {
6317 int i = 0, k;
6318 struct s2io_nic *sp = netdev_priv(dev);
6319 struct stat_block *stats = sp->mac_control.stats_info;
6320 struct swStat *swstats = &stats->sw_stat;
6321 struct xpakStat *xstats = &stats->xpak_stat;
6322
6323 s2io_updt_stats(sp);
6324 tmp_stats[i++] =
6325 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6326 le32_to_cpu(stats->tmac_frms);
6327 tmp_stats[i++] =
6328 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6329 le32_to_cpu(stats->tmac_data_octets);
6330 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6331 tmp_stats[i++] =
6332 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6333 le32_to_cpu(stats->tmac_mcst_frms);
6334 tmp_stats[i++] =
6335 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6336 le32_to_cpu(stats->tmac_bcst_frms);
6337 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6338 tmp_stats[i++] =
6339 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6340 le32_to_cpu(stats->tmac_ttl_octets);
6341 tmp_stats[i++] =
6342 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6343 le32_to_cpu(stats->tmac_ucst_frms);
6344 tmp_stats[i++] =
6345 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6346 le32_to_cpu(stats->tmac_nucst_frms);
6347 tmp_stats[i++] =
6348 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6349 le32_to_cpu(stats->tmac_any_err_frms);
6350 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6351 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6352 tmp_stats[i++] =
6353 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6354 le32_to_cpu(stats->tmac_vld_ip);
6355 tmp_stats[i++] =
6356 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6357 le32_to_cpu(stats->tmac_drop_ip);
6358 tmp_stats[i++] =
6359 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6360 le32_to_cpu(stats->tmac_icmp);
6361 tmp_stats[i++] =
6362 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6363 le32_to_cpu(stats->tmac_rst_tcp);
6364 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6365 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6366 le32_to_cpu(stats->tmac_udp);
6367 tmp_stats[i++] =
6368 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6369 le32_to_cpu(stats->rmac_vld_frms);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6372 le32_to_cpu(stats->rmac_data_octets);
6373 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6374 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6375 tmp_stats[i++] =
6376 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6377 le32_to_cpu(stats->rmac_vld_mcst_frms);
6378 tmp_stats[i++] =
6379 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6380 le32_to_cpu(stats->rmac_vld_bcst_frms);
6381 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6382 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6384 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6385 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6386 tmp_stats[i++] =
6387 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6388 le32_to_cpu(stats->rmac_ttl_octets);
6389 tmp_stats[i++] =
6390 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6391 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6392 tmp_stats[i++] =
6393 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6394 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6395 tmp_stats[i++] =
6396 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6397 le32_to_cpu(stats->rmac_discarded_frms);
6398 tmp_stats[i++] =
6399 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6400 << 32 | le32_to_cpu(stats->rmac_drop_events);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6403 tmp_stats[i++] =
6404 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_usized_frms);
6406 tmp_stats[i++] =
6407 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6408 le32_to_cpu(stats->rmac_osized_frms);
6409 tmp_stats[i++] =
6410 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6411 le32_to_cpu(stats->rmac_frag_frms);
6412 tmp_stats[i++] =
6413 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6414 le32_to_cpu(stats->rmac_jabber_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6420 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6421 tmp_stats[i++] =
6422 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6423 le32_to_cpu(stats->rmac_ip);
6424 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6425 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6426 tmp_stats[i++] =
6427 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6428 le32_to_cpu(stats->rmac_drop_ip);
6429 tmp_stats[i++] =
6430 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6431 le32_to_cpu(stats->rmac_icmp);
6432 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6433 tmp_stats[i++] =
6434 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6435 le32_to_cpu(stats->rmac_udp);
6436 tmp_stats[i++] =
6437 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6438 le32_to_cpu(stats->rmac_err_drp_udp);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6454 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6455 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6456 tmp_stats[i++] =
6457 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6458 le32_to_cpu(stats->rmac_pause_cnt);
6459 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6460 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6461 tmp_stats[i++] =
6462 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6463 le32_to_cpu(stats->rmac_accepted_ip);
6464 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6465 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6482 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6483
6484 /* Enhanced statistics exist only for Hercules */
6485 if (sp->device_type == XFRAME_II_DEVICE) {
6486 tmp_stats[i++] =
6487 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6488 tmp_stats[i++] =
6489 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6490 tmp_stats[i++] =
6491 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6495 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6496 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6503 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6504 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6505 }
6506
6507 tmp_stats[i++] = 0;
6508 tmp_stats[i++] = swstats->single_ecc_errs;
6509 tmp_stats[i++] = swstats->double_ecc_errs;
6510 tmp_stats[i++] = swstats->parity_err_cnt;
6511 tmp_stats[i++] = swstats->serious_err_cnt;
6512 tmp_stats[i++] = swstats->soft_reset_cnt;
6513 tmp_stats[i++] = swstats->fifo_full_cnt;
6514 for (k = 0; k < MAX_RX_RINGS; k++)
6515 tmp_stats[i++] = swstats->ring_full_cnt[k];
6516 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6517 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6518 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6519 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6520 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6521 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6522 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6523 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6524 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6525 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6526 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6527 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6528 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6529 tmp_stats[i++] = swstats->sending_both;
6530 tmp_stats[i++] = swstats->outof_sequence_pkts;
6531 tmp_stats[i++] = swstats->flush_max_pkts;
6532 if (swstats->num_aggregations) {
6533 u64 tmp = swstats->sum_avg_pkts_aggregated;
6534 int count = 0;
6535 /*
6536 * Since 64-bit divide does not work on all platforms,
6537 * do repeated subtraction.
6538 */
6539 while (tmp >= swstats->num_aggregations) {
6540 tmp -= swstats->num_aggregations;
6541 count++;
6542 }
6543 tmp_stats[i++] = count;
6544 } else
6545 tmp_stats[i++] = 0;
6546 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6547 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6548 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6549 tmp_stats[i++] = swstats->mem_allocated;
6550 tmp_stats[i++] = swstats->mem_freed;
6551 tmp_stats[i++] = swstats->link_up_cnt;
6552 tmp_stats[i++] = swstats->link_down_cnt;
6553 tmp_stats[i++] = swstats->link_up_time;
6554 tmp_stats[i++] = swstats->link_down_time;
6555
6556 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6557 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6558 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6559 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6560 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6561
6562 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6563 tmp_stats[i++] = swstats->rx_abort_cnt;
6564 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6565 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6566 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6567 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6568 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6569 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6570 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6571 tmp_stats[i++] = swstats->tda_err_cnt;
6572 tmp_stats[i++] = swstats->pfc_err_cnt;
6573 tmp_stats[i++] = swstats->pcc_err_cnt;
6574 tmp_stats[i++] = swstats->tti_err_cnt;
6575 tmp_stats[i++] = swstats->tpa_err_cnt;
6576 tmp_stats[i++] = swstats->sm_err_cnt;
6577 tmp_stats[i++] = swstats->lso_err_cnt;
6578 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6579 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6580 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6581 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6582 tmp_stats[i++] = swstats->rc_err_cnt;
6583 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6584 tmp_stats[i++] = swstats->rpa_err_cnt;
6585 tmp_stats[i++] = swstats->rda_err_cnt;
6586 tmp_stats[i++] = swstats->rti_err_cnt;
6587 tmp_stats[i++] = swstats->mc_err_cnt;
6588 }
6589
6590 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6591 {
6592 return XENA_REG_SPACE;
6593 }
6594
6595
6596 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6597 {
6598 struct s2io_nic *sp = netdev_priv(dev);
6599
6600 return sp->rx_csum;
6601 }
6602
6603 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6604 {
6605 struct s2io_nic *sp = netdev_priv(dev);
6606
6607 if (data)
6608 sp->rx_csum = 1;
6609 else
6610 sp->rx_csum = 0;
6611
6612 return 0;
6613 }
6614
6615 static int s2io_get_eeprom_len(struct net_device *dev)
6616 {
6617 return XENA_EEPROM_SPACE;
6618 }
6619
6620 static int s2io_get_sset_count(struct net_device *dev, int sset)
6621 {
6622 struct s2io_nic *sp = netdev_priv(dev);
6623
6624 switch (sset) {
6625 case ETH_SS_TEST:
6626 return S2IO_TEST_LEN;
6627 case ETH_SS_STATS:
6628 switch (sp->device_type) {
6629 case XFRAME_I_DEVICE:
6630 return XFRAME_I_STAT_LEN;
6631 case XFRAME_II_DEVICE:
6632 return XFRAME_II_STAT_LEN;
6633 default:
6634 return 0;
6635 }
6636 default:
6637 return -EOPNOTSUPP;
6638 }
6639 }
6640
6641 static void s2io_ethtool_get_strings(struct net_device *dev,
6642 u32 stringset, u8 *data)
6643 {
6644 int stat_size = 0;
6645 struct s2io_nic *sp = netdev_priv(dev);
6646
6647 switch (stringset) {
6648 case ETH_SS_TEST:
6649 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6650 break;
6651 case ETH_SS_STATS:
6652 stat_size = sizeof(ethtool_xena_stats_keys);
6653 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6654 if (sp->device_type == XFRAME_II_DEVICE) {
6655 memcpy(data + stat_size,
6656 &ethtool_enhanced_stats_keys,
6657 sizeof(ethtool_enhanced_stats_keys));
6658 stat_size += sizeof(ethtool_enhanced_stats_keys);
6659 }
6660
6661 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6662 sizeof(ethtool_driver_stats_keys));
6663 }
6664 }
6665
6666 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6667 {
6668 if (data)
6669 dev->features |= NETIF_F_IP_CSUM;
6670 else
6671 dev->features &= ~NETIF_F_IP_CSUM;
6672
6673 return 0;
6674 }
6675
6676 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6677 {
6678 return (dev->features & NETIF_F_TSO) != 0;
6679 }
6680 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6681 {
6682 if (data)
6683 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6684 else
6685 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6686
6687 return 0;
6688 }
6689
6690 static const struct ethtool_ops netdev_ethtool_ops = {
6691 .get_settings = s2io_ethtool_gset,
6692 .set_settings = s2io_ethtool_sset,
6693 .get_drvinfo = s2io_ethtool_gdrvinfo,
6694 .get_regs_len = s2io_ethtool_get_regs_len,
6695 .get_regs = s2io_ethtool_gregs,
6696 .get_link = ethtool_op_get_link,
6697 .get_eeprom_len = s2io_get_eeprom_len,
6698 .get_eeprom = s2io_ethtool_geeprom,
6699 .set_eeprom = s2io_ethtool_seeprom,
6700 .get_ringparam = s2io_ethtool_gringparam,
6701 .get_pauseparam = s2io_ethtool_getpause_data,
6702 .set_pauseparam = s2io_ethtool_setpause_data,
6703 .get_rx_csum = s2io_ethtool_get_rx_csum,
6704 .set_rx_csum = s2io_ethtool_set_rx_csum,
6705 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6706 .set_sg = ethtool_op_set_sg,
6707 .get_tso = s2io_ethtool_op_get_tso,
6708 .set_tso = s2io_ethtool_op_set_tso,
6709 .set_ufo = ethtool_op_set_ufo,
6710 .self_test = s2io_ethtool_test,
6711 .get_strings = s2io_ethtool_get_strings,
6712 .phys_id = s2io_ethtool_idnic,
6713 .get_ethtool_stats = s2io_get_ethtool_stats,
6714 .get_sset_count = s2io_get_sset_count,
6715 };
6716
6717 /**
6718 * s2io_ioctl - Entry point for the Ioctl
6719 * @dev : Device pointer.
6720 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6721 * a proprietary structure used to pass information to the driver.
6722 * @cmd : This is used to distinguish between the different commands that
6723 * can be passed to the IOCTL functions.
6724 * Description:
6725 * Currently there are no special functionality supported in IOCTL, hence
6726 * function always return EOPNOTSUPPORTED
6727 */
6728
6729 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6730 {
6731 return -EOPNOTSUPP;
6732 }
6733
6734 /**
6735 * s2io_change_mtu - entry point to change MTU size for the device.
6736 * @dev : device pointer.
6737 * @new_mtu : the new MTU size for the device.
6738 * Description: A driver entry point to change MTU size for the device.
6739 * Before changing the MTU the device must be stopped.
6740 * Return value:
6741 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6742 * file on failure.
6743 */
6744
6745 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6746 {
6747 struct s2io_nic *sp = netdev_priv(dev);
6748 int ret = 0;
6749
6750 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6751 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6752 return -EPERM;
6753 }
6754
6755 dev->mtu = new_mtu;
6756 if (netif_running(dev)) {
6757 s2io_stop_all_tx_queue(sp);
6758 s2io_card_down(sp);
6759 ret = s2io_card_up(sp);
6760 if (ret) {
6761 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6762 __func__);
6763 return ret;
6764 }
6765 s2io_wake_all_tx_queue(sp);
6766 } else { /* Device is down */
6767 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6768 u64 val64 = new_mtu;
6769
6770 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6771 }
6772
6773 return ret;
6774 }
6775
6776 /**
6777 * s2io_set_link - Set the LInk status
6778 * @data: long pointer to device private structue
6779 * Description: Sets the link status for the adapter
6780 */
6781
6782 static void s2io_set_link(struct work_struct *work)
6783 {
6784 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6785 set_link_task);
6786 struct net_device *dev = nic->dev;
6787 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6788 register u64 val64;
6789 u16 subid;
6790
6791 rtnl_lock();
6792
6793 if (!netif_running(dev))
6794 goto out_unlock;
6795
6796 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6797 /* The card is being reset, no point doing anything */
6798 goto out_unlock;
6799 }
6800
6801 subid = nic->pdev->subsystem_device;
6802 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6803 /*
6804 * Allow a small delay for the NICs self initiated
6805 * cleanup to complete.
6806 */
6807 msleep(100);
6808 }
6809
6810 val64 = readq(&bar0->adapter_status);
6811 if (LINK_IS_UP(val64)) {
6812 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6813 if (verify_xena_quiescence(nic)) {
6814 val64 = readq(&bar0->adapter_control);
6815 val64 |= ADAPTER_CNTL_EN;
6816 writeq(val64, &bar0->adapter_control);
6817 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6818 nic->device_type, subid)) {
6819 val64 = readq(&bar0->gpio_control);
6820 val64 |= GPIO_CTRL_GPIO_0;
6821 writeq(val64, &bar0->gpio_control);
6822 val64 = readq(&bar0->gpio_control);
6823 } else {
6824 val64 |= ADAPTER_LED_ON;
6825 writeq(val64, &bar0->adapter_control);
6826 }
6827 nic->device_enabled_once = true;
6828 } else {
6829 DBG_PRINT(ERR_DBG,
6830 "%s: Error: device is not Quiescent\n",
6831 dev->name);
6832 s2io_stop_all_tx_queue(nic);
6833 }
6834 }
6835 val64 = readq(&bar0->adapter_control);
6836 val64 |= ADAPTER_LED_ON;
6837 writeq(val64, &bar0->adapter_control);
6838 s2io_link(nic, LINK_UP);
6839 } else {
6840 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6841 subid)) {
6842 val64 = readq(&bar0->gpio_control);
6843 val64 &= ~GPIO_CTRL_GPIO_0;
6844 writeq(val64, &bar0->gpio_control);
6845 val64 = readq(&bar0->gpio_control);
6846 }
6847 /* turn off LED */
6848 val64 = readq(&bar0->adapter_control);
6849 val64 = val64 & (~ADAPTER_LED_ON);
6850 writeq(val64, &bar0->adapter_control);
6851 s2io_link(nic, LINK_DOWN);
6852 }
6853 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6854
6855 out_unlock:
6856 rtnl_unlock();
6857 }
6858
6859 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6860 struct buffAdd *ba,
6861 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6862 u64 *temp2, int size)
6863 {
6864 struct net_device *dev = sp->dev;
6865 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6866
6867 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6868 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6869 /* allocate skb */
6870 if (*skb) {
6871 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6872 /*
6873 * As Rx frame are not going to be processed,
6874 * using same mapped address for the Rxd
6875 * buffer pointer
6876 */
6877 rxdp1->Buffer0_ptr = *temp0;
6878 } else {
6879 *skb = dev_alloc_skb(size);
6880 if (!(*skb)) {
6881 DBG_PRINT(INFO_DBG,
6882 "%s: Out of memory to allocate %s\n",
6883 dev->name, "1 buf mode SKBs");
6884 stats->mem_alloc_fail_cnt++;
6885 return -ENOMEM ;
6886 }
6887 stats->mem_allocated += (*skb)->truesize;
6888 /* storing the mapped addr in a temp variable
6889 * such it will be used for next rxd whose
6890 * Host Control is NULL
6891 */
6892 rxdp1->Buffer0_ptr = *temp0 =
6893 pci_map_single(sp->pdev, (*skb)->data,
6894 size - NET_IP_ALIGN,
6895 PCI_DMA_FROMDEVICE);
6896 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6897 goto memalloc_failed;
6898 rxdp->Host_Control = (unsigned long) (*skb);
6899 }
6900 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6901 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6902 /* Two buffer Mode */
6903 if (*skb) {
6904 rxdp3->Buffer2_ptr = *temp2;
6905 rxdp3->Buffer0_ptr = *temp0;
6906 rxdp3->Buffer1_ptr = *temp1;
6907 } else {
6908 *skb = dev_alloc_skb(size);
6909 if (!(*skb)) {
6910 DBG_PRINT(INFO_DBG,
6911 "%s: Out of memory to allocate %s\n",
6912 dev->name,
6913 "2 buf mode SKBs");
6914 stats->mem_alloc_fail_cnt++;
6915 return -ENOMEM;
6916 }
6917 stats->mem_allocated += (*skb)->truesize;
6918 rxdp3->Buffer2_ptr = *temp2 =
6919 pci_map_single(sp->pdev, (*skb)->data,
6920 dev->mtu + 4,
6921 PCI_DMA_FROMDEVICE);
6922 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6923 goto memalloc_failed;
6924 rxdp3->Buffer0_ptr = *temp0 =
6925 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6926 PCI_DMA_FROMDEVICE);
6927 if (pci_dma_mapping_error(sp->pdev,
6928 rxdp3->Buffer0_ptr)) {
6929 pci_unmap_single(sp->pdev,
6930 (dma_addr_t)rxdp3->Buffer2_ptr,
6931 dev->mtu + 4,
6932 PCI_DMA_FROMDEVICE);
6933 goto memalloc_failed;
6934 }
6935 rxdp->Host_Control = (unsigned long) (*skb);
6936
6937 /* Buffer-1 will be dummy buffer not used */
6938 rxdp3->Buffer1_ptr = *temp1 =
6939 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6940 PCI_DMA_FROMDEVICE);
6941 if (pci_dma_mapping_error(sp->pdev,
6942 rxdp3->Buffer1_ptr)) {
6943 pci_unmap_single(sp->pdev,
6944 (dma_addr_t)rxdp3->Buffer0_ptr,
6945 BUF0_LEN, PCI_DMA_FROMDEVICE);
6946 pci_unmap_single(sp->pdev,
6947 (dma_addr_t)rxdp3->Buffer2_ptr,
6948 dev->mtu + 4,
6949 PCI_DMA_FROMDEVICE);
6950 goto memalloc_failed;
6951 }
6952 }
6953 }
6954 return 0;
6955
6956 memalloc_failed:
6957 stats->pci_map_fail_cnt++;
6958 stats->mem_freed += (*skb)->truesize;
6959 dev_kfree_skb(*skb);
6960 return -ENOMEM;
6961 }
6962
6963 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6964 int size)
6965 {
6966 struct net_device *dev = sp->dev;
6967 if (sp->rxd_mode == RXD_MODE_1) {
6968 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6969 } else if (sp->rxd_mode == RXD_MODE_3B) {
6970 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6971 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6972 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6973 }
6974 }
6975
6976 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6977 {
6978 int i, j, k, blk_cnt = 0, size;
6979 struct config_param *config = &sp->config;
6980 struct mac_info *mac_control = &sp->mac_control;
6981 struct net_device *dev = sp->dev;
6982 struct RxD_t *rxdp = NULL;
6983 struct sk_buff *skb = NULL;
6984 struct buffAdd *ba = NULL;
6985 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6986
6987 /* Calculate the size based on ring mode */
6988 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6989 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6990 if (sp->rxd_mode == RXD_MODE_1)
6991 size += NET_IP_ALIGN;
6992 else if (sp->rxd_mode == RXD_MODE_3B)
6993 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6994
6995 for (i = 0; i < config->rx_ring_num; i++) {
6996 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6997 struct ring_info *ring = &mac_control->rings[i];
6998
6999 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7000
7001 for (j = 0; j < blk_cnt; j++) {
7002 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7003 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7004 if (sp->rxd_mode == RXD_MODE_3B)
7005 ba = &ring->ba[j][k];
7006 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7007 (u64 *)&temp0_64,
7008 (u64 *)&temp1_64,
7009 (u64 *)&temp2_64,
7010 size) == -ENOMEM) {
7011 return 0;
7012 }
7013
7014 set_rxd_buffer_size(sp, rxdp, size);
7015 wmb();
7016 /* flip the Ownership bit to Hardware */
7017 rxdp->Control_1 |= RXD_OWN_XENA;
7018 }
7019 }
7020 }
7021 return 0;
7022
7023 }
7024
7025 static int s2io_add_isr(struct s2io_nic *sp)
7026 {
7027 int ret = 0;
7028 struct net_device *dev = sp->dev;
7029 int err = 0;
7030
7031 if (sp->config.intr_type == MSI_X)
7032 ret = s2io_enable_msi_x(sp);
7033 if (ret) {
7034 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7035 sp->config.intr_type = INTA;
7036 }
7037
7038 /*
7039 * Store the values of the MSIX table in
7040 * the struct s2io_nic structure
7041 */
7042 store_xmsi_data(sp);
7043
7044 /* After proper initialization of H/W, register ISR */
7045 if (sp->config.intr_type == MSI_X) {
7046 int i, msix_rx_cnt = 0;
7047
7048 for (i = 0; i < sp->num_entries; i++) {
7049 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7050 if (sp->s2io_entries[i].type ==
7051 MSIX_RING_TYPE) {
7052 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7053 dev->name, i);
7054 err = request_irq(sp->entries[i].vector,
7055 s2io_msix_ring_handle,
7056 0,
7057 sp->desc[i],
7058 sp->s2io_entries[i].arg);
7059 } else if (sp->s2io_entries[i].type ==
7060 MSIX_ALARM_TYPE) {
7061 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7062 dev->name, i);
7063 err = request_irq(sp->entries[i].vector,
7064 s2io_msix_fifo_handle,
7065 0,
7066 sp->desc[i],
7067 sp->s2io_entries[i].arg);
7068
7069 }
7070 /* if either data or addr is zero print it. */
7071 if (!(sp->msix_info[i].addr &&
7072 sp->msix_info[i].data)) {
7073 DBG_PRINT(ERR_DBG,
7074 "%s @Addr:0x%llx Data:0x%llx\n",
7075 sp->desc[i],
7076 (unsigned long long)
7077 sp->msix_info[i].addr,
7078 (unsigned long long)
7079 ntohl(sp->msix_info[i].data));
7080 } else
7081 msix_rx_cnt++;
7082 if (err) {
7083 remove_msix_isr(sp);
7084
7085 DBG_PRINT(ERR_DBG,
7086 "%s:MSI-X-%d registration "
7087 "failed\n", dev->name, i);
7088
7089 DBG_PRINT(ERR_DBG,
7090 "%s: Defaulting to INTA\n",
7091 dev->name);
7092 sp->config.intr_type = INTA;
7093 break;
7094 }
7095 sp->s2io_entries[i].in_use =
7096 MSIX_REGISTERED_SUCCESS;
7097 }
7098 }
7099 if (!err) {
7100 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7101 DBG_PRINT(INFO_DBG,
7102 "MSI-X-TX entries enabled through alarm vector\n");
7103 }
7104 }
7105 if (sp->config.intr_type == INTA) {
7106 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7107 sp->name, dev);
7108 if (err) {
7109 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7110 dev->name);
7111 return -1;
7112 }
7113 }
7114 return 0;
7115 }
7116
7117 static void s2io_rem_isr(struct s2io_nic *sp)
7118 {
7119 if (sp->config.intr_type == MSI_X)
7120 remove_msix_isr(sp);
7121 else
7122 remove_inta_isr(sp);
7123 }
7124
7125 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7126 {
7127 int cnt = 0;
7128 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7129 register u64 val64 = 0;
7130 struct config_param *config;
7131 config = &sp->config;
7132
7133 if (!is_s2io_card_up(sp))
7134 return;
7135
7136 del_timer_sync(&sp->alarm_timer);
7137 /* If s2io_set_link task is executing, wait till it completes. */
7138 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7139 msleep(50);
7140 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7141
7142 /* Disable napi */
7143 if (sp->config.napi) {
7144 int off = 0;
7145 if (config->intr_type == MSI_X) {
7146 for (; off < sp->config.rx_ring_num; off++)
7147 napi_disable(&sp->mac_control.rings[off].napi);
7148 }
7149 else
7150 napi_disable(&sp->napi);
7151 }
7152
7153 /* disable Tx and Rx traffic on the NIC */
7154 if (do_io)
7155 stop_nic(sp);
7156
7157 s2io_rem_isr(sp);
7158
7159 /* stop the tx queue, indicate link down */
7160 s2io_link(sp, LINK_DOWN);
7161
7162 /* Check if the device is Quiescent and then Reset the NIC */
7163 while (do_io) {
7164 /* As per the HW requirement we need to replenish the
7165 * receive buffer to avoid the ring bump. Since there is
7166 * no intention of processing the Rx frame at this pointwe are
7167 * just settting the ownership bit of rxd in Each Rx
7168 * ring to HW and set the appropriate buffer size
7169 * based on the ring mode
7170 */
7171 rxd_owner_bit_reset(sp);
7172
7173 val64 = readq(&bar0->adapter_status);
7174 if (verify_xena_quiescence(sp)) {
7175 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7176 break;
7177 }
7178
7179 msleep(50);
7180 cnt++;
7181 if (cnt == 10) {
7182 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7183 "adapter status reads 0x%llx\n",
7184 (unsigned long long)val64);
7185 break;
7186 }
7187 }
7188 if (do_io)
7189 s2io_reset(sp);
7190
7191 /* Free all Tx buffers */
7192 free_tx_buffers(sp);
7193
7194 /* Free all Rx buffers */
7195 free_rx_buffers(sp);
7196
7197 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7198 }
7199
7200 static void s2io_card_down(struct s2io_nic *sp)
7201 {
7202 do_s2io_card_down(sp, 1);
7203 }
7204
7205 static int s2io_card_up(struct s2io_nic *sp)
7206 {
7207 int i, ret = 0;
7208 struct config_param *config;
7209 struct mac_info *mac_control;
7210 struct net_device *dev = (struct net_device *)sp->dev;
7211 u16 interruptible;
7212
7213 /* Initialize the H/W I/O registers */
7214 ret = init_nic(sp);
7215 if (ret != 0) {
7216 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7217 dev->name);
7218 if (ret != -EIO)
7219 s2io_reset(sp);
7220 return ret;
7221 }
7222
7223 /*
7224 * Initializing the Rx buffers. For now we are considering only 1
7225 * Rx ring and initializing buffers into 30 Rx blocks
7226 */
7227 config = &sp->config;
7228 mac_control = &sp->mac_control;
7229
7230 for (i = 0; i < config->rx_ring_num; i++) {
7231 struct ring_info *ring = &mac_control->rings[i];
7232
7233 ring->mtu = dev->mtu;
7234 ret = fill_rx_buffers(sp, ring, 1);
7235 if (ret) {
7236 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7237 dev->name);
7238 s2io_reset(sp);
7239 free_rx_buffers(sp);
7240 return -ENOMEM;
7241 }
7242 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7243 ring->rx_bufs_left);
7244 }
7245
7246 /* Initialise napi */
7247 if (config->napi) {
7248 if (config->intr_type == MSI_X) {
7249 for (i = 0; i < sp->config.rx_ring_num; i++)
7250 napi_enable(&sp->mac_control.rings[i].napi);
7251 } else {
7252 napi_enable(&sp->napi);
7253 }
7254 }
7255
7256 /* Maintain the state prior to the open */
7257 if (sp->promisc_flg)
7258 sp->promisc_flg = 0;
7259 if (sp->m_cast_flg) {
7260 sp->m_cast_flg = 0;
7261 sp->all_multi_pos = 0;
7262 }
7263
7264 /* Setting its receive mode */
7265 s2io_set_multicast(dev);
7266
7267 if (sp->lro) {
7268 /* Initialize max aggregatable pkts per session based on MTU */
7269 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7270 /* Check if we can use (if specified) user provided value */
7271 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7272 sp->lro_max_aggr_per_sess = lro_max_pkts;
7273 }
7274
7275 /* Enable Rx Traffic and interrupts on the NIC */
7276 if (start_nic(sp)) {
7277 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7278 s2io_reset(sp);
7279 free_rx_buffers(sp);
7280 return -ENODEV;
7281 }
7282
7283 /* Add interrupt service routine */
7284 if (s2io_add_isr(sp) != 0) {
7285 if (sp->config.intr_type == MSI_X)
7286 s2io_rem_isr(sp);
7287 s2io_reset(sp);
7288 free_rx_buffers(sp);
7289 return -ENODEV;
7290 }
7291
7292 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7293
7294 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7295
7296 /* Enable select interrupts */
7297 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7298 if (sp->config.intr_type != INTA) {
7299 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7300 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7301 } else {
7302 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7303 interruptible |= TX_PIC_INTR;
7304 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7305 }
7306
7307 return 0;
7308 }
7309
7310 /**
7311 * s2io_restart_nic - Resets the NIC.
7312 * @data : long pointer to the device private structure
7313 * Description:
7314 * This function is scheduled to be run by the s2io_tx_watchdog
7315 * function after 0.5 secs to reset the NIC. The idea is to reduce
7316 * the run time of the watch dog routine which is run holding a
7317 * spin lock.
7318 */
7319
7320 static void s2io_restart_nic(struct work_struct *work)
7321 {
7322 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7323 struct net_device *dev = sp->dev;
7324
7325 rtnl_lock();
7326
7327 if (!netif_running(dev))
7328 goto out_unlock;
7329
7330 s2io_card_down(sp);
7331 if (s2io_card_up(sp)) {
7332 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7333 }
7334 s2io_wake_all_tx_queue(sp);
7335 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7336 out_unlock:
7337 rtnl_unlock();
7338 }
7339
7340 /**
7341 * s2io_tx_watchdog - Watchdog for transmit side.
7342 * @dev : Pointer to net device structure
7343 * Description:
7344 * This function is triggered if the Tx Queue is stopped
7345 * for a pre-defined amount of time when the Interface is still up.
7346 * If the Interface is jammed in such a situation, the hardware is
7347 * reset (by s2io_close) and restarted again (by s2io_open) to
7348 * overcome any problem that might have been caused in the hardware.
7349 * Return value:
7350 * void
7351 */
7352
7353 static void s2io_tx_watchdog(struct net_device *dev)
7354 {
7355 struct s2io_nic *sp = netdev_priv(dev);
7356 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7357
7358 if (netif_carrier_ok(dev)) {
7359 swstats->watchdog_timer_cnt++;
7360 schedule_work(&sp->rst_timer_task);
7361 swstats->soft_reset_cnt++;
7362 }
7363 }
7364
7365 /**
7366 * rx_osm_handler - To perform some OS related operations on SKB.
7367 * @sp: private member of the device structure,pointer to s2io_nic structure.
7368 * @skb : the socket buffer pointer.
7369 * @len : length of the packet
7370 * @cksum : FCS checksum of the frame.
7371 * @ring_no : the ring from which this RxD was extracted.
7372 * Description:
7373 * This function is called by the Rx interrupt serivce routine to perform
7374 * some OS related operations on the SKB before passing it to the upper
7375 * layers. It mainly checks if the checksum is OK, if so adds it to the
7376 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7377 * to the upper layer. If the checksum is wrong, it increments the Rx
7378 * packet error count, frees the SKB and returns error.
7379 * Return value:
7380 * SUCCESS on success and -1 on failure.
7381 */
7382 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7383 {
7384 struct s2io_nic *sp = ring_data->nic;
7385 struct net_device *dev = (struct net_device *)ring_data->dev;
7386 struct sk_buff *skb = (struct sk_buff *)
7387 ((unsigned long)rxdp->Host_Control);
7388 int ring_no = ring_data->ring_no;
7389 u16 l3_csum, l4_csum;
7390 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7391 struct lro *uninitialized_var(lro);
7392 u8 err_mask;
7393 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7394
7395 skb->dev = dev;
7396
7397 if (err) {
7398 /* Check for parity error */
7399 if (err & 0x1)
7400 swstats->parity_err_cnt++;
7401
7402 err_mask = err >> 48;
7403 switch (err_mask) {
7404 case 1:
7405 swstats->rx_parity_err_cnt++;
7406 break;
7407
7408 case 2:
7409 swstats->rx_abort_cnt++;
7410 break;
7411
7412 case 3:
7413 swstats->rx_parity_abort_cnt++;
7414 break;
7415
7416 case 4:
7417 swstats->rx_rda_fail_cnt++;
7418 break;
7419
7420 case 5:
7421 swstats->rx_unkn_prot_cnt++;
7422 break;
7423
7424 case 6:
7425 swstats->rx_fcs_err_cnt++;
7426 break;
7427
7428 case 7:
7429 swstats->rx_buf_size_err_cnt++;
7430 break;
7431
7432 case 8:
7433 swstats->rx_rxd_corrupt_cnt++;
7434 break;
7435
7436 case 15:
7437 swstats->rx_unkn_err_cnt++;
7438 break;
7439 }
7440 /*
7441 * Drop the packet if bad transfer code. Exception being
7442 * 0x5, which could be due to unsupported IPv6 extension header.
7443 * In this case, we let stack handle the packet.
7444 * Note that in this case, since checksum will be incorrect,
7445 * stack will validate the same.
7446 */
7447 if (err_mask != 0x5) {
7448 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7449 dev->name, err_mask);
7450 dev->stats.rx_crc_errors++;
7451 swstats->mem_freed
7452 += skb->truesize;
7453 dev_kfree_skb(skb);
7454 ring_data->rx_bufs_left -= 1;
7455 rxdp->Host_Control = 0;
7456 return 0;
7457 }
7458 }
7459
7460 /* Updating statistics */
7461 ring_data->rx_packets++;
7462 rxdp->Host_Control = 0;
7463 if (sp->rxd_mode == RXD_MODE_1) {
7464 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7465
7466 ring_data->rx_bytes += len;
7467 skb_put(skb, len);
7468
7469 } else if (sp->rxd_mode == RXD_MODE_3B) {
7470 int get_block = ring_data->rx_curr_get_info.block_index;
7471 int get_off = ring_data->rx_curr_get_info.offset;
7472 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7473 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7474 unsigned char *buff = skb_push(skb, buf0_len);
7475
7476 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7477 ring_data->rx_bytes += buf0_len + buf2_len;
7478 memcpy(buff, ba->ba_0, buf0_len);
7479 skb_put(skb, buf2_len);
7480 }
7481
7482 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7483 ((!ring_data->lro) ||
7484 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7485 (sp->rx_csum)) {
7486 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7487 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7488 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7489 /*
7490 * NIC verifies if the Checksum of the received
7491 * frame is Ok or not and accordingly returns
7492 * a flag in the RxD.
7493 */
7494 skb->ip_summed = CHECKSUM_UNNECESSARY;
7495 if (ring_data->lro) {
7496 u32 tcp_len;
7497 u8 *tcp;
7498 int ret = 0;
7499
7500 ret = s2io_club_tcp_session(ring_data,
7501 skb->data, &tcp,
7502 &tcp_len, &lro,
7503 rxdp, sp);
7504 switch (ret) {
7505 case 3: /* Begin anew */
7506 lro->parent = skb;
7507 goto aggregate;
7508 case 1: /* Aggregate */
7509 lro_append_pkt(sp, lro, skb, tcp_len);
7510 goto aggregate;
7511 case 4: /* Flush session */
7512 lro_append_pkt(sp, lro, skb, tcp_len);
7513 queue_rx_frame(lro->parent,
7514 lro->vlan_tag);
7515 clear_lro_session(lro);
7516 swstats->flush_max_pkts++;
7517 goto aggregate;
7518 case 2: /* Flush both */
7519 lro->parent->data_len = lro->frags_len;
7520 swstats->sending_both++;
7521 queue_rx_frame(lro->parent,
7522 lro->vlan_tag);
7523 clear_lro_session(lro);
7524 goto send_up;
7525 case 0: /* sessions exceeded */
7526 case -1: /* non-TCP or not L2 aggregatable */
7527 case 5: /*
7528 * First pkt in session not
7529 * L3/L4 aggregatable
7530 */
7531 break;
7532 default:
7533 DBG_PRINT(ERR_DBG,
7534 "%s: Samadhana!!\n",
7535 __func__);
7536 BUG();
7537 }
7538 }
7539 } else {
7540 /*
7541 * Packet with erroneous checksum, let the
7542 * upper layers deal with it.
7543 */
7544 skb->ip_summed = CHECKSUM_NONE;
7545 }
7546 } else
7547 skb->ip_summed = CHECKSUM_NONE;
7548
7549 swstats->mem_freed += skb->truesize;
7550 send_up:
7551 skb_record_rx_queue(skb, ring_no);
7552 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7553 aggregate:
7554 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7555 return SUCCESS;
7556 }
7557
7558 /**
7559 * s2io_link - stops/starts the Tx queue.
7560 * @sp : private member of the device structure, which is a pointer to the
7561 * s2io_nic structure.
7562 * @link : inidicates whether link is UP/DOWN.
7563 * Description:
7564 * This function stops/starts the Tx queue depending on whether the link
7565 * status of the NIC is is down or up. This is called by the Alarm
7566 * interrupt handler whenever a link change interrupt comes up.
7567 * Return value:
7568 * void.
7569 */
7570
7571 static void s2io_link(struct s2io_nic *sp, int link)
7572 {
7573 struct net_device *dev = (struct net_device *)sp->dev;
7574 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7575
7576 if (link != sp->last_link_state) {
7577 init_tti(sp, link);
7578 if (link == LINK_DOWN) {
7579 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7580 s2io_stop_all_tx_queue(sp);
7581 netif_carrier_off(dev);
7582 if (swstats->link_up_cnt)
7583 swstats->link_up_time =
7584 jiffies - sp->start_time;
7585 swstats->link_down_cnt++;
7586 } else {
7587 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7588 if (swstats->link_down_cnt)
7589 swstats->link_down_time =
7590 jiffies - sp->start_time;
7591 swstats->link_up_cnt++;
7592 netif_carrier_on(dev);
7593 s2io_wake_all_tx_queue(sp);
7594 }
7595 }
7596 sp->last_link_state = link;
7597 sp->start_time = jiffies;
7598 }
7599
7600 /**
7601 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7602 * @sp : private member of the device structure, which is a pointer to the
7603 * s2io_nic structure.
7604 * Description:
7605 * This function initializes a few of the PCI and PCI-X configuration registers
7606 * with recommended values.
7607 * Return value:
7608 * void
7609 */
7610
7611 static void s2io_init_pci(struct s2io_nic *sp)
7612 {
7613 u16 pci_cmd = 0, pcix_cmd = 0;
7614
7615 /* Enable Data Parity Error Recovery in PCI-X command register. */
7616 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7617 &(pcix_cmd));
7618 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7619 (pcix_cmd | 1));
7620 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7621 &(pcix_cmd));
7622
7623 /* Set the PErr Response bit in PCI command register. */
7624 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7625 pci_write_config_word(sp->pdev, PCI_COMMAND,
7626 (pci_cmd | PCI_COMMAND_PARITY));
7627 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7628 }
7629
7630 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7631 u8 *dev_multiq)
7632 {
7633 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7634 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7635 "(%d) not supported\n", tx_fifo_num);
7636
7637 if (tx_fifo_num < 1)
7638 tx_fifo_num = 1;
7639 else
7640 tx_fifo_num = MAX_TX_FIFOS;
7641
7642 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7643 }
7644
7645 if (multiq)
7646 *dev_multiq = multiq;
7647
7648 if (tx_steering_type && (1 == tx_fifo_num)) {
7649 if (tx_steering_type != TX_DEFAULT_STEERING)
7650 DBG_PRINT(ERR_DBG,
7651 "Tx steering is not supported with "
7652 "one fifo. Disabling Tx steering.\n");
7653 tx_steering_type = NO_STEERING;
7654 }
7655
7656 if ((tx_steering_type < NO_STEERING) ||
7657 (tx_steering_type > TX_DEFAULT_STEERING)) {
7658 DBG_PRINT(ERR_DBG,
7659 "Requested transmit steering not supported\n");
7660 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7661 tx_steering_type = NO_STEERING;
7662 }
7663
7664 if (rx_ring_num > MAX_RX_RINGS) {
7665 DBG_PRINT(ERR_DBG,
7666 "Requested number of rx rings not supported\n");
7667 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7668 MAX_RX_RINGS);
7669 rx_ring_num = MAX_RX_RINGS;
7670 }
7671
7672 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7673 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7674 "Defaulting to INTA\n");
7675 *dev_intr_type = INTA;
7676 }
7677
7678 if ((*dev_intr_type == MSI_X) &&
7679 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7680 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7681 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7682 "Defaulting to INTA\n");
7683 *dev_intr_type = INTA;
7684 }
7685
7686 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7687 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7688 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7689 rx_ring_mode = 1;
7690 }
7691 return SUCCESS;
7692 }
7693
7694 /**
7695 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7696 * or Traffic class respectively.
7697 * @nic: device private variable
7698 * Description: The function configures the receive steering to
7699 * desired receive ring.
7700 * Return Value: SUCCESS on success and
7701 * '-1' on failure (endian settings incorrect).
7702 */
7703 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7704 {
7705 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7706 register u64 val64 = 0;
7707
7708 if (ds_codepoint > 63)
7709 return FAILURE;
7710
7711 val64 = RTS_DS_MEM_DATA(ring);
7712 writeq(val64, &bar0->rts_ds_mem_data);
7713
7714 val64 = RTS_DS_MEM_CTRL_WE |
7715 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7716 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7717
7718 writeq(val64, &bar0->rts_ds_mem_ctrl);
7719
7720 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7721 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7722 S2IO_BIT_RESET);
7723 }
7724
7725 static const struct net_device_ops s2io_netdev_ops = {
7726 .ndo_open = s2io_open,
7727 .ndo_stop = s2io_close,
7728 .ndo_get_stats = s2io_get_stats,
7729 .ndo_start_xmit = s2io_xmit,
7730 .ndo_validate_addr = eth_validate_addr,
7731 .ndo_set_multicast_list = s2io_set_multicast,
7732 .ndo_do_ioctl = s2io_ioctl,
7733 .ndo_set_mac_address = s2io_set_mac_addr,
7734 .ndo_change_mtu = s2io_change_mtu,
7735 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7736 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7737 .ndo_tx_timeout = s2io_tx_watchdog,
7738 #ifdef CONFIG_NET_POLL_CONTROLLER
7739 .ndo_poll_controller = s2io_netpoll,
7740 #endif
7741 };
7742
7743 /**
7744 * s2io_init_nic - Initialization of the adapter .
7745 * @pdev : structure containing the PCI related information of the device.
7746 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7747 * Description:
7748 * The function initializes an adapter identified by the pci_dec structure.
7749 * All OS related initialization including memory and device structure and
7750 * initlaization of the device private variable is done. Also the swapper
7751 * control register is initialized to enable read and write into the I/O
7752 * registers of the device.
7753 * Return value:
7754 * returns 0 on success and negative on failure.
7755 */
7756
7757 static int __devinit
7758 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7759 {
7760 struct s2io_nic *sp;
7761 struct net_device *dev;
7762 int i, j, ret;
7763 int dma_flag = false;
7764 u32 mac_up, mac_down;
7765 u64 val64 = 0, tmp64 = 0;
7766 struct XENA_dev_config __iomem *bar0 = NULL;
7767 u16 subid;
7768 struct config_param *config;
7769 struct mac_info *mac_control;
7770 int mode;
7771 u8 dev_intr_type = intr_type;
7772 u8 dev_multiq = 0;
7773
7774 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7775 if (ret)
7776 return ret;
7777
7778 ret = pci_enable_device(pdev);
7779 if (ret) {
7780 DBG_PRINT(ERR_DBG,
7781 "%s: pci_enable_device failed\n", __func__);
7782 return ret;
7783 }
7784
7785 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7786 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7787 dma_flag = true;
7788 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7789 DBG_PRINT(ERR_DBG,
7790 "Unable to obtain 64bit DMA "
7791 "for consistent allocations\n");
7792 pci_disable_device(pdev);
7793 return -ENOMEM;
7794 }
7795 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7796 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7797 } else {
7798 pci_disable_device(pdev);
7799 return -ENOMEM;
7800 }
7801 ret = pci_request_regions(pdev, s2io_driver_name);
7802 if (ret) {
7803 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7804 __func__, ret);
7805 pci_disable_device(pdev);
7806 return -ENODEV;
7807 }
7808 if (dev_multiq)
7809 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7810 else
7811 dev = alloc_etherdev(sizeof(struct s2io_nic));
7812 if (dev == NULL) {
7813 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7814 pci_disable_device(pdev);
7815 pci_release_regions(pdev);
7816 return -ENODEV;
7817 }
7818
7819 pci_set_master(pdev);
7820 pci_set_drvdata(pdev, dev);
7821 SET_NETDEV_DEV(dev, &pdev->dev);
7822
7823 /* Private member variable initialized to s2io NIC structure */
7824 sp = netdev_priv(dev);
7825 memset(sp, 0, sizeof(struct s2io_nic));
7826 sp->dev = dev;
7827 sp->pdev = pdev;
7828 sp->high_dma_flag = dma_flag;
7829 sp->device_enabled_once = false;
7830 if (rx_ring_mode == 1)
7831 sp->rxd_mode = RXD_MODE_1;
7832 if (rx_ring_mode == 2)
7833 sp->rxd_mode = RXD_MODE_3B;
7834
7835 sp->config.intr_type = dev_intr_type;
7836
7837 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7838 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7839 sp->device_type = XFRAME_II_DEVICE;
7840 else
7841 sp->device_type = XFRAME_I_DEVICE;
7842
7843 sp->lro = lro_enable;
7844
7845 /* Initialize some PCI/PCI-X fields of the NIC. */
7846 s2io_init_pci(sp);
7847
7848 /*
7849 * Setting the device configuration parameters.
7850 * Most of these parameters can be specified by the user during
7851 * module insertion as they are module loadable parameters. If
7852 * these parameters are not not specified during load time, they
7853 * are initialized with default values.
7854 */
7855 config = &sp->config;
7856 mac_control = &sp->mac_control;
7857
7858 config->napi = napi;
7859 config->tx_steering_type = tx_steering_type;
7860
7861 /* Tx side parameters. */
7862 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7863 config->tx_fifo_num = MAX_TX_FIFOS;
7864 else
7865 config->tx_fifo_num = tx_fifo_num;
7866
7867 /* Initialize the fifos used for tx steering */
7868 if (config->tx_fifo_num < 5) {
7869 if (config->tx_fifo_num == 1)
7870 sp->total_tcp_fifos = 1;
7871 else
7872 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7873 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7874 sp->total_udp_fifos = 1;
7875 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7876 } else {
7877 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7878 FIFO_OTHER_MAX_NUM);
7879 sp->udp_fifo_idx = sp->total_tcp_fifos;
7880 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7881 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7882 }
7883
7884 config->multiq = dev_multiq;
7885 for (i = 0; i < config->tx_fifo_num; i++) {
7886 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7887
7888 tx_cfg->fifo_len = tx_fifo_len[i];
7889 tx_cfg->fifo_priority = i;
7890 }
7891
7892 /* mapping the QoS priority to the configured fifos */
7893 for (i = 0; i < MAX_TX_FIFOS; i++)
7894 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7895
7896 /* map the hashing selector table to the configured fifos */
7897 for (i = 0; i < config->tx_fifo_num; i++)
7898 sp->fifo_selector[i] = fifo_selector[i];
7899
7900
7901 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7902 for (i = 0; i < config->tx_fifo_num; i++) {
7903 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7904
7905 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7906 if (tx_cfg->fifo_len < 65) {
7907 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7908 break;
7909 }
7910 }
7911 /* + 2 because one Txd for skb->data and one Txd for UFO */
7912 config->max_txds = MAX_SKB_FRAGS + 2;
7913
7914 /* Rx side parameters. */
7915 config->rx_ring_num = rx_ring_num;
7916 for (i = 0; i < config->rx_ring_num; i++) {
7917 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7918 struct ring_info *ring = &mac_control->rings[i];
7919
7920 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7921 rx_cfg->ring_priority = i;
7922 ring->rx_bufs_left = 0;
7923 ring->rxd_mode = sp->rxd_mode;
7924 ring->rxd_count = rxd_count[sp->rxd_mode];
7925 ring->pdev = sp->pdev;
7926 ring->dev = sp->dev;
7927 }
7928
7929 for (i = 0; i < rx_ring_num; i++) {
7930 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7931
7932 rx_cfg->ring_org = RING_ORG_BUFF1;
7933 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7934 }
7935
7936 /* Setting Mac Control parameters */
7937 mac_control->rmac_pause_time = rmac_pause_time;
7938 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7939 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7940
7941
7942 /* initialize the shared memory used by the NIC and the host */
7943 if (init_shared_mem(sp)) {
7944 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7945 ret = -ENOMEM;
7946 goto mem_alloc_failed;
7947 }
7948
7949 sp->bar0 = pci_ioremap_bar(pdev, 0);
7950 if (!sp->bar0) {
7951 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7952 dev->name);
7953 ret = -ENOMEM;
7954 goto bar0_remap_failed;
7955 }
7956
7957 sp->bar1 = pci_ioremap_bar(pdev, 2);
7958 if (!sp->bar1) {
7959 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7960 dev->name);
7961 ret = -ENOMEM;
7962 goto bar1_remap_failed;
7963 }
7964
7965 dev->irq = pdev->irq;
7966 dev->base_addr = (unsigned long)sp->bar0;
7967
7968 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7969 for (j = 0; j < MAX_TX_FIFOS; j++) {
7970 mac_control->tx_FIFO_start[j] =
7971 (struct TxFIFO_element __iomem *)
7972 (sp->bar1 + (j * 0x00020000));
7973 }
7974
7975 /* Driver entry points */
7976 dev->netdev_ops = &s2io_netdev_ops;
7977 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7978 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7979
7980 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7981 if (sp->high_dma_flag == true)
7982 dev->features |= NETIF_F_HIGHDMA;
7983 dev->features |= NETIF_F_TSO;
7984 dev->features |= NETIF_F_TSO6;
7985 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7986 dev->features |= NETIF_F_UFO;
7987 dev->features |= NETIF_F_HW_CSUM;
7988 }
7989 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7990 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7991 INIT_WORK(&sp->set_link_task, s2io_set_link);
7992
7993 pci_save_state(sp->pdev);
7994
7995 /* Setting swapper control on the NIC, for proper reset operation */
7996 if (s2io_set_swapper(sp)) {
7997 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7998 dev->name);
7999 ret = -EAGAIN;
8000 goto set_swap_failed;
8001 }
8002
8003 /* Verify if the Herc works on the slot its placed into */
8004 if (sp->device_type & XFRAME_II_DEVICE) {
8005 mode = s2io_verify_pci_mode(sp);
8006 if (mode < 0) {
8007 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8008 __func__);
8009 ret = -EBADSLT;
8010 goto set_swap_failed;
8011 }
8012 }
8013
8014 if (sp->config.intr_type == MSI_X) {
8015 sp->num_entries = config->rx_ring_num + 1;
8016 ret = s2io_enable_msi_x(sp);
8017
8018 if (!ret) {
8019 ret = s2io_test_msi(sp);
8020 /* rollback MSI-X, will re-enable during add_isr() */
8021 remove_msix_isr(sp);
8022 }
8023 if (ret) {
8024
8025 DBG_PRINT(ERR_DBG,
8026 "MSI-X requested but failed to enable\n");
8027 sp->config.intr_type = INTA;
8028 }
8029 }
8030
8031 if (config->intr_type == MSI_X) {
8032 for (i = 0; i < config->rx_ring_num ; i++) {
8033 struct ring_info *ring = &mac_control->rings[i];
8034
8035 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8036 }
8037 } else {
8038 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8039 }
8040
8041 /* Not needed for Herc */
8042 if (sp->device_type & XFRAME_I_DEVICE) {
8043 /*
8044 * Fix for all "FFs" MAC address problems observed on
8045 * Alpha platforms
8046 */
8047 fix_mac_address(sp);
8048 s2io_reset(sp);
8049 }
8050
8051 /*
8052 * MAC address initialization.
8053 * For now only one mac address will be read and used.
8054 */
8055 bar0 = sp->bar0;
8056 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8057 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8058 writeq(val64, &bar0->rmac_addr_cmd_mem);
8059 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8060 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8061 S2IO_BIT_RESET);
8062 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8063 mac_down = (u32)tmp64;
8064 mac_up = (u32) (tmp64 >> 32);
8065
8066 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8067 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8068 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8069 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8070 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8071 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8072
8073 /* Set the factory defined MAC address initially */
8074 dev->addr_len = ETH_ALEN;
8075 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8076 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8077
8078 /* initialize number of multicast & unicast MAC entries variables */
8079 if (sp->device_type == XFRAME_I_DEVICE) {
8080 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8081 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8082 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8083 } else if (sp->device_type == XFRAME_II_DEVICE) {
8084 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8085 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8086 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8087 }
8088
8089 /* store mac addresses from CAM to s2io_nic structure */
8090 do_s2io_store_unicast_mc(sp);
8091
8092 /* Configure MSIX vector for number of rings configured plus one */
8093 if ((sp->device_type == XFRAME_II_DEVICE) &&
8094 (config->intr_type == MSI_X))
8095 sp->num_entries = config->rx_ring_num + 1;
8096
8097 /* Store the values of the MSIX table in the s2io_nic structure */
8098 store_xmsi_data(sp);
8099 /* reset Nic and bring it to known state */
8100 s2io_reset(sp);
8101
8102 /*
8103 * Initialize link state flags
8104 * and the card state parameter
8105 */
8106 sp->state = 0;
8107
8108 /* Initialize spinlocks */
8109 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8110 struct fifo_info *fifo = &mac_control->fifos[i];
8111
8112 spin_lock_init(&fifo->tx_lock);
8113 }
8114
8115 /*
8116 * SXE-002: Configure link and activity LED to init state
8117 * on driver load.
8118 */
8119 subid = sp->pdev->subsystem_device;
8120 if ((subid & 0xFF) >= 0x07) {
8121 val64 = readq(&bar0->gpio_control);
8122 val64 |= 0x0000800000000000ULL;
8123 writeq(val64, &bar0->gpio_control);
8124 val64 = 0x0411040400000000ULL;
8125 writeq(val64, (void __iomem *)bar0 + 0x2700);
8126 val64 = readq(&bar0->gpio_control);
8127 }
8128
8129 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8130
8131 if (register_netdev(dev)) {
8132 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8133 ret = -ENODEV;
8134 goto register_failed;
8135 }
8136 s2io_vpd_read(sp);
8137 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8138 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8139 sp->product_name, pdev->revision);
8140 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8141 s2io_driver_version);
8142 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8143 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8144 if (sp->device_type & XFRAME_II_DEVICE) {
8145 mode = s2io_print_pci_mode(sp);
8146 if (mode < 0) {
8147 ret = -EBADSLT;
8148 unregister_netdev(dev);
8149 goto set_swap_failed;
8150 }
8151 }
8152 switch (sp->rxd_mode) {
8153 case RXD_MODE_1:
8154 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8155 dev->name);
8156 break;
8157 case RXD_MODE_3B:
8158 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8159 dev->name);
8160 break;
8161 }
8162
8163 switch (sp->config.napi) {
8164 case 0:
8165 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8166 break;
8167 case 1:
8168 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8169 break;
8170 }
8171
8172 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8173 sp->config.tx_fifo_num);
8174
8175 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8176 sp->config.rx_ring_num);
8177
8178 switch (sp->config.intr_type) {
8179 case INTA:
8180 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8181 break;
8182 case MSI_X:
8183 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8184 break;
8185 }
8186 if (sp->config.multiq) {
8187 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8188 struct fifo_info *fifo = &mac_control->fifos[i];
8189
8190 fifo->multiq = config->multiq;
8191 }
8192 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8193 dev->name);
8194 } else
8195 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8196 dev->name);
8197
8198 switch (sp->config.tx_steering_type) {
8199 case NO_STEERING:
8200 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8201 dev->name);
8202 break;
8203 case TX_PRIORITY_STEERING:
8204 DBG_PRINT(ERR_DBG,
8205 "%s: Priority steering enabled for transmit\n",
8206 dev->name);
8207 break;
8208 case TX_DEFAULT_STEERING:
8209 DBG_PRINT(ERR_DBG,
8210 "%s: Default steering enabled for transmit\n",
8211 dev->name);
8212 }
8213
8214 if (sp->lro)
8215 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8216 dev->name);
8217 if (ufo)
8218 DBG_PRINT(ERR_DBG,
8219 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8220 dev->name);
8221 /* Initialize device name */
8222 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8223
8224 if (vlan_tag_strip)
8225 sp->vlan_strip_flag = 1;
8226 else
8227 sp->vlan_strip_flag = 0;
8228
8229 /*
8230 * Make Link state as off at this point, when the Link change
8231 * interrupt comes the state will be automatically changed to
8232 * the right state.
8233 */
8234 netif_carrier_off(dev);
8235
8236 return 0;
8237
8238 register_failed:
8239 set_swap_failed:
8240 iounmap(sp->bar1);
8241 bar1_remap_failed:
8242 iounmap(sp->bar0);
8243 bar0_remap_failed:
8244 mem_alloc_failed:
8245 free_shared_mem(sp);
8246 pci_disable_device(pdev);
8247 pci_release_regions(pdev);
8248 pci_set_drvdata(pdev, NULL);
8249 free_netdev(dev);
8250
8251 return ret;
8252 }
8253
8254 /**
8255 * s2io_rem_nic - Free the PCI device
8256 * @pdev: structure containing the PCI related information of the device.
8257 * Description: This function is called by the Pci subsystem to release a
8258 * PCI device and free up all resource held up by the device. This could
8259 * be in response to a Hot plug event or when the driver is to be removed
8260 * from memory.
8261 */
8262
8263 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8264 {
8265 struct net_device *dev =
8266 (struct net_device *)pci_get_drvdata(pdev);
8267 struct s2io_nic *sp;
8268
8269 if (dev == NULL) {
8270 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8271 return;
8272 }
8273
8274 flush_scheduled_work();
8275
8276 sp = netdev_priv(dev);
8277 unregister_netdev(dev);
8278
8279 free_shared_mem(sp);
8280 iounmap(sp->bar0);
8281 iounmap(sp->bar1);
8282 pci_release_regions(pdev);
8283 pci_set_drvdata(pdev, NULL);
8284 free_netdev(dev);
8285 pci_disable_device(pdev);
8286 }
8287
8288 /**
8289 * s2io_starter - Entry point for the driver
8290 * Description: This function is the entry point for the driver. It verifies
8291 * the module loadable parameters and initializes PCI configuration space.
8292 */
8293
8294 static int __init s2io_starter(void)
8295 {
8296 return pci_register_driver(&s2io_driver);
8297 }
8298
8299 /**
8300 * s2io_closer - Cleanup routine for the driver
8301 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8302 */
8303
8304 static __exit void s2io_closer(void)
8305 {
8306 pci_unregister_driver(&s2io_driver);
8307 DBG_PRINT(INIT_DBG, "cleanup done\n");
8308 }
8309
8310 module_init(s2io_starter);
8311 module_exit(s2io_closer);
8312
8313 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8314 struct tcphdr **tcp, struct RxD_t *rxdp,
8315 struct s2io_nic *sp)
8316 {
8317 int ip_off;
8318 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8319
8320 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8321 DBG_PRINT(INIT_DBG,
8322 "%s: Non-TCP frames not supported for LRO\n",
8323 __func__);
8324 return -1;
8325 }
8326
8327 /* Checking for DIX type or DIX type with VLAN */
8328 if ((l2_type == 0) || (l2_type == 4)) {
8329 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8330 /*
8331 * If vlan stripping is disabled and the frame is VLAN tagged,
8332 * shift the offset by the VLAN header size bytes.
8333 */
8334 if ((!sp->vlan_strip_flag) &&
8335 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8336 ip_off += HEADER_VLAN_SIZE;
8337 } else {
8338 /* LLC, SNAP etc are considered non-mergeable */
8339 return -1;
8340 }
8341
8342 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8343 ip_len = (u8)((*ip)->ihl);
8344 ip_len <<= 2;
8345 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8346
8347 return 0;
8348 }
8349
8350 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8351 struct tcphdr *tcp)
8352 {
8353 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8354 if ((lro->iph->saddr != ip->saddr) ||
8355 (lro->iph->daddr != ip->daddr) ||
8356 (lro->tcph->source != tcp->source) ||
8357 (lro->tcph->dest != tcp->dest))
8358 return -1;
8359 return 0;
8360 }
8361
8362 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8363 {
8364 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8365 }
8366
8367 static void initiate_new_session(struct lro *lro, u8 *l2h,
8368 struct iphdr *ip, struct tcphdr *tcp,
8369 u32 tcp_pyld_len, u16 vlan_tag)
8370 {
8371 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8372 lro->l2h = l2h;
8373 lro->iph = ip;
8374 lro->tcph = tcp;
8375 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8376 lro->tcp_ack = tcp->ack_seq;
8377 lro->sg_num = 1;
8378 lro->total_len = ntohs(ip->tot_len);
8379 lro->frags_len = 0;
8380 lro->vlan_tag = vlan_tag;
8381 /*
8382 * Check if we saw TCP timestamp.
8383 * Other consistency checks have already been done.
8384 */
8385 if (tcp->doff == 8) {
8386 __be32 *ptr;
8387 ptr = (__be32 *)(tcp+1);
8388 lro->saw_ts = 1;
8389 lro->cur_tsval = ntohl(*(ptr+1));
8390 lro->cur_tsecr = *(ptr+2);
8391 }
8392 lro->in_use = 1;
8393 }
8394
8395 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8396 {
8397 struct iphdr *ip = lro->iph;
8398 struct tcphdr *tcp = lro->tcph;
8399 __sum16 nchk;
8400 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8401
8402 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8403
8404 /* Update L3 header */
8405 ip->tot_len = htons(lro->total_len);
8406 ip->check = 0;
8407 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8408 ip->check = nchk;
8409
8410 /* Update L4 header */
8411 tcp->ack_seq = lro->tcp_ack;
8412 tcp->window = lro->window;
8413
8414 /* Update tsecr field if this session has timestamps enabled */
8415 if (lro->saw_ts) {
8416 __be32 *ptr = (__be32 *)(tcp + 1);
8417 *(ptr+2) = lro->cur_tsecr;
8418 }
8419
8420 /* Update counters required for calculation of
8421 * average no. of packets aggregated.
8422 */
8423 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8424 swstats->num_aggregations++;
8425 }
8426
8427 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8428 struct tcphdr *tcp, u32 l4_pyld)
8429 {
8430 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8431 lro->total_len += l4_pyld;
8432 lro->frags_len += l4_pyld;
8433 lro->tcp_next_seq += l4_pyld;
8434 lro->sg_num++;
8435
8436 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8437 lro->tcp_ack = tcp->ack_seq;
8438 lro->window = tcp->window;
8439
8440 if (lro->saw_ts) {
8441 __be32 *ptr;
8442 /* Update tsecr and tsval from this packet */
8443 ptr = (__be32 *)(tcp+1);
8444 lro->cur_tsval = ntohl(*(ptr+1));
8445 lro->cur_tsecr = *(ptr + 2);
8446 }
8447 }
8448
8449 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8450 struct tcphdr *tcp, u32 tcp_pyld_len)
8451 {
8452 u8 *ptr;
8453
8454 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8455
8456 if (!tcp_pyld_len) {
8457 /* Runt frame or a pure ack */
8458 return -1;
8459 }
8460
8461 if (ip->ihl != 5) /* IP has options */
8462 return -1;
8463
8464 /* If we see CE codepoint in IP header, packet is not mergeable */
8465 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8466 return -1;
8467
8468 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8469 if (tcp->urg || tcp->psh || tcp->rst ||
8470 tcp->syn || tcp->fin ||
8471 tcp->ece || tcp->cwr || !tcp->ack) {
8472 /*
8473 * Currently recognize only the ack control word and
8474 * any other control field being set would result in
8475 * flushing the LRO session
8476 */
8477 return -1;
8478 }
8479
8480 /*
8481 * Allow only one TCP timestamp option. Don't aggregate if
8482 * any other options are detected.
8483 */
8484 if (tcp->doff != 5 && tcp->doff != 8)
8485 return -1;
8486
8487 if (tcp->doff == 8) {
8488 ptr = (u8 *)(tcp + 1);
8489 while (*ptr == TCPOPT_NOP)
8490 ptr++;
8491 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8492 return -1;
8493
8494 /* Ensure timestamp value increases monotonically */
8495 if (l_lro)
8496 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8497 return -1;
8498
8499 /* timestamp echo reply should be non-zero */
8500 if (*((__be32 *)(ptr+6)) == 0)
8501 return -1;
8502 }
8503
8504 return 0;
8505 }
8506
8507 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8508 u8 **tcp, u32 *tcp_len, struct lro **lro,
8509 struct RxD_t *rxdp, struct s2io_nic *sp)
8510 {
8511 struct iphdr *ip;
8512 struct tcphdr *tcph;
8513 int ret = 0, i;
8514 u16 vlan_tag = 0;
8515 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8516
8517 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8518 rxdp, sp);
8519 if (ret)
8520 return ret;
8521
8522 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8523
8524 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8525 tcph = (struct tcphdr *)*tcp;
8526 *tcp_len = get_l4_pyld_length(ip, tcph);
8527 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8528 struct lro *l_lro = &ring_data->lro0_n[i];
8529 if (l_lro->in_use) {
8530 if (check_for_socket_match(l_lro, ip, tcph))
8531 continue;
8532 /* Sock pair matched */
8533 *lro = l_lro;
8534
8535 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8536 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8537 "expected 0x%x, actual 0x%x\n",
8538 __func__,
8539 (*lro)->tcp_next_seq,
8540 ntohl(tcph->seq));
8541
8542 swstats->outof_sequence_pkts++;
8543 ret = 2;
8544 break;
8545 }
8546
8547 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8548 *tcp_len))
8549 ret = 1; /* Aggregate */
8550 else
8551 ret = 2; /* Flush both */
8552 break;
8553 }
8554 }
8555
8556 if (ret == 0) {
8557 /* Before searching for available LRO objects,
8558 * check if the pkt is L3/L4 aggregatable. If not
8559 * don't create new LRO session. Just send this
8560 * packet up.
8561 */
8562 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8563 return 5;
8564
8565 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8566 struct lro *l_lro = &ring_data->lro0_n[i];
8567 if (!(l_lro->in_use)) {
8568 *lro = l_lro;
8569 ret = 3; /* Begin anew */
8570 break;
8571 }
8572 }
8573 }
8574
8575 if (ret == 0) { /* sessions exceeded */
8576 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8577 __func__);
8578 *lro = NULL;
8579 return ret;
8580 }
8581
8582 switch (ret) {
8583 case 3:
8584 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8585 vlan_tag);
8586 break;
8587 case 2:
8588 update_L3L4_header(sp, *lro);
8589 break;
8590 case 1:
8591 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8592 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8593 update_L3L4_header(sp, *lro);
8594 ret = 4; /* Flush the LRO */
8595 }
8596 break;
8597 default:
8598 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8599 break;
8600 }
8601
8602 return ret;
8603 }
8604
8605 static void clear_lro_session(struct lro *lro)
8606 {
8607 static u16 lro_struct_size = sizeof(struct lro);
8608
8609 memset(lro, 0, lro_struct_size);
8610 }
8611
8612 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8613 {
8614 struct net_device *dev = skb->dev;
8615 struct s2io_nic *sp = netdev_priv(dev);
8616
8617 skb->protocol = eth_type_trans(skb, dev);
8618 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8619 /* Queueing the vlan frame to the upper layer */
8620 if (sp->config.napi)
8621 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8622 else
8623 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8624 } else {
8625 if (sp->config.napi)
8626 netif_receive_skb(skb);
8627 else
8628 netif_rx(skb);
8629 }
8630 }
8631
8632 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8633 struct sk_buff *skb, u32 tcp_len)
8634 {
8635 struct sk_buff *first = lro->parent;
8636 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8637
8638 first->len += tcp_len;
8639 first->data_len = lro->frags_len;
8640 skb_pull(skb, (skb->len - tcp_len));
8641 if (skb_shinfo(first)->frag_list)
8642 lro->last_frag->next = skb;
8643 else
8644 skb_shinfo(first)->frag_list = skb;
8645 first->truesize += skb->truesize;
8646 lro->last_frag = skb;
8647 swstats->clubbed_frms_cnt++;
8648 return;
8649 }
8650
8651 /**
8652 * s2io_io_error_detected - called when PCI error is detected
8653 * @pdev: Pointer to PCI device
8654 * @state: The current pci connection state
8655 *
8656 * This function is called after a PCI bus error affecting
8657 * this device has been detected.
8658 */
8659 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8660 pci_channel_state_t state)
8661 {
8662 struct net_device *netdev = pci_get_drvdata(pdev);
8663 struct s2io_nic *sp = netdev_priv(netdev);
8664
8665 netif_device_detach(netdev);
8666
8667 if (state == pci_channel_io_perm_failure)
8668 return PCI_ERS_RESULT_DISCONNECT;
8669
8670 if (netif_running(netdev)) {
8671 /* Bring down the card, while avoiding PCI I/O */
8672 do_s2io_card_down(sp, 0);
8673 }
8674 pci_disable_device(pdev);
8675
8676 return PCI_ERS_RESULT_NEED_RESET;
8677 }
8678
8679 /**
8680 * s2io_io_slot_reset - called after the pci bus has been reset.
8681 * @pdev: Pointer to PCI device
8682 *
8683 * Restart the card from scratch, as if from a cold-boot.
8684 * At this point, the card has exprienced a hard reset,
8685 * followed by fixups by BIOS, and has its config space
8686 * set up identically to what it was at cold boot.
8687 */
8688 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8689 {
8690 struct net_device *netdev = pci_get_drvdata(pdev);
8691 struct s2io_nic *sp = netdev_priv(netdev);
8692
8693 if (pci_enable_device(pdev)) {
8694 pr_err("Cannot re-enable PCI device after reset.\n");
8695 return PCI_ERS_RESULT_DISCONNECT;
8696 }
8697
8698 pci_set_master(pdev);
8699 s2io_reset(sp);
8700
8701 return PCI_ERS_RESULT_RECOVERED;
8702 }
8703
8704 /**
8705 * s2io_io_resume - called when traffic can start flowing again.
8706 * @pdev: Pointer to PCI device
8707 *
8708 * This callback is called when the error recovery driver tells
8709 * us that its OK to resume normal operation.
8710 */
8711 static void s2io_io_resume(struct pci_dev *pdev)
8712 {
8713 struct net_device *netdev = pci_get_drvdata(pdev);
8714 struct s2io_nic *sp = netdev_priv(netdev);
8715
8716 if (netif_running(netdev)) {
8717 if (s2io_card_up(sp)) {
8718 pr_err("Can't bring device back up after reset.\n");
8719 return;
8720 }
8721
8722 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8723 s2io_card_down(sp);
8724 pr_err("Can't restore mac addr after reset.\n");
8725 return;
8726 }
8727 }
8728
8729 netif_device_attach(netdev);
8730 netif_tx_wake_all_queues(netdev);
8731 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree