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ARM: JIVE: Update mach-jive to use gpiolib API
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e100.c
blob791080303db100cf7f5f53d961253846e6e3049e
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/sched.h>
155 #include <linux/slab.h>
156 #include <linux/delay.h>
157 #include <linux/init.h>
158 #include <linux/pci.h>
159 #include <linux/dma-mapping.h>
160 #include <linux/dmapool.h>
161 #include <linux/netdevice.h>
162 #include <linux/etherdevice.h>
163 #include <linux/mii.h>
164 #include <linux/if_vlan.h>
165 #include <linux/skbuff.h>
166 #include <linux/ethtool.h>
167 #include <linux/string.h>
168 #include <linux/firmware.h>
169 #include <linux/rtnetlink.h>
170 #include <asm/unaligned.h>
171
172
173 #define DRV_NAME "e100"
174 #define DRV_EXT "-NAPI"
175 #define DRV_VERSION "3.5.24-k2"DRV_EXT
176 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
177 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
178 #define PFX DRV_NAME ": "
179
180 #define E100_WATCHDOG_PERIOD (2 * HZ)
181 #define E100_NAPI_WEIGHT 16
182
183 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
184 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
185 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
186
187 MODULE_DESCRIPTION(DRV_DESCRIPTION);
188 MODULE_AUTHOR(DRV_COPYRIGHT);
189 MODULE_LICENSE("GPL");
190 MODULE_VERSION(DRV_VERSION);
191 MODULE_FIRMWARE(FIRMWARE_D101M);
192 MODULE_FIRMWARE(FIRMWARE_D101S);
193 MODULE_FIRMWARE(FIRMWARE_D102E);
194
195 static int debug = 3;
196 static int eeprom_bad_csum_allow = 0;
197 static int use_io = 0;
198 module_param(debug, int, 0);
199 module_param(eeprom_bad_csum_allow, int, 0);
200 module_param(use_io, int, 0);
201 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
202 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
203 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
204 #define DPRINTK(nlevel, klevel, fmt, args...) \
205 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
206 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
207 __func__ , ## args))
208
209 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
210 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
211 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
212 static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
213 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
219 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
220 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
225 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
226 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
233 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
234 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
235 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
242 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
243 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
247 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
248 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
249 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
250 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
251 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
253 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
254 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
255 { 0, }
256 };
257 MODULE_DEVICE_TABLE(pci, e100_id_table);
258
259 enum mac {
260 mac_82557_D100_A = 0,
261 mac_82557_D100_B = 1,
262 mac_82557_D100_C = 2,
263 mac_82558_D101_A4 = 4,
264 mac_82558_D101_B0 = 5,
265 mac_82559_D101M = 8,
266 mac_82559_D101S = 9,
267 mac_82550_D102 = 12,
268 mac_82550_D102_C = 13,
269 mac_82551_E = 14,
270 mac_82551_F = 15,
271 mac_82551_10 = 16,
272 mac_unknown = 0xFF,
273 };
274
275 enum phy {
276 phy_100a = 0x000003E0,
277 phy_100c = 0x035002A8,
278 phy_82555_tx = 0x015002A8,
279 phy_nsc_tx = 0x5C002000,
280 phy_82562_et = 0x033002A8,
281 phy_82562_em = 0x032002A8,
282 phy_82562_ek = 0x031002A8,
283 phy_82562_eh = 0x017002A8,
284 phy_82552_v = 0xd061004d,
285 phy_unknown = 0xFFFFFFFF,
286 };
287
288 /* CSR (Control/Status Registers) */
289 struct csr {
290 struct {
291 u8 status;
292 u8 stat_ack;
293 u8 cmd_lo;
294 u8 cmd_hi;
295 u32 gen_ptr;
296 } scb;
297 u32 port;
298 u16 flash_ctrl;
299 u8 eeprom_ctrl_lo;
300 u8 eeprom_ctrl_hi;
301 u32 mdi_ctrl;
302 u32 rx_dma_count;
303 };
304
305 enum scb_status {
306 rus_no_res = 0x08,
307 rus_ready = 0x10,
308 rus_mask = 0x3C,
309 };
310
311 enum ru_state {
312 RU_SUSPENDED = 0,
313 RU_RUNNING = 1,
314 RU_UNINITIALIZED = -1,
315 };
316
317 enum scb_stat_ack {
318 stat_ack_not_ours = 0x00,
319 stat_ack_sw_gen = 0x04,
320 stat_ack_rnr = 0x10,
321 stat_ack_cu_idle = 0x20,
322 stat_ack_frame_rx = 0x40,
323 stat_ack_cu_cmd_done = 0x80,
324 stat_ack_not_present = 0xFF,
325 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
326 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
327 };
328
329 enum scb_cmd_hi {
330 irq_mask_none = 0x00,
331 irq_mask_all = 0x01,
332 irq_sw_gen = 0x02,
333 };
334
335 enum scb_cmd_lo {
336 cuc_nop = 0x00,
337 ruc_start = 0x01,
338 ruc_load_base = 0x06,
339 cuc_start = 0x10,
340 cuc_resume = 0x20,
341 cuc_dump_addr = 0x40,
342 cuc_dump_stats = 0x50,
343 cuc_load_base = 0x60,
344 cuc_dump_reset = 0x70,
345 };
346
347 enum cuc_dump {
348 cuc_dump_complete = 0x0000A005,
349 cuc_dump_reset_complete = 0x0000A007,
350 };
351
352 enum port {
353 software_reset = 0x0000,
354 selftest = 0x0001,
355 selective_reset = 0x0002,
356 };
357
358 enum eeprom_ctrl_lo {
359 eesk = 0x01,
360 eecs = 0x02,
361 eedi = 0x04,
362 eedo = 0x08,
363 };
364
365 enum mdi_ctrl {
366 mdi_write = 0x04000000,
367 mdi_read = 0x08000000,
368 mdi_ready = 0x10000000,
369 };
370
371 enum eeprom_op {
372 op_write = 0x05,
373 op_read = 0x06,
374 op_ewds = 0x10,
375 op_ewen = 0x13,
376 };
377
378 enum eeprom_offsets {
379 eeprom_cnfg_mdix = 0x03,
380 eeprom_phy_iface = 0x06,
381 eeprom_id = 0x0A,
382 eeprom_config_asf = 0x0D,
383 eeprom_smbus_addr = 0x90,
384 };
385
386 enum eeprom_cnfg_mdix {
387 eeprom_mdix_enabled = 0x0080,
388 };
389
390 enum eeprom_phy_iface {
391 NoSuchPhy = 0,
392 I82553AB,
393 I82553C,
394 I82503,
395 DP83840,
396 S80C240,
397 S80C24,
398 I82555,
399 DP83840A = 10,
400 };
401
402 enum eeprom_id {
403 eeprom_id_wol = 0x0020,
404 };
405
406 enum eeprom_config_asf {
407 eeprom_asf = 0x8000,
408 eeprom_gcl = 0x4000,
409 };
410
411 enum cb_status {
412 cb_complete = 0x8000,
413 cb_ok = 0x2000,
414 };
415
416 enum cb_command {
417 cb_nop = 0x0000,
418 cb_iaaddr = 0x0001,
419 cb_config = 0x0002,
420 cb_multi = 0x0003,
421 cb_tx = 0x0004,
422 cb_ucode = 0x0005,
423 cb_dump = 0x0006,
424 cb_tx_sf = 0x0008,
425 cb_cid = 0x1f00,
426 cb_i = 0x2000,
427 cb_s = 0x4000,
428 cb_el = 0x8000,
429 };
430
431 struct rfd {
432 __le16 status;
433 __le16 command;
434 __le32 link;
435 __le32 rbd;
436 __le16 actual_size;
437 __le16 size;
438 };
439
440 struct rx {
441 struct rx *next, *prev;
442 struct sk_buff *skb;
443 dma_addr_t dma_addr;
444 };
445
446 #if defined(__BIG_ENDIAN_BITFIELD)
447 #define X(a,b) b,a
448 #else
449 #define X(a,b) a,b
450 #endif
451 struct config {
452 /*0*/ u8 X(byte_count:6, pad0:2);
453 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
454 /*2*/ u8 adaptive_ifs;
455 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
456 term_write_cache_line:1), pad3:4);
457 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
458 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
459 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
460 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
461 rx_discard_overruns:1), rx_save_bad_frames:1);
462 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
463 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
464 tx_dynamic_tbd:1);
465 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
466 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
467 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
468 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
469 loopback:2);
470 /*11*/ u8 X(linear_priority:3, pad11:5);
471 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
472 /*13*/ u8 ip_addr_lo;
473 /*14*/ u8 ip_addr_hi;
474 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
475 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
476 pad15_2:1), crs_or_cdt:1);
477 /*16*/ u8 fc_delay_lo;
478 /*17*/ u8 fc_delay_hi;
479 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
480 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
481 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
482 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
483 full_duplex_force:1), full_duplex_pin:1);
484 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
485 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
486 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
487 u8 pad_d102[9];
488 };
489
490 #define E100_MAX_MULTICAST_ADDRS 64
491 struct multi {
492 __le16 count;
493 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
494 };
495
496 /* Important: keep total struct u32-aligned */
497 #define UCODE_SIZE 134
498 struct cb {
499 __le16 status;
500 __le16 command;
501 __le32 link;
502 union {
503 u8 iaaddr[ETH_ALEN];
504 __le32 ucode[UCODE_SIZE];
505 struct config config;
506 struct multi multi;
507 struct {
508 u32 tbd_array;
509 u16 tcb_byte_count;
510 u8 threshold;
511 u8 tbd_count;
512 struct {
513 __le32 buf_addr;
514 __le16 size;
515 u16 eol;
516 } tbd;
517 } tcb;
518 __le32 dump_buffer_addr;
519 } u;
520 struct cb *next, *prev;
521 dma_addr_t dma_addr;
522 struct sk_buff *skb;
523 };
524
525 enum loopback {
526 lb_none = 0, lb_mac = 1, lb_phy = 3,
527 };
528
529 struct stats {
530 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
531 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
532 tx_multiple_collisions, tx_total_collisions;
533 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
534 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
535 rx_short_frame_errors;
536 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
537 __le16 xmt_tco_frames, rcv_tco_frames;
538 __le32 complete;
539 };
540
541 struct mem {
542 struct {
543 u32 signature;
544 u32 result;
545 } selftest;
546 struct stats stats;
547 u8 dump_buf[596];
548 };
549
550 struct param_range {
551 u32 min;
552 u32 max;
553 u32 count;
554 };
555
556 struct params {
557 struct param_range rfds;
558 struct param_range cbs;
559 };
560
561 struct nic {
562 /* Begin: frequently used values: keep adjacent for cache effect */
563 u32 msg_enable ____cacheline_aligned;
564 struct net_device *netdev;
565 struct pci_dev *pdev;
566 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
567
568 struct rx *rxs ____cacheline_aligned;
569 struct rx *rx_to_use;
570 struct rx *rx_to_clean;
571 struct rfd blank_rfd;
572 enum ru_state ru_running;
573
574 spinlock_t cb_lock ____cacheline_aligned;
575 spinlock_t cmd_lock;
576 struct csr __iomem *csr;
577 enum scb_cmd_lo cuc_cmd;
578 unsigned int cbs_avail;
579 struct napi_struct napi;
580 struct cb *cbs;
581 struct cb *cb_to_use;
582 struct cb *cb_to_send;
583 struct cb *cb_to_clean;
584 __le16 tx_command;
585 /* End: frequently used values: keep adjacent for cache effect */
586
587 enum {
588 ich = (1 << 0),
589 promiscuous = (1 << 1),
590 multicast_all = (1 << 2),
591 wol_magic = (1 << 3),
592 ich_10h_workaround = (1 << 4),
593 } flags ____cacheline_aligned;
594
595 enum mac mac;
596 enum phy phy;
597 struct params params;
598 struct timer_list watchdog;
599 struct timer_list blink_timer;
600 struct mii_if_info mii;
601 struct work_struct tx_timeout_task;
602 enum loopback loopback;
603
604 struct mem *mem;
605 dma_addr_t dma_addr;
606
607 struct pci_pool *cbs_pool;
608 dma_addr_t cbs_dma_addr;
609 u8 adaptive_ifs;
610 u8 tx_threshold;
611 u32 tx_frames;
612 u32 tx_collisions;
613 u32 tx_deferred;
614 u32 tx_single_collisions;
615 u32 tx_multiple_collisions;
616 u32 tx_fc_pause;
617 u32 tx_tco_frames;
618
619 u32 rx_fc_pause;
620 u32 rx_fc_unsupported;
621 u32 rx_tco_frames;
622 u32 rx_over_length_errors;
623
624 u16 leds;
625 u16 eeprom_wc;
626 __le16 eeprom[256];
627 spinlock_t mdio_lock;
628 const struct firmware *fw;
629 };
630
631 static inline void e100_write_flush(struct nic *nic)
632 {
633 /* Flush previous PCI writes through intermediate bridges
634 * by doing a benign read */
635 (void)ioread8(&nic->csr->scb.status);
636 }
637
638 static void e100_enable_irq(struct nic *nic)
639 {
640 unsigned long flags;
641
642 spin_lock_irqsave(&nic->cmd_lock, flags);
643 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
644 e100_write_flush(nic);
645 spin_unlock_irqrestore(&nic->cmd_lock, flags);
646 }
647
648 static void e100_disable_irq(struct nic *nic)
649 {
650 unsigned long flags;
651
652 spin_lock_irqsave(&nic->cmd_lock, flags);
653 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
654 e100_write_flush(nic);
655 spin_unlock_irqrestore(&nic->cmd_lock, flags);
656 }
657
658 static void e100_hw_reset(struct nic *nic)
659 {
660 /* Put CU and RU into idle with a selective reset to get
661 * device off of PCI bus */
662 iowrite32(selective_reset, &nic->csr->port);
663 e100_write_flush(nic); udelay(20);
664
665 /* Now fully reset device */
666 iowrite32(software_reset, &nic->csr->port);
667 e100_write_flush(nic); udelay(20);
668
669 /* Mask off our interrupt line - it's unmasked after reset */
670 e100_disable_irq(nic);
671 }
672
673 static int e100_self_test(struct nic *nic)
674 {
675 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
676
677 /* Passing the self-test is a pretty good indication
678 * that the device can DMA to/from host memory */
679
680 nic->mem->selftest.signature = 0;
681 nic->mem->selftest.result = 0xFFFFFFFF;
682
683 iowrite32(selftest | dma_addr, &nic->csr->port);
684 e100_write_flush(nic);
685 /* Wait 10 msec for self-test to complete */
686 msleep(10);
687
688 /* Interrupts are enabled after self-test */
689 e100_disable_irq(nic);
690
691 /* Check results of self-test */
692 if (nic->mem->selftest.result != 0) {
693 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
694 nic->mem->selftest.result);
695 return -ETIMEDOUT;
696 }
697 if (nic->mem->selftest.signature == 0) {
698 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
699 return -ETIMEDOUT;
700 }
701
702 return 0;
703 }
704
705 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
706 {
707 u32 cmd_addr_data[3];
708 u8 ctrl;
709 int i, j;
710
711 /* Three cmds: write/erase enable, write data, write/erase disable */
712 cmd_addr_data[0] = op_ewen << (addr_len - 2);
713 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
714 le16_to_cpu(data);
715 cmd_addr_data[2] = op_ewds << (addr_len - 2);
716
717 /* Bit-bang cmds to write word to eeprom */
718 for (j = 0; j < 3; j++) {
719
720 /* Chip select */
721 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
722 e100_write_flush(nic); udelay(4);
723
724 for (i = 31; i >= 0; i--) {
725 ctrl = (cmd_addr_data[j] & (1 << i)) ?
726 eecs | eedi : eecs;
727 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
728 e100_write_flush(nic); udelay(4);
729
730 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
731 e100_write_flush(nic); udelay(4);
732 }
733 /* Wait 10 msec for cmd to complete */
734 msleep(10);
735
736 /* Chip deselect */
737 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
738 e100_write_flush(nic); udelay(4);
739 }
740 };
741
742 /* General technique stolen from the eepro100 driver - very clever */
743 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
744 {
745 u32 cmd_addr_data;
746 u16 data = 0;
747 u8 ctrl;
748 int i;
749
750 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
751
752 /* Chip select */
753 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
754 e100_write_flush(nic); udelay(4);
755
756 /* Bit-bang to read word from eeprom */
757 for (i = 31; i >= 0; i--) {
758 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
759 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
760 e100_write_flush(nic); udelay(4);
761
762 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
763 e100_write_flush(nic); udelay(4);
764
765 /* Eeprom drives a dummy zero to EEDO after receiving
766 * complete address. Use this to adjust addr_len. */
767 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
768 if (!(ctrl & eedo) && i > 16) {
769 *addr_len -= (i - 16);
770 i = 17;
771 }
772
773 data = (data << 1) | (ctrl & eedo ? 1 : 0);
774 }
775
776 /* Chip deselect */
777 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
778 e100_write_flush(nic); udelay(4);
779
780 return cpu_to_le16(data);
781 };
782
783 /* Load entire EEPROM image into driver cache and validate checksum */
784 static int e100_eeprom_load(struct nic *nic)
785 {
786 u16 addr, addr_len = 8, checksum = 0;
787
788 /* Try reading with an 8-bit addr len to discover actual addr len */
789 e100_eeprom_read(nic, &addr_len, 0);
790 nic->eeprom_wc = 1 << addr_len;
791
792 for (addr = 0; addr < nic->eeprom_wc; addr++) {
793 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
794 if (addr < nic->eeprom_wc - 1)
795 checksum += le16_to_cpu(nic->eeprom[addr]);
796 }
797
798 /* The checksum, stored in the last word, is calculated such that
799 * the sum of words should be 0xBABA */
800 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
801 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
802 if (!eeprom_bad_csum_allow)
803 return -EAGAIN;
804 }
805
806 return 0;
807 }
808
809 /* Save (portion of) driver EEPROM cache to device and update checksum */
810 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
811 {
812 u16 addr, addr_len = 8, checksum = 0;
813
814 /* Try reading with an 8-bit addr len to discover actual addr len */
815 e100_eeprom_read(nic, &addr_len, 0);
816 nic->eeprom_wc = 1 << addr_len;
817
818 if (start + count >= nic->eeprom_wc)
819 return -EINVAL;
820
821 for (addr = start; addr < start + count; addr++)
822 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
823
824 /* The checksum, stored in the last word, is calculated such that
825 * the sum of words should be 0xBABA */
826 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
827 checksum += le16_to_cpu(nic->eeprom[addr]);
828 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
829 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
830 nic->eeprom[nic->eeprom_wc - 1]);
831
832 return 0;
833 }
834
835 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
836 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
837 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
838 {
839 unsigned long flags;
840 unsigned int i;
841 int err = 0;
842
843 spin_lock_irqsave(&nic->cmd_lock, flags);
844
845 /* Previous command is accepted when SCB clears */
846 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
847 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
848 break;
849 cpu_relax();
850 if (unlikely(i > E100_WAIT_SCB_FAST))
851 udelay(5);
852 }
853 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
854 err = -EAGAIN;
855 goto err_unlock;
856 }
857
858 if (unlikely(cmd != cuc_resume))
859 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
860 iowrite8(cmd, &nic->csr->scb.cmd_lo);
861
862 err_unlock:
863 spin_unlock_irqrestore(&nic->cmd_lock, flags);
864
865 return err;
866 }
867
868 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
869 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
870 {
871 struct cb *cb;
872 unsigned long flags;
873 int err = 0;
874
875 spin_lock_irqsave(&nic->cb_lock, flags);
876
877 if (unlikely(!nic->cbs_avail)) {
878 err = -ENOMEM;
879 goto err_unlock;
880 }
881
882 cb = nic->cb_to_use;
883 nic->cb_to_use = cb->next;
884 nic->cbs_avail--;
885 cb->skb = skb;
886
887 if (unlikely(!nic->cbs_avail))
888 err = -ENOSPC;
889
890 cb_prepare(nic, cb, skb);
891
892 /* Order is important otherwise we'll be in a race with h/w:
893 * set S-bit in current first, then clear S-bit in previous. */
894 cb->command |= cpu_to_le16(cb_s);
895 wmb();
896 cb->prev->command &= cpu_to_le16(~cb_s);
897
898 while (nic->cb_to_send != nic->cb_to_use) {
899 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
900 nic->cb_to_send->dma_addr))) {
901 /* Ok, here's where things get sticky. It's
902 * possible that we can't schedule the command
903 * because the controller is too busy, so
904 * let's just queue the command and try again
905 * when another command is scheduled. */
906 if (err == -ENOSPC) {
907 //request a reset
908 schedule_work(&nic->tx_timeout_task);
909 }
910 break;
911 } else {
912 nic->cuc_cmd = cuc_resume;
913 nic->cb_to_send = nic->cb_to_send->next;
914 }
915 }
916
917 err_unlock:
918 spin_unlock_irqrestore(&nic->cb_lock, flags);
919
920 return err;
921 }
922
923 static int mdio_read(struct net_device *netdev, int addr, int reg)
924 {
925 struct nic *nic = netdev_priv(netdev);
926 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
927 }
928
929 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
930 {
931 struct nic *nic = netdev_priv(netdev);
932
933 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
934 }
935
936 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
937 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
938 {
939 u32 data_out = 0;
940 unsigned int i;
941 unsigned long flags;
942
943
944 /*
945 * Stratus87247: we shouldn't be writing the MDI control
946 * register until the Ready bit shows True. Also, since
947 * manipulation of the MDI control registers is a multi-step
948 * procedure it should be done under lock.
949 */
950 spin_lock_irqsave(&nic->mdio_lock, flags);
951 for (i = 100; i; --i) {
952 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
953 break;
954 udelay(20);
955 }
956 if (unlikely(!i)) {
957 printk("e100.mdio_ctrl(%s) won't go Ready\n",
958 nic->netdev->name );
959 spin_unlock_irqrestore(&nic->mdio_lock, flags);
960 return 0; /* No way to indicate timeout error */
961 }
962 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
963
964 for (i = 0; i < 100; i++) {
965 udelay(20);
966 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
967 break;
968 }
969 spin_unlock_irqrestore(&nic->mdio_lock, flags);
970 DPRINTK(HW, DEBUG,
971 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
972 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
973 return (u16)data_out;
974 }
975
976 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
977 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
978 u32 addr,
979 u32 dir,
980 u32 reg,
981 u16 data)
982 {
983 if ((reg == MII_BMCR) && (dir == mdi_write)) {
984 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
985 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
986 MII_ADVERTISE);
987
988 /*
989 * Workaround Si issue where sometimes the part will not
990 * autoneg to 100Mbps even when advertised.
991 */
992 if (advert & ADVERTISE_100FULL)
993 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
994 else if (advert & ADVERTISE_100HALF)
995 data |= BMCR_SPEED100;
996 }
997 }
998 return mdio_ctrl_hw(nic, addr, dir, reg, data);
999 }
1000
1001 /* Fully software-emulated mdio_ctrl() function for cards without
1002 * MII-compliant PHYs.
1003 * For now, this is mainly geared towards 80c24 support; in case of further
1004 * requirements for other types (i82503, ...?) either extend this mechanism
1005 * or split it, whichever is cleaner.
1006 */
1007 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1008 u32 addr,
1009 u32 dir,
1010 u32 reg,
1011 u16 data)
1012 {
1013 /* might need to allocate a netdev_priv'ed register array eventually
1014 * to be able to record state changes, but for now
1015 * some fully hardcoded register handling ought to be ok I guess. */
1016
1017 if (dir == mdi_read) {
1018 switch (reg) {
1019 case MII_BMCR:
1020 /* Auto-negotiation, right? */
1021 return BMCR_ANENABLE |
1022 BMCR_FULLDPLX;
1023 case MII_BMSR:
1024 return BMSR_LSTATUS /* for mii_link_ok() */ |
1025 BMSR_ANEGCAPABLE |
1026 BMSR_10FULL;
1027 case MII_ADVERTISE:
1028 /* 80c24 is a "combo card" PHY, right? */
1029 return ADVERTISE_10HALF |
1030 ADVERTISE_10FULL;
1031 default:
1032 DPRINTK(HW, DEBUG,
1033 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1034 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1035 return 0xFFFF;
1036 }
1037 } else {
1038 switch (reg) {
1039 default:
1040 DPRINTK(HW, DEBUG,
1041 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1042 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1043 return 0xFFFF;
1044 }
1045 }
1046 }
1047 static inline int e100_phy_supports_mii(struct nic *nic)
1048 {
1049 /* for now, just check it by comparing whether we
1050 are using MII software emulation.
1051 */
1052 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1053 }
1054
1055 static void e100_get_defaults(struct nic *nic)
1056 {
1057 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1058 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1059
1060 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1061 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1062 if (nic->mac == mac_unknown)
1063 nic->mac = mac_82557_D100_A;
1064
1065 nic->params.rfds = rfds;
1066 nic->params.cbs = cbs;
1067
1068 /* Quadwords to DMA into FIFO before starting frame transmit */
1069 nic->tx_threshold = 0xE0;
1070
1071 /* no interrupt for every tx completion, delay = 256us if not 557 */
1072 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1073 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1074
1075 /* Template for a freshly allocated RFD */
1076 nic->blank_rfd.command = 0;
1077 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1078 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1079
1080 /* MII setup */
1081 nic->mii.phy_id_mask = 0x1F;
1082 nic->mii.reg_num_mask = 0x1F;
1083 nic->mii.dev = nic->netdev;
1084 nic->mii.mdio_read = mdio_read;
1085 nic->mii.mdio_write = mdio_write;
1086 }
1087
1088 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1089 {
1090 struct config *config = &cb->u.config;
1091 u8 *c = (u8 *)config;
1092
1093 cb->command = cpu_to_le16(cb_config);
1094
1095 memset(config, 0, sizeof(struct config));
1096
1097 config->byte_count = 0x16; /* bytes in this struct */
1098 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1099 config->direct_rx_dma = 0x1; /* reserved */
1100 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1101 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1102 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1103 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1104 if (e100_phy_supports_mii(nic))
1105 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1106 config->pad10 = 0x6;
1107 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1108 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1109 config->ifs = 0x6; /* x16 = inter frame spacing */
1110 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1111 config->pad15_1 = 0x1;
1112 config->pad15_2 = 0x1;
1113 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1114 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1115 config->tx_padding = 0x1; /* 1=pad short frames */
1116 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1117 config->pad18 = 0x1;
1118 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1119 config->pad20_1 = 0x1F;
1120 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1121 config->pad21_1 = 0x5;
1122
1123 config->adaptive_ifs = nic->adaptive_ifs;
1124 config->loopback = nic->loopback;
1125
1126 if (nic->mii.force_media && nic->mii.full_duplex)
1127 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1128
1129 if (nic->flags & promiscuous || nic->loopback) {
1130 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1131 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1132 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1133 }
1134
1135 if (nic->flags & multicast_all)
1136 config->multicast_all = 0x1; /* 1=accept, 0=no */
1137
1138 /* disable WoL when up */
1139 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1140 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1141
1142 if (nic->mac >= mac_82558_D101_A4) {
1143 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1144 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1145 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1146 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1147 if (nic->mac >= mac_82559_D101M) {
1148 config->tno_intr = 0x1; /* TCO stats enable */
1149 /* Enable TCO in extended config */
1150 if (nic->mac >= mac_82551_10) {
1151 config->byte_count = 0x20; /* extended bytes */
1152 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1153 }
1154 } else {
1155 config->standard_stat_counter = 0x0;
1156 }
1157 }
1158
1159 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1160 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1161 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1162 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1163 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1164 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1165 }
1166
1167 /*************************************************************************
1168 * CPUSaver parameters
1169 *
1170 * All CPUSaver parameters are 16-bit literals that are part of a
1171 * "move immediate value" instruction. By changing the value of
1172 * the literal in the instruction before the code is loaded, the
1173 * driver can change the algorithm.
1174 *
1175 * INTDELAY - This loads the dead-man timer with its initial value.
1176 * When this timer expires the interrupt is asserted, and the
1177 * timer is reset each time a new packet is received. (see
1178 * BUNDLEMAX below to set the limit on number of chained packets)
1179 * The current default is 0x600 or 1536. Experiments show that
1180 * the value should probably stay within the 0x200 - 0x1000.
1181 *
1182 * BUNDLEMAX -
1183 * This sets the maximum number of frames that will be bundled. In
1184 * some situations, such as the TCP windowing algorithm, it may be
1185 * better to limit the growth of the bundle size than let it go as
1186 * high as it can, because that could cause too much added latency.
1187 * The default is six, because this is the number of packets in the
1188 * default TCP window size. A value of 1 would make CPUSaver indicate
1189 * an interrupt for every frame received. If you do not want to put
1190 * a limit on the bundle size, set this value to xFFFF.
1191 *
1192 * BUNDLESMALL -
1193 * This contains a bit-mask describing the minimum size frame that
1194 * will be bundled. The default masks the lower 7 bits, which means
1195 * that any frame less than 128 bytes in length will not be bundled,
1196 * but will instead immediately generate an interrupt. This does
1197 * not affect the current bundle in any way. Any frame that is 128
1198 * bytes or large will be bundled normally. This feature is meant
1199 * to provide immediate indication of ACK frames in a TCP environment.
1200 * Customers were seeing poor performance when a machine with CPUSaver
1201 * enabled was sending but not receiving. The delay introduced when
1202 * the ACKs were received was enough to reduce total throughput, because
1203 * the sender would sit idle until the ACK was finally seen.
1204 *
1205 * The current default is 0xFF80, which masks out the lower 7 bits.
1206 * This means that any frame which is x7F (127) bytes or smaller
1207 * will cause an immediate interrupt. Because this value must be a
1208 * bit mask, there are only a few valid values that can be used. To
1209 * turn this feature off, the driver can write the value xFFFF to the
1210 * lower word of this instruction (in the same way that the other
1211 * parameters are used). Likewise, a value of 0xF800 (2047) would
1212 * cause an interrupt to be generated for every frame, because all
1213 * standard Ethernet frames are <= 2047 bytes in length.
1214 *************************************************************************/
1215
1216 /* if you wish to disable the ucode functionality, while maintaining the
1217 * workarounds it provides, set the following defines to:
1218 * BUNDLESMALL 0
1219 * BUNDLEMAX 1
1220 * INTDELAY 1
1221 */
1222 #define BUNDLESMALL 1
1223 #define BUNDLEMAX (u16)6
1224 #define INTDELAY (u16)1536 /* 0x600 */
1225
1226 /* Initialize firmware */
1227 static const struct firmware *e100_request_firmware(struct nic *nic)
1228 {
1229 const char *fw_name;
1230 const struct firmware *fw = nic->fw;
1231 u8 timer, bundle, min_size;
1232 int err = 0;
1233
1234 /* do not load u-code for ICH devices */
1235 if (nic->flags & ich)
1236 return NULL;
1237
1238 /* Search for ucode match against h/w revision */
1239 if (nic->mac == mac_82559_D101M)
1240 fw_name = FIRMWARE_D101M;
1241 else if (nic->mac == mac_82559_D101S)
1242 fw_name = FIRMWARE_D101S;
1243 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1244 fw_name = FIRMWARE_D102E;
1245 else /* No ucode on other devices */
1246 return NULL;
1247
1248 /* If the firmware has not previously been loaded, request a pointer
1249 * to it. If it was previously loaded, we are reinitializing the
1250 * adapter, possibly in a resume from hibernate, in which case
1251 * request_firmware() cannot be used.
1252 */
1253 if (!fw)
1254 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1255
1256 if (err) {
1257 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1258 fw_name, err);
1259 return ERR_PTR(err);
1260 }
1261
1262 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1263 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1264 if (fw->size != UCODE_SIZE * 4 + 3) {
1265 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1266 fw_name, fw->size);
1267 release_firmware(fw);
1268 return ERR_PTR(-EINVAL);
1269 }
1270
1271 /* Read timer, bundle and min_size from end of firmware blob */
1272 timer = fw->data[UCODE_SIZE * 4];
1273 bundle = fw->data[UCODE_SIZE * 4 + 1];
1274 min_size = fw->data[UCODE_SIZE * 4 + 2];
1275
1276 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1277 min_size >= UCODE_SIZE) {
1278 DPRINTK(PROBE, ERR,
1279 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1280 fw_name, timer, bundle, min_size);
1281 release_firmware(fw);
1282 return ERR_PTR(-EINVAL);
1283 }
1284
1285 /* OK, firmware is validated and ready to use. Save a pointer
1286 * to it in the nic */
1287 nic->fw = fw;
1288 return fw;
1289 }
1290
1291 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1292 struct sk_buff *skb)
1293 {
1294 const struct firmware *fw = (void *)skb;
1295 u8 timer, bundle, min_size;
1296
1297 /* It's not a real skb; we just abused the fact that e100_exec_cb
1298 will pass it through to here... */
1299 cb->skb = NULL;
1300
1301 /* firmware is stored as little endian already */
1302 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1303
1304 /* Read timer, bundle and min_size from end of firmware blob */
1305 timer = fw->data[UCODE_SIZE * 4];
1306 bundle = fw->data[UCODE_SIZE * 4 + 1];
1307 min_size = fw->data[UCODE_SIZE * 4 + 2];
1308
1309 /* Insert user-tunable settings in cb->u.ucode */
1310 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1311 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1312 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1313 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1314 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1315 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1316
1317 cb->command = cpu_to_le16(cb_ucode | cb_el);
1318 }
1319
1320 static inline int e100_load_ucode_wait(struct nic *nic)
1321 {
1322 const struct firmware *fw;
1323 int err = 0, counter = 50;
1324 struct cb *cb = nic->cb_to_clean;
1325
1326 fw = e100_request_firmware(nic);
1327 /* If it's NULL, then no ucode is required */
1328 if (!fw || IS_ERR(fw))
1329 return PTR_ERR(fw);
1330
1331 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1332 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1333
1334 /* must restart cuc */
1335 nic->cuc_cmd = cuc_start;
1336
1337 /* wait for completion */
1338 e100_write_flush(nic);
1339 udelay(10);
1340
1341 /* wait for possibly (ouch) 500ms */
1342 while (!(cb->status & cpu_to_le16(cb_complete))) {
1343 msleep(10);
1344 if (!--counter) break;
1345 }
1346
1347 /* ack any interrupts, something could have been set */
1348 iowrite8(~0, &nic->csr->scb.stat_ack);
1349
1350 /* if the command failed, or is not OK, notify and return */
1351 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1352 DPRINTK(PROBE,ERR, "ucode load failed\n");
1353 err = -EPERM;
1354 }
1355
1356 return err;
1357 }
1358
1359 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1360 struct sk_buff *skb)
1361 {
1362 cb->command = cpu_to_le16(cb_iaaddr);
1363 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1364 }
1365
1366 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1367 {
1368 cb->command = cpu_to_le16(cb_dump);
1369 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1370 offsetof(struct mem, dump_buf));
1371 }
1372
1373 static int e100_phy_check_without_mii(struct nic *nic)
1374 {
1375 u8 phy_type;
1376 int without_mii;
1377
1378 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1379
1380 switch (phy_type) {
1381 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1382 case I82503: /* Non-MII PHY; UNTESTED! */
1383 case S80C24: /* Non-MII PHY; tested and working */
1384 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1385 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1386 * doesn't have a programming interface of any sort. The
1387 * media is sensed automatically based on how the link partner
1388 * is configured. This is, in essence, manual configuration.
1389 */
1390 DPRINTK(PROBE, INFO,
1391 "found MII-less i82503 or 80c24 or other PHY\n");
1392
1393 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1394 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1395
1396 /* these might be needed for certain MII-less cards...
1397 * nic->flags |= ich;
1398 * nic->flags |= ich_10h_workaround; */
1399
1400 without_mii = 1;
1401 break;
1402 default:
1403 without_mii = 0;
1404 break;
1405 }
1406 return without_mii;
1407 }
1408
1409 #define NCONFIG_AUTO_SWITCH 0x0080
1410 #define MII_NSC_CONG MII_RESV1
1411 #define NSC_CONG_ENABLE 0x0100
1412 #define NSC_CONG_TXREADY 0x0400
1413 #define ADVERTISE_FC_SUPPORTED 0x0400
1414 static int e100_phy_init(struct nic *nic)
1415 {
1416 struct net_device *netdev = nic->netdev;
1417 u32 addr;
1418 u16 bmcr, stat, id_lo, id_hi, cong;
1419
1420 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1421 for (addr = 0; addr < 32; addr++) {
1422 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1423 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1424 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1425 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1426 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1427 break;
1428 }
1429 if (addr == 32) {
1430 /* uhoh, no PHY detected: check whether we seem to be some
1431 * weird, rare variant which is *known* to not have any MII.
1432 * But do this AFTER MII checking only, since this does
1433 * lookup of EEPROM values which may easily be unreliable. */
1434 if (e100_phy_check_without_mii(nic))
1435 return 0; /* simply return and hope for the best */
1436 else {
1437 /* for unknown cases log a fatal error */
1438 DPRINTK(HW, ERR,
1439 "Failed to locate any known PHY, aborting.\n");
1440 return -EAGAIN;
1441 }
1442 } else
1443 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1444
1445 /* Get phy ID */
1446 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1447 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1448 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1449 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1450
1451 /* Select the phy and isolate the rest */
1452 for (addr = 0; addr < 32; addr++) {
1453 if (addr != nic->mii.phy_id) {
1454 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1455 } else if (nic->phy != phy_82552_v) {
1456 bmcr = mdio_read(netdev, addr, MII_BMCR);
1457 mdio_write(netdev, addr, MII_BMCR,
1458 bmcr & ~BMCR_ISOLATE);
1459 }
1460 }
1461 /*
1462 * Workaround for 82552:
1463 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1464 * other phy_id's) using bmcr value from addr discovery loop above.
1465 */
1466 if (nic->phy == phy_82552_v)
1467 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1468 bmcr & ~BMCR_ISOLATE);
1469
1470 /* Handle National tx phys */
1471 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1472 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1473 /* Disable congestion control */
1474 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1475 cong |= NSC_CONG_TXREADY;
1476 cong &= ~NSC_CONG_ENABLE;
1477 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1478 }
1479
1480 if (nic->phy == phy_82552_v) {
1481 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1482
1483 /* assign special tweaked mdio_ctrl() function */
1484 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1485
1486 /* Workaround Si not advertising flow-control during autoneg */
1487 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1488 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1489
1490 /* Reset for the above changes to take effect */
1491 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1492 bmcr |= BMCR_RESET;
1493 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1494 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1495 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1496 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1497 /* enable/disable MDI/MDI-X auto-switching. */
1498 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1499 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1500 }
1501
1502 return 0;
1503 }
1504
1505 static int e100_hw_init(struct nic *nic)
1506 {
1507 int err;
1508
1509 e100_hw_reset(nic);
1510
1511 DPRINTK(HW, ERR, "e100_hw_init\n");
1512 if (!in_interrupt() && (err = e100_self_test(nic)))
1513 return err;
1514
1515 if ((err = e100_phy_init(nic)))
1516 return err;
1517 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1518 return err;
1519 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1520 return err;
1521 if ((err = e100_load_ucode_wait(nic)))
1522 return err;
1523 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1524 return err;
1525 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1526 return err;
1527 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1528 nic->dma_addr + offsetof(struct mem, stats))))
1529 return err;
1530 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1531 return err;
1532
1533 e100_disable_irq(nic);
1534
1535 return 0;
1536 }
1537
1538 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1539 {
1540 struct net_device *netdev = nic->netdev;
1541 struct dev_mc_list *list;
1542 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1543
1544 cb->command = cpu_to_le16(cb_multi);
1545 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1546 i = 0;
1547 netdev_for_each_mc_addr(list, netdev) {
1548 if (i == count)
1549 break;
1550 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &list->dmi_addr,
1551 ETH_ALEN);
1552 }
1553 }
1554
1555 static void e100_set_multicast_list(struct net_device *netdev)
1556 {
1557 struct nic *nic = netdev_priv(netdev);
1558
1559 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1560 netdev_mc_count(netdev), netdev->flags);
1561
1562 if (netdev->flags & IFF_PROMISC)
1563 nic->flags |= promiscuous;
1564 else
1565 nic->flags &= ~promiscuous;
1566
1567 if (netdev->flags & IFF_ALLMULTI ||
1568 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1569 nic->flags |= multicast_all;
1570 else
1571 nic->flags &= ~multicast_all;
1572
1573 e100_exec_cb(nic, NULL, e100_configure);
1574 e100_exec_cb(nic, NULL, e100_multi);
1575 }
1576
1577 static void e100_update_stats(struct nic *nic)
1578 {
1579 struct net_device *dev = nic->netdev;
1580 struct net_device_stats *ns = &dev->stats;
1581 struct stats *s = &nic->mem->stats;
1582 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1583 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1584 &s->complete;
1585
1586 /* Device's stats reporting may take several microseconds to
1587 * complete, so we're always waiting for results of the
1588 * previous command. */
1589
1590 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1591 *complete = 0;
1592 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1593 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1594 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1595 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1596 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1597 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1598 ns->collisions += nic->tx_collisions;
1599 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1600 le32_to_cpu(s->tx_lost_crs);
1601 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1602 nic->rx_over_length_errors;
1603 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1604 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1605 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1606 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1607 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1608 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1609 le32_to_cpu(s->rx_alignment_errors) +
1610 le32_to_cpu(s->rx_short_frame_errors) +
1611 le32_to_cpu(s->rx_cdt_errors);
1612 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1613 nic->tx_single_collisions +=
1614 le32_to_cpu(s->tx_single_collisions);
1615 nic->tx_multiple_collisions +=
1616 le32_to_cpu(s->tx_multiple_collisions);
1617 if (nic->mac >= mac_82558_D101_A4) {
1618 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1619 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1620 nic->rx_fc_unsupported +=
1621 le32_to_cpu(s->fc_rcv_unsupported);
1622 if (nic->mac >= mac_82559_D101M) {
1623 nic->tx_tco_frames +=
1624 le16_to_cpu(s->xmt_tco_frames);
1625 nic->rx_tco_frames +=
1626 le16_to_cpu(s->rcv_tco_frames);
1627 }
1628 }
1629 }
1630
1631
1632 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1633 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1634 }
1635
1636 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1637 {
1638 /* Adjust inter-frame-spacing (IFS) between two transmits if
1639 * we're getting collisions on a half-duplex connection. */
1640
1641 if (duplex == DUPLEX_HALF) {
1642 u32 prev = nic->adaptive_ifs;
1643 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1644
1645 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1646 (nic->tx_frames > min_frames)) {
1647 if (nic->adaptive_ifs < 60)
1648 nic->adaptive_ifs += 5;
1649 } else if (nic->tx_frames < min_frames) {
1650 if (nic->adaptive_ifs >= 5)
1651 nic->adaptive_ifs -= 5;
1652 }
1653 if (nic->adaptive_ifs != prev)
1654 e100_exec_cb(nic, NULL, e100_configure);
1655 }
1656 }
1657
1658 static void e100_watchdog(unsigned long data)
1659 {
1660 struct nic *nic = (struct nic *)data;
1661 struct ethtool_cmd cmd;
1662
1663 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1664
1665 /* mii library handles link maintenance tasks */
1666
1667 mii_ethtool_gset(&nic->mii, &cmd);
1668
1669 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1670 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1671 nic->netdev->name,
1672 cmd.speed == SPEED_100 ? "100" : "10",
1673 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1674 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1675 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1676 nic->netdev->name);
1677 }
1678
1679 mii_check_link(&nic->mii);
1680
1681 /* Software generated interrupt to recover from (rare) Rx
1682 * allocation failure.
1683 * Unfortunately have to use a spinlock to not re-enable interrupts
1684 * accidentally, due to hardware that shares a register between the
1685 * interrupt mask bit and the SW Interrupt generation bit */
1686 spin_lock_irq(&nic->cmd_lock);
1687 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1688 e100_write_flush(nic);
1689 spin_unlock_irq(&nic->cmd_lock);
1690
1691 e100_update_stats(nic);
1692 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1693
1694 if (nic->mac <= mac_82557_D100_C)
1695 /* Issue a multicast command to workaround a 557 lock up */
1696 e100_set_multicast_list(nic->netdev);
1697
1698 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1699 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1700 nic->flags |= ich_10h_workaround;
1701 else
1702 nic->flags &= ~ich_10h_workaround;
1703
1704 mod_timer(&nic->watchdog,
1705 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1706 }
1707
1708 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1709 struct sk_buff *skb)
1710 {
1711 cb->command = nic->tx_command;
1712 /* interrupt every 16 packets regardless of delay */
1713 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1714 cb->command |= cpu_to_le16(cb_i);
1715 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1716 cb->u.tcb.tcb_byte_count = 0;
1717 cb->u.tcb.threshold = nic->tx_threshold;
1718 cb->u.tcb.tbd_count = 1;
1719 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1720 skb->data, skb->len, PCI_DMA_TODEVICE));
1721 /* check for mapping failure? */
1722 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1723 }
1724
1725 static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1726 struct net_device *netdev)
1727 {
1728 struct nic *nic = netdev_priv(netdev);
1729 int err;
1730
1731 if (nic->flags & ich_10h_workaround) {
1732 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1733 Issue a NOP command followed by a 1us delay before
1734 issuing the Tx command. */
1735 if (e100_exec_cmd(nic, cuc_nop, 0))
1736 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1737 udelay(1);
1738 }
1739
1740 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1741
1742 switch (err) {
1743 case -ENOSPC:
1744 /* We queued the skb, but now we're out of space. */
1745 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1746 netif_stop_queue(netdev);
1747 break;
1748 case -ENOMEM:
1749 /* This is a hard error - log it. */
1750 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1751 netif_stop_queue(netdev);
1752 return NETDEV_TX_BUSY;
1753 }
1754
1755 netdev->trans_start = jiffies;
1756 return NETDEV_TX_OK;
1757 }
1758
1759 static int e100_tx_clean(struct nic *nic)
1760 {
1761 struct net_device *dev = nic->netdev;
1762 struct cb *cb;
1763 int tx_cleaned = 0;
1764
1765 spin_lock(&nic->cb_lock);
1766
1767 /* Clean CBs marked complete */
1768 for (cb = nic->cb_to_clean;
1769 cb->status & cpu_to_le16(cb_complete);
1770 cb = nic->cb_to_clean = cb->next) {
1771 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1772 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1773 cb->status);
1774
1775 if (likely(cb->skb != NULL)) {
1776 dev->stats.tx_packets++;
1777 dev->stats.tx_bytes += cb->skb->len;
1778
1779 pci_unmap_single(nic->pdev,
1780 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1781 le16_to_cpu(cb->u.tcb.tbd.size),
1782 PCI_DMA_TODEVICE);
1783 dev_kfree_skb_any(cb->skb);
1784 cb->skb = NULL;
1785 tx_cleaned = 1;
1786 }
1787 cb->status = 0;
1788 nic->cbs_avail++;
1789 }
1790
1791 spin_unlock(&nic->cb_lock);
1792
1793 /* Recover from running out of Tx resources in xmit_frame */
1794 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1795 netif_wake_queue(nic->netdev);
1796
1797 return tx_cleaned;
1798 }
1799
1800 static void e100_clean_cbs(struct nic *nic)
1801 {
1802 if (nic->cbs) {
1803 while (nic->cbs_avail != nic->params.cbs.count) {
1804 struct cb *cb = nic->cb_to_clean;
1805 if (cb->skb) {
1806 pci_unmap_single(nic->pdev,
1807 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1808 le16_to_cpu(cb->u.tcb.tbd.size),
1809 PCI_DMA_TODEVICE);
1810 dev_kfree_skb(cb->skb);
1811 }
1812 nic->cb_to_clean = nic->cb_to_clean->next;
1813 nic->cbs_avail++;
1814 }
1815 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1816 nic->cbs = NULL;
1817 nic->cbs_avail = 0;
1818 }
1819 nic->cuc_cmd = cuc_start;
1820 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1821 nic->cbs;
1822 }
1823
1824 static int e100_alloc_cbs(struct nic *nic)
1825 {
1826 struct cb *cb;
1827 unsigned int i, count = nic->params.cbs.count;
1828
1829 nic->cuc_cmd = cuc_start;
1830 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1831 nic->cbs_avail = 0;
1832
1833 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1834 &nic->cbs_dma_addr);
1835 if (!nic->cbs)
1836 return -ENOMEM;
1837 memset(nic->cbs, 0, count * sizeof(struct cb));
1838
1839 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1840 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1841 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1842
1843 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1844 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1845 ((i+1) % count) * sizeof(struct cb));
1846 }
1847
1848 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1849 nic->cbs_avail = count;
1850
1851 return 0;
1852 }
1853
1854 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1855 {
1856 if (!nic->rxs) return;
1857 if (RU_SUSPENDED != nic->ru_running) return;
1858
1859 /* handle init time starts */
1860 if (!rx) rx = nic->rxs;
1861
1862 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1863 if (rx->skb) {
1864 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1865 nic->ru_running = RU_RUNNING;
1866 }
1867 }
1868
1869 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1870 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1871 {
1872 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1873 return -ENOMEM;
1874
1875 /* Init, and map the RFD. */
1876 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1877 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1878 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1879
1880 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1881 dev_kfree_skb_any(rx->skb);
1882 rx->skb = NULL;
1883 rx->dma_addr = 0;
1884 return -ENOMEM;
1885 }
1886
1887 /* Link the RFD to end of RFA by linking previous RFD to
1888 * this one. We are safe to touch the previous RFD because
1889 * it is protected by the before last buffer's el bit being set */
1890 if (rx->prev->skb) {
1891 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1892 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1893 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1894 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1895 }
1896
1897 return 0;
1898 }
1899
1900 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1901 unsigned int *work_done, unsigned int work_to_do)
1902 {
1903 struct net_device *dev = nic->netdev;
1904 struct sk_buff *skb = rx->skb;
1905 struct rfd *rfd = (struct rfd *)skb->data;
1906 u16 rfd_status, actual_size;
1907
1908 if (unlikely(work_done && *work_done >= work_to_do))
1909 return -EAGAIN;
1910
1911 /* Need to sync before taking a peek at cb_complete bit */
1912 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1913 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1914 rfd_status = le16_to_cpu(rfd->status);
1915
1916 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1917
1918 /* If data isn't ready, nothing to indicate */
1919 if (unlikely(!(rfd_status & cb_complete))) {
1920 /* If the next buffer has the el bit, but we think the receiver
1921 * is still running, check to see if it really stopped while
1922 * we had interrupts off.
1923 * This allows for a fast restart without re-enabling
1924 * interrupts */
1925 if ((le16_to_cpu(rfd->command) & cb_el) &&
1926 (RU_RUNNING == nic->ru_running))
1927
1928 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1929 nic->ru_running = RU_SUSPENDED;
1930 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1931 sizeof(struct rfd),
1932 PCI_DMA_FROMDEVICE);
1933 return -ENODATA;
1934 }
1935
1936 /* Get actual data size */
1937 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1938 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1939 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1940
1941 /* Get data */
1942 pci_unmap_single(nic->pdev, rx->dma_addr,
1943 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1944
1945 /* If this buffer has the el bit, but we think the receiver
1946 * is still running, check to see if it really stopped while
1947 * we had interrupts off.
1948 * This allows for a fast restart without re-enabling interrupts.
1949 * This can happen when the RU sees the size change but also sees
1950 * the el bit set. */
1951 if ((le16_to_cpu(rfd->command) & cb_el) &&
1952 (RU_RUNNING == nic->ru_running)) {
1953
1954 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1955 nic->ru_running = RU_SUSPENDED;
1956 }
1957
1958 /* Pull off the RFD and put the actual data (minus eth hdr) */
1959 skb_reserve(skb, sizeof(struct rfd));
1960 skb_put(skb, actual_size);
1961 skb->protocol = eth_type_trans(skb, nic->netdev);
1962
1963 if (unlikely(!(rfd_status & cb_ok))) {
1964 /* Don't indicate if hardware indicates errors */
1965 dev_kfree_skb_any(skb);
1966 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1967 /* Don't indicate oversized frames */
1968 nic->rx_over_length_errors++;
1969 dev_kfree_skb_any(skb);
1970 } else {
1971 dev->stats.rx_packets++;
1972 dev->stats.rx_bytes += actual_size;
1973 netif_receive_skb(skb);
1974 if (work_done)
1975 (*work_done)++;
1976 }
1977
1978 rx->skb = NULL;
1979
1980 return 0;
1981 }
1982
1983 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1984 unsigned int work_to_do)
1985 {
1986 struct rx *rx;
1987 int restart_required = 0, err = 0;
1988 struct rx *old_before_last_rx, *new_before_last_rx;
1989 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1990
1991 /* Indicate newly arrived packets */
1992 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1993 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1994 /* Hit quota or no more to clean */
1995 if (-EAGAIN == err || -ENODATA == err)
1996 break;
1997 }
1998
1999
2000 /* On EAGAIN, hit quota so have more work to do, restart once
2001 * cleanup is complete.
2002 * Else, are we already rnr? then pay attention!!! this ensures that
2003 * the state machine progression never allows a start with a
2004 * partially cleaned list, avoiding a race between hardware
2005 * and rx_to_clean when in NAPI mode */
2006 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2007 restart_required = 1;
2008
2009 old_before_last_rx = nic->rx_to_use->prev->prev;
2010 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2011
2012 /* Alloc new skbs to refill list */
2013 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2014 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2015 break; /* Better luck next time (see watchdog) */
2016 }
2017
2018 new_before_last_rx = nic->rx_to_use->prev->prev;
2019 if (new_before_last_rx != old_before_last_rx) {
2020 /* Set the el-bit on the buffer that is before the last buffer.
2021 * This lets us update the next pointer on the last buffer
2022 * without worrying about hardware touching it.
2023 * We set the size to 0 to prevent hardware from touching this
2024 * buffer.
2025 * When the hardware hits the before last buffer with el-bit
2026 * and size of 0, it will RNR interrupt, the RUS will go into
2027 * the No Resources state. It will not complete nor write to
2028 * this buffer. */
2029 new_before_last_rfd =
2030 (struct rfd *)new_before_last_rx->skb->data;
2031 new_before_last_rfd->size = 0;
2032 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2033 pci_dma_sync_single_for_device(nic->pdev,
2034 new_before_last_rx->dma_addr, sizeof(struct rfd),
2035 PCI_DMA_BIDIRECTIONAL);
2036
2037 /* Now that we have a new stopping point, we can clear the old
2038 * stopping point. We must sync twice to get the proper
2039 * ordering on the hardware side of things. */
2040 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2041 pci_dma_sync_single_for_device(nic->pdev,
2042 old_before_last_rx->dma_addr, sizeof(struct rfd),
2043 PCI_DMA_BIDIRECTIONAL);
2044 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2045 pci_dma_sync_single_for_device(nic->pdev,
2046 old_before_last_rx->dma_addr, sizeof(struct rfd),
2047 PCI_DMA_BIDIRECTIONAL);
2048 }
2049
2050 if (restart_required) {
2051 // ack the rnr?
2052 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2053 e100_start_receiver(nic, nic->rx_to_clean);
2054 if (work_done)
2055 (*work_done)++;
2056 }
2057 }
2058
2059 static void e100_rx_clean_list(struct nic *nic)
2060 {
2061 struct rx *rx;
2062 unsigned int i, count = nic->params.rfds.count;
2063
2064 nic->ru_running = RU_UNINITIALIZED;
2065
2066 if (nic->rxs) {
2067 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2068 if (rx->skb) {
2069 pci_unmap_single(nic->pdev, rx->dma_addr,
2070 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2071 dev_kfree_skb(rx->skb);
2072 }
2073 }
2074 kfree(nic->rxs);
2075 nic->rxs = NULL;
2076 }
2077
2078 nic->rx_to_use = nic->rx_to_clean = NULL;
2079 }
2080
2081 static int e100_rx_alloc_list(struct nic *nic)
2082 {
2083 struct rx *rx;
2084 unsigned int i, count = nic->params.rfds.count;
2085 struct rfd *before_last;
2086
2087 nic->rx_to_use = nic->rx_to_clean = NULL;
2088 nic->ru_running = RU_UNINITIALIZED;
2089
2090 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2091 return -ENOMEM;
2092
2093 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2094 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2095 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2096 if (e100_rx_alloc_skb(nic, rx)) {
2097 e100_rx_clean_list(nic);
2098 return -ENOMEM;
2099 }
2100 }
2101 /* Set the el-bit on the buffer that is before the last buffer.
2102 * This lets us update the next pointer on the last buffer without
2103 * worrying about hardware touching it.
2104 * We set the size to 0 to prevent hardware from touching this buffer.
2105 * When the hardware hits the before last buffer with el-bit and size
2106 * of 0, it will RNR interrupt, the RU will go into the No Resources
2107 * state. It will not complete nor write to this buffer. */
2108 rx = nic->rxs->prev->prev;
2109 before_last = (struct rfd *)rx->skb->data;
2110 before_last->command |= cpu_to_le16(cb_el);
2111 before_last->size = 0;
2112 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2113 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2114
2115 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2116 nic->ru_running = RU_SUSPENDED;
2117
2118 return 0;
2119 }
2120
2121 static irqreturn_t e100_intr(int irq, void *dev_id)
2122 {
2123 struct net_device *netdev = dev_id;
2124 struct nic *nic = netdev_priv(netdev);
2125 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2126
2127 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2128
2129 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2130 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2131 return IRQ_NONE;
2132
2133 /* Ack interrupt(s) */
2134 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2135
2136 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2137 if (stat_ack & stat_ack_rnr)
2138 nic->ru_running = RU_SUSPENDED;
2139
2140 if (likely(napi_schedule_prep(&nic->napi))) {
2141 e100_disable_irq(nic);
2142 __napi_schedule(&nic->napi);
2143 }
2144
2145 return IRQ_HANDLED;
2146 }
2147
2148 static int e100_poll(struct napi_struct *napi, int budget)
2149 {
2150 struct nic *nic = container_of(napi, struct nic, napi);
2151 unsigned int work_done = 0;
2152
2153 e100_rx_clean(nic, &work_done, budget);
2154 e100_tx_clean(nic);
2155
2156 /* If budget not fully consumed, exit the polling mode */
2157 if (work_done < budget) {
2158 napi_complete(napi);
2159 e100_enable_irq(nic);
2160 }
2161
2162 return work_done;
2163 }
2164
2165 #ifdef CONFIG_NET_POLL_CONTROLLER
2166 static void e100_netpoll(struct net_device *netdev)
2167 {
2168 struct nic *nic = netdev_priv(netdev);
2169
2170 e100_disable_irq(nic);
2171 e100_intr(nic->pdev->irq, netdev);
2172 e100_tx_clean(nic);
2173 e100_enable_irq(nic);
2174 }
2175 #endif
2176
2177 static int e100_set_mac_address(struct net_device *netdev, void *p)
2178 {
2179 struct nic *nic = netdev_priv(netdev);
2180 struct sockaddr *addr = p;
2181
2182 if (!is_valid_ether_addr(addr->sa_data))
2183 return -EADDRNOTAVAIL;
2184
2185 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2186 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2187
2188 return 0;
2189 }
2190
2191 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2192 {
2193 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2194 return -EINVAL;
2195 netdev->mtu = new_mtu;
2196 return 0;
2197 }
2198
2199 static int e100_asf(struct nic *nic)
2200 {
2201 /* ASF can be enabled from eeprom */
2202 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2203 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2204 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2205 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2206 }
2207
2208 static int e100_up(struct nic *nic)
2209 {
2210 int err;
2211
2212 if ((err = e100_rx_alloc_list(nic)))
2213 return err;
2214 if ((err = e100_alloc_cbs(nic)))
2215 goto err_rx_clean_list;
2216 if ((err = e100_hw_init(nic)))
2217 goto err_clean_cbs;
2218 e100_set_multicast_list(nic->netdev);
2219 e100_start_receiver(nic, NULL);
2220 mod_timer(&nic->watchdog, jiffies);
2221 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2222 nic->netdev->name, nic->netdev)))
2223 goto err_no_irq;
2224 netif_wake_queue(nic->netdev);
2225 napi_enable(&nic->napi);
2226 /* enable ints _after_ enabling poll, preventing a race between
2227 * disable ints+schedule */
2228 e100_enable_irq(nic);
2229 return 0;
2230
2231 err_no_irq:
2232 del_timer_sync(&nic->watchdog);
2233 err_clean_cbs:
2234 e100_clean_cbs(nic);
2235 err_rx_clean_list:
2236 e100_rx_clean_list(nic);
2237 return err;
2238 }
2239
2240 static void e100_down(struct nic *nic)
2241 {
2242 /* wait here for poll to complete */
2243 napi_disable(&nic->napi);
2244 netif_stop_queue(nic->netdev);
2245 e100_hw_reset(nic);
2246 free_irq(nic->pdev->irq, nic->netdev);
2247 del_timer_sync(&nic->watchdog);
2248 netif_carrier_off(nic->netdev);
2249 e100_clean_cbs(nic);
2250 e100_rx_clean_list(nic);
2251 }
2252
2253 static void e100_tx_timeout(struct net_device *netdev)
2254 {
2255 struct nic *nic = netdev_priv(netdev);
2256
2257 /* Reset outside of interrupt context, to avoid request_irq
2258 * in interrupt context */
2259 schedule_work(&nic->tx_timeout_task);
2260 }
2261
2262 static void e100_tx_timeout_task(struct work_struct *work)
2263 {
2264 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2265 struct net_device *netdev = nic->netdev;
2266
2267 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2268 ioread8(&nic->csr->scb.status));
2269
2270 rtnl_lock();
2271 if (netif_running(netdev)) {
2272 e100_down(netdev_priv(netdev));
2273 e100_up(netdev_priv(netdev));
2274 }
2275 rtnl_unlock();
2276 }
2277
2278 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2279 {
2280 int err;
2281 struct sk_buff *skb;
2282
2283 /* Use driver resources to perform internal MAC or PHY
2284 * loopback test. A single packet is prepared and transmitted
2285 * in loopback mode, and the test passes if the received
2286 * packet compares byte-for-byte to the transmitted packet. */
2287
2288 if ((err = e100_rx_alloc_list(nic)))
2289 return err;
2290 if ((err = e100_alloc_cbs(nic)))
2291 goto err_clean_rx;
2292
2293 /* ICH PHY loopback is broken so do MAC loopback instead */
2294 if (nic->flags & ich && loopback_mode == lb_phy)
2295 loopback_mode = lb_mac;
2296
2297 nic->loopback = loopback_mode;
2298 if ((err = e100_hw_init(nic)))
2299 goto err_loopback_none;
2300
2301 if (loopback_mode == lb_phy)
2302 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2303 BMCR_LOOPBACK);
2304
2305 e100_start_receiver(nic, NULL);
2306
2307 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2308 err = -ENOMEM;
2309 goto err_loopback_none;
2310 }
2311 skb_put(skb, ETH_DATA_LEN);
2312 memset(skb->data, 0xFF, ETH_DATA_LEN);
2313 e100_xmit_frame(skb, nic->netdev);
2314
2315 msleep(10);
2316
2317 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2318 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2319
2320 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2321 skb->data, ETH_DATA_LEN))
2322 err = -EAGAIN;
2323
2324 err_loopback_none:
2325 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2326 nic->loopback = lb_none;
2327 e100_clean_cbs(nic);
2328 e100_hw_reset(nic);
2329 err_clean_rx:
2330 e100_rx_clean_list(nic);
2331 return err;
2332 }
2333
2334 #define MII_LED_CONTROL 0x1B
2335 #define E100_82552_LED_OVERRIDE 0x19
2336 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2337 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2338 static void e100_blink_led(unsigned long data)
2339 {
2340 struct nic *nic = (struct nic *)data;
2341 enum led_state {
2342 led_on = 0x01,
2343 led_off = 0x04,
2344 led_on_559 = 0x05,
2345 led_on_557 = 0x07,
2346 };
2347 u16 led_reg = MII_LED_CONTROL;
2348
2349 if (nic->phy == phy_82552_v) {
2350 led_reg = E100_82552_LED_OVERRIDE;
2351
2352 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2353 E100_82552_LED_OFF : E100_82552_LED_ON;
2354 } else {
2355 nic->leds = (nic->leds & led_on) ? led_off :
2356 (nic->mac < mac_82559_D101M) ? led_on_557 :
2357 led_on_559;
2358 }
2359 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2360 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2361 }
2362
2363 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2364 {
2365 struct nic *nic = netdev_priv(netdev);
2366 return mii_ethtool_gset(&nic->mii, cmd);
2367 }
2368
2369 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2370 {
2371 struct nic *nic = netdev_priv(netdev);
2372 int err;
2373
2374 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2375 err = mii_ethtool_sset(&nic->mii, cmd);
2376 e100_exec_cb(nic, NULL, e100_configure);
2377
2378 return err;
2379 }
2380
2381 static void e100_get_drvinfo(struct net_device *netdev,
2382 struct ethtool_drvinfo *info)
2383 {
2384 struct nic *nic = netdev_priv(netdev);
2385 strcpy(info->driver, DRV_NAME);
2386 strcpy(info->version, DRV_VERSION);
2387 strcpy(info->fw_version, "N/A");
2388 strcpy(info->bus_info, pci_name(nic->pdev));
2389 }
2390
2391 #define E100_PHY_REGS 0x1C
2392 static int e100_get_regs_len(struct net_device *netdev)
2393 {
2394 struct nic *nic = netdev_priv(netdev);
2395 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2396 }
2397
2398 static void e100_get_regs(struct net_device *netdev,
2399 struct ethtool_regs *regs, void *p)
2400 {
2401 struct nic *nic = netdev_priv(netdev);
2402 u32 *buff = p;
2403 int i;
2404
2405 regs->version = (1 << 24) | nic->pdev->revision;
2406 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2407 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2408 ioread16(&nic->csr->scb.status);
2409 for (i = E100_PHY_REGS; i >= 0; i--)
2410 buff[1 + E100_PHY_REGS - i] =
2411 mdio_read(netdev, nic->mii.phy_id, i);
2412 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2413 e100_exec_cb(nic, NULL, e100_dump);
2414 msleep(10);
2415 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2416 sizeof(nic->mem->dump_buf));
2417 }
2418
2419 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2420 {
2421 struct nic *nic = netdev_priv(netdev);
2422 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2423 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2424 }
2425
2426 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2427 {
2428 struct nic *nic = netdev_priv(netdev);
2429
2430 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2431 !device_can_wakeup(&nic->pdev->dev))
2432 return -EOPNOTSUPP;
2433
2434 if (wol->wolopts)
2435 nic->flags |= wol_magic;
2436 else
2437 nic->flags &= ~wol_magic;
2438
2439 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2440
2441 e100_exec_cb(nic, NULL, e100_configure);
2442
2443 return 0;
2444 }
2445
2446 static u32 e100_get_msglevel(struct net_device *netdev)
2447 {
2448 struct nic *nic = netdev_priv(netdev);
2449 return nic->msg_enable;
2450 }
2451
2452 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2453 {
2454 struct nic *nic = netdev_priv(netdev);
2455 nic->msg_enable = value;
2456 }
2457
2458 static int e100_nway_reset(struct net_device *netdev)
2459 {
2460 struct nic *nic = netdev_priv(netdev);
2461 return mii_nway_restart(&nic->mii);
2462 }
2463
2464 static u32 e100_get_link(struct net_device *netdev)
2465 {
2466 struct nic *nic = netdev_priv(netdev);
2467 return mii_link_ok(&nic->mii);
2468 }
2469
2470 static int e100_get_eeprom_len(struct net_device *netdev)
2471 {
2472 struct nic *nic = netdev_priv(netdev);
2473 return nic->eeprom_wc << 1;
2474 }
2475
2476 #define E100_EEPROM_MAGIC 0x1234
2477 static int e100_get_eeprom(struct net_device *netdev,
2478 struct ethtool_eeprom *eeprom, u8 *bytes)
2479 {
2480 struct nic *nic = netdev_priv(netdev);
2481
2482 eeprom->magic = E100_EEPROM_MAGIC;
2483 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2484
2485 return 0;
2486 }
2487
2488 static int e100_set_eeprom(struct net_device *netdev,
2489 struct ethtool_eeprom *eeprom, u8 *bytes)
2490 {
2491 struct nic *nic = netdev_priv(netdev);
2492
2493 if (eeprom->magic != E100_EEPROM_MAGIC)
2494 return -EINVAL;
2495
2496 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2497
2498 return e100_eeprom_save(nic, eeprom->offset >> 1,
2499 (eeprom->len >> 1) + 1);
2500 }
2501
2502 static void e100_get_ringparam(struct net_device *netdev,
2503 struct ethtool_ringparam *ring)
2504 {
2505 struct nic *nic = netdev_priv(netdev);
2506 struct param_range *rfds = &nic->params.rfds;
2507 struct param_range *cbs = &nic->params.cbs;
2508
2509 ring->rx_max_pending = rfds->max;
2510 ring->tx_max_pending = cbs->max;
2511 ring->rx_mini_max_pending = 0;
2512 ring->rx_jumbo_max_pending = 0;
2513 ring->rx_pending = rfds->count;
2514 ring->tx_pending = cbs->count;
2515 ring->rx_mini_pending = 0;
2516 ring->rx_jumbo_pending = 0;
2517 }
2518
2519 static int e100_set_ringparam(struct net_device *netdev,
2520 struct ethtool_ringparam *ring)
2521 {
2522 struct nic *nic = netdev_priv(netdev);
2523 struct param_range *rfds = &nic->params.rfds;
2524 struct param_range *cbs = &nic->params.cbs;
2525
2526 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2527 return -EINVAL;
2528
2529 if (netif_running(netdev))
2530 e100_down(nic);
2531 rfds->count = max(ring->rx_pending, rfds->min);
2532 rfds->count = min(rfds->count, rfds->max);
2533 cbs->count = max(ring->tx_pending, cbs->min);
2534 cbs->count = min(cbs->count, cbs->max);
2535 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2536 rfds->count, cbs->count);
2537 if (netif_running(netdev))
2538 e100_up(nic);
2539
2540 return 0;
2541 }
2542
2543 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2544 "Link test (on/offline)",
2545 "Eeprom test (on/offline)",
2546 "Self test (offline)",
2547 "Mac loopback (offline)",
2548 "Phy loopback (offline)",
2549 };
2550 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2551
2552 static void e100_diag_test(struct net_device *netdev,
2553 struct ethtool_test *test, u64 *data)
2554 {
2555 struct ethtool_cmd cmd;
2556 struct nic *nic = netdev_priv(netdev);
2557 int i, err;
2558
2559 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2560 data[0] = !mii_link_ok(&nic->mii);
2561 data[1] = e100_eeprom_load(nic);
2562 if (test->flags & ETH_TEST_FL_OFFLINE) {
2563
2564 /* save speed, duplex & autoneg settings */
2565 err = mii_ethtool_gset(&nic->mii, &cmd);
2566
2567 if (netif_running(netdev))
2568 e100_down(nic);
2569 data[2] = e100_self_test(nic);
2570 data[3] = e100_loopback_test(nic, lb_mac);
2571 data[4] = e100_loopback_test(nic, lb_phy);
2572
2573 /* restore speed, duplex & autoneg settings */
2574 err = mii_ethtool_sset(&nic->mii, &cmd);
2575
2576 if (netif_running(netdev))
2577 e100_up(nic);
2578 }
2579 for (i = 0; i < E100_TEST_LEN; i++)
2580 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2581
2582 msleep_interruptible(4 * 1000);
2583 }
2584
2585 static int e100_phys_id(struct net_device *netdev, u32 data)
2586 {
2587 struct nic *nic = netdev_priv(netdev);
2588 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2589 MII_LED_CONTROL;
2590
2591 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2592 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2593 mod_timer(&nic->blink_timer, jiffies);
2594 msleep_interruptible(data * 1000);
2595 del_timer_sync(&nic->blink_timer);
2596 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2597
2598 return 0;
2599 }
2600
2601 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2602 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2603 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2604 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2605 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2606 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2607 "tx_heartbeat_errors", "tx_window_errors",
2608 /* device-specific stats */
2609 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2610 "tx_flow_control_pause", "rx_flow_control_pause",
2611 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2612 };
2613 #define E100_NET_STATS_LEN 21
2614 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2615
2616 static int e100_get_sset_count(struct net_device *netdev, int sset)
2617 {
2618 switch (sset) {
2619 case ETH_SS_TEST:
2620 return E100_TEST_LEN;
2621 case ETH_SS_STATS:
2622 return E100_STATS_LEN;
2623 default:
2624 return -EOPNOTSUPP;
2625 }
2626 }
2627
2628 static void e100_get_ethtool_stats(struct net_device *netdev,
2629 struct ethtool_stats *stats, u64 *data)
2630 {
2631 struct nic *nic = netdev_priv(netdev);
2632 int i;
2633
2634 for (i = 0; i < E100_NET_STATS_LEN; i++)
2635 data[i] = ((unsigned long *)&netdev->stats)[i];
2636
2637 data[i++] = nic->tx_deferred;
2638 data[i++] = nic->tx_single_collisions;
2639 data[i++] = nic->tx_multiple_collisions;
2640 data[i++] = nic->tx_fc_pause;
2641 data[i++] = nic->rx_fc_pause;
2642 data[i++] = nic->rx_fc_unsupported;
2643 data[i++] = nic->tx_tco_frames;
2644 data[i++] = nic->rx_tco_frames;
2645 }
2646
2647 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2648 {
2649 switch (stringset) {
2650 case ETH_SS_TEST:
2651 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2652 break;
2653 case ETH_SS_STATS:
2654 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2655 break;
2656 }
2657 }
2658
2659 static const struct ethtool_ops e100_ethtool_ops = {
2660 .get_settings = e100_get_settings,
2661 .set_settings = e100_set_settings,
2662 .get_drvinfo = e100_get_drvinfo,
2663 .get_regs_len = e100_get_regs_len,
2664 .get_regs = e100_get_regs,
2665 .get_wol = e100_get_wol,
2666 .set_wol = e100_set_wol,
2667 .get_msglevel = e100_get_msglevel,
2668 .set_msglevel = e100_set_msglevel,
2669 .nway_reset = e100_nway_reset,
2670 .get_link = e100_get_link,
2671 .get_eeprom_len = e100_get_eeprom_len,
2672 .get_eeprom = e100_get_eeprom,
2673 .set_eeprom = e100_set_eeprom,
2674 .get_ringparam = e100_get_ringparam,
2675 .set_ringparam = e100_set_ringparam,
2676 .self_test = e100_diag_test,
2677 .get_strings = e100_get_strings,
2678 .phys_id = e100_phys_id,
2679 .get_ethtool_stats = e100_get_ethtool_stats,
2680 .get_sset_count = e100_get_sset_count,
2681 };
2682
2683 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2684 {
2685 struct nic *nic = netdev_priv(netdev);
2686
2687 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2688 }
2689
2690 static int e100_alloc(struct nic *nic)
2691 {
2692 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2693 &nic->dma_addr);
2694 return nic->mem ? 0 : -ENOMEM;
2695 }
2696
2697 static void e100_free(struct nic *nic)
2698 {
2699 if (nic->mem) {
2700 pci_free_consistent(nic->pdev, sizeof(struct mem),
2701 nic->mem, nic->dma_addr);
2702 nic->mem = NULL;
2703 }
2704 }
2705
2706 static int e100_open(struct net_device *netdev)
2707 {
2708 struct nic *nic = netdev_priv(netdev);
2709 int err = 0;
2710
2711 netif_carrier_off(netdev);
2712 if ((err = e100_up(nic)))
2713 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2714 return err;
2715 }
2716
2717 static int e100_close(struct net_device *netdev)
2718 {
2719 e100_down(netdev_priv(netdev));
2720 return 0;
2721 }
2722
2723 static const struct net_device_ops e100_netdev_ops = {
2724 .ndo_open = e100_open,
2725 .ndo_stop = e100_close,
2726 .ndo_start_xmit = e100_xmit_frame,
2727 .ndo_validate_addr = eth_validate_addr,
2728 .ndo_set_multicast_list = e100_set_multicast_list,
2729 .ndo_set_mac_address = e100_set_mac_address,
2730 .ndo_change_mtu = e100_change_mtu,
2731 .ndo_do_ioctl = e100_do_ioctl,
2732 .ndo_tx_timeout = e100_tx_timeout,
2733 #ifdef CONFIG_NET_POLL_CONTROLLER
2734 .ndo_poll_controller = e100_netpoll,
2735 #endif
2736 };
2737
2738 static int __devinit e100_probe(struct pci_dev *pdev,
2739 const struct pci_device_id *ent)
2740 {
2741 struct net_device *netdev;
2742 struct nic *nic;
2743 int err;
2744
2745 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2746 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2747 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2748 return -ENOMEM;
2749 }
2750
2751 netdev->netdev_ops = &e100_netdev_ops;
2752 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2753 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2754 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2755
2756 nic = netdev_priv(netdev);
2757 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2758 nic->netdev = netdev;
2759 nic->pdev = pdev;
2760 nic->msg_enable = (1 << debug) - 1;
2761 nic->mdio_ctrl = mdio_ctrl_hw;
2762 pci_set_drvdata(pdev, netdev);
2763
2764 if ((err = pci_enable_device(pdev))) {
2765 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2766 goto err_out_free_dev;
2767 }
2768
2769 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2770 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2771 "base address, aborting.\n");
2772 err = -ENODEV;
2773 goto err_out_disable_pdev;
2774 }
2775
2776 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2777 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2778 goto err_out_disable_pdev;
2779 }
2780
2781 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2782 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2783 goto err_out_free_res;
2784 }
2785
2786 SET_NETDEV_DEV(netdev, &pdev->dev);
2787
2788 if (use_io)
2789 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2790
2791 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2792 if (!nic->csr) {
2793 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2794 err = -ENOMEM;
2795 goto err_out_free_res;
2796 }
2797
2798 if (ent->driver_data)
2799 nic->flags |= ich;
2800 else
2801 nic->flags &= ~ich;
2802
2803 e100_get_defaults(nic);
2804
2805 /* locks must be initialized before calling hw_reset */
2806 spin_lock_init(&nic->cb_lock);
2807 spin_lock_init(&nic->cmd_lock);
2808 spin_lock_init(&nic->mdio_lock);
2809
2810 /* Reset the device before pci_set_master() in case device is in some
2811 * funky state and has an interrupt pending - hint: we don't have the
2812 * interrupt handler registered yet. */
2813 e100_hw_reset(nic);
2814
2815 pci_set_master(pdev);
2816
2817 init_timer(&nic->watchdog);
2818 nic->watchdog.function = e100_watchdog;
2819 nic->watchdog.data = (unsigned long)nic;
2820 init_timer(&nic->blink_timer);
2821 nic->blink_timer.function = e100_blink_led;
2822 nic->blink_timer.data = (unsigned long)nic;
2823
2824 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2825
2826 if ((err = e100_alloc(nic))) {
2827 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2828 goto err_out_iounmap;
2829 }
2830
2831 if ((err = e100_eeprom_load(nic)))
2832 goto err_out_free;
2833
2834 e100_phy_init(nic);
2835
2836 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2837 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2838 if (!is_valid_ether_addr(netdev->perm_addr)) {
2839 if (!eeprom_bad_csum_allow) {
2840 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2841 "EEPROM, aborting.\n");
2842 err = -EAGAIN;
2843 goto err_out_free;
2844 } else {
2845 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2846 "you MUST configure one.\n");
2847 }
2848 }
2849
2850 /* Wol magic packet can be enabled from eeprom */
2851 if ((nic->mac >= mac_82558_D101_A4) &&
2852 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2853 nic->flags |= wol_magic;
2854 device_set_wakeup_enable(&pdev->dev, true);
2855 }
2856
2857 /* ack any pending wake events, disable PME */
2858 pci_pme_active(pdev, false);
2859
2860 strcpy(netdev->name, "eth%d");
2861 if ((err = register_netdev(netdev))) {
2862 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2863 goto err_out_free;
2864 }
2865 nic->cbs_pool = pci_pool_create(netdev->name,
2866 nic->pdev,
2867 nic->params.cbs.max * sizeof(struct cb),
2868 sizeof(u32),
2869 0);
2870 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2871 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2872 pdev->irq, netdev->dev_addr);
2873
2874 return 0;
2875
2876 err_out_free:
2877 e100_free(nic);
2878 err_out_iounmap:
2879 pci_iounmap(pdev, nic->csr);
2880 err_out_free_res:
2881 pci_release_regions(pdev);
2882 err_out_disable_pdev:
2883 pci_disable_device(pdev);
2884 err_out_free_dev:
2885 pci_set_drvdata(pdev, NULL);
2886 free_netdev(netdev);
2887 return err;
2888 }
2889
2890 static void __devexit e100_remove(struct pci_dev *pdev)
2891 {
2892 struct net_device *netdev = pci_get_drvdata(pdev);
2893
2894 if (netdev) {
2895 struct nic *nic = netdev_priv(netdev);
2896 unregister_netdev(netdev);
2897 e100_free(nic);
2898 pci_iounmap(pdev, nic->csr);
2899 pci_pool_destroy(nic->cbs_pool);
2900 free_netdev(netdev);
2901 pci_release_regions(pdev);
2902 pci_disable_device(pdev);
2903 pci_set_drvdata(pdev, NULL);
2904 }
2905 }
2906
2907 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2908 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2909 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2910 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2911 {
2912 struct net_device *netdev = pci_get_drvdata(pdev);
2913 struct nic *nic = netdev_priv(netdev);
2914
2915 if (netif_running(netdev))
2916 e100_down(nic);
2917 netif_device_detach(netdev);
2918
2919 pci_save_state(pdev);
2920
2921 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2922 /* enable reverse auto-negotiation */
2923 if (nic->phy == phy_82552_v) {
2924 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2925 E100_82552_SMARTSPEED);
2926
2927 mdio_write(netdev, nic->mii.phy_id,
2928 E100_82552_SMARTSPEED, smartspeed |
2929 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2930 }
2931 *enable_wake = true;
2932 } else {
2933 *enable_wake = false;
2934 }
2935
2936 pci_disable_device(pdev);
2937 }
2938
2939 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2940 {
2941 if (wake)
2942 return pci_prepare_to_sleep(pdev);
2943
2944 pci_wake_from_d3(pdev, false);
2945 pci_set_power_state(pdev, PCI_D3hot);
2946
2947 return 0;
2948 }
2949
2950 #ifdef CONFIG_PM
2951 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2952 {
2953 bool wake;
2954 __e100_shutdown(pdev, &wake);
2955 return __e100_power_off(pdev, wake);
2956 }
2957
2958 static int e100_resume(struct pci_dev *pdev)
2959 {
2960 struct net_device *netdev = pci_get_drvdata(pdev);
2961 struct nic *nic = netdev_priv(netdev);
2962
2963 pci_set_power_state(pdev, PCI_D0);
2964 pci_restore_state(pdev);
2965 /* ack any pending wake events, disable PME */
2966 pci_enable_wake(pdev, 0, 0);
2967
2968 /* disable reverse auto-negotiation */
2969 if (nic->phy == phy_82552_v) {
2970 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2971 E100_82552_SMARTSPEED);
2972
2973 mdio_write(netdev, nic->mii.phy_id,
2974 E100_82552_SMARTSPEED,
2975 smartspeed & ~(E100_82552_REV_ANEG));
2976 }
2977
2978 netif_device_attach(netdev);
2979 if (netif_running(netdev))
2980 e100_up(nic);
2981
2982 return 0;
2983 }
2984 #endif /* CONFIG_PM */
2985
2986 static void e100_shutdown(struct pci_dev *pdev)
2987 {
2988 bool wake;
2989 __e100_shutdown(pdev, &wake);
2990 if (system_state == SYSTEM_POWER_OFF)
2991 __e100_power_off(pdev, wake);
2992 }
2993
2994 /* ------------------ PCI Error Recovery infrastructure -------------- */
2995 /**
2996 * e100_io_error_detected - called when PCI error is detected.
2997 * @pdev: Pointer to PCI device
2998 * @state: The current pci connection state
2999 */
3000 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3001 {
3002 struct net_device *netdev = pci_get_drvdata(pdev);
3003 struct nic *nic = netdev_priv(netdev);
3004
3005 netif_device_detach(netdev);
3006
3007 if (state == pci_channel_io_perm_failure)
3008 return PCI_ERS_RESULT_DISCONNECT;
3009
3010 if (netif_running(netdev))
3011 e100_down(nic);
3012 pci_disable_device(pdev);
3013
3014 /* Request a slot reset. */
3015 return PCI_ERS_RESULT_NEED_RESET;
3016 }
3017
3018 /**
3019 * e100_io_slot_reset - called after the pci bus has been reset.
3020 * @pdev: Pointer to PCI device
3021 *
3022 * Restart the card from scratch.
3023 */
3024 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3025 {
3026 struct net_device *netdev = pci_get_drvdata(pdev);
3027 struct nic *nic = netdev_priv(netdev);
3028
3029 if (pci_enable_device(pdev)) {
3030 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
3031 return PCI_ERS_RESULT_DISCONNECT;
3032 }
3033 pci_set_master(pdev);
3034
3035 /* Only one device per card can do a reset */
3036 if (0 != PCI_FUNC(pdev->devfn))
3037 return PCI_ERS_RESULT_RECOVERED;
3038 e100_hw_reset(nic);
3039 e100_phy_init(nic);
3040
3041 return PCI_ERS_RESULT_RECOVERED;
3042 }
3043
3044 /**
3045 * e100_io_resume - resume normal operations
3046 * @pdev: Pointer to PCI device
3047 *
3048 * Resume normal operations after an error recovery
3049 * sequence has been completed.
3050 */
3051 static void e100_io_resume(struct pci_dev *pdev)
3052 {
3053 struct net_device *netdev = pci_get_drvdata(pdev);
3054 struct nic *nic = netdev_priv(netdev);
3055
3056 /* ack any pending wake events, disable PME */
3057 pci_enable_wake(pdev, 0, 0);
3058
3059 netif_device_attach(netdev);
3060 if (netif_running(netdev)) {
3061 e100_open(netdev);
3062 mod_timer(&nic->watchdog, jiffies);
3063 }
3064 }
3065
3066 static struct pci_error_handlers e100_err_handler = {
3067 .error_detected = e100_io_error_detected,
3068 .slot_reset = e100_io_slot_reset,
3069 .resume = e100_io_resume,
3070 };
3071
3072 static struct pci_driver e100_driver = {
3073 .name = DRV_NAME,
3074 .id_table = e100_id_table,
3075 .probe = e100_probe,
3076 .remove = __devexit_p(e100_remove),
3077 #ifdef CONFIG_PM
3078 /* Power Management hooks */
3079 .suspend = e100_suspend,
3080 .resume = e100_resume,
3081 #endif
3082 .shutdown = e100_shutdown,
3083 .err_handler = &e100_err_handler,
3084 };
3085
3086 static int __init e100_init_module(void)
3087 {
3088 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3089 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3090 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3091 }
3092 return pci_register_driver(&e100_driver);
3093 }
3094
3095 static void __exit e100_cleanup_module(void)
3096 {
3097 pci_unregister_driver(&e100_driver);
3098 }
3099
3100 module_init(e100_init_module);
3101 module_exit(e100_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree