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b43: Add panic reason code that doesn't trigger restart
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / b43 / main.c
blobe1dfb40746766c0423ec3a88e0e39bbe5afbab41
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
44
45 #include "b43.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "nphy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
91
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
100 SSB_DEVTABLE_END
101 };
102
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
114 }
115
116 /*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
133 };
134
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
141
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149 }
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165 };
166 #undef CHAN4G
167
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175 }
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
232 };
233
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254 };
255 #undef CHAN5G
256
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
263 };
264
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
271 };
272
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
279 };
280
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
285
286 static int b43_ratelimit(struct b43_wl *wl)
287 {
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295 }
296
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
298 {
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308 }
309
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
311 {
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321 }
322
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
324 {
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334 }
335
336 #if B43_DEBUG
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338 {
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346 }
347 #endif /* DEBUG */
348
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350 {
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362 }
363
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
366 {
367 u32 control;
368
369 /* "offset" is the WORD offset. */
370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374 }
375
376 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
377 {
378 struct b43_wl *wl = dev->wl;
379 unsigned long flags;
380 u32 ret;
381
382 spin_lock_irqsave(&wl->shm_lock, flags);
383 if (routing == B43_SHM_SHARED) {
384 B43_WARN_ON(offset & 0x0001);
385 if (offset & 0x0003) {
386 /* Unaligned access */
387 b43_shm_control_word(dev, routing, offset >> 2);
388 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
389 ret <<= 16;
390 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
391 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
392
393 goto out;
394 }
395 offset >>= 2;
396 }
397 b43_shm_control_word(dev, routing, offset);
398 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
399 out:
400 spin_unlock_irqrestore(&wl->shm_lock, flags);
401
402 return ret;
403 }
404
405 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
406 {
407 struct b43_wl *wl = dev->wl;
408 unsigned long flags;
409 u16 ret;
410
411 spin_lock_irqsave(&wl->shm_lock, flags);
412 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev, routing, offset >> 2);
417 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
418
419 goto out;
420 }
421 offset >>= 2;
422 }
423 b43_shm_control_word(dev, routing, offset);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
425 out:
426 spin_unlock_irqrestore(&wl->shm_lock, flags);
427
428 return ret;
429 }
430
431 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
432 {
433 struct b43_wl *wl = dev->wl;
434 unsigned long flags;
435
436 spin_lock_irqsave(&wl->shm_lock, flags);
437 if (routing == B43_SHM_SHARED) {
438 B43_WARN_ON(offset & 0x0001);
439 if (offset & 0x0003) {
440 /* Unaligned access */
441 b43_shm_control_word(dev, routing, offset >> 2);
442 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
443 (value >> 16) & 0xffff);
444 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
445 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
446 goto out;
447 }
448 offset >>= 2;
449 }
450 b43_shm_control_word(dev, routing, offset);
451 b43_write32(dev, B43_MMIO_SHM_DATA, value);
452 out:
453 spin_unlock_irqrestore(&wl->shm_lock, flags);
454 }
455
456 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
457 {
458 struct b43_wl *wl = dev->wl;
459 unsigned long flags;
460
461 spin_lock_irqsave(&wl->shm_lock, flags);
462 if (routing == B43_SHM_SHARED) {
463 B43_WARN_ON(offset & 0x0001);
464 if (offset & 0x0003) {
465 /* Unaligned access */
466 b43_shm_control_word(dev, routing, offset >> 2);
467 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
468 goto out;
469 }
470 offset >>= 2;
471 }
472 b43_shm_control_word(dev, routing, offset);
473 b43_write16(dev, B43_MMIO_SHM_DATA, value);
474 out:
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
476 }
477
478 /* Read HostFlags */
479 u64 b43_hf_read(struct b43_wldev * dev)
480 {
481 u64 ret;
482
483 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
484 ret <<= 16;
485 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
486 ret <<= 16;
487 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488
489 return ret;
490 }
491
492 /* Write HostFlags */
493 void b43_hf_write(struct b43_wldev *dev, u64 value)
494 {
495 u16 lo, mi, hi;
496
497 lo = (value & 0x00000000FFFFULL);
498 mi = (value & 0x0000FFFF0000ULL) >> 16;
499 hi = (value & 0xFFFF00000000ULL) >> 32;
500 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
501 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
502 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
503 }
504
505 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
506 {
507 /* We need to be careful. As we read the TSF from multiple
508 * registers, we should take care of register overflows.
509 * In theory, the whole tsf read process should be atomic.
510 * We try to be atomic here, by restaring the read process,
511 * if any of the high registers changed (overflew).
512 */
513 if (dev->dev->id.revision >= 3) {
514 u32 low, high, high2;
515
516 do {
517 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
518 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
519 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
520 } while (unlikely(high != high2));
521
522 *tsf = high;
523 *tsf <<= 32;
524 *tsf |= low;
525 } else {
526 u64 tmp;
527 u16 v0, v1, v2, v3;
528 u16 test1, test2, test3;
529
530 do {
531 v3 = b43_read16(dev, B43_MMIO_TSF_3);
532 v2 = b43_read16(dev, B43_MMIO_TSF_2);
533 v1 = b43_read16(dev, B43_MMIO_TSF_1);
534 v0 = b43_read16(dev, B43_MMIO_TSF_0);
535
536 test3 = b43_read16(dev, B43_MMIO_TSF_3);
537 test2 = b43_read16(dev, B43_MMIO_TSF_2);
538 test1 = b43_read16(dev, B43_MMIO_TSF_1);
539 } while (v3 != test3 || v2 != test2 || v1 != test1);
540
541 *tsf = v3;
542 *tsf <<= 48;
543 tmp = v2;
544 tmp <<= 32;
545 *tsf |= tmp;
546 tmp = v1;
547 tmp <<= 16;
548 *tsf |= tmp;
549 *tsf |= v0;
550 }
551 }
552
553 static void b43_time_lock(struct b43_wldev *dev)
554 {
555 u32 macctl;
556
557 macctl = b43_read32(dev, B43_MMIO_MACCTL);
558 macctl |= B43_MACCTL_TBTTHOLD;
559 b43_write32(dev, B43_MMIO_MACCTL, macctl);
560 /* Commit the write */
561 b43_read32(dev, B43_MMIO_MACCTL);
562 }
563
564 static void b43_time_unlock(struct b43_wldev *dev)
565 {
566 u32 macctl;
567
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl &= ~B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
573 }
574
575 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
576 {
577 /* Be careful with the in-progress timer.
578 * First zero out the low register, so we have a full
579 * register-overflow duration to complete the operation.
580 */
581 if (dev->dev->id.revision >= 3) {
582 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
583 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
584
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
586 mmiowb();
587 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
588 mmiowb();
589 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
590 } else {
591 u16 v0 = (tsf & 0x000000000000FFFFULL);
592 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
593 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
594 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
595
596 b43_write16(dev, B43_MMIO_TSF_0, 0);
597 mmiowb();
598 b43_write16(dev, B43_MMIO_TSF_3, v3);
599 mmiowb();
600 b43_write16(dev, B43_MMIO_TSF_2, v2);
601 mmiowb();
602 b43_write16(dev, B43_MMIO_TSF_1, v1);
603 mmiowb();
604 b43_write16(dev, B43_MMIO_TSF_0, v0);
605 }
606 }
607
608 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
609 {
610 b43_time_lock(dev);
611 b43_tsf_write_locked(dev, tsf);
612 b43_time_unlock(dev);
613 }
614
615 static
616 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
617 {
618 static const u8 zero_addr[ETH_ALEN] = { 0 };
619 u16 data;
620
621 if (!mac)
622 mac = zero_addr;
623
624 offset |= 0x0020;
625 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
626
627 data = mac[0];
628 data |= mac[1] << 8;
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630 data = mac[2];
631 data |= mac[3] << 8;
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
633 data = mac[4];
634 data |= mac[5] << 8;
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636 }
637
638 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
639 {
640 const u8 *mac;
641 const u8 *bssid;
642 u8 mac_bssid[ETH_ALEN * 2];
643 int i;
644 u32 tmp;
645
646 bssid = dev->wl->bssid;
647 mac = dev->wl->mac_addr;
648
649 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
650
651 memcpy(mac_bssid, mac, ETH_ALEN);
652 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
653
654 /* Write our MAC address and BSSID to template ram */
655 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
656 tmp = (u32) (mac_bssid[i + 0]);
657 tmp |= (u32) (mac_bssid[i + 1]) << 8;
658 tmp |= (u32) (mac_bssid[i + 2]) << 16;
659 tmp |= (u32) (mac_bssid[i + 3]) << 24;
660 b43_ram_write(dev, 0x20 + i, tmp);
661 }
662 }
663
664 static void b43_upload_card_macaddress(struct b43_wldev *dev)
665 {
666 b43_write_mac_bssid_templates(dev);
667 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
668 }
669
670 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
671 {
672 /* slot_time is in usec. */
673 if (dev->phy.type != B43_PHYTYPE_G)
674 return;
675 b43_write16(dev, 0x684, 510 + slot_time);
676 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
677 }
678
679 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
680 {
681 b43_set_slot_time(dev, 9);
682 dev->short_slot = 1;
683 }
684
685 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
686 {
687 b43_set_slot_time(dev, 20);
688 dev->short_slot = 0;
689 }
690
691 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
692 * Returns the _previously_ enabled IRQ mask.
693 */
694 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
695 {
696 u32 old_mask;
697
698 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
699 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
700
701 return old_mask;
702 }
703
704 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
705 * Returns the _previously_ enabled IRQ mask.
706 */
707 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
708 {
709 u32 old_mask;
710
711 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
712 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
713
714 return old_mask;
715 }
716
717 /* Synchronize IRQ top- and bottom-half.
718 * IRQs must be masked before calling this.
719 * This must not be called with the irq_lock held.
720 */
721 static void b43_synchronize_irq(struct b43_wldev *dev)
722 {
723 synchronize_irq(dev->dev->irq);
724 tasklet_kill(&dev->isr_tasklet);
725 }
726
727 /* DummyTransmission function, as documented on
728 * http://bcm-specs.sipsolutions.net/DummyTransmission
729 */
730 void b43_dummy_transmission(struct b43_wldev *dev)
731 {
732 struct b43_wl *wl = dev->wl;
733 struct b43_phy *phy = &dev->phy;
734 unsigned int i, max_loop;
735 u16 value;
736 u32 buffer[5] = {
737 0x00000000,
738 0x00D40000,
739 0x00000000,
740 0x01000000,
741 0x00000000,
742 };
743
744 switch (phy->type) {
745 case B43_PHYTYPE_A:
746 max_loop = 0x1E;
747 buffer[0] = 0x000201CC;
748 break;
749 case B43_PHYTYPE_B:
750 case B43_PHYTYPE_G:
751 max_loop = 0xFA;
752 buffer[0] = 0x000B846E;
753 break;
754 default:
755 B43_WARN_ON(1);
756 return;
757 }
758
759 spin_lock_irq(&wl->irq_lock);
760 write_lock(&wl->tx_lock);
761
762 for (i = 0; i < 5; i++)
763 b43_ram_write(dev, i * 4, buffer[i]);
764
765 /* Commit writes */
766 b43_read32(dev, B43_MMIO_MACCTL);
767
768 b43_write16(dev, 0x0568, 0x0000);
769 b43_write16(dev, 0x07C0, 0x0000);
770 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
771 b43_write16(dev, 0x050C, value);
772 b43_write16(dev, 0x0508, 0x0000);
773 b43_write16(dev, 0x050A, 0x0000);
774 b43_write16(dev, 0x054C, 0x0000);
775 b43_write16(dev, 0x056A, 0x0014);
776 b43_write16(dev, 0x0568, 0x0826);
777 b43_write16(dev, 0x0500, 0x0000);
778 b43_write16(dev, 0x0502, 0x0030);
779
780 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
781 b43_radio_write16(dev, 0x0051, 0x0017);
782 for (i = 0x00; i < max_loop; i++) {
783 value = b43_read16(dev, 0x050E);
784 if (value & 0x0080)
785 break;
786 udelay(10);
787 }
788 for (i = 0x00; i < 0x0A; i++) {
789 value = b43_read16(dev, 0x050E);
790 if (value & 0x0400)
791 break;
792 udelay(10);
793 }
794 for (i = 0x00; i < 0x0A; i++) {
795 value = b43_read16(dev, 0x0690);
796 if (!(value & 0x0100))
797 break;
798 udelay(10);
799 }
800 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
801 b43_radio_write16(dev, 0x0051, 0x0037);
802
803 write_unlock(&wl->tx_lock);
804 spin_unlock_irq(&wl->irq_lock);
805 }
806
807 static void key_write(struct b43_wldev *dev,
808 u8 index, u8 algorithm, const u8 * key)
809 {
810 unsigned int i;
811 u32 offset;
812 u16 value;
813 u16 kidx;
814
815 /* Key index/algo block */
816 kidx = b43_kidx_to_fw(dev, index);
817 value = ((kidx << 4) | algorithm);
818 b43_shm_write16(dev, B43_SHM_SHARED,
819 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
820
821 /* Write the key to the Key Table Pointer offset */
822 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
823 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
824 value = key[i];
825 value |= (u16) (key[i + 1]) << 8;
826 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
827 }
828 }
829
830 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
831 {
832 u32 addrtmp[2] = { 0, 0, };
833 u8 per_sta_keys_start = 8;
834
835 if (b43_new_kidx_api(dev))
836 per_sta_keys_start = 4;
837
838 B43_WARN_ON(index < per_sta_keys_start);
839 /* We have two default TX keys and possibly two default RX keys.
840 * Physical mac 0 is mapped to physical key 4 or 8, depending
841 * on the firmware version.
842 * So we must adjust the index here.
843 */
844 index -= per_sta_keys_start;
845
846 if (addr) {
847 addrtmp[0] = addr[0];
848 addrtmp[0] |= ((u32) (addr[1]) << 8);
849 addrtmp[0] |= ((u32) (addr[2]) << 16);
850 addrtmp[0] |= ((u32) (addr[3]) << 24);
851 addrtmp[1] = addr[4];
852 addrtmp[1] |= ((u32) (addr[5]) << 8);
853 }
854
855 if (dev->dev->id.revision >= 5) {
856 /* Receive match transmitter address mechanism */
857 b43_shm_write32(dev, B43_SHM_RCMTA,
858 (index * 2) + 0, addrtmp[0]);
859 b43_shm_write16(dev, B43_SHM_RCMTA,
860 (index * 2) + 1, addrtmp[1]);
861 } else {
862 /* RXE (Receive Engine) and
863 * PSM (Programmable State Machine) mechanism
864 */
865 if (index < 8) {
866 /* TODO write to RCM 16, 19, 22 and 25 */
867 } else {
868 b43_shm_write32(dev, B43_SHM_SHARED,
869 B43_SHM_SH_PSM + (index * 6) + 0,
870 addrtmp[0]);
871 b43_shm_write16(dev, B43_SHM_SHARED,
872 B43_SHM_SH_PSM + (index * 6) + 4,
873 addrtmp[1]);
874 }
875 }
876 }
877
878 static void do_key_write(struct b43_wldev *dev,
879 u8 index, u8 algorithm,
880 const u8 * key, size_t key_len, const u8 * mac_addr)
881 {
882 u8 buf[B43_SEC_KEYSIZE] = { 0, };
883 u8 per_sta_keys_start = 8;
884
885 if (b43_new_kidx_api(dev))
886 per_sta_keys_start = 4;
887
888 B43_WARN_ON(index >= dev->max_nr_keys);
889 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
890
891 if (index >= per_sta_keys_start)
892 keymac_write(dev, index, NULL); /* First zero out mac. */
893 if (key)
894 memcpy(buf, key, key_len);
895 key_write(dev, index, algorithm, buf);
896 if (index >= per_sta_keys_start)
897 keymac_write(dev, index, mac_addr);
898
899 dev->key[index].algorithm = algorithm;
900 }
901
902 static int b43_key_write(struct b43_wldev *dev,
903 int index, u8 algorithm,
904 const u8 * key, size_t key_len,
905 const u8 * mac_addr,
906 struct ieee80211_key_conf *keyconf)
907 {
908 int i;
909 int sta_keys_start;
910
911 if (key_len > B43_SEC_KEYSIZE)
912 return -EINVAL;
913 for (i = 0; i < dev->max_nr_keys; i++) {
914 /* Check that we don't already have this key. */
915 B43_WARN_ON(dev->key[i].keyconf == keyconf);
916 }
917 if (index < 0) {
918 /* Either pairwise key or address is 00:00:00:00:00:00
919 * for transmit-only keys. Search the index. */
920 if (b43_new_kidx_api(dev))
921 sta_keys_start = 4;
922 else
923 sta_keys_start = 8;
924 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
925 if (!dev->key[i].keyconf) {
926 /* found empty */
927 index = i;
928 break;
929 }
930 }
931 if (index < 0) {
932 b43err(dev->wl, "Out of hardware key memory\n");
933 return -ENOSPC;
934 }
935 } else
936 B43_WARN_ON(index > 3);
937
938 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
939 if ((index <= 3) && !b43_new_kidx_api(dev)) {
940 /* Default RX key */
941 B43_WARN_ON(mac_addr);
942 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
943 }
944 keyconf->hw_key_idx = index;
945 dev->key[index].keyconf = keyconf;
946
947 return 0;
948 }
949
950 static int b43_key_clear(struct b43_wldev *dev, int index)
951 {
952 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
953 return -EINVAL;
954 do_key_write(dev, index, B43_SEC_ALGO_NONE,
955 NULL, B43_SEC_KEYSIZE, NULL);
956 if ((index <= 3) && !b43_new_kidx_api(dev)) {
957 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
958 NULL, B43_SEC_KEYSIZE, NULL);
959 }
960 dev->key[index].keyconf = NULL;
961
962 return 0;
963 }
964
965 static void b43_clear_keys(struct b43_wldev *dev)
966 {
967 int i;
968
969 for (i = 0; i < dev->max_nr_keys; i++)
970 b43_key_clear(dev, i);
971 }
972
973 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
974 {
975 u32 macctl;
976 u16 ucstat;
977 bool hwps;
978 bool awake;
979 int i;
980
981 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
982 (ps_flags & B43_PS_DISABLED));
983 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
984
985 if (ps_flags & B43_PS_ENABLED) {
986 hwps = 1;
987 } else if (ps_flags & B43_PS_DISABLED) {
988 hwps = 0;
989 } else {
990 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
991 // and thus is not an AP and we are associated, set bit 25
992 }
993 if (ps_flags & B43_PS_AWAKE) {
994 awake = 1;
995 } else if (ps_flags & B43_PS_ASLEEP) {
996 awake = 0;
997 } else {
998 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
999 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1000 // successful, set bit26
1001 }
1002
1003 /* FIXME: For now we force awake-on and hwps-off */
1004 hwps = 0;
1005 awake = 1;
1006
1007 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1008 if (hwps)
1009 macctl |= B43_MACCTL_HWPS;
1010 else
1011 macctl &= ~B43_MACCTL_HWPS;
1012 if (awake)
1013 macctl |= B43_MACCTL_AWAKE;
1014 else
1015 macctl &= ~B43_MACCTL_AWAKE;
1016 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1017 /* Commit write */
1018 b43_read32(dev, B43_MMIO_MACCTL);
1019 if (awake && dev->dev->id.revision >= 5) {
1020 /* Wait for the microcode to wake up. */
1021 for (i = 0; i < 100; i++) {
1022 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1023 B43_SHM_SH_UCODESTAT);
1024 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1025 break;
1026 udelay(10);
1027 }
1028 }
1029 }
1030
1031 /* Turn the Analog ON/OFF */
1032 static void b43_switch_analog(struct b43_wldev *dev, int on)
1033 {
1034 switch (dev->phy.type) {
1035 case B43_PHYTYPE_A:
1036 case B43_PHYTYPE_G:
1037 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1038 break;
1039 case B43_PHYTYPE_N:
1040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1041 on ? 0 : 0x7FFF);
1042 break;
1043 default:
1044 B43_WARN_ON(1);
1045 }
1046 }
1047
1048 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1049 {
1050 u32 tmslow;
1051 u32 macctl;
1052
1053 flags |= B43_TMSLOW_PHYCLKEN;
1054 flags |= B43_TMSLOW_PHYRESET;
1055 ssb_device_enable(dev->dev, flags);
1056 msleep(2); /* Wait for the PLL to turn on. */
1057
1058 /* Now take the PHY out of Reset again */
1059 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1060 tmslow |= SSB_TMSLOW_FGC;
1061 tmslow &= ~B43_TMSLOW_PHYRESET;
1062 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1063 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1064 msleep(1);
1065 tmslow &= ~SSB_TMSLOW_FGC;
1066 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1067 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1068 msleep(1);
1069
1070 /* Turn Analog ON */
1071 b43_switch_analog(dev, 1);
1072
1073 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1074 macctl &= ~B43_MACCTL_GMODE;
1075 if (flags & B43_TMSLOW_GMODE)
1076 macctl |= B43_MACCTL_GMODE;
1077 macctl |= B43_MACCTL_IHR_ENABLED;
1078 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1079 }
1080
1081 static void handle_irq_transmit_status(struct b43_wldev *dev)
1082 {
1083 u32 v0, v1;
1084 u16 tmp;
1085 struct b43_txstatus stat;
1086
1087 while (1) {
1088 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1089 if (!(v0 & 0x00000001))
1090 break;
1091 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1092
1093 stat.cookie = (v0 >> 16);
1094 stat.seq = (v1 & 0x0000FFFF);
1095 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1096 tmp = (v0 & 0x0000FFFF);
1097 stat.frame_count = ((tmp & 0xF000) >> 12);
1098 stat.rts_count = ((tmp & 0x0F00) >> 8);
1099 stat.supp_reason = ((tmp & 0x001C) >> 2);
1100 stat.pm_indicated = !!(tmp & 0x0080);
1101 stat.intermediate = !!(tmp & 0x0040);
1102 stat.for_ampdu = !!(tmp & 0x0020);
1103 stat.acked = !!(tmp & 0x0002);
1104
1105 b43_handle_txstatus(dev, &stat);
1106 }
1107 }
1108
1109 static void drain_txstatus_queue(struct b43_wldev *dev)
1110 {
1111 u32 dummy;
1112
1113 if (dev->dev->id.revision < 5)
1114 return;
1115 /* Read all entries from the microcode TXstatus FIFO
1116 * and throw them away.
1117 */
1118 while (1) {
1119 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1120 if (!(dummy & 0x00000001))
1121 break;
1122 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1123 }
1124 }
1125
1126 static u32 b43_jssi_read(struct b43_wldev *dev)
1127 {
1128 u32 val = 0;
1129
1130 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1131 val <<= 16;
1132 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1133
1134 return val;
1135 }
1136
1137 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1138 {
1139 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1140 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1141 }
1142
1143 static void b43_generate_noise_sample(struct b43_wldev *dev)
1144 {
1145 b43_jssi_write(dev, 0x7F7F7F7F);
1146 b43_write32(dev, B43_MMIO_MACCMD,
1147 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1148 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1149 }
1150
1151 static void b43_calculate_link_quality(struct b43_wldev *dev)
1152 {
1153 /* Top half of Link Quality calculation. */
1154
1155 if (dev->noisecalc.calculation_running)
1156 return;
1157 dev->noisecalc.channel_at_start = dev->phy.channel;
1158 dev->noisecalc.calculation_running = 1;
1159 dev->noisecalc.nr_samples = 0;
1160
1161 b43_generate_noise_sample(dev);
1162 }
1163
1164 static void handle_irq_noise(struct b43_wldev *dev)
1165 {
1166 struct b43_phy *phy = &dev->phy;
1167 u16 tmp;
1168 u8 noise[4];
1169 u8 i, j;
1170 s32 average;
1171
1172 /* Bottom half of Link Quality calculation. */
1173
1174 B43_WARN_ON(!dev->noisecalc.calculation_running);
1175 if (dev->noisecalc.channel_at_start != phy->channel)
1176 goto drop_calculation;
1177 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1178 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1179 noise[2] == 0x7F || noise[3] == 0x7F)
1180 goto generate_new;
1181
1182 /* Get the noise samples. */
1183 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1184 i = dev->noisecalc.nr_samples;
1185 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1186 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1187 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1188 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1189 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1190 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1191 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1192 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1193 dev->noisecalc.nr_samples++;
1194 if (dev->noisecalc.nr_samples == 8) {
1195 /* Calculate the Link Quality by the noise samples. */
1196 average = 0;
1197 for (i = 0; i < 8; i++) {
1198 for (j = 0; j < 4; j++)
1199 average += dev->noisecalc.samples[i][j];
1200 }
1201 average /= (8 * 4);
1202 average *= 125;
1203 average += 64;
1204 average /= 128;
1205 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1206 tmp = (tmp / 128) & 0x1F;
1207 if (tmp >= 8)
1208 average += 2;
1209 else
1210 average -= 25;
1211 if (tmp == 8)
1212 average -= 72;
1213 else
1214 average -= 48;
1215
1216 dev->stats.link_noise = average;
1217 drop_calculation:
1218 dev->noisecalc.calculation_running = 0;
1219 return;
1220 }
1221 generate_new:
1222 b43_generate_noise_sample(dev);
1223 }
1224
1225 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1226 {
1227 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1228 ///TODO: PS TBTT
1229 } else {
1230 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1231 b43_power_saving_ctl_bits(dev, 0);
1232 }
1233 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1234 dev->dfq_valid = 1;
1235 }
1236
1237 static void handle_irq_atim_end(struct b43_wldev *dev)
1238 {
1239 if (dev->dfq_valid) {
1240 b43_write32(dev, B43_MMIO_MACCMD,
1241 b43_read32(dev, B43_MMIO_MACCMD)
1242 | B43_MACCMD_DFQ_VALID);
1243 dev->dfq_valid = 0;
1244 }
1245 }
1246
1247 static void handle_irq_pmq(struct b43_wldev *dev)
1248 {
1249 u32 tmp;
1250
1251 //TODO: AP mode.
1252
1253 while (1) {
1254 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1255 if (!(tmp & 0x00000008))
1256 break;
1257 }
1258 /* 16bit write is odd, but correct. */
1259 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1260 }
1261
1262 static void b43_write_template_common(struct b43_wldev *dev,
1263 const u8 * data, u16 size,
1264 u16 ram_offset,
1265 u16 shm_size_offset, u8 rate)
1266 {
1267 u32 i, tmp;
1268 struct b43_plcp_hdr4 plcp;
1269
1270 plcp.data = 0;
1271 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1272 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1273 ram_offset += sizeof(u32);
1274 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1275 * So leave the first two bytes of the next write blank.
1276 */
1277 tmp = (u32) (data[0]) << 16;
1278 tmp |= (u32) (data[1]) << 24;
1279 b43_ram_write(dev, ram_offset, tmp);
1280 ram_offset += sizeof(u32);
1281 for (i = 2; i < size; i += sizeof(u32)) {
1282 tmp = (u32) (data[i + 0]);
1283 if (i + 1 < size)
1284 tmp |= (u32) (data[i + 1]) << 8;
1285 if (i + 2 < size)
1286 tmp |= (u32) (data[i + 2]) << 16;
1287 if (i + 3 < size)
1288 tmp |= (u32) (data[i + 3]) << 24;
1289 b43_ram_write(dev, ram_offset + i - 2, tmp);
1290 }
1291 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1292 size + sizeof(struct b43_plcp_hdr6));
1293 }
1294
1295 /* Check if the use of the antenna that ieee80211 told us to
1296 * use is possible. This will fall back to DEFAULT.
1297 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1298 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1299 u8 antenna_nr)
1300 {
1301 u8 antenna_mask;
1302
1303 if (antenna_nr == 0) {
1304 /* Zero means "use default antenna". That's always OK. */
1305 return 0;
1306 }
1307
1308 /* Get the mask of available antennas. */
1309 if (dev->phy.gmode)
1310 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1311 else
1312 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1313
1314 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1315 /* This antenna is not available. Fall back to default. */
1316 return 0;
1317 }
1318
1319 return antenna_nr;
1320 }
1321
1322 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1323 {
1324 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1325 switch (antenna) {
1326 case 0: /* default/diversity */
1327 return B43_ANTENNA_DEFAULT;
1328 case 1: /* Antenna 0 */
1329 return B43_ANTENNA0;
1330 case 2: /* Antenna 1 */
1331 return B43_ANTENNA1;
1332 case 3: /* Antenna 2 */
1333 return B43_ANTENNA2;
1334 case 4: /* Antenna 3 */
1335 return B43_ANTENNA3;
1336 default:
1337 return B43_ANTENNA_DEFAULT;
1338 }
1339 }
1340
1341 /* Convert a b43 antenna number value to the PHY TX control value. */
1342 static u16 b43_antenna_to_phyctl(int antenna)
1343 {
1344 switch (antenna) {
1345 case B43_ANTENNA0:
1346 return B43_TXH_PHY_ANT0;
1347 case B43_ANTENNA1:
1348 return B43_TXH_PHY_ANT1;
1349 case B43_ANTENNA2:
1350 return B43_TXH_PHY_ANT2;
1351 case B43_ANTENNA3:
1352 return B43_TXH_PHY_ANT3;
1353 case B43_ANTENNA_AUTO:
1354 return B43_TXH_PHY_ANT01AUTO;
1355 }
1356 B43_WARN_ON(1);
1357 return 0;
1358 }
1359
1360 static void b43_write_beacon_template(struct b43_wldev *dev,
1361 u16 ram_offset,
1362 u16 shm_size_offset)
1363 {
1364 unsigned int i, len, variable_len;
1365 const struct ieee80211_mgmt *bcn;
1366 const u8 *ie;
1367 bool tim_found = 0;
1368 unsigned int rate;
1369 u16 ctl;
1370 int antenna;
1371 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1372
1373 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1374 len = min((size_t) dev->wl->current_beacon->len,
1375 0x200 - sizeof(struct b43_plcp_hdr6));
1376 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1377
1378 b43_write_template_common(dev, (const u8 *)bcn,
1379 len, ram_offset, shm_size_offset, rate);
1380
1381 /* Write the PHY TX control parameters. */
1382 antenna = b43_antenna_from_ieee80211(dev, info->antenna_sel_tx);
1383 antenna = b43_antenna_to_phyctl(antenna);
1384 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1385 /* We can't send beacons with short preamble. Would get PHY errors. */
1386 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1387 ctl &= ~B43_TXH_PHY_ANT;
1388 ctl &= ~B43_TXH_PHY_ENC;
1389 ctl |= antenna;
1390 if (b43_is_cck_rate(rate))
1391 ctl |= B43_TXH_PHY_ENC_CCK;
1392 else
1393 ctl |= B43_TXH_PHY_ENC_OFDM;
1394 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1395
1396 /* Find the position of the TIM and the DTIM_period value
1397 * and write them to SHM. */
1398 ie = bcn->u.beacon.variable;
1399 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1400 for (i = 0; i < variable_len - 2; ) {
1401 uint8_t ie_id, ie_len;
1402
1403 ie_id = ie[i];
1404 ie_len = ie[i + 1];
1405 if (ie_id == 5) {
1406 u16 tim_position;
1407 u16 dtim_period;
1408 /* This is the TIM Information Element */
1409
1410 /* Check whether the ie_len is in the beacon data range. */
1411 if (variable_len < ie_len + 2 + i)
1412 break;
1413 /* A valid TIM is at least 4 bytes long. */
1414 if (ie_len < 4)
1415 break;
1416 tim_found = 1;
1417
1418 tim_position = sizeof(struct b43_plcp_hdr6);
1419 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1420 tim_position += i;
1421
1422 dtim_period = ie[i + 3];
1423
1424 b43_shm_write16(dev, B43_SHM_SHARED,
1425 B43_SHM_SH_TIMBPOS, tim_position);
1426 b43_shm_write16(dev, B43_SHM_SHARED,
1427 B43_SHM_SH_DTIMPER, dtim_period);
1428 break;
1429 }
1430 i += ie_len + 2;
1431 }
1432 if (!tim_found) {
1433 b43warn(dev->wl, "Did not find a valid TIM IE in "
1434 "the beacon template packet. AP or IBSS operation "
1435 "may be broken.\n");
1436 } else
1437 b43dbg(dev->wl, "Updated beacon template\n");
1438 }
1439
1440 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1441 u16 shm_offset, u16 size,
1442 struct ieee80211_rate *rate)
1443 {
1444 struct b43_plcp_hdr4 plcp;
1445 u32 tmp;
1446 __le16 dur;
1447
1448 plcp.data = 0;
1449 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1450 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1451 dev->wl->vif, size,
1452 rate);
1453 /* Write PLCP in two parts and timing for packet transfer */
1454 tmp = le32_to_cpu(plcp.data);
1455 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1456 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1457 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1458 }
1459
1460 /* Instead of using custom probe response template, this function
1461 * just patches custom beacon template by:
1462 * 1) Changing packet type
1463 * 2) Patching duration field
1464 * 3) Stripping TIM
1465 */
1466 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1467 u16 *dest_size,
1468 struct ieee80211_rate *rate)
1469 {
1470 const u8 *src_data;
1471 u8 *dest_data;
1472 u16 src_size, elem_size, src_pos, dest_pos;
1473 __le16 dur;
1474 struct ieee80211_hdr *hdr;
1475 size_t ie_start;
1476
1477 src_size = dev->wl->current_beacon->len;
1478 src_data = (const u8 *)dev->wl->current_beacon->data;
1479
1480 /* Get the start offset of the variable IEs in the packet. */
1481 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1482 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1483
1484 if (B43_WARN_ON(src_size < ie_start))
1485 return NULL;
1486
1487 dest_data = kmalloc(src_size, GFP_ATOMIC);
1488 if (unlikely(!dest_data))
1489 return NULL;
1490
1491 /* Copy the static data and all Information Elements, except the TIM. */
1492 memcpy(dest_data, src_data, ie_start);
1493 src_pos = ie_start;
1494 dest_pos = ie_start;
1495 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1496 elem_size = src_data[src_pos + 1] + 2;
1497 if (src_data[src_pos] == 5) {
1498 /* This is the TIM. */
1499 continue;
1500 }
1501 memcpy(dest_data + dest_pos, src_data + src_pos,
1502 elem_size);
1503 dest_pos += elem_size;
1504 }
1505 *dest_size = dest_pos;
1506 hdr = (struct ieee80211_hdr *)dest_data;
1507
1508 /* Set the frame control. */
1509 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1510 IEEE80211_STYPE_PROBE_RESP);
1511 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1512 dev->wl->vif, *dest_size,
1513 rate);
1514 hdr->duration_id = dur;
1515
1516 return dest_data;
1517 }
1518
1519 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1520 u16 ram_offset,
1521 u16 shm_size_offset,
1522 struct ieee80211_rate *rate)
1523 {
1524 const u8 *probe_resp_data;
1525 u16 size;
1526
1527 size = dev->wl->current_beacon->len;
1528 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1529 if (unlikely(!probe_resp_data))
1530 return;
1531
1532 /* Looks like PLCP headers plus packet timings are stored for
1533 * all possible basic rates
1534 */
1535 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1536 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1537 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1538 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1539
1540 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1541 b43_write_template_common(dev, probe_resp_data,
1542 size, ram_offset, shm_size_offset,
1543 rate->hw_value);
1544 kfree(probe_resp_data);
1545 }
1546
1547 static void handle_irq_beacon(struct b43_wldev *dev)
1548 {
1549 struct b43_wl *wl = dev->wl;
1550 u32 cmd, beacon0_valid, beacon1_valid;
1551
1552 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1553 return;
1554
1555 /* This is the bottom half of the asynchronous beacon update. */
1556
1557 /* Ignore interrupt in the future. */
1558 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1559
1560 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1561 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1562 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1563
1564 /* Schedule interrupt manually, if busy. */
1565 if (beacon0_valid && beacon1_valid) {
1566 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1567 dev->irq_savedstate |= B43_IRQ_BEACON;
1568 return;
1569 }
1570
1571 if (!beacon0_valid) {
1572 if (!wl->beacon0_uploaded) {
1573 b43_write_beacon_template(dev, 0x68, 0x18);
1574 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1575 &__b43_ratetable[3]);
1576 wl->beacon0_uploaded = 1;
1577 }
1578 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1579 cmd |= B43_MACCMD_BEACON0_VALID;
1580 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1581 } else if (!beacon1_valid) {
1582 if (!wl->beacon1_uploaded) {
1583 b43_write_beacon_template(dev, 0x468, 0x1A);
1584 wl->beacon1_uploaded = 1;
1585 }
1586 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1587 cmd |= B43_MACCMD_BEACON1_VALID;
1588 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1589 }
1590 }
1591
1592 static void b43_beacon_update_trigger_work(struct work_struct *work)
1593 {
1594 struct b43_wl *wl = container_of(work, struct b43_wl,
1595 beacon_update_trigger);
1596 struct b43_wldev *dev;
1597
1598 mutex_lock(&wl->mutex);
1599 dev = wl->current_dev;
1600 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1601 spin_lock_irq(&wl->irq_lock);
1602 /* update beacon right away or defer to irq */
1603 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1604 handle_irq_beacon(dev);
1605 /* The handler might have updated the IRQ mask. */
1606 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1607 dev->irq_savedstate);
1608 mmiowb();
1609 spin_unlock_irq(&wl->irq_lock);
1610 }
1611 mutex_unlock(&wl->mutex);
1612 }
1613
1614 /* Asynchronously update the packet templates in template RAM.
1615 * Locking: Requires wl->irq_lock to be locked. */
1616 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1617 {
1618 /* This is the top half of the ansynchronous beacon update.
1619 * The bottom half is the beacon IRQ.
1620 * Beacon update must be asynchronous to avoid sending an
1621 * invalid beacon. This can happen for example, if the firmware
1622 * transmits a beacon while we are updating it. */
1623
1624 if (wl->current_beacon)
1625 dev_kfree_skb_any(wl->current_beacon);
1626 wl->current_beacon = beacon;
1627 wl->beacon0_uploaded = 0;
1628 wl->beacon1_uploaded = 0;
1629 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1630 }
1631
1632 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1633 {
1634 u32 tmp;
1635 u16 i, len;
1636
1637 len = min((u16) ssid_len, (u16) 0x100);
1638 for (i = 0; i < len; i += sizeof(u32)) {
1639 tmp = (u32) (ssid[i + 0]);
1640 if (i + 1 < len)
1641 tmp |= (u32) (ssid[i + 1]) << 8;
1642 if (i + 2 < len)
1643 tmp |= (u32) (ssid[i + 2]) << 16;
1644 if (i + 3 < len)
1645 tmp |= (u32) (ssid[i + 3]) << 24;
1646 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1647 }
1648 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1649 }
1650
1651 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1652 {
1653 b43_time_lock(dev);
1654 if (dev->dev->id.revision >= 3) {
1655 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1656 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1657 } else {
1658 b43_write16(dev, 0x606, (beacon_int >> 6));
1659 b43_write16(dev, 0x610, beacon_int);
1660 }
1661 b43_time_unlock(dev);
1662 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1663 }
1664
1665 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1666 {
1667 u16 reason;
1668
1669 /* Read the register that contains the reason code for the panic. */
1670 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1671 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1672
1673 switch (reason) {
1674 default:
1675 b43dbg(dev->wl, "The panic reason is unknown.\n");
1676 /* fallthrough */
1677 case B43_FWPANIC_DIE:
1678 /* Do not restart the controller or firmware.
1679 * The device is nonfunctional from now on.
1680 * Restarting would result in this panic to trigger again,
1681 * so we avoid that recursion. */
1682 break;
1683 case B43_FWPANIC_RESTART:
1684 b43_controller_restart(dev, "Microcode panic");
1685 break;
1686 }
1687 }
1688
1689 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1690 {
1691 unsigned int i, cnt;
1692 u16 reason;
1693 __le16 *buf;
1694
1695 /* The proprietary firmware doesn't have this IRQ. */
1696 if (!dev->fw.opensource)
1697 return;
1698
1699 /* Read the register that contains the reason code for this IRQ. */
1700 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1701
1702 switch (reason) {
1703 case B43_DEBUGIRQ_PANIC:
1704 b43_handle_firmware_panic(dev);
1705 break;
1706 case B43_DEBUGIRQ_DUMP_SHM:
1707 if (!B43_DEBUG)
1708 break; /* Only with driver debugging enabled. */
1709 buf = kmalloc(4096, GFP_ATOMIC);
1710 if (!buf) {
1711 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1712 goto out;
1713 }
1714 for (i = 0; i < 4096; i += 2) {
1715 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1716 buf[i / 2] = cpu_to_le16(tmp);
1717 }
1718 b43info(dev->wl, "Shared memory dump:\n");
1719 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1720 16, 2, buf, 4096, 1);
1721 kfree(buf);
1722 break;
1723 case B43_DEBUGIRQ_DUMP_REGS:
1724 if (!B43_DEBUG)
1725 break; /* Only with driver debugging enabled. */
1726 b43info(dev->wl, "Microcode register dump:\n");
1727 for (i = 0, cnt = 0; i < 64; i++) {
1728 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1729 if (cnt == 0)
1730 printk(KERN_INFO);
1731 printk("r%02u: 0x%04X ", i, tmp);
1732 cnt++;
1733 if (cnt == 6) {
1734 printk("\n");
1735 cnt = 0;
1736 }
1737 }
1738 printk("\n");
1739 break;
1740 default:
1741 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1742 reason);
1743 }
1744 out:
1745 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1746 b43_shm_write16(dev, B43_SHM_SCRATCH,
1747 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1748 }
1749
1750 /* Interrupt handler bottom-half */
1751 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1752 {
1753 u32 reason;
1754 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1755 u32 merged_dma_reason = 0;
1756 int i;
1757 unsigned long flags;
1758
1759 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1760
1761 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1762
1763 reason = dev->irq_reason;
1764 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1765 dma_reason[i] = dev->dma_reason[i];
1766 merged_dma_reason |= dma_reason[i];
1767 }
1768
1769 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1770 b43err(dev->wl, "MAC transmission error\n");
1771
1772 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1773 b43err(dev->wl, "PHY transmission error\n");
1774 rmb();
1775 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1776 atomic_set(&dev->phy.txerr_cnt,
1777 B43_PHY_TX_BADNESS_LIMIT);
1778 b43err(dev->wl, "Too many PHY TX errors, "
1779 "restarting the controller\n");
1780 b43_controller_restart(dev, "PHY TX errors");
1781 }
1782 }
1783
1784 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1785 B43_DMAIRQ_NONFATALMASK))) {
1786 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1787 b43err(dev->wl, "Fatal DMA error: "
1788 "0x%08X, 0x%08X, 0x%08X, "
1789 "0x%08X, 0x%08X, 0x%08X\n",
1790 dma_reason[0], dma_reason[1],
1791 dma_reason[2], dma_reason[3],
1792 dma_reason[4], dma_reason[5]);
1793 b43_controller_restart(dev, "DMA error");
1794 mmiowb();
1795 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1796 return;
1797 }
1798 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1799 b43err(dev->wl, "DMA error: "
1800 "0x%08X, 0x%08X, 0x%08X, "
1801 "0x%08X, 0x%08X, 0x%08X\n",
1802 dma_reason[0], dma_reason[1],
1803 dma_reason[2], dma_reason[3],
1804 dma_reason[4], dma_reason[5]);
1805 }
1806 }
1807
1808 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1809 handle_irq_ucode_debug(dev);
1810 if (reason & B43_IRQ_TBTT_INDI)
1811 handle_irq_tbtt_indication(dev);
1812 if (reason & B43_IRQ_ATIM_END)
1813 handle_irq_atim_end(dev);
1814 if (reason & B43_IRQ_BEACON)
1815 handle_irq_beacon(dev);
1816 if (reason & B43_IRQ_PMQ)
1817 handle_irq_pmq(dev);
1818 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1819 ;/* TODO */
1820 if (reason & B43_IRQ_NOISESAMPLE_OK)
1821 handle_irq_noise(dev);
1822
1823 /* Check the DMA reason registers for received data. */
1824 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1825 if (b43_using_pio_transfers(dev))
1826 b43_pio_rx(dev->pio.rx_queue);
1827 else
1828 b43_dma_rx(dev->dma.rx_ring);
1829 }
1830 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1831 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1832 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1833 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1834 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1835
1836 if (reason & B43_IRQ_TX_OK)
1837 handle_irq_transmit_status(dev);
1838
1839 b43_interrupt_enable(dev, dev->irq_savedstate);
1840 mmiowb();
1841 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1842 }
1843
1844 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1845 {
1846 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1847
1848 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1849 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1850 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1851 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1852 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1853 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1854 }
1855
1856 /* Interrupt handler top-half */
1857 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1858 {
1859 irqreturn_t ret = IRQ_NONE;
1860 struct b43_wldev *dev = dev_id;
1861 u32 reason;
1862
1863 if (!dev)
1864 return IRQ_NONE;
1865
1866 spin_lock(&dev->wl->irq_lock);
1867
1868 if (b43_status(dev) < B43_STAT_STARTED)
1869 goto out;
1870 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1871 if (reason == 0xffffffff) /* shared IRQ */
1872 goto out;
1873 ret = IRQ_HANDLED;
1874 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1875 if (!reason)
1876 goto out;
1877
1878 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1879 & 0x0001DC00;
1880 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1881 & 0x0000DC00;
1882 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1883 & 0x0000DC00;
1884 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1885 & 0x0001DC00;
1886 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1887 & 0x0000DC00;
1888 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1889 & 0x0000DC00;
1890
1891 b43_interrupt_ack(dev, reason);
1892 /* disable all IRQs. They are enabled again in the bottom half. */
1893 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1894 /* save the reason code and call our bottom half. */
1895 dev->irq_reason = reason;
1896 tasklet_schedule(&dev->isr_tasklet);
1897 out:
1898 mmiowb();
1899 spin_unlock(&dev->wl->irq_lock);
1900
1901 return ret;
1902 }
1903
1904 static void do_release_fw(struct b43_firmware_file *fw)
1905 {
1906 release_firmware(fw->data);
1907 fw->data = NULL;
1908 fw->filename = NULL;
1909 }
1910
1911 static void b43_release_firmware(struct b43_wldev *dev)
1912 {
1913 do_release_fw(&dev->fw.ucode);
1914 do_release_fw(&dev->fw.pcm);
1915 do_release_fw(&dev->fw.initvals);
1916 do_release_fw(&dev->fw.initvals_band);
1917 }
1918
1919 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1920 {
1921 const char *text;
1922
1923 text = "You must go to "
1924 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1925 "and download the latest firmware (version 4).\n";
1926 if (error)
1927 b43err(wl, text);
1928 else
1929 b43warn(wl, text);
1930 }
1931
1932 static int do_request_fw(struct b43_wldev *dev,
1933 const char *name,
1934 struct b43_firmware_file *fw,
1935 bool silent)
1936 {
1937 char path[sizeof(modparam_fwpostfix) + 32];
1938 const struct firmware *blob;
1939 struct b43_fw_header *hdr;
1940 u32 size;
1941 int err;
1942
1943 if (!name) {
1944 /* Don't fetch anything. Free possibly cached firmware. */
1945 do_release_fw(fw);
1946 return 0;
1947 }
1948 if (fw->filename) {
1949 if (strcmp(fw->filename, name) == 0)
1950 return 0; /* Already have this fw. */
1951 /* Free the cached firmware first. */
1952 do_release_fw(fw);
1953 }
1954
1955 snprintf(path, ARRAY_SIZE(path),
1956 "b43%s/%s.fw",
1957 modparam_fwpostfix, name);
1958 err = request_firmware(&blob, path, dev->dev->dev);
1959 if (err == -ENOENT) {
1960 if (!silent) {
1961 b43err(dev->wl, "Firmware file \"%s\" not found\n",
1962 path);
1963 }
1964 return err;
1965 } else if (err) {
1966 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
1967 path, err);
1968 return err;
1969 }
1970 if (blob->size < sizeof(struct b43_fw_header))
1971 goto err_format;
1972 hdr = (struct b43_fw_header *)(blob->data);
1973 switch (hdr->type) {
1974 case B43_FW_TYPE_UCODE:
1975 case B43_FW_TYPE_PCM:
1976 size = be32_to_cpu(hdr->size);
1977 if (size != blob->size - sizeof(struct b43_fw_header))
1978 goto err_format;
1979 /* fallthrough */
1980 case B43_FW_TYPE_IV:
1981 if (hdr->ver != 1)
1982 goto err_format;
1983 break;
1984 default:
1985 goto err_format;
1986 }
1987
1988 fw->data = blob;
1989 fw->filename = name;
1990
1991 return 0;
1992
1993 err_format:
1994 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1995 release_firmware(blob);
1996
1997 return -EPROTO;
1998 }
1999
2000 static int b43_request_firmware(struct b43_wldev *dev)
2001 {
2002 struct b43_firmware *fw = &dev->fw;
2003 const u8 rev = dev->dev->id.revision;
2004 const char *filename;
2005 u32 tmshigh;
2006 int err;
2007
2008 /* Get microcode */
2009 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2010 if ((rev >= 5) && (rev <= 10))
2011 filename = "ucode5";
2012 else if ((rev >= 11) && (rev <= 12))
2013 filename = "ucode11";
2014 else if (rev >= 13)
2015 filename = "ucode13";
2016 else
2017 goto err_no_ucode;
2018 err = do_request_fw(dev, filename, &fw->ucode, 0);
2019 if (err)
2020 goto err_load;
2021
2022 /* Get PCM code */
2023 if ((rev >= 5) && (rev <= 10))
2024 filename = "pcm5";
2025 else if (rev >= 11)
2026 filename = NULL;
2027 else
2028 goto err_no_pcm;
2029 fw->pcm_request_failed = 0;
2030 err = do_request_fw(dev, filename, &fw->pcm, 1);
2031 if (err == -ENOENT) {
2032 /* We did not find a PCM file? Not fatal, but
2033 * core rev <= 10 must do without hwcrypto then. */
2034 fw->pcm_request_failed = 1;
2035 } else if (err)
2036 goto err_load;
2037
2038 /* Get initvals */
2039 switch (dev->phy.type) {
2040 case B43_PHYTYPE_A:
2041 if ((rev >= 5) && (rev <= 10)) {
2042 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2043 filename = "a0g1initvals5";
2044 else
2045 filename = "a0g0initvals5";
2046 } else
2047 goto err_no_initvals;
2048 break;
2049 case B43_PHYTYPE_G:
2050 if ((rev >= 5) && (rev <= 10))
2051 filename = "b0g0initvals5";
2052 else if (rev >= 13)
2053 filename = "b0g0initvals13";
2054 else
2055 goto err_no_initvals;
2056 break;
2057 case B43_PHYTYPE_N:
2058 if ((rev >= 11) && (rev <= 12))
2059 filename = "n0initvals11";
2060 else
2061 goto err_no_initvals;
2062 break;
2063 default:
2064 goto err_no_initvals;
2065 }
2066 err = do_request_fw(dev, filename, &fw->initvals, 0);
2067 if (err)
2068 goto err_load;
2069
2070 /* Get bandswitch initvals */
2071 switch (dev->phy.type) {
2072 case B43_PHYTYPE_A:
2073 if ((rev >= 5) && (rev <= 10)) {
2074 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2075 filename = "a0g1bsinitvals5";
2076 else
2077 filename = "a0g0bsinitvals5";
2078 } else if (rev >= 11)
2079 filename = NULL;
2080 else
2081 goto err_no_initvals;
2082 break;
2083 case B43_PHYTYPE_G:
2084 if ((rev >= 5) && (rev <= 10))
2085 filename = "b0g0bsinitvals5";
2086 else if (rev >= 11)
2087 filename = NULL;
2088 else
2089 goto err_no_initvals;
2090 break;
2091 case B43_PHYTYPE_N:
2092 if ((rev >= 11) && (rev <= 12))
2093 filename = "n0bsinitvals11";
2094 else
2095 goto err_no_initvals;
2096 break;
2097 default:
2098 goto err_no_initvals;
2099 }
2100 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2101 if (err)
2102 goto err_load;
2103
2104 return 0;
2105
2106 err_load:
2107 b43_print_fw_helptext(dev->wl, 1);
2108 goto error;
2109
2110 err_no_ucode:
2111 err = -ENODEV;
2112 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2113 goto error;
2114
2115 err_no_pcm:
2116 err = -ENODEV;
2117 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2118 goto error;
2119
2120 err_no_initvals:
2121 err = -ENODEV;
2122 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2123 "core rev %u\n", dev->phy.type, rev);
2124 goto error;
2125
2126 error:
2127 b43_release_firmware(dev);
2128 return err;
2129 }
2130
2131 static int b43_upload_microcode(struct b43_wldev *dev)
2132 {
2133 const size_t hdr_len = sizeof(struct b43_fw_header);
2134 const __be32 *data;
2135 unsigned int i, len;
2136 u16 fwrev, fwpatch, fwdate, fwtime;
2137 u32 tmp, macctl;
2138 int err = 0;
2139
2140 /* Jump the microcode PSM to offset 0 */
2141 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2142 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2143 macctl |= B43_MACCTL_PSM_JMP0;
2144 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2145 /* Zero out all microcode PSM registers and shared memory. */
2146 for (i = 0; i < 64; i++)
2147 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2148 for (i = 0; i < 4096; i += 2)
2149 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2150
2151 /* Upload Microcode. */
2152 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2153 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2154 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2155 for (i = 0; i < len; i++) {
2156 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2157 udelay(10);
2158 }
2159
2160 if (dev->fw.pcm.data) {
2161 /* Upload PCM data. */
2162 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2163 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2164 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2165 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2166 /* No need for autoinc bit in SHM_HW */
2167 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2168 for (i = 0; i < len; i++) {
2169 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2170 udelay(10);
2171 }
2172 }
2173
2174 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2175
2176 /* Start the microcode PSM */
2177 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2178 macctl &= ~B43_MACCTL_PSM_JMP0;
2179 macctl |= B43_MACCTL_PSM_RUN;
2180 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2181
2182 /* Wait for the microcode to load and respond */
2183 i = 0;
2184 while (1) {
2185 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2186 if (tmp == B43_IRQ_MAC_SUSPENDED)
2187 break;
2188 i++;
2189 if (i >= 20) {
2190 b43err(dev->wl, "Microcode not responding\n");
2191 b43_print_fw_helptext(dev->wl, 1);
2192 err = -ENODEV;
2193 goto error;
2194 }
2195 msleep_interruptible(50);
2196 if (signal_pending(current)) {
2197 err = -EINTR;
2198 goto error;
2199 }
2200 }
2201 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2202
2203 /* Get and check the revisions. */
2204 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2205 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2206 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2207 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2208
2209 if (fwrev <= 0x128) {
2210 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2211 "binary drivers older than version 4.x is unsupported. "
2212 "You must upgrade your firmware files.\n");
2213 b43_print_fw_helptext(dev->wl, 1);
2214 err = -EOPNOTSUPP;
2215 goto error;
2216 }
2217 dev->fw.rev = fwrev;
2218 dev->fw.patch = fwpatch;
2219 dev->fw.opensource = (fwdate == 0xFFFF);
2220
2221 if (dev->fw.opensource) {
2222 /* Patchlevel info is encoded in the "time" field. */
2223 dev->fw.patch = fwtime;
2224 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2225 dev->fw.rev, dev->fw.patch,
2226 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2227 } else {
2228 b43info(dev->wl, "Loading firmware version %u.%u "
2229 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2230 fwrev, fwpatch,
2231 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2232 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2233 if (dev->fw.pcm_request_failed) {
2234 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2235 "Hardware accelerated cryptography is disabled.\n");
2236 b43_print_fw_helptext(dev->wl, 0);
2237 }
2238 }
2239
2240 if (b43_is_old_txhdr_format(dev)) {
2241 b43warn(dev->wl, "You are using an old firmware image. "
2242 "Support for old firmware will be removed in July 2008.\n");
2243 b43_print_fw_helptext(dev->wl, 0);
2244 }
2245
2246 return 0;
2247
2248 error:
2249 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2250 macctl &= ~B43_MACCTL_PSM_RUN;
2251 macctl |= B43_MACCTL_PSM_JMP0;
2252 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2253
2254 return err;
2255 }
2256
2257 static int b43_write_initvals(struct b43_wldev *dev,
2258 const struct b43_iv *ivals,
2259 size_t count,
2260 size_t array_size)
2261 {
2262 const struct b43_iv *iv;
2263 u16 offset;
2264 size_t i;
2265 bool bit32;
2266
2267 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2268 iv = ivals;
2269 for (i = 0; i < count; i++) {
2270 if (array_size < sizeof(iv->offset_size))
2271 goto err_format;
2272 array_size -= sizeof(iv->offset_size);
2273 offset = be16_to_cpu(iv->offset_size);
2274 bit32 = !!(offset & B43_IV_32BIT);
2275 offset &= B43_IV_OFFSET_MASK;
2276 if (offset >= 0x1000)
2277 goto err_format;
2278 if (bit32) {
2279 u32 value;
2280
2281 if (array_size < sizeof(iv->data.d32))
2282 goto err_format;
2283 array_size -= sizeof(iv->data.d32);
2284
2285 value = get_unaligned_be32(&iv->data.d32);
2286 b43_write32(dev, offset, value);
2287
2288 iv = (const struct b43_iv *)((const uint8_t *)iv +
2289 sizeof(__be16) +
2290 sizeof(__be32));
2291 } else {
2292 u16 value;
2293
2294 if (array_size < sizeof(iv->data.d16))
2295 goto err_format;
2296 array_size -= sizeof(iv->data.d16);
2297
2298 value = be16_to_cpu(iv->data.d16);
2299 b43_write16(dev, offset, value);
2300
2301 iv = (const struct b43_iv *)((const uint8_t *)iv +
2302 sizeof(__be16) +
2303 sizeof(__be16));
2304 }
2305 }
2306 if (array_size)
2307 goto err_format;
2308
2309 return 0;
2310
2311 err_format:
2312 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2313 b43_print_fw_helptext(dev->wl, 1);
2314
2315 return -EPROTO;
2316 }
2317
2318 static int b43_upload_initvals(struct b43_wldev *dev)
2319 {
2320 const size_t hdr_len = sizeof(struct b43_fw_header);
2321 const struct b43_fw_header *hdr;
2322 struct b43_firmware *fw = &dev->fw;
2323 const struct b43_iv *ivals;
2324 size_t count;
2325 int err;
2326
2327 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2328 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2329 count = be32_to_cpu(hdr->size);
2330 err = b43_write_initvals(dev, ivals, count,
2331 fw->initvals.data->size - hdr_len);
2332 if (err)
2333 goto out;
2334 if (fw->initvals_band.data) {
2335 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2336 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2337 count = be32_to_cpu(hdr->size);
2338 err = b43_write_initvals(dev, ivals, count,
2339 fw->initvals_band.data->size - hdr_len);
2340 if (err)
2341 goto out;
2342 }
2343 out:
2344
2345 return err;
2346 }
2347
2348 /* Initialize the GPIOs
2349 * http://bcm-specs.sipsolutions.net/GPIO
2350 */
2351 static int b43_gpio_init(struct b43_wldev *dev)
2352 {
2353 struct ssb_bus *bus = dev->dev->bus;
2354 struct ssb_device *gpiodev, *pcidev = NULL;
2355 u32 mask, set;
2356
2357 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2358 & ~B43_MACCTL_GPOUTSMSK);
2359
2360 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2361 | 0x000F);
2362
2363 mask = 0x0000001F;
2364 set = 0x0000000F;
2365 if (dev->dev->bus->chip_id == 0x4301) {
2366 mask |= 0x0060;
2367 set |= 0x0060;
2368 }
2369 if (0 /* FIXME: conditional unknown */ ) {
2370 b43_write16(dev, B43_MMIO_GPIO_MASK,
2371 b43_read16(dev, B43_MMIO_GPIO_MASK)
2372 | 0x0100);
2373 mask |= 0x0180;
2374 set |= 0x0180;
2375 }
2376 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2377 b43_write16(dev, B43_MMIO_GPIO_MASK,
2378 b43_read16(dev, B43_MMIO_GPIO_MASK)
2379 | 0x0200);
2380 mask |= 0x0200;
2381 set |= 0x0200;
2382 }
2383 if (dev->dev->id.revision >= 2)
2384 mask |= 0x0010; /* FIXME: This is redundant. */
2385
2386 #ifdef CONFIG_SSB_DRIVER_PCICORE
2387 pcidev = bus->pcicore.dev;
2388 #endif
2389 gpiodev = bus->chipco.dev ? : pcidev;
2390 if (!gpiodev)
2391 return 0;
2392 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2393 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2394 & mask) | set);
2395
2396 return 0;
2397 }
2398
2399 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2400 static void b43_gpio_cleanup(struct b43_wldev *dev)
2401 {
2402 struct ssb_bus *bus = dev->dev->bus;
2403 struct ssb_device *gpiodev, *pcidev = NULL;
2404
2405 #ifdef CONFIG_SSB_DRIVER_PCICORE
2406 pcidev = bus->pcicore.dev;
2407 #endif
2408 gpiodev = bus->chipco.dev ? : pcidev;
2409 if (!gpiodev)
2410 return;
2411 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2412 }
2413
2414 /* http://bcm-specs.sipsolutions.net/EnableMac */
2415 void b43_mac_enable(struct b43_wldev *dev)
2416 {
2417 dev->mac_suspended--;
2418 B43_WARN_ON(dev->mac_suspended < 0);
2419 if (dev->mac_suspended == 0) {
2420 b43_write32(dev, B43_MMIO_MACCTL,
2421 b43_read32(dev, B43_MMIO_MACCTL)
2422 | B43_MACCTL_ENABLED);
2423 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2424 B43_IRQ_MAC_SUSPENDED);
2425 /* Commit writes */
2426 b43_read32(dev, B43_MMIO_MACCTL);
2427 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2428 b43_power_saving_ctl_bits(dev, 0);
2429 }
2430 }
2431
2432 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2433 void b43_mac_suspend(struct b43_wldev *dev)
2434 {
2435 int i;
2436 u32 tmp;
2437
2438 might_sleep();
2439 B43_WARN_ON(dev->mac_suspended < 0);
2440
2441 if (dev->mac_suspended == 0) {
2442 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2443 b43_write32(dev, B43_MMIO_MACCTL,
2444 b43_read32(dev, B43_MMIO_MACCTL)
2445 & ~B43_MACCTL_ENABLED);
2446 /* force pci to flush the write */
2447 b43_read32(dev, B43_MMIO_MACCTL);
2448 for (i = 35; i; i--) {
2449 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2450 if (tmp & B43_IRQ_MAC_SUSPENDED)
2451 goto out;
2452 udelay(10);
2453 }
2454 /* Hm, it seems this will take some time. Use msleep(). */
2455 for (i = 40; i; i--) {
2456 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2457 if (tmp & B43_IRQ_MAC_SUSPENDED)
2458 goto out;
2459 msleep(1);
2460 }
2461 b43err(dev->wl, "MAC suspend failed\n");
2462 }
2463 out:
2464 dev->mac_suspended++;
2465 }
2466
2467 static void b43_adjust_opmode(struct b43_wldev *dev)
2468 {
2469 struct b43_wl *wl = dev->wl;
2470 u32 ctl;
2471 u16 cfp_pretbtt;
2472
2473 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2474 /* Reset status to STA infrastructure mode. */
2475 ctl &= ~B43_MACCTL_AP;
2476 ctl &= ~B43_MACCTL_KEEP_CTL;
2477 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2478 ctl &= ~B43_MACCTL_KEEP_BAD;
2479 ctl &= ~B43_MACCTL_PROMISC;
2480 ctl &= ~B43_MACCTL_BEACPROMISC;
2481 ctl |= B43_MACCTL_INFRA;
2482
2483 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2484 ctl |= B43_MACCTL_AP;
2485 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2486 ctl &= ~B43_MACCTL_INFRA;
2487
2488 if (wl->filter_flags & FIF_CONTROL)
2489 ctl |= B43_MACCTL_KEEP_CTL;
2490 if (wl->filter_flags & FIF_FCSFAIL)
2491 ctl |= B43_MACCTL_KEEP_BAD;
2492 if (wl->filter_flags & FIF_PLCPFAIL)
2493 ctl |= B43_MACCTL_KEEP_BADPLCP;
2494 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2495 ctl |= B43_MACCTL_PROMISC;
2496 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2497 ctl |= B43_MACCTL_BEACPROMISC;
2498
2499 /* Workaround: On old hardware the HW-MAC-address-filter
2500 * doesn't work properly, so always run promisc in filter
2501 * it in software. */
2502 if (dev->dev->id.revision <= 4)
2503 ctl |= B43_MACCTL_PROMISC;
2504
2505 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2506
2507 cfp_pretbtt = 2;
2508 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2509 if (dev->dev->bus->chip_id == 0x4306 &&
2510 dev->dev->bus->chip_rev == 3)
2511 cfp_pretbtt = 100;
2512 else
2513 cfp_pretbtt = 50;
2514 }
2515 b43_write16(dev, 0x612, cfp_pretbtt);
2516 }
2517
2518 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2519 {
2520 u16 offset;
2521
2522 if (is_ofdm) {
2523 offset = 0x480;
2524 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2525 } else {
2526 offset = 0x4C0;
2527 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2528 }
2529 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2530 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2531 }
2532
2533 static void b43_rate_memory_init(struct b43_wldev *dev)
2534 {
2535 switch (dev->phy.type) {
2536 case B43_PHYTYPE_A:
2537 case B43_PHYTYPE_G:
2538 case B43_PHYTYPE_N:
2539 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2540 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2541 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2542 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2543 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2544 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2545 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2546 if (dev->phy.type == B43_PHYTYPE_A)
2547 break;
2548 /* fallthrough */
2549 case B43_PHYTYPE_B:
2550 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2551 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2552 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2553 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2554 break;
2555 default:
2556 B43_WARN_ON(1);
2557 }
2558 }
2559
2560 /* Set the default values for the PHY TX Control Words. */
2561 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2562 {
2563 u16 ctl = 0;
2564
2565 ctl |= B43_TXH_PHY_ENC_CCK;
2566 ctl |= B43_TXH_PHY_ANT01AUTO;
2567 ctl |= B43_TXH_PHY_TXPWR;
2568
2569 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2570 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2571 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2572 }
2573
2574 /* Set the TX-Antenna for management frames sent by firmware. */
2575 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2576 {
2577 u16 ant;
2578 u16 tmp;
2579
2580 ant = b43_antenna_to_phyctl(antenna);
2581
2582 /* For ACK/CTS */
2583 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2584 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2585 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2586 /* For Probe Resposes */
2587 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2588 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2589 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2590 }
2591
2592 /* This is the opposite of b43_chip_init() */
2593 static void b43_chip_exit(struct b43_wldev *dev)
2594 {
2595 b43_radio_turn_off(dev, 1);
2596 b43_gpio_cleanup(dev);
2597 b43_lo_g_cleanup(dev);
2598 /* firmware is released later */
2599 }
2600
2601 /* Initialize the chip
2602 * http://bcm-specs.sipsolutions.net/ChipInit
2603 */
2604 static int b43_chip_init(struct b43_wldev *dev)
2605 {
2606 struct b43_phy *phy = &dev->phy;
2607 int err, tmp;
2608 u32 value32, macctl;
2609 u16 value16;
2610
2611 /* Initialize the MAC control */
2612 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2613 if (dev->phy.gmode)
2614 macctl |= B43_MACCTL_GMODE;
2615 macctl |= B43_MACCTL_INFRA;
2616 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2617
2618 err = b43_request_firmware(dev);
2619 if (err)
2620 goto out;
2621 err = b43_upload_microcode(dev);
2622 if (err)
2623 goto out; /* firmware is released later */
2624
2625 err = b43_gpio_init(dev);
2626 if (err)
2627 goto out; /* firmware is released later */
2628
2629 err = b43_upload_initvals(dev);
2630 if (err)
2631 goto err_gpio_clean;
2632 b43_radio_turn_on(dev);
2633
2634 b43_write16(dev, 0x03E6, 0x0000);
2635 err = b43_phy_init(dev);
2636 if (err)
2637 goto err_radio_off;
2638
2639 /* Select initial Interference Mitigation. */
2640 tmp = phy->interfmode;
2641 phy->interfmode = B43_INTERFMODE_NONE;
2642 b43_radio_set_interference_mitigation(dev, tmp);
2643
2644 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2645 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2646
2647 if (phy->type == B43_PHYTYPE_B) {
2648 value16 = b43_read16(dev, 0x005E);
2649 value16 |= 0x0004;
2650 b43_write16(dev, 0x005E, value16);
2651 }
2652 b43_write32(dev, 0x0100, 0x01000000);
2653 if (dev->dev->id.revision < 5)
2654 b43_write32(dev, 0x010C, 0x01000000);
2655
2656 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2657 & ~B43_MACCTL_INFRA);
2658 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2659 | B43_MACCTL_INFRA);
2660
2661 /* Probe Response Timeout value */
2662 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2663 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2664
2665 /* Initially set the wireless operation mode. */
2666 b43_adjust_opmode(dev);
2667
2668 if (dev->dev->id.revision < 3) {
2669 b43_write16(dev, 0x060E, 0x0000);
2670 b43_write16(dev, 0x0610, 0x8000);
2671 b43_write16(dev, 0x0604, 0x0000);
2672 b43_write16(dev, 0x0606, 0x0200);
2673 } else {
2674 b43_write32(dev, 0x0188, 0x80000000);
2675 b43_write32(dev, 0x018C, 0x02000000);
2676 }
2677 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2678 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2679 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2680 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2681 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2682 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2683 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2684
2685 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2686 value32 |= 0x00100000;
2687 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2688
2689 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2690 dev->dev->bus->chipco.fast_pwrup_delay);
2691
2692 err = 0;
2693 b43dbg(dev->wl, "Chip initialized\n");
2694 out:
2695 return err;
2696
2697 err_radio_off:
2698 b43_radio_turn_off(dev, 1);
2699 err_gpio_clean:
2700 b43_gpio_cleanup(dev);
2701 return err;
2702 }
2703
2704 static void b43_periodic_every60sec(struct b43_wldev *dev)
2705 {
2706 struct b43_phy *phy = &dev->phy;
2707
2708 if (phy->type != B43_PHYTYPE_G)
2709 return;
2710 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2711 b43_mac_suspend(dev);
2712 b43_calc_nrssi_slope(dev);
2713 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2714 u8 old_chan = phy->channel;
2715
2716 /* VCO Calibration */
2717 if (old_chan >= 8)
2718 b43_radio_selectchannel(dev, 1, 0);
2719 else
2720 b43_radio_selectchannel(dev, 13, 0);
2721 b43_radio_selectchannel(dev, old_chan, 0);
2722 }
2723 b43_mac_enable(dev);
2724 }
2725 }
2726
2727 static void b43_periodic_every30sec(struct b43_wldev *dev)
2728 {
2729 /* Update device statistics. */
2730 b43_calculate_link_quality(dev);
2731 }
2732
2733 static void b43_periodic_every15sec(struct b43_wldev *dev)
2734 {
2735 struct b43_phy *phy = &dev->phy;
2736
2737 if (phy->type == B43_PHYTYPE_G) {
2738 //TODO: update_aci_moving_average
2739 if (phy->aci_enable && phy->aci_wlan_automatic) {
2740 b43_mac_suspend(dev);
2741 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2742 if (0 /*TODO: bunch of conditions */ ) {
2743 b43_radio_set_interference_mitigation
2744 (dev, B43_INTERFMODE_MANUALWLAN);
2745 }
2746 } else if (1 /*TODO*/) {
2747 /*
2748 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2749 b43_radio_set_interference_mitigation(dev,
2750 B43_INTERFMODE_NONE);
2751 }
2752 */
2753 }
2754 b43_mac_enable(dev);
2755 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2756 phy->rev == 1) {
2757 //TODO: implement rev1 workaround
2758 }
2759 }
2760 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2761 b43_lo_g_maintanance_work(dev);
2762 //TODO for APHY (temperature?)
2763
2764 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2765 wmb();
2766 }
2767
2768 static void do_periodic_work(struct b43_wldev *dev)
2769 {
2770 unsigned int state;
2771
2772 state = dev->periodic_state;
2773 if (state % 4 == 0)
2774 b43_periodic_every60sec(dev);
2775 if (state % 2 == 0)
2776 b43_periodic_every30sec(dev);
2777 b43_periodic_every15sec(dev);
2778 }
2779
2780 /* Periodic work locking policy:
2781 * The whole periodic work handler is protected by
2782 * wl->mutex. If another lock is needed somewhere in the
2783 * pwork callchain, it's aquired in-place, where it's needed.
2784 */
2785 static void b43_periodic_work_handler(struct work_struct *work)
2786 {
2787 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2788 periodic_work.work);
2789 struct b43_wl *wl = dev->wl;
2790 unsigned long delay;
2791
2792 mutex_lock(&wl->mutex);
2793
2794 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2795 goto out;
2796 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2797 goto out_requeue;
2798
2799 do_periodic_work(dev);
2800
2801 dev->periodic_state++;
2802 out_requeue:
2803 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2804 delay = msecs_to_jiffies(50);
2805 else
2806 delay = round_jiffies_relative(HZ * 15);
2807 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2808 out:
2809 mutex_unlock(&wl->mutex);
2810 }
2811
2812 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2813 {
2814 struct delayed_work *work = &dev->periodic_work;
2815
2816 dev->periodic_state = 0;
2817 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2818 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2819 }
2820
2821 /* Check if communication with the device works correctly. */
2822 static int b43_validate_chipaccess(struct b43_wldev *dev)
2823 {
2824 u32 v, backup;
2825
2826 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2827
2828 /* Check for read/write and endianness problems. */
2829 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2830 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2831 goto error;
2832 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2833 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2834 goto error;
2835
2836 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2837
2838 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2839 /* The 32bit register shadows the two 16bit registers
2840 * with update sideeffects. Validate this. */
2841 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2842 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2843 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2844 goto error;
2845 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2846 goto error;
2847 }
2848 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2849
2850 v = b43_read32(dev, B43_MMIO_MACCTL);
2851 v |= B43_MACCTL_GMODE;
2852 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2853 goto error;
2854
2855 return 0;
2856 error:
2857 b43err(dev->wl, "Failed to validate the chipaccess\n");
2858 return -ENODEV;
2859 }
2860
2861 static void b43_security_init(struct b43_wldev *dev)
2862 {
2863 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2864 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2865 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2866 /* KTP is a word address, but we address SHM bytewise.
2867 * So multiply by two.
2868 */
2869 dev->ktp *= 2;
2870 if (dev->dev->id.revision >= 5) {
2871 /* Number of RCMTA address slots */
2872 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2873 }
2874 b43_clear_keys(dev);
2875 }
2876
2877 static int b43_rng_read(struct hwrng *rng, u32 * data)
2878 {
2879 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2880 unsigned long flags;
2881
2882 /* Don't take wl->mutex here, as it could deadlock with
2883 * hwrng internal locking. It's not needed to take
2884 * wl->mutex here, anyway. */
2885
2886 spin_lock_irqsave(&wl->irq_lock, flags);
2887 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2888 spin_unlock_irqrestore(&wl->irq_lock, flags);
2889
2890 return (sizeof(u16));
2891 }
2892
2893 static void b43_rng_exit(struct b43_wl *wl)
2894 {
2895 if (wl->rng_initialized)
2896 hwrng_unregister(&wl->rng);
2897 }
2898
2899 static int b43_rng_init(struct b43_wl *wl)
2900 {
2901 int err;
2902
2903 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2904 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2905 wl->rng.name = wl->rng_name;
2906 wl->rng.data_read = b43_rng_read;
2907 wl->rng.priv = (unsigned long)wl;
2908 wl->rng_initialized = 1;
2909 err = hwrng_register(&wl->rng);
2910 if (err) {
2911 wl->rng_initialized = 0;
2912 b43err(wl, "Failed to register the random "
2913 "number generator (%d)\n", err);
2914 }
2915
2916 return err;
2917 }
2918
2919 static int b43_op_tx(struct ieee80211_hw *hw,
2920 struct sk_buff *skb)
2921 {
2922 struct b43_wl *wl = hw_to_b43_wl(hw);
2923 struct b43_wldev *dev = wl->current_dev;
2924 unsigned long flags;
2925 int err;
2926
2927 if (unlikely(skb->len < 2 + 2 + 6)) {
2928 /* Too short, this can't be a valid frame. */
2929 dev_kfree_skb_any(skb);
2930 return NETDEV_TX_OK;
2931 }
2932 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2933 if (unlikely(!dev))
2934 return NETDEV_TX_BUSY;
2935
2936 /* Transmissions on seperate queues can run concurrently. */
2937 read_lock_irqsave(&wl->tx_lock, flags);
2938
2939 err = -ENODEV;
2940 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2941 if (b43_using_pio_transfers(dev))
2942 err = b43_pio_tx(dev, skb);
2943 else
2944 err = b43_dma_tx(dev, skb);
2945 }
2946
2947 read_unlock_irqrestore(&wl->tx_lock, flags);
2948
2949 if (unlikely(err))
2950 return NETDEV_TX_BUSY;
2951 return NETDEV_TX_OK;
2952 }
2953
2954 /* Locking: wl->irq_lock */
2955 static void b43_qos_params_upload(struct b43_wldev *dev,
2956 const struct ieee80211_tx_queue_params *p,
2957 u16 shm_offset)
2958 {
2959 u16 params[B43_NR_QOSPARAMS];
2960 int cw_min, cw_max, aifs, bslots, tmp;
2961 unsigned int i;
2962
2963 const u16 aCWmin = 0x0001;
2964 const u16 aCWmax = 0x03FF;
2965
2966 /* Calculate the default values for the parameters, if needed. */
2967 switch (shm_offset) {
2968 case B43_QOS_VOICE:
2969 aifs = (p->aifs == -1) ? 2 : p->aifs;
2970 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2971 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2972 break;
2973 case B43_QOS_VIDEO:
2974 aifs = (p->aifs == -1) ? 2 : p->aifs;
2975 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2976 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2977 break;
2978 case B43_QOS_BESTEFFORT:
2979 aifs = (p->aifs == -1) ? 3 : p->aifs;
2980 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2981 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2982 break;
2983 case B43_QOS_BACKGROUND:
2984 aifs = (p->aifs == -1) ? 7 : p->aifs;
2985 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2986 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2987 break;
2988 default:
2989 B43_WARN_ON(1);
2990 return;
2991 }
2992 if (cw_min <= 0)
2993 cw_min = aCWmin;
2994 if (cw_max <= 0)
2995 cw_max = aCWmin;
2996 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2997
2998 memset(&params, 0, sizeof(params));
2999
3000 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3001 params[B43_QOSPARAM_CWMIN] = cw_min;
3002 params[B43_QOSPARAM_CWMAX] = cw_max;
3003 params[B43_QOSPARAM_CWCUR] = cw_min;
3004 params[B43_QOSPARAM_AIFS] = aifs;
3005 params[B43_QOSPARAM_BSLOTS] = bslots;
3006 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
3007
3008 for (i = 0; i < ARRAY_SIZE(params); i++) {
3009 if (i == B43_QOSPARAM_STATUS) {
3010 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3011 shm_offset + (i * 2));
3012 /* Mark the parameters as updated. */
3013 tmp |= 0x100;
3014 b43_shm_write16(dev, B43_SHM_SHARED,
3015 shm_offset + (i * 2),
3016 tmp);
3017 } else {
3018 b43_shm_write16(dev, B43_SHM_SHARED,
3019 shm_offset + (i * 2),
3020 params[i]);
3021 }
3022 }
3023 }
3024
3025 /* Update the QOS parameters in hardware. */
3026 static void b43_qos_update(struct b43_wldev *dev)
3027 {
3028 struct b43_wl *wl = dev->wl;
3029 struct b43_qos_params *params;
3030 unsigned long flags;
3031 unsigned int i;
3032
3033 /* Mapping of mac80211 queues to b43 SHM offsets. */
3034 static const u16 qos_shm_offsets[] = {
3035 [0] = B43_QOS_VOICE,
3036 [1] = B43_QOS_VIDEO,
3037 [2] = B43_QOS_BESTEFFORT,
3038 [3] = B43_QOS_BACKGROUND,
3039 };
3040 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
3041
3042 b43_mac_suspend(dev);
3043 spin_lock_irqsave(&wl->irq_lock, flags);
3044
3045 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3046 params = &(wl->qos_params[i]);
3047 if (params->need_hw_update) {
3048 b43_qos_params_upload(dev, &(params->p),
3049 qos_shm_offsets[i]);
3050 params->need_hw_update = 0;
3051 }
3052 }
3053
3054 spin_unlock_irqrestore(&wl->irq_lock, flags);
3055 b43_mac_enable(dev);
3056 }
3057
3058 static void b43_qos_clear(struct b43_wl *wl)
3059 {
3060 struct b43_qos_params *params;
3061 unsigned int i;
3062
3063 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3064 params = &(wl->qos_params[i]);
3065
3066 memset(&(params->p), 0, sizeof(params->p));
3067 params->p.aifs = -1;
3068 params->need_hw_update = 1;
3069 }
3070 }
3071
3072 /* Initialize the core's QOS capabilities */
3073 static void b43_qos_init(struct b43_wldev *dev)
3074 {
3075 struct b43_wl *wl = dev->wl;
3076 unsigned int i;
3077
3078 /* Upload the current QOS parameters. */
3079 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
3080 wl->qos_params[i].need_hw_update = 1;
3081 b43_qos_update(dev);
3082
3083 /* Enable QOS support. */
3084 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3085 b43_write16(dev, B43_MMIO_IFSCTL,
3086 b43_read16(dev, B43_MMIO_IFSCTL)
3087 | B43_MMIO_IFSCTL_USE_EDCF);
3088 }
3089
3090 static void b43_qos_update_work(struct work_struct *work)
3091 {
3092 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
3093 struct b43_wldev *dev;
3094
3095 mutex_lock(&wl->mutex);
3096 dev = wl->current_dev;
3097 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
3098 b43_qos_update(dev);
3099 mutex_unlock(&wl->mutex);
3100 }
3101
3102 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3103 const struct ieee80211_tx_queue_params *params)
3104 {
3105 struct b43_wl *wl = hw_to_b43_wl(hw);
3106 unsigned long flags;
3107 unsigned int queue = (unsigned int)_queue;
3108 struct b43_qos_params *p;
3109
3110 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3111 /* Queue not available or don't support setting
3112 * params on this queue. Return success to not
3113 * confuse mac80211. */
3114 return 0;
3115 }
3116
3117 spin_lock_irqsave(&wl->irq_lock, flags);
3118 p = &(wl->qos_params[queue]);
3119 memcpy(&(p->p), params, sizeof(p->p));
3120 p->need_hw_update = 1;
3121 spin_unlock_irqrestore(&wl->irq_lock, flags);
3122
3123 queue_work(hw->workqueue, &wl->qos_update_work);
3124
3125 return 0;
3126 }
3127
3128 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3129 struct ieee80211_tx_queue_stats *stats)
3130 {
3131 struct b43_wl *wl = hw_to_b43_wl(hw);
3132 struct b43_wldev *dev = wl->current_dev;
3133 unsigned long flags;
3134 int err = -ENODEV;
3135
3136 if (!dev)
3137 goto out;
3138 spin_lock_irqsave(&wl->irq_lock, flags);
3139 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3140 if (b43_using_pio_transfers(dev))
3141 b43_pio_get_tx_stats(dev, stats);
3142 else
3143 b43_dma_get_tx_stats(dev, stats);
3144 err = 0;
3145 }
3146 spin_unlock_irqrestore(&wl->irq_lock, flags);
3147 out:
3148 return err;
3149 }
3150
3151 static int b43_op_get_stats(struct ieee80211_hw *hw,
3152 struct ieee80211_low_level_stats *stats)
3153 {
3154 struct b43_wl *wl = hw_to_b43_wl(hw);
3155 unsigned long flags;
3156
3157 spin_lock_irqsave(&wl->irq_lock, flags);
3158 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3159 spin_unlock_irqrestore(&wl->irq_lock, flags);
3160
3161 return 0;
3162 }
3163
3164 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3165 {
3166 struct ssb_device *sdev = dev->dev;
3167 u32 tmslow;
3168
3169 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3170 tmslow &= ~B43_TMSLOW_GMODE;
3171 tmslow |= B43_TMSLOW_PHYRESET;
3172 tmslow |= SSB_TMSLOW_FGC;
3173 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3174 msleep(1);
3175
3176 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3177 tmslow &= ~SSB_TMSLOW_FGC;
3178 tmslow |= B43_TMSLOW_PHYRESET;
3179 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3180 msleep(1);
3181 }
3182
3183 static const char * band_to_string(enum ieee80211_band band)
3184 {
3185 switch (band) {
3186 case IEEE80211_BAND_5GHZ:
3187 return "5";
3188 case IEEE80211_BAND_2GHZ:
3189 return "2.4";
3190 default:
3191 break;
3192 }
3193 B43_WARN_ON(1);
3194 return "";
3195 }
3196
3197 /* Expects wl->mutex locked */
3198 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3199 {
3200 struct b43_wldev *up_dev = NULL;
3201 struct b43_wldev *down_dev;
3202 struct b43_wldev *d;
3203 int err;
3204 bool gmode;
3205 int prev_status;
3206
3207 /* Find a device and PHY which supports the band. */
3208 list_for_each_entry(d, &wl->devlist, list) {
3209 switch (chan->band) {
3210 case IEEE80211_BAND_5GHZ:
3211 if (d->phy.supports_5ghz) {
3212 up_dev = d;
3213 gmode = 0;
3214 }
3215 break;
3216 case IEEE80211_BAND_2GHZ:
3217 if (d->phy.supports_2ghz) {
3218 up_dev = d;
3219 gmode = 1;
3220 }
3221 break;
3222 default:
3223 B43_WARN_ON(1);
3224 return -EINVAL;
3225 }
3226 if (up_dev)
3227 break;
3228 }
3229 if (!up_dev) {
3230 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3231 band_to_string(chan->band));
3232 return -ENODEV;
3233 }
3234 if ((up_dev == wl->current_dev) &&
3235 (!!wl->current_dev->phy.gmode == !!gmode)) {
3236 /* This device is already running. */
3237 return 0;
3238 }
3239 b43dbg(wl, "Switching to %s-GHz band\n",
3240 band_to_string(chan->band));
3241 down_dev = wl->current_dev;
3242
3243 prev_status = b43_status(down_dev);
3244 /* Shutdown the currently running core. */
3245 if (prev_status >= B43_STAT_STARTED)
3246 b43_wireless_core_stop(down_dev);
3247 if (prev_status >= B43_STAT_INITIALIZED)
3248 b43_wireless_core_exit(down_dev);
3249
3250 if (down_dev != up_dev) {
3251 /* We switch to a different core, so we put PHY into
3252 * RESET on the old core. */
3253 b43_put_phy_into_reset(down_dev);
3254 }
3255
3256 /* Now start the new core. */
3257 up_dev->phy.gmode = gmode;
3258 if (prev_status >= B43_STAT_INITIALIZED) {
3259 err = b43_wireless_core_init(up_dev);
3260 if (err) {
3261 b43err(wl, "Fatal: Could not initialize device for "
3262 "selected %s-GHz band\n",
3263 band_to_string(chan->band));
3264 goto init_failure;
3265 }
3266 }
3267 if (prev_status >= B43_STAT_STARTED) {
3268 err = b43_wireless_core_start(up_dev);
3269 if (err) {
3270 b43err(wl, "Fatal: Coult not start device for "
3271 "selected %s-GHz band\n",
3272 band_to_string(chan->band));
3273 b43_wireless_core_exit(up_dev);
3274 goto init_failure;
3275 }
3276 }
3277 B43_WARN_ON(b43_status(up_dev) != prev_status);
3278
3279 wl->current_dev = up_dev;
3280
3281 return 0;
3282 init_failure:
3283 /* Whoops, failed to init the new core. No core is operating now. */
3284 wl->current_dev = NULL;
3285 return err;
3286 }
3287
3288 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3289 {
3290 struct b43_wl *wl = hw_to_b43_wl(hw);
3291 struct b43_wldev *dev;
3292 struct b43_phy *phy;
3293 unsigned long flags;
3294 int antenna;
3295 int err = 0;
3296 u32 savedirqs;
3297
3298 mutex_lock(&wl->mutex);
3299
3300 /* Switch the band (if necessary). This might change the active core. */
3301 err = b43_switch_band(wl, conf->channel);
3302 if (err)
3303 goto out_unlock_mutex;
3304 dev = wl->current_dev;
3305 phy = &dev->phy;
3306
3307 /* Disable IRQs while reconfiguring the device.
3308 * This makes it possible to drop the spinlock throughout
3309 * the reconfiguration process. */
3310 spin_lock_irqsave(&wl->irq_lock, flags);
3311 if (b43_status(dev) < B43_STAT_STARTED) {
3312 spin_unlock_irqrestore(&wl->irq_lock, flags);
3313 goto out_unlock_mutex;
3314 }
3315 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3316 spin_unlock_irqrestore(&wl->irq_lock, flags);
3317 b43_synchronize_irq(dev);
3318
3319 /* Switch to the requested channel.
3320 * The firmware takes care of races with the TX handler. */
3321 if (conf->channel->hw_value != phy->channel)
3322 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
3323
3324 /* Enable/Disable ShortSlot timing. */
3325 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3326 dev->short_slot) {
3327 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3328 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3329 b43_short_slot_timing_enable(dev);
3330 else
3331 b43_short_slot_timing_disable(dev);
3332 }
3333
3334 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3335
3336 /* Adjust the desired TX power level. */
3337 if (conf->power_level != 0) {
3338 if (conf->power_level != phy->power_level) {
3339 phy->power_level = conf->power_level;
3340 b43_phy_xmitpower(dev);
3341 }
3342 }
3343
3344 /* Antennas for RX and management frame TX. */
3345 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3346 b43_mgmtframe_txantenna(dev, antenna);
3347 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3348 b43_set_rx_antenna(dev, antenna);
3349
3350 /* Update templates for AP mode. */
3351 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3352 b43_set_beacon_int(dev, conf->beacon_int);
3353
3354 if (!!conf->radio_enabled != phy->radio_on) {
3355 if (conf->radio_enabled) {
3356 b43_radio_turn_on(dev);
3357 b43info(dev->wl, "Radio turned on by software\n");
3358 if (!dev->radio_hw_enable) {
3359 b43info(dev->wl, "The hardware RF-kill button "
3360 "still turns the radio physically off. "
3361 "Press the button to turn it on.\n");
3362 }
3363 } else {
3364 b43_radio_turn_off(dev, 0);
3365 b43info(dev->wl, "Radio turned off by software\n");
3366 }
3367 }
3368
3369 spin_lock_irqsave(&wl->irq_lock, flags);
3370 b43_interrupt_enable(dev, savedirqs);
3371 mmiowb();
3372 spin_unlock_irqrestore(&wl->irq_lock, flags);
3373 out_unlock_mutex:
3374 mutex_unlock(&wl->mutex);
3375
3376 return err;
3377 }
3378
3379 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3380 const u8 *local_addr, const u8 *addr,
3381 struct ieee80211_key_conf *key)
3382 {
3383 struct b43_wl *wl = hw_to_b43_wl(hw);
3384 struct b43_wldev *dev;
3385 unsigned long flags;
3386 u8 algorithm;
3387 u8 index;
3388 int err;
3389 DECLARE_MAC_BUF(mac);
3390
3391 if (modparam_nohwcrypt)
3392 return -ENOSPC; /* User disabled HW-crypto */
3393
3394 mutex_lock(&wl->mutex);
3395 spin_lock_irqsave(&wl->irq_lock, flags);
3396
3397 dev = wl->current_dev;
3398 err = -ENODEV;
3399 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3400 goto out_unlock;
3401
3402 if (dev->fw.pcm_request_failed) {
3403 /* We don't have firmware for the crypto engine.
3404 * Must use software-crypto. */
3405 err = -EOPNOTSUPP;
3406 goto out_unlock;
3407 }
3408
3409 err = -EINVAL;
3410 switch (key->alg) {
3411 case ALG_WEP:
3412 if (key->keylen == 5)
3413 algorithm = B43_SEC_ALGO_WEP40;
3414 else
3415 algorithm = B43_SEC_ALGO_WEP104;
3416 break;
3417 case ALG_TKIP:
3418 algorithm = B43_SEC_ALGO_TKIP;
3419 break;
3420 case ALG_CCMP:
3421 algorithm = B43_SEC_ALGO_AES;
3422 break;
3423 default:
3424 B43_WARN_ON(1);
3425 goto out_unlock;
3426 }
3427 index = (u8) (key->keyidx);
3428 if (index > 3)
3429 goto out_unlock;
3430
3431 switch (cmd) {
3432 case SET_KEY:
3433 if (algorithm == B43_SEC_ALGO_TKIP) {
3434 /* FIXME: No TKIP hardware encryption for now. */
3435 err = -EOPNOTSUPP;
3436 goto out_unlock;
3437 }
3438
3439 if (is_broadcast_ether_addr(addr)) {
3440 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3441 err = b43_key_write(dev, index, algorithm,
3442 key->key, key->keylen, NULL, key);
3443 } else {
3444 /*
3445 * either pairwise key or address is 00:00:00:00:00:00
3446 * for transmit-only keys
3447 */
3448 err = b43_key_write(dev, -1, algorithm,
3449 key->key, key->keylen, addr, key);
3450 }
3451 if (err)
3452 goto out_unlock;
3453
3454 if (algorithm == B43_SEC_ALGO_WEP40 ||
3455 algorithm == B43_SEC_ALGO_WEP104) {
3456 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3457 } else {
3458 b43_hf_write(dev,
3459 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3460 }
3461 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3462 break;
3463 case DISABLE_KEY: {
3464 err = b43_key_clear(dev, key->hw_key_idx);
3465 if (err)
3466 goto out_unlock;
3467 break;
3468 }
3469 default:
3470 B43_WARN_ON(1);
3471 }
3472 out_unlock:
3473 spin_unlock_irqrestore(&wl->irq_lock, flags);
3474 mutex_unlock(&wl->mutex);
3475 if (!err) {
3476 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3477 "mac: %s\n",
3478 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3479 print_mac(mac, addr));
3480 }
3481 return err;
3482 }
3483
3484 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3485 unsigned int changed, unsigned int *fflags,
3486 int mc_count, struct dev_addr_list *mc_list)
3487 {
3488 struct b43_wl *wl = hw_to_b43_wl(hw);
3489 struct b43_wldev *dev = wl->current_dev;
3490 unsigned long flags;
3491
3492 if (!dev) {
3493 *fflags = 0;
3494 return;
3495 }
3496
3497 spin_lock_irqsave(&wl->irq_lock, flags);
3498 *fflags &= FIF_PROMISC_IN_BSS |
3499 FIF_ALLMULTI |
3500 FIF_FCSFAIL |
3501 FIF_PLCPFAIL |
3502 FIF_CONTROL |
3503 FIF_OTHER_BSS |
3504 FIF_BCN_PRBRESP_PROMISC;
3505
3506 changed &= FIF_PROMISC_IN_BSS |
3507 FIF_ALLMULTI |
3508 FIF_FCSFAIL |
3509 FIF_PLCPFAIL |
3510 FIF_CONTROL |
3511 FIF_OTHER_BSS |
3512 FIF_BCN_PRBRESP_PROMISC;
3513
3514 wl->filter_flags = *fflags;
3515
3516 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3517 b43_adjust_opmode(dev);
3518 spin_unlock_irqrestore(&wl->irq_lock, flags);
3519 }
3520
3521 static int b43_op_config_interface(struct ieee80211_hw *hw,
3522 struct ieee80211_vif *vif,
3523 struct ieee80211_if_conf *conf)
3524 {
3525 struct b43_wl *wl = hw_to_b43_wl(hw);
3526 struct b43_wldev *dev = wl->current_dev;
3527 unsigned long flags;
3528
3529 if (!dev)
3530 return -ENODEV;
3531 mutex_lock(&wl->mutex);
3532 spin_lock_irqsave(&wl->irq_lock, flags);
3533 B43_WARN_ON(wl->vif != vif);
3534 if (conf->bssid)
3535 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3536 else
3537 memset(wl->bssid, 0, ETH_ALEN);
3538 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3539 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3540 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3541 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3542 if (conf->beacon)
3543 b43_update_templates(wl, conf->beacon);
3544 }
3545 b43_write_mac_bssid_templates(dev);
3546 }
3547 spin_unlock_irqrestore(&wl->irq_lock, flags);
3548 mutex_unlock(&wl->mutex);
3549
3550 return 0;
3551 }
3552
3553 /* Locking: wl->mutex */
3554 static void b43_wireless_core_stop(struct b43_wldev *dev)
3555 {
3556 struct b43_wl *wl = dev->wl;
3557 unsigned long flags;
3558
3559 if (b43_status(dev) < B43_STAT_STARTED)
3560 return;
3561
3562 /* Disable and sync interrupts. We must do this before than
3563 * setting the status to INITIALIZED, as the interrupt handler
3564 * won't care about IRQs then. */
3565 spin_lock_irqsave(&wl->irq_lock, flags);
3566 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3567 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3568 spin_unlock_irqrestore(&wl->irq_lock, flags);
3569 b43_synchronize_irq(dev);
3570
3571 write_lock_irqsave(&wl->tx_lock, flags);
3572 b43_set_status(dev, B43_STAT_INITIALIZED);
3573 write_unlock_irqrestore(&wl->tx_lock, flags);
3574
3575 b43_pio_stop(dev);
3576 mutex_unlock(&wl->mutex);
3577 /* Must unlock as it would otherwise deadlock. No races here.
3578 * Cancel the possibly running self-rearming periodic work. */
3579 cancel_delayed_work_sync(&dev->periodic_work);
3580 mutex_lock(&wl->mutex);
3581
3582 b43_mac_suspend(dev);
3583 free_irq(dev->dev->irq, dev);
3584 b43dbg(wl, "Wireless interface stopped\n");
3585 }
3586
3587 /* Locking: wl->mutex */
3588 static int b43_wireless_core_start(struct b43_wldev *dev)
3589 {
3590 int err;
3591
3592 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3593
3594 drain_txstatus_queue(dev);
3595 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3596 IRQF_SHARED, KBUILD_MODNAME, dev);
3597 if (err) {
3598 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3599 goto out;
3600 }
3601
3602 /* We are ready to run. */
3603 b43_set_status(dev, B43_STAT_STARTED);
3604
3605 /* Start data flow (TX/RX). */
3606 b43_mac_enable(dev);
3607 b43_interrupt_enable(dev, dev->irq_savedstate);
3608
3609 /* Start maintainance work */
3610 b43_periodic_tasks_setup(dev);
3611
3612 b43dbg(dev->wl, "Wireless interface started\n");
3613 out:
3614 return err;
3615 }
3616
3617 /* Get PHY and RADIO versioning numbers */
3618 static int b43_phy_versioning(struct b43_wldev *dev)
3619 {
3620 struct b43_phy *phy = &dev->phy;
3621 u32 tmp;
3622 u8 analog_type;
3623 u8 phy_type;
3624 u8 phy_rev;
3625 u16 radio_manuf;
3626 u16 radio_ver;
3627 u16 radio_rev;
3628 int unsupported = 0;
3629
3630 /* Get PHY versioning */
3631 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3632 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3633 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3634 phy_rev = (tmp & B43_PHYVER_VERSION);
3635 switch (phy_type) {
3636 case B43_PHYTYPE_A:
3637 if (phy_rev >= 4)
3638 unsupported = 1;
3639 break;
3640 case B43_PHYTYPE_B:
3641 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3642 && phy_rev != 7)
3643 unsupported = 1;
3644 break;
3645 case B43_PHYTYPE_G:
3646 if (phy_rev > 9)
3647 unsupported = 1;
3648 break;
3649 #ifdef CONFIG_B43_NPHY
3650 case B43_PHYTYPE_N:
3651 if (phy_rev > 1)
3652 unsupported = 1;
3653 break;
3654 #endif
3655 default:
3656 unsupported = 1;
3657 };
3658 if (unsupported) {
3659 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3660 "(Analog %u, Type %u, Revision %u)\n",
3661 analog_type, phy_type, phy_rev);
3662 return -EOPNOTSUPP;
3663 }
3664 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3665 analog_type, phy_type, phy_rev);
3666
3667 /* Get RADIO versioning */
3668 if (dev->dev->bus->chip_id == 0x4317) {
3669 if (dev->dev->bus->chip_rev == 0)
3670 tmp = 0x3205017F;
3671 else if (dev->dev->bus->chip_rev == 1)
3672 tmp = 0x4205017F;
3673 else
3674 tmp = 0x5205017F;
3675 } else {
3676 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3677 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3678 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3679 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3680 }
3681 radio_manuf = (tmp & 0x00000FFF);
3682 radio_ver = (tmp & 0x0FFFF000) >> 12;
3683 radio_rev = (tmp & 0xF0000000) >> 28;
3684 if (radio_manuf != 0x17F /* Broadcom */)
3685 unsupported = 1;
3686 switch (phy_type) {
3687 case B43_PHYTYPE_A:
3688 if (radio_ver != 0x2060)
3689 unsupported = 1;
3690 if (radio_rev != 1)
3691 unsupported = 1;
3692 if (radio_manuf != 0x17F)
3693 unsupported = 1;
3694 break;
3695 case B43_PHYTYPE_B:
3696 if ((radio_ver & 0xFFF0) != 0x2050)
3697 unsupported = 1;
3698 break;
3699 case B43_PHYTYPE_G:
3700 if (radio_ver != 0x2050)
3701 unsupported = 1;
3702 break;
3703 case B43_PHYTYPE_N:
3704 if (radio_ver != 0x2055)
3705 unsupported = 1;
3706 break;
3707 default:
3708 B43_WARN_ON(1);
3709 }
3710 if (unsupported) {
3711 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3712 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3713 radio_manuf, radio_ver, radio_rev);
3714 return -EOPNOTSUPP;
3715 }
3716 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3717 radio_manuf, radio_ver, radio_rev);
3718
3719 phy->radio_manuf = radio_manuf;
3720 phy->radio_ver = radio_ver;
3721 phy->radio_rev = radio_rev;
3722
3723 phy->analog = analog_type;
3724 phy->type = phy_type;
3725 phy->rev = phy_rev;
3726
3727 return 0;
3728 }
3729
3730 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3731 struct b43_phy *phy)
3732 {
3733 struct b43_txpower_lo_control *lo;
3734 int i;
3735
3736 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3737 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3738
3739 phy->aci_enable = 0;
3740 phy->aci_wlan_automatic = 0;
3741 phy->aci_hw_rssi = 0;
3742
3743 phy->radio_off_context.valid = 0;
3744
3745 lo = phy->lo_control;
3746 if (lo) {
3747 memset(lo, 0, sizeof(*(phy->lo_control)));
3748 lo->tx_bias = 0xFF;
3749 INIT_LIST_HEAD(&lo->calib_list);
3750 }
3751 phy->max_lb_gain = 0;
3752 phy->trsw_rx_gain = 0;
3753 phy->txpwr_offset = 0;
3754
3755 /* NRSSI */
3756 phy->nrssislope = 0;
3757 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3758 phy->nrssi[i] = -1000;
3759 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3760 phy->nrssi_lt[i] = i;
3761
3762 phy->lofcal = 0xFFFF;
3763 phy->initval = 0xFFFF;
3764
3765 phy->interfmode = B43_INTERFMODE_NONE;
3766 phy->channel = 0xFF;
3767
3768 phy->hardware_power_control = !!modparam_hwpctl;
3769
3770 /* PHY TX errors counter. */
3771 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3772
3773 /* OFDM-table address caching. */
3774 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3775 }
3776
3777 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3778 {
3779 dev->dfq_valid = 0;
3780
3781 /* Assume the radio is enabled. If it's not enabled, the state will
3782 * immediately get fixed on the first periodic work run. */
3783 dev->radio_hw_enable = 1;
3784
3785 /* Stats */
3786 memset(&dev->stats, 0, sizeof(dev->stats));
3787
3788 setup_struct_phy_for_init(dev, &dev->phy);
3789
3790 /* IRQ related flags */
3791 dev->irq_reason = 0;
3792 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3793 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3794
3795 dev->mac_suspended = 1;
3796
3797 /* Noise calculation context */
3798 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3799 }
3800
3801 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3802 {
3803 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3804 u64 hf;
3805
3806 if (!modparam_btcoex)
3807 return;
3808 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3809 return;
3810 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3811 return;
3812
3813 hf = b43_hf_read(dev);
3814 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3815 hf |= B43_HF_BTCOEXALT;
3816 else
3817 hf |= B43_HF_BTCOEX;
3818 b43_hf_write(dev, hf);
3819 }
3820
3821 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3822 {
3823 if (!modparam_btcoex)
3824 return;
3825 //TODO
3826 }
3827
3828 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3829 {
3830 #ifdef CONFIG_SSB_DRIVER_PCICORE
3831 struct ssb_bus *bus = dev->dev->bus;
3832 u32 tmp;
3833
3834 if (bus->pcicore.dev &&
3835 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3836 bus->pcicore.dev->id.revision <= 5) {
3837 /* IMCFGLO timeouts workaround. */
3838 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3839 tmp &= ~SSB_IMCFGLO_REQTO;
3840 tmp &= ~SSB_IMCFGLO_SERTO;
3841 switch (bus->bustype) {
3842 case SSB_BUSTYPE_PCI:
3843 case SSB_BUSTYPE_PCMCIA:
3844 tmp |= 0x32;
3845 break;
3846 case SSB_BUSTYPE_SSB:
3847 tmp |= 0x53;
3848 break;
3849 }
3850 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3851 }
3852 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3853 }
3854
3855 /* Write the short and long frame retry limit values. */
3856 static void b43_set_retry_limits(struct b43_wldev *dev,
3857 unsigned int short_retry,
3858 unsigned int long_retry)
3859 {
3860 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3861 * the chip-internal counter. */
3862 short_retry = min(short_retry, (unsigned int)0xF);
3863 long_retry = min(long_retry, (unsigned int)0xF);
3864
3865 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3866 short_retry);
3867 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3868 long_retry);
3869 }
3870
3871 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3872 {
3873 u16 pu_delay;
3874
3875 /* The time value is in microseconds. */
3876 if (dev->phy.type == B43_PHYTYPE_A)
3877 pu_delay = 3700;
3878 else
3879 pu_delay = 1050;
3880 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
3881 pu_delay = 500;
3882 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3883 pu_delay = max(pu_delay, (u16)2400);
3884
3885 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3886 }
3887
3888 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3889 static void b43_set_pretbtt(struct b43_wldev *dev)
3890 {
3891 u16 pretbtt;
3892
3893 /* The time value is in microseconds. */
3894 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
3895 pretbtt = 2;
3896 } else {
3897 if (dev->phy.type == B43_PHYTYPE_A)
3898 pretbtt = 120;
3899 else
3900 pretbtt = 250;
3901 }
3902 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3903 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3904 }
3905
3906 /* Shutdown a wireless core */
3907 /* Locking: wl->mutex */
3908 static void b43_wireless_core_exit(struct b43_wldev *dev)
3909 {
3910 struct b43_phy *phy = &dev->phy;
3911 u32 macctl;
3912
3913 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3914 if (b43_status(dev) != B43_STAT_INITIALIZED)
3915 return;
3916 b43_set_status(dev, B43_STAT_UNINIT);
3917
3918 /* Stop the microcode PSM. */
3919 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3920 macctl &= ~B43_MACCTL_PSM_RUN;
3921 macctl |= B43_MACCTL_PSM_JMP0;
3922 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3923
3924 if (!dev->suspend_in_progress) {
3925 b43_leds_exit(dev);
3926 b43_rng_exit(dev->wl);
3927 }
3928 b43_dma_free(dev);
3929 b43_pio_free(dev);
3930 b43_chip_exit(dev);
3931 b43_radio_turn_off(dev, 1);
3932 b43_switch_analog(dev, 0);
3933 if (phy->dyn_tssi_tbl)
3934 kfree(phy->tssi2dbm);
3935 kfree(phy->lo_control);
3936 phy->lo_control = NULL;
3937 if (dev->wl->current_beacon) {
3938 dev_kfree_skb_any(dev->wl->current_beacon);
3939 dev->wl->current_beacon = NULL;
3940 }
3941
3942 ssb_device_disable(dev->dev, 0);
3943 ssb_bus_may_powerdown(dev->dev->bus);
3944 }
3945
3946 /* Initialize a wireless core */
3947 static int b43_wireless_core_init(struct b43_wldev *dev)
3948 {
3949 struct b43_wl *wl = dev->wl;
3950 struct ssb_bus *bus = dev->dev->bus;
3951 struct ssb_sprom *sprom = &bus->sprom;
3952 struct b43_phy *phy = &dev->phy;
3953 int err;
3954 u64 hf;
3955 u32 tmp;
3956
3957 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3958
3959 err = ssb_bus_powerup(bus, 0);
3960 if (err)
3961 goto out;
3962 if (!ssb_device_is_enabled(dev->dev)) {
3963 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3964 b43_wireless_core_reset(dev, tmp);
3965 }
3966
3967 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3968 phy->lo_control =
3969 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3970 if (!phy->lo_control) {
3971 err = -ENOMEM;
3972 goto err_busdown;
3973 }
3974 }
3975 setup_struct_wldev_for_init(dev);
3976
3977 err = b43_phy_init_tssi2dbm_table(dev);
3978 if (err)
3979 goto err_kfree_lo_control;
3980
3981 /* Enable IRQ routing to this device. */
3982 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3983
3984 b43_imcfglo_timeouts_workaround(dev);
3985 b43_bluetooth_coext_disable(dev);
3986 b43_phy_early_init(dev);
3987 err = b43_chip_init(dev);
3988 if (err)
3989 goto err_kfree_tssitbl;
3990 b43_shm_write16(dev, B43_SHM_SHARED,
3991 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3992 hf = b43_hf_read(dev);
3993 if (phy->type == B43_PHYTYPE_G) {
3994 hf |= B43_HF_SYMW;
3995 if (phy->rev == 1)
3996 hf |= B43_HF_GDCW;
3997 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3998 hf |= B43_HF_OFDMPABOOST;
3999 } else if (phy->type == B43_PHYTYPE_B) {
4000 hf |= B43_HF_SYMW;
4001 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4002 hf &= ~B43_HF_GDCW;
4003 }
4004 b43_hf_write(dev, hf);
4005
4006 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4007 B43_DEFAULT_LONG_RETRY_LIMIT);
4008 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4009 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4010
4011 /* Disable sending probe responses from firmware.
4012 * Setting the MaxTime to one usec will always trigger
4013 * a timeout, so we never send any probe resp.
4014 * A timeout of zero is infinite. */
4015 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4016
4017 b43_rate_memory_init(dev);
4018 b43_set_phytxctl_defaults(dev);
4019
4020 /* Minimum Contention Window */
4021 if (phy->type == B43_PHYTYPE_B) {
4022 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4023 } else {
4024 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4025 }
4026 /* Maximum Contention Window */
4027 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4028
4029 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4030 dev->__using_pio_transfers = 1;
4031 err = b43_pio_init(dev);
4032 } else {
4033 dev->__using_pio_transfers = 0;
4034 err = b43_dma_init(dev);
4035 }
4036 if (err)
4037 goto err_chip_exit;
4038 b43_qos_init(dev);
4039 b43_set_synth_pu_delay(dev, 1);
4040 b43_bluetooth_coext_enable(dev);
4041
4042 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4043 b43_upload_card_macaddress(dev);
4044 b43_security_init(dev);
4045 if (!dev->suspend_in_progress)
4046 b43_rng_init(wl);
4047
4048 b43_set_status(dev, B43_STAT_INITIALIZED);
4049
4050 if (!dev->suspend_in_progress)
4051 b43_leds_init(dev);
4052 out:
4053 return err;
4054
4055 err_chip_exit:
4056 b43_chip_exit(dev);
4057 err_kfree_tssitbl:
4058 if (phy->dyn_tssi_tbl)
4059 kfree(phy->tssi2dbm);
4060 err_kfree_lo_control:
4061 kfree(phy->lo_control);
4062 phy->lo_control = NULL;
4063 err_busdown:
4064 ssb_bus_may_powerdown(bus);
4065 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4066 return err;
4067 }
4068
4069 static int b43_op_add_interface(struct ieee80211_hw *hw,
4070 struct ieee80211_if_init_conf *conf)
4071 {
4072 struct b43_wl *wl = hw_to_b43_wl(hw);
4073 struct b43_wldev *dev;
4074 unsigned long flags;
4075 int err = -EOPNOTSUPP;
4076
4077 /* TODO: allow WDS/AP devices to coexist */
4078
4079 if (conf->type != IEEE80211_IF_TYPE_AP &&
4080 conf->type != IEEE80211_IF_TYPE_STA &&
4081 conf->type != IEEE80211_IF_TYPE_WDS &&
4082 conf->type != IEEE80211_IF_TYPE_IBSS)
4083 return -EOPNOTSUPP;
4084
4085 mutex_lock(&wl->mutex);
4086 if (wl->operating)
4087 goto out_mutex_unlock;
4088
4089 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4090
4091 dev = wl->current_dev;
4092 wl->operating = 1;
4093 wl->vif = conf->vif;
4094 wl->if_type = conf->type;
4095 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4096
4097 spin_lock_irqsave(&wl->irq_lock, flags);
4098 b43_adjust_opmode(dev);
4099 b43_set_pretbtt(dev);
4100 b43_set_synth_pu_delay(dev, 0);
4101 b43_upload_card_macaddress(dev);
4102 spin_unlock_irqrestore(&wl->irq_lock, flags);
4103
4104 err = 0;
4105 out_mutex_unlock:
4106 mutex_unlock(&wl->mutex);
4107
4108 return err;
4109 }
4110
4111 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4112 struct ieee80211_if_init_conf *conf)
4113 {
4114 struct b43_wl *wl = hw_to_b43_wl(hw);
4115 struct b43_wldev *dev = wl->current_dev;
4116 unsigned long flags;
4117
4118 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4119
4120 mutex_lock(&wl->mutex);
4121
4122 B43_WARN_ON(!wl->operating);
4123 B43_WARN_ON(wl->vif != conf->vif);
4124 wl->vif = NULL;
4125
4126 wl->operating = 0;
4127
4128 spin_lock_irqsave(&wl->irq_lock, flags);
4129 b43_adjust_opmode(dev);
4130 memset(wl->mac_addr, 0, ETH_ALEN);
4131 b43_upload_card_macaddress(dev);
4132 spin_unlock_irqrestore(&wl->irq_lock, flags);
4133
4134 mutex_unlock(&wl->mutex);
4135 }
4136
4137 static int b43_op_start(struct ieee80211_hw *hw)
4138 {
4139 struct b43_wl *wl = hw_to_b43_wl(hw);
4140 struct b43_wldev *dev = wl->current_dev;
4141 int did_init = 0;
4142 int err = 0;
4143 bool do_rfkill_exit = 0;
4144
4145 /* Kill all old instance specific information to make sure
4146 * the card won't use it in the short timeframe between start
4147 * and mac80211 reconfiguring it. */
4148 memset(wl->bssid, 0, ETH_ALEN);
4149 memset(wl->mac_addr, 0, ETH_ALEN);
4150 wl->filter_flags = 0;
4151 wl->radiotap_enabled = 0;
4152 b43_qos_clear(wl);
4153
4154 /* First register RFkill.
4155 * LEDs that are registered later depend on it. */
4156 b43_rfkill_init(dev);
4157
4158 mutex_lock(&wl->mutex);
4159
4160 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4161 err = b43_wireless_core_init(dev);
4162 if (err) {
4163 do_rfkill_exit = 1;
4164 goto out_mutex_unlock;
4165 }
4166 did_init = 1;
4167 }
4168
4169 if (b43_status(dev) < B43_STAT_STARTED) {
4170 err = b43_wireless_core_start(dev);
4171 if (err) {
4172 if (did_init)
4173 b43_wireless_core_exit(dev);
4174 do_rfkill_exit = 1;
4175 goto out_mutex_unlock;
4176 }
4177 }
4178
4179 out_mutex_unlock:
4180 mutex_unlock(&wl->mutex);
4181
4182 if (do_rfkill_exit)
4183 b43_rfkill_exit(dev);
4184
4185 return err;
4186 }
4187
4188 static void b43_op_stop(struct ieee80211_hw *hw)
4189 {
4190 struct b43_wl *wl = hw_to_b43_wl(hw);
4191 struct b43_wldev *dev = wl->current_dev;
4192
4193 b43_rfkill_exit(dev);
4194 cancel_work_sync(&(wl->qos_update_work));
4195 cancel_work_sync(&(wl->beacon_update_trigger));
4196
4197 mutex_lock(&wl->mutex);
4198 if (b43_status(dev) >= B43_STAT_STARTED)
4199 b43_wireless_core_stop(dev);
4200 b43_wireless_core_exit(dev);
4201 mutex_unlock(&wl->mutex);
4202 }
4203
4204 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4205 u32 short_retry_limit, u32 long_retry_limit)
4206 {
4207 struct b43_wl *wl = hw_to_b43_wl(hw);
4208 struct b43_wldev *dev;
4209 int err = 0;
4210
4211 mutex_lock(&wl->mutex);
4212 dev = wl->current_dev;
4213 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4214 err = -ENODEV;
4215 goto out_unlock;
4216 }
4217 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4218 out_unlock:
4219 mutex_unlock(&wl->mutex);
4220
4221 return err;
4222 }
4223
4224 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4225 {
4226 struct b43_wl *wl = hw_to_b43_wl(hw);
4227 struct sk_buff *beacon;
4228 unsigned long flags;
4229
4230 /* We could modify the existing beacon and set the aid bit in
4231 * the TIM field, but that would probably require resizing and
4232 * moving of data within the beacon template.
4233 * Simply request a new beacon and let mac80211 do the hard work. */
4234 beacon = ieee80211_beacon_get(hw, wl->vif);
4235 if (unlikely(!beacon))
4236 return -ENOMEM;
4237 spin_lock_irqsave(&wl->irq_lock, flags);
4238 b43_update_templates(wl, beacon);
4239 spin_unlock_irqrestore(&wl->irq_lock, flags);
4240
4241 return 0;
4242 }
4243
4244 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4245 struct sk_buff *beacon)
4246 {
4247 struct b43_wl *wl = hw_to_b43_wl(hw);
4248 unsigned long flags;
4249
4250 spin_lock_irqsave(&wl->irq_lock, flags);
4251 b43_update_templates(wl, beacon);
4252 spin_unlock_irqrestore(&wl->irq_lock, flags);
4253
4254 return 0;
4255 }
4256
4257 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4258 struct ieee80211_vif *vif,
4259 enum sta_notify_cmd notify_cmd,
4260 const u8 *addr)
4261 {
4262 struct b43_wl *wl = hw_to_b43_wl(hw);
4263
4264 B43_WARN_ON(!vif || wl->vif != vif);
4265 }
4266
4267 static const struct ieee80211_ops b43_hw_ops = {
4268 .tx = b43_op_tx,
4269 .conf_tx = b43_op_conf_tx,
4270 .add_interface = b43_op_add_interface,
4271 .remove_interface = b43_op_remove_interface,
4272 .config = b43_op_config,
4273 .config_interface = b43_op_config_interface,
4274 .configure_filter = b43_op_configure_filter,
4275 .set_key = b43_op_set_key,
4276 .get_stats = b43_op_get_stats,
4277 .get_tx_stats = b43_op_get_tx_stats,
4278 .start = b43_op_start,
4279 .stop = b43_op_stop,
4280 .set_retry_limit = b43_op_set_retry_limit,
4281 .set_tim = b43_op_beacon_set_tim,
4282 .beacon_update = b43_op_ibss_beacon_update,
4283 .sta_notify = b43_op_sta_notify,
4284 };
4285
4286 /* Hard-reset the chip. Do not call this directly.
4287 * Use b43_controller_restart()
4288 */
4289 static void b43_chip_reset(struct work_struct *work)
4290 {
4291 struct b43_wldev *dev =
4292 container_of(work, struct b43_wldev, restart_work);
4293 struct b43_wl *wl = dev->wl;
4294 int err = 0;
4295 int prev_status;
4296
4297 mutex_lock(&wl->mutex);
4298
4299 prev_status = b43_status(dev);
4300 /* Bring the device down... */
4301 if (prev_status >= B43_STAT_STARTED)
4302 b43_wireless_core_stop(dev);
4303 if (prev_status >= B43_STAT_INITIALIZED)
4304 b43_wireless_core_exit(dev);
4305
4306 /* ...and up again. */
4307 if (prev_status >= B43_STAT_INITIALIZED) {
4308 err = b43_wireless_core_init(dev);
4309 if (err)
4310 goto out;
4311 }
4312 if (prev_status >= B43_STAT_STARTED) {
4313 err = b43_wireless_core_start(dev);
4314 if (err) {
4315 b43_wireless_core_exit(dev);
4316 goto out;
4317 }
4318 }
4319 out:
4320 mutex_unlock(&wl->mutex);
4321 if (err)
4322 b43err(wl, "Controller restart FAILED\n");
4323 else
4324 b43info(wl, "Controller restarted\n");
4325 }
4326
4327 static int b43_setup_bands(struct b43_wldev *dev,
4328 bool have_2ghz_phy, bool have_5ghz_phy)
4329 {
4330 struct ieee80211_hw *hw = dev->wl->hw;
4331
4332 if (have_2ghz_phy)
4333 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4334 if (dev->phy.type == B43_PHYTYPE_N) {
4335 if (have_5ghz_phy)
4336 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4337 } else {
4338 if (have_5ghz_phy)
4339 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4340 }
4341
4342 dev->phy.supports_2ghz = have_2ghz_phy;
4343 dev->phy.supports_5ghz = have_5ghz_phy;
4344
4345 return 0;
4346 }
4347
4348 static void b43_wireless_core_detach(struct b43_wldev *dev)
4349 {
4350 /* We release firmware that late to not be required to re-request
4351 * is all the time when we reinit the core. */
4352 b43_release_firmware(dev);
4353 }
4354
4355 static int b43_wireless_core_attach(struct b43_wldev *dev)
4356 {
4357 struct b43_wl *wl = dev->wl;
4358 struct ssb_bus *bus = dev->dev->bus;
4359 struct pci_dev *pdev = bus->host_pci;
4360 int err;
4361 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4362 u32 tmp;
4363
4364 /* Do NOT do any device initialization here.
4365 * Do it in wireless_core_init() instead.
4366 * This function is for gathering basic information about the HW, only.
4367 * Also some structs may be set up here. But most likely you want to have
4368 * that in core_init(), too.
4369 */
4370
4371 err = ssb_bus_powerup(bus, 0);
4372 if (err) {
4373 b43err(wl, "Bus powerup failed\n");
4374 goto out;
4375 }
4376 /* Get the PHY type. */
4377 if (dev->dev->id.revision >= 5) {
4378 u32 tmshigh;
4379
4380 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4381 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4382 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4383 } else
4384 B43_WARN_ON(1);
4385
4386 dev->phy.gmode = have_2ghz_phy;
4387 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4388 b43_wireless_core_reset(dev, tmp);
4389
4390 err = b43_phy_versioning(dev);
4391 if (err)
4392 goto err_powerdown;
4393 /* Check if this device supports multiband. */
4394 if (!pdev ||
4395 (pdev->device != 0x4312 &&
4396 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4397 /* No multiband support. */
4398 have_2ghz_phy = 0;
4399 have_5ghz_phy = 0;
4400 switch (dev->phy.type) {
4401 case B43_PHYTYPE_A:
4402 have_5ghz_phy = 1;
4403 break;
4404 case B43_PHYTYPE_G:
4405 case B43_PHYTYPE_N:
4406 have_2ghz_phy = 1;
4407 break;
4408 default:
4409 B43_WARN_ON(1);
4410 }
4411 }
4412 if (dev->phy.type == B43_PHYTYPE_A) {
4413 /* FIXME */
4414 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4415 err = -EOPNOTSUPP;
4416 goto err_powerdown;
4417 }
4418 if (1 /* disable A-PHY */) {
4419 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4420 if (dev->phy.type != B43_PHYTYPE_N) {
4421 have_2ghz_phy = 1;
4422 have_5ghz_phy = 0;
4423 }
4424 }
4425
4426 dev->phy.gmode = have_2ghz_phy;
4427 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4428 b43_wireless_core_reset(dev, tmp);
4429
4430 err = b43_validate_chipaccess(dev);
4431 if (err)
4432 goto err_powerdown;
4433 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4434 if (err)
4435 goto err_powerdown;
4436
4437 /* Now set some default "current_dev" */
4438 if (!wl->current_dev)
4439 wl->current_dev = dev;
4440 INIT_WORK(&dev->restart_work, b43_chip_reset);
4441
4442 b43_radio_turn_off(dev, 1);
4443 b43_switch_analog(dev, 0);
4444 ssb_device_disable(dev->dev, 0);
4445 ssb_bus_may_powerdown(bus);
4446
4447 out:
4448 return err;
4449
4450 err_powerdown:
4451 ssb_bus_may_powerdown(bus);
4452 return err;
4453 }
4454
4455 static void b43_one_core_detach(struct ssb_device *dev)
4456 {
4457 struct b43_wldev *wldev;
4458 struct b43_wl *wl;
4459
4460 wldev = ssb_get_drvdata(dev);
4461 wl = wldev->wl;
4462 cancel_work_sync(&wldev->restart_work);
4463 b43_debugfs_remove_device(wldev);
4464 b43_wireless_core_detach(wldev);
4465 list_del(&wldev->list);
4466 wl->nr_devs--;
4467 ssb_set_drvdata(dev, NULL);
4468 kfree(wldev);
4469 }
4470
4471 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4472 {
4473 struct b43_wldev *wldev;
4474 struct pci_dev *pdev;
4475 int err = -ENOMEM;
4476
4477 if (!list_empty(&wl->devlist)) {
4478 /* We are not the first core on this chip. */
4479 pdev = dev->bus->host_pci;
4480 /* Only special chips support more than one wireless
4481 * core, although some of the other chips have more than
4482 * one wireless core as well. Check for this and
4483 * bail out early.
4484 */
4485 if (!pdev ||
4486 ((pdev->device != 0x4321) &&
4487 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4488 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4489 return -ENODEV;
4490 }
4491 }
4492
4493 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4494 if (!wldev)
4495 goto out;
4496
4497 wldev->dev = dev;
4498 wldev->wl = wl;
4499 b43_set_status(wldev, B43_STAT_UNINIT);
4500 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4501 tasklet_init(&wldev->isr_tasklet,
4502 (void (*)(unsigned long))b43_interrupt_tasklet,
4503 (unsigned long)wldev);
4504 INIT_LIST_HEAD(&wldev->list);
4505
4506 err = b43_wireless_core_attach(wldev);
4507 if (err)
4508 goto err_kfree_wldev;
4509
4510 list_add(&wldev->list, &wl->devlist);
4511 wl->nr_devs++;
4512 ssb_set_drvdata(dev, wldev);
4513 b43_debugfs_add_device(wldev);
4514
4515 out:
4516 return err;
4517
4518 err_kfree_wldev:
4519 kfree(wldev);
4520 return err;
4521 }
4522
4523 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4524 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4525 (pdev->device == _device) && \
4526 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4527 (pdev->subsystem_device == _subdevice) )
4528
4529 static void b43_sprom_fixup(struct ssb_bus *bus)
4530 {
4531 struct pci_dev *pdev;
4532
4533 /* boardflags workarounds */
4534 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4535 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4536 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4537 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4538 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4539 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4540 if (bus->bustype == SSB_BUSTYPE_PCI) {
4541 pdev = bus->host_pci;
4542 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4543 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4544 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4545 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4546 }
4547 }
4548
4549 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4550 {
4551 struct ieee80211_hw *hw = wl->hw;
4552
4553 ssb_set_devtypedata(dev, NULL);
4554 ieee80211_free_hw(hw);
4555 }
4556
4557 static int b43_wireless_init(struct ssb_device *dev)
4558 {
4559 struct ssb_sprom *sprom = &dev->bus->sprom;
4560 struct ieee80211_hw *hw;
4561 struct b43_wl *wl;
4562 int err = -ENOMEM;
4563
4564 b43_sprom_fixup(dev->bus);
4565
4566 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4567 if (!hw) {
4568 b43err(NULL, "Could not allocate ieee80211 device\n");
4569 goto out;
4570 }
4571
4572 /* fill hw info */
4573 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4574 IEEE80211_HW_RX_INCLUDES_FCS |
4575 IEEE80211_HW_SIGNAL_DBM |
4576 IEEE80211_HW_NOISE_DBM;
4577
4578 hw->queues = b43_modparam_qos ? 4 : 1;
4579 SET_IEEE80211_DEV(hw, dev->dev);
4580 if (is_valid_ether_addr(sprom->et1mac))
4581 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4582 else
4583 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4584
4585 /* Get and initialize struct b43_wl */
4586 wl = hw_to_b43_wl(hw);
4587 memset(wl, 0, sizeof(*wl));
4588 wl->hw = hw;
4589 spin_lock_init(&wl->irq_lock);
4590 rwlock_init(&wl->tx_lock);
4591 spin_lock_init(&wl->leds_lock);
4592 spin_lock_init(&wl->shm_lock);
4593 mutex_init(&wl->mutex);
4594 INIT_LIST_HEAD(&wl->devlist);
4595 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4596 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4597
4598 ssb_set_devtypedata(dev, wl);
4599 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4600 err = 0;
4601 out:
4602 return err;
4603 }
4604
4605 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4606 {
4607 struct b43_wl *wl;
4608 int err;
4609 int first = 0;
4610
4611 wl = ssb_get_devtypedata(dev);
4612 if (!wl) {
4613 /* Probing the first core. Must setup common struct b43_wl */
4614 first = 1;
4615 err = b43_wireless_init(dev);
4616 if (err)
4617 goto out;
4618 wl = ssb_get_devtypedata(dev);
4619 B43_WARN_ON(!wl);
4620 }
4621 err = b43_one_core_attach(dev, wl);
4622 if (err)
4623 goto err_wireless_exit;
4624
4625 if (first) {
4626 err = ieee80211_register_hw(wl->hw);
4627 if (err)
4628 goto err_one_core_detach;
4629 }
4630
4631 out:
4632 return err;
4633
4634 err_one_core_detach:
4635 b43_one_core_detach(dev);
4636 err_wireless_exit:
4637 if (first)
4638 b43_wireless_exit(dev, wl);
4639 return err;
4640 }
4641
4642 static void b43_remove(struct ssb_device *dev)
4643 {
4644 struct b43_wl *wl = ssb_get_devtypedata(dev);
4645 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4646
4647 B43_WARN_ON(!wl);
4648 if (wl->current_dev == wldev)
4649 ieee80211_unregister_hw(wl->hw);
4650
4651 b43_one_core_detach(dev);
4652
4653 if (list_empty(&wl->devlist)) {
4654 /* Last core on the chip unregistered.
4655 * We can destroy common struct b43_wl.
4656 */
4657 b43_wireless_exit(dev, wl);
4658 }
4659 }
4660
4661 /* Perform a hardware reset. This can be called from any context. */
4662 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4663 {
4664 /* Must avoid requeueing, if we are in shutdown. */
4665 if (b43_status(dev) < B43_STAT_INITIALIZED)
4666 return;
4667 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4668 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4669 }
4670
4671 #ifdef CONFIG_PM
4672
4673 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4674 {
4675 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4676 struct b43_wl *wl = wldev->wl;
4677
4678 b43dbg(wl, "Suspending...\n");
4679
4680 mutex_lock(&wl->mutex);
4681 wldev->suspend_in_progress = true;
4682 wldev->suspend_init_status = b43_status(wldev);
4683 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4684 b43_wireless_core_stop(wldev);
4685 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4686 b43_wireless_core_exit(wldev);
4687 mutex_unlock(&wl->mutex);
4688
4689 b43dbg(wl, "Device suspended.\n");
4690
4691 return 0;
4692 }
4693
4694 static int b43_resume(struct ssb_device *dev)
4695 {
4696 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4697 struct b43_wl *wl = wldev->wl;
4698 int err = 0;
4699
4700 b43dbg(wl, "Resuming...\n");
4701
4702 mutex_lock(&wl->mutex);
4703 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4704 err = b43_wireless_core_init(wldev);
4705 if (err) {
4706 b43err(wl, "Resume failed at core init\n");
4707 goto out;
4708 }
4709 }
4710 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4711 err = b43_wireless_core_start(wldev);
4712 if (err) {
4713 b43_leds_exit(wldev);
4714 b43_rng_exit(wldev->wl);
4715 b43_wireless_core_exit(wldev);
4716 b43err(wl, "Resume failed at core start\n");
4717 goto out;
4718 }
4719 }
4720 b43dbg(wl, "Device resumed.\n");
4721 out:
4722 wldev->suspend_in_progress = false;
4723 mutex_unlock(&wl->mutex);
4724 return err;
4725 }
4726
4727 #else /* CONFIG_PM */
4728 # define b43_suspend NULL
4729 # define b43_resume NULL
4730 #endif /* CONFIG_PM */
4731
4732 static struct ssb_driver b43_ssb_driver = {
4733 .name = KBUILD_MODNAME,
4734 .id_table = b43_ssb_tbl,
4735 .probe = b43_probe,
4736 .remove = b43_remove,
4737 .suspend = b43_suspend,
4738 .resume = b43_resume,
4739 };
4740
4741 static void b43_print_driverinfo(void)
4742 {
4743 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4744 *feat_leds = "", *feat_rfkill = "";
4745
4746 #ifdef CONFIG_B43_PCI_AUTOSELECT
4747 feat_pci = "P";
4748 #endif
4749 #ifdef CONFIG_B43_PCMCIA
4750 feat_pcmcia = "M";
4751 #endif
4752 #ifdef CONFIG_B43_NPHY
4753 feat_nphy = "N";
4754 #endif
4755 #ifdef CONFIG_B43_LEDS
4756 feat_leds = "L";
4757 #endif
4758 #ifdef CONFIG_B43_RFKILL
4759 feat_rfkill = "R";
4760 #endif
4761 printk(KERN_INFO "Broadcom 43xx driver loaded "
4762 "[ Features: %s%s%s%s%s, Firmware-ID: "
4763 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4764 feat_pci, feat_pcmcia, feat_nphy,
4765 feat_leds, feat_rfkill);
4766 }
4767
4768 static int __init b43_init(void)
4769 {
4770 int err;
4771
4772 b43_debugfs_init();
4773 err = b43_pcmcia_init();
4774 if (err)
4775 goto err_dfs_exit;
4776 err = ssb_driver_register(&b43_ssb_driver);
4777 if (err)
4778 goto err_pcmcia_exit;
4779 b43_print_driverinfo();
4780
4781 return err;
4782
4783 err_pcmcia_exit:
4784 b43_pcmcia_exit();
4785 err_dfs_exit:
4786 b43_debugfs_exit();
4787 return err;
4788 }
4789
4790 static void __exit b43_exit(void)
4791 {
4792 ssb_driver_unregister(&b43_ssb_driver);
4793 b43_pcmcia_exit();
4794 b43_debugfs_exit();
4795 }
4796
4797 module_init(b43_init)
4798 module_exit(b43_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree