2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
30 * Allocates a generic ring segment from the ring pool, sets the dma address,
31 * initializes the segment to zero, and sets the private next pointer to NULL.
34 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
38 struct xhci_segment
*seg
;
41 seg
= kzalloc(sizeof *seg
, flags
);
44 xhci_dbg(xhci
, "Allocating priv segment structure at %p\n", seg
);
46 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
51 xhci_dbg(xhci
, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
52 seg
->trbs
, (unsigned long long)dma
);
54 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
61 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
66 xhci_dbg(xhci
, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
67 seg
->trbs
, (unsigned long long)seg
->dma
);
68 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
71 xhci_dbg(xhci
, "Freeing priv segment structure at %p\n", seg
);
76 * Make the prev segment point to the next segment.
78 * Change the last TRB in the prev segment to be a Link TRB which points to the
79 * DMA address of the next segment. The caller needs to set any Link TRB
80 * related flags, such as End TRB, Toggle Cycle, and no snoop.
82 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
83 struct xhci_segment
*next
, bool link_trbs
)
91 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
= next
->dma
;
93 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
94 val
= prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
;
95 val
&= ~TRB_TYPE_BITMASK
;
96 val
|= TRB_TYPE(TRB_LINK
);
97 /* Always set the chain bit with 0.95 hardware */
98 if (xhci_link_trb_quirk(xhci
))
100 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= val
;
102 xhci_dbg(xhci
, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
103 (unsigned long long)prev
->dma
,
104 (unsigned long long)next
->dma
);
107 /* XXX: Do we need the hcd structure in all these functions? */
108 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
110 struct xhci_segment
*seg
;
111 struct xhci_segment
*first_seg
;
113 if (!ring
|| !ring
->first_seg
)
115 first_seg
= ring
->first_seg
;
116 seg
= first_seg
->next
;
117 xhci_dbg(xhci
, "Freeing ring at %p\n", ring
);
118 while (seg
!= first_seg
) {
119 struct xhci_segment
*next
= seg
->next
;
120 xhci_segment_free(xhci
, seg
);
123 xhci_segment_free(xhci
, first_seg
);
124 ring
->first_seg
= NULL
;
129 * Create a new ring with zero or more segments.
131 * Link each segment together into a ring.
132 * Set the end flag and the cycle toggle bit on the last segment.
133 * See section 4.9.1 and figures 15 and 16.
135 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
136 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
138 struct xhci_ring
*ring
;
139 struct xhci_segment
*prev
;
141 ring
= kzalloc(sizeof *(ring
), flags
);
142 xhci_dbg(xhci
, "Allocating ring at %p\n", ring
);
146 INIT_LIST_HEAD(&ring
->td_list
);
147 INIT_LIST_HEAD(&ring
->cancelled_td_list
);
151 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
152 if (!ring
->first_seg
)
156 prev
= ring
->first_seg
;
157 while (num_segs
> 0) {
158 struct xhci_segment
*next
;
160 next
= xhci_segment_alloc(xhci
, flags
);
163 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
168 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
171 /* See section 4.9.2.1 and 6.4.4.1 */
172 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
|= (LINK_TOGGLE
);
173 xhci_dbg(xhci
, "Wrote link toggle flag to"
174 " segment %p (virtual), 0x%llx (DMA)\n",
175 prev
, (unsigned long long)prev
->dma
);
177 /* The ring is empty, so the enqueue pointer == dequeue pointer */
178 ring
->enqueue
= ring
->first_seg
->trbs
;
179 ring
->enq_seg
= ring
->first_seg
;
180 ring
->dequeue
= ring
->enqueue
;
181 ring
->deq_seg
= ring
->first_seg
;
182 /* The ring is initialized to 0. The producer must write 1 to the cycle
183 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
184 * compare CCS to the cycle bit to check ownership, so CCS = 1.
186 ring
->cycle_state
= 1;
191 xhci_ring_free(xhci
, ring
);
195 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
197 struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
198 int type
, gfp_t flags
)
200 struct xhci_container_ctx
*ctx
= kzalloc(sizeof(*ctx
), flags
);
204 BUG_ON((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
));
206 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
207 if (type
== XHCI_CTX_TYPE_INPUT
)
208 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
210 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
211 memset(ctx
->bytes
, 0, ctx
->size
);
215 void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
216 struct xhci_container_ctx
*ctx
)
218 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
222 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
223 struct xhci_container_ctx
*ctx
)
225 BUG_ON(ctx
->type
!= XHCI_CTX_TYPE_INPUT
);
226 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
229 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
230 struct xhci_container_ctx
*ctx
)
232 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
233 return (struct xhci_slot_ctx
*)ctx
->bytes
;
235 return (struct xhci_slot_ctx
*)
236 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
239 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
240 struct xhci_container_ctx
*ctx
,
241 unsigned int ep_index
)
243 /* increment ep index by offset of start of ep ctx array */
245 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
248 return (struct xhci_ep_ctx
*)
249 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
252 /* All the xhci_tds in the ring's TD list should be freed at this point */
253 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
255 struct xhci_virt_device
*dev
;
258 /* Slot ID 0 is reserved */
259 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
262 dev
= xhci
->devs
[slot_id
];
263 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
267 for (i
= 0; i
< 31; ++i
)
268 if (dev
->ep_rings
[i
])
269 xhci_ring_free(xhci
, dev
->ep_rings
[i
]);
272 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
274 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
276 kfree(xhci
->devs
[slot_id
]);
277 xhci
->devs
[slot_id
] = 0;
280 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
281 struct usb_device
*udev
, gfp_t flags
)
283 struct xhci_virt_device
*dev
;
285 /* Slot ID 0 is reserved */
286 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
287 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
291 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
292 if (!xhci
->devs
[slot_id
])
294 dev
= xhci
->devs
[slot_id
];
296 /* Allocate the (output) device context that will be used in the HC. */
297 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
301 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
302 (unsigned long long)dev
->out_ctx
->dma
);
304 /* Allocate the (input) device context for address device command */
305 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
309 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
310 (unsigned long long)dev
->in_ctx
->dma
);
312 /* Allocate endpoint 0 ring */
313 dev
->ep_rings
[0] = xhci_ring_alloc(xhci
, 1, true, flags
);
314 if (!dev
->ep_rings
[0])
317 init_completion(&dev
->cmd_completion
);
319 /* Point to output device context in dcbaa. */
320 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = dev
->out_ctx
->dma
;
321 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
323 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
324 (unsigned long long) xhci
->dcbaa
->dev_context_ptrs
[slot_id
]);
328 xhci_free_virt_device(xhci
, slot_id
);
332 /* Setup an xHCI virtual device for a Set Address command */
333 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
335 struct xhci_virt_device
*dev
;
336 struct xhci_ep_ctx
*ep0_ctx
;
337 struct usb_device
*top_dev
;
338 struct xhci_slot_ctx
*slot_ctx
;
339 struct xhci_input_control_ctx
*ctrl_ctx
;
341 dev
= xhci
->devs
[udev
->slot_id
];
342 /* Slot ID 0 is reserved */
343 if (udev
->slot_id
== 0 || !dev
) {
344 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
348 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
349 ctrl_ctx
= xhci_get_input_control_ctx(xhci
, dev
->in_ctx
);
350 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
352 /* 2) New slot context and endpoint 0 context are valid*/
353 ctrl_ctx
->add_flags
= SLOT_FLAG
| EP0_FLAG
;
355 /* 3) Only the control endpoint is valid - one endpoint context */
356 slot_ctx
->dev_info
|= LAST_CTX(1);
358 switch (udev
->speed
) {
359 case USB_SPEED_SUPER
:
360 slot_ctx
->dev_info
|= (u32
) udev
->route
;
361 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_SS
;
364 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_HS
;
367 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_FS
;
370 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_LS
;
372 case USB_SPEED_VARIABLE
:
373 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
377 /* Speed was set earlier, this shouldn't happen. */
380 /* Find the root hub port this device is under */
381 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
382 top_dev
= top_dev
->parent
)
383 /* Found device below root hub */;
384 slot_ctx
->dev_info2
|= (u32
) ROOT_HUB_PORT(top_dev
->portnum
);
385 xhci_dbg(xhci
, "Set root hub portnum to %d\n", top_dev
->portnum
);
387 /* Is this a LS/FS device under a HS hub? */
389 * FIXME: I don't think this is right, where does the TT info for the
390 * roothub or parent hub come from?
392 if ((udev
->speed
== USB_SPEED_LOW
|| udev
->speed
== USB_SPEED_FULL
) &&
394 slot_ctx
->tt_info
= udev
->tt
->hub
->slot_id
;
395 slot_ctx
->tt_info
|= udev
->ttport
<< 8;
397 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
398 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
400 /* Step 4 - ring already allocated */
402 ep0_ctx
->ep_info2
= EP_TYPE(CTRL_EP
);
404 * XXX: Not sure about wireless USB devices.
406 switch (udev
->speed
) {
407 case USB_SPEED_SUPER
:
408 ep0_ctx
->ep_info2
|= MAX_PACKET(512);
411 /* USB core guesses at a 64-byte max packet first for FS devices */
413 ep0_ctx
->ep_info2
|= MAX_PACKET(64);
416 ep0_ctx
->ep_info2
|= MAX_PACKET(8);
418 case USB_SPEED_VARIABLE
:
419 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
426 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
427 ep0_ctx
->ep_info2
|= MAX_BURST(0);
428 ep0_ctx
->ep_info2
|= ERROR_COUNT(3);
431 dev
->ep_rings
[0]->first_seg
->dma
;
432 ep0_ctx
->deq
|= dev
->ep_rings
[0]->cycle_state
;
434 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
439 /* Return the polling or NAK interval.
441 * The polling interval is expressed in "microframes". If xHCI's Interval field
442 * is set to N, it will service the endpoint every 2^(Interval)*125us.
444 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
447 static inline unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
448 struct usb_host_endpoint
*ep
)
450 unsigned int interval
= 0;
452 switch (udev
->speed
) {
455 if (usb_endpoint_xfer_control(&ep
->desc
) ||
456 usb_endpoint_xfer_bulk(&ep
->desc
))
457 interval
= ep
->desc
.bInterval
;
458 /* Fall through - SS and HS isoc/int have same decoding */
459 case USB_SPEED_SUPER
:
460 if (usb_endpoint_xfer_int(&ep
->desc
) ||
461 usb_endpoint_xfer_isoc(&ep
->desc
)) {
462 if (ep
->desc
.bInterval
== 0)
465 interval
= ep
->desc
.bInterval
- 1;
468 if (interval
!= ep
->desc
.bInterval
+ 1)
469 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
470 ep
->desc
.bEndpointAddress
, 1 << interval
);
473 /* Convert bInterval (in 1-255 frames) to microframes and round down to
474 * nearest power of 2.
478 if (usb_endpoint_xfer_int(&ep
->desc
) ||
479 usb_endpoint_xfer_isoc(&ep
->desc
)) {
480 interval
= fls(8*ep
->desc
.bInterval
) - 1;
485 if ((1 << interval
) != 8*ep
->desc
.bInterval
)
486 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
487 ep
->desc
.bEndpointAddress
, 1 << interval
);
493 return EP_INTERVAL(interval
);
496 static inline u32
xhci_get_endpoint_type(struct usb_device
*udev
,
497 struct usb_host_endpoint
*ep
)
502 in
= usb_endpoint_dir_in(&ep
->desc
);
503 if (usb_endpoint_xfer_control(&ep
->desc
)) {
504 type
= EP_TYPE(CTRL_EP
);
505 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
507 type
= EP_TYPE(BULK_IN_EP
);
509 type
= EP_TYPE(BULK_OUT_EP
);
510 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
512 type
= EP_TYPE(ISOC_IN_EP
);
514 type
= EP_TYPE(ISOC_OUT_EP
);
515 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
517 type
= EP_TYPE(INT_IN_EP
);
519 type
= EP_TYPE(INT_OUT_EP
);
526 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
527 struct xhci_virt_device
*virt_dev
,
528 struct usb_device
*udev
,
529 struct usb_host_endpoint
*ep
,
532 unsigned int ep_index
;
533 struct xhci_ep_ctx
*ep_ctx
;
534 struct xhci_ring
*ep_ring
;
535 unsigned int max_packet
;
536 unsigned int max_burst
;
538 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
539 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
541 /* Set up the endpoint ring */
542 virt_dev
->new_ep_rings
[ep_index
] = xhci_ring_alloc(xhci
, 1, true, mem_flags
);
543 if (!virt_dev
->new_ep_rings
[ep_index
])
545 ep_ring
= virt_dev
->new_ep_rings
[ep_index
];
546 ep_ctx
->deq
= ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
;
548 ep_ctx
->ep_info
= xhci_get_endpoint_interval(udev
, ep
);
550 /* FIXME dig Mult and streams info out of ep companion desc */
552 /* Allow 3 retries for everything but isoc;
553 * error count = 0 means infinite retries.
555 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
556 ep_ctx
->ep_info2
= ERROR_COUNT(3);
558 ep_ctx
->ep_info2
= ERROR_COUNT(1);
560 ep_ctx
->ep_info2
|= xhci_get_endpoint_type(udev
, ep
);
562 /* Set the max packet size and max burst */
563 switch (udev
->speed
) {
564 case USB_SPEED_SUPER
:
565 max_packet
= ep
->desc
.wMaxPacketSize
;
566 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
567 /* dig out max burst from ep companion desc */
568 if (!ep
->ss_ep_comp
) {
569 xhci_warn(xhci
, "WARN no SS endpoint companion descriptor.\n");
572 max_packet
= ep
->ss_ep_comp
->desc
.bMaxBurst
;
574 ep_ctx
->ep_info2
|= MAX_BURST(max_packet
);
577 /* bits 11:12 specify the number of additional transaction
578 * opportunities per microframe (USB 2.0, section 9.6.6)
580 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
581 usb_endpoint_xfer_int(&ep
->desc
)) {
582 max_burst
= (ep
->desc
.wMaxPacketSize
& 0x1800) >> 11;
583 ep_ctx
->ep_info2
|= MAX_BURST(max_burst
);
588 max_packet
= ep
->desc
.wMaxPacketSize
& 0x3ff;
589 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
594 /* FIXME Debug endpoint context */
598 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
599 struct xhci_virt_device
*virt_dev
,
600 struct usb_host_endpoint
*ep
)
602 unsigned int ep_index
;
603 struct xhci_ep_ctx
*ep_ctx
;
605 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
606 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
609 ep_ctx
->ep_info2
= 0;
612 /* Don't free the endpoint ring until the set interface or configuration
617 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
618 * Useful when you want to change one particular aspect of the endpoint and then
619 * issue a configure endpoint command.
621 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
622 struct xhci_virt_device
*vdev
, unsigned int ep_index
)
624 struct xhci_ep_ctx
*out_ep_ctx
;
625 struct xhci_ep_ctx
*in_ep_ctx
;
627 out_ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->out_ctx
, ep_index
);
628 in_ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->in_ctx
, ep_index
);
630 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
631 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
632 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
633 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
636 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
637 * Useful when you want to change one particular aspect of the endpoint and then
638 * issue a configure endpoint command. Only the context entries field matters,
639 * but we'll copy the whole thing anyway.
641 void xhci_slot_copy(struct xhci_hcd
*xhci
, struct xhci_virt_device
*vdev
)
643 struct xhci_slot_ctx
*in_slot_ctx
;
644 struct xhci_slot_ctx
*out_slot_ctx
;
646 in_slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->in_ctx
);
647 out_slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
649 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
650 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
651 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
652 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
655 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
656 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
659 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
660 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
662 xhci_dbg(xhci
, "Allocating %d scratchpad buffers\n", num_sp
);
667 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
668 if (!xhci
->scratchpad
)
671 xhci
->scratchpad
->sp_array
=
672 pci_alloc_consistent(to_pci_dev(dev
),
673 num_sp
* sizeof(u64
),
674 &xhci
->scratchpad
->sp_dma
);
675 if (!xhci
->scratchpad
->sp_array
)
678 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
679 if (!xhci
->scratchpad
->sp_buffers
)
682 xhci
->scratchpad
->sp_dma_buffers
=
683 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
685 if (!xhci
->scratchpad
->sp_dma_buffers
)
688 xhci
->dcbaa
->dev_context_ptrs
[0] = xhci
->scratchpad
->sp_dma
;
689 for (i
= 0; i
< num_sp
; i
++) {
691 void *buf
= pci_alloc_consistent(to_pci_dev(dev
),
692 xhci
->page_size
, &dma
);
696 xhci
->scratchpad
->sp_array
[i
] = dma
;
697 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
698 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
704 for (i
= i
- 1; i
>= 0; i
--) {
705 pci_free_consistent(to_pci_dev(dev
), xhci
->page_size
,
706 xhci
->scratchpad
->sp_buffers
[i
],
707 xhci
->scratchpad
->sp_dma_buffers
[i
]);
709 kfree(xhci
->scratchpad
->sp_dma_buffers
);
712 kfree(xhci
->scratchpad
->sp_buffers
);
715 pci_free_consistent(to_pci_dev(dev
), num_sp
* sizeof(u64
),
716 xhci
->scratchpad
->sp_array
,
717 xhci
->scratchpad
->sp_dma
);
720 kfree(xhci
->scratchpad
);
721 xhci
->scratchpad
= NULL
;
727 static void scratchpad_free(struct xhci_hcd
*xhci
)
731 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
733 if (!xhci
->scratchpad
)
736 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
738 for (i
= 0; i
< num_sp
; i
++) {
739 pci_free_consistent(pdev
, xhci
->page_size
,
740 xhci
->scratchpad
->sp_buffers
[i
],
741 xhci
->scratchpad
->sp_dma_buffers
[i
]);
743 kfree(xhci
->scratchpad
->sp_dma_buffers
);
744 kfree(xhci
->scratchpad
->sp_buffers
);
745 pci_free_consistent(pdev
, num_sp
* sizeof(u64
),
746 xhci
->scratchpad
->sp_array
,
747 xhci
->scratchpad
->sp_dma
);
748 kfree(xhci
->scratchpad
);
749 xhci
->scratchpad
= NULL
;
752 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
754 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
758 /* Free the Event Ring Segment Table and the actual Event Ring */
759 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
760 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_base
);
761 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_dequeue
);
762 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
763 if (xhci
->erst
.entries
)
764 pci_free_consistent(pdev
, size
,
765 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
766 xhci
->erst
.entries
= NULL
;
767 xhci_dbg(xhci
, "Freed ERST\n");
768 if (xhci
->event_ring
)
769 xhci_ring_free(xhci
, xhci
->event_ring
);
770 xhci
->event_ring
= NULL
;
771 xhci_dbg(xhci
, "Freed event ring\n");
773 xhci_write_64(xhci
, 0, &xhci
->op_regs
->cmd_ring
);
775 xhci_ring_free(xhci
, xhci
->cmd_ring
);
776 xhci
->cmd_ring
= NULL
;
777 xhci_dbg(xhci
, "Freed command ring\n");
779 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
780 xhci_free_virt_device(xhci
, i
);
782 if (xhci
->segment_pool
)
783 dma_pool_destroy(xhci
->segment_pool
);
784 xhci
->segment_pool
= NULL
;
785 xhci_dbg(xhci
, "Freed segment pool\n");
787 if (xhci
->device_pool
)
788 dma_pool_destroy(xhci
->device_pool
);
789 xhci
->device_pool
= NULL
;
790 xhci_dbg(xhci
, "Freed device context pool\n");
792 xhci_write_64(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
);
794 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
795 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
799 xhci
->page_shift
= 0;
800 scratchpad_free(xhci
);
803 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
806 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
807 unsigned int val
, val2
;
809 struct xhci_segment
*seg
;
813 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
814 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
815 for (i
= 0; i
< 16; i
++) {
816 if ((0x1 & page_size
) != 0)
818 page_size
= page_size
>> 1;
821 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
823 xhci_warn(xhci
, "WARN: no supported page size\n");
824 /* Use 4K pages, since that's common and the minimum the HC supports */
825 xhci
->page_shift
= 12;
826 xhci
->page_size
= 1 << xhci
->page_shift
;
827 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
830 * Program the Number of Device Slots Enabled field in the CONFIG
831 * register with the max value of slots the HC can handle.
833 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
834 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
836 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
837 val
|= (val2
& ~HCS_SLOTS_MASK
);
838 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
840 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
843 * Section 5.4.8 - doorbell array must be
844 * "physically contiguous and 64-byte (cache line) aligned".
846 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
847 sizeof(*xhci
->dcbaa
), &dma
);
850 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
851 xhci
->dcbaa
->dma
= dma
;
852 xhci_dbg(xhci
, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
853 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
854 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
857 * Initialize the ring segment pool. The ring must be a contiguous
858 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
859 * however, the command ring segment needs 64-byte aligned segments,
860 * so we pick the greater alignment need.
862 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
863 SEGMENT_SIZE
, 64, xhci
->page_size
);
865 /* See Table 46 and Note on Figure 55 */
866 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
867 2112, 64, xhci
->page_size
);
868 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
871 /* Set up the command ring to have one segments for now. */
872 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
875 xhci_dbg(xhci
, "Allocated command ring at %p\n", xhci
->cmd_ring
);
876 xhci_dbg(xhci
, "First segment DMA is 0x%llx\n",
877 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
879 /* Set the address in the Command Ring Control register */
880 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
881 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
882 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
883 xhci
->cmd_ring
->cycle_state
;
884 xhci_dbg(xhci
, "// Setting command ring address to 0x%x\n", val
);
885 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
886 xhci_dbg_cmd_ptrs(xhci
);
888 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
890 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
891 " from cap regs base addr\n", val
);
892 xhci
->dba
= (void *) xhci
->cap_regs
+ val
;
894 xhci_print_run_regs(xhci
);
895 /* Set ir_set to interrupt register set 0 */
896 xhci
->ir_set
= (void *) xhci
->run_regs
->ir_set
;
899 * Event ring setup: Allocate a normal ring, but also setup
900 * the event ring segment table (ERST). Section 4.9.3.
902 xhci_dbg(xhci
, "// Allocating event ring\n");
903 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
904 if (!xhci
->event_ring
)
907 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
908 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
909 if (!xhci
->erst
.entries
)
911 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%llx\n",
912 (unsigned long long)dma
);
914 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
915 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
916 xhci
->erst
.erst_dma_addr
= dma
;
917 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
918 xhci
->erst
.num_entries
,
920 (unsigned long long)xhci
->erst
.erst_dma_addr
);
922 /* set ring base address and size for each segment table entry */
923 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
924 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
925 entry
->seg_addr
= seg
->dma
;
926 entry
->seg_size
= TRBS_PER_SEGMENT
;
931 /* set ERST count with the number of entries in the segment table */
932 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
933 val
&= ERST_SIZE_MASK
;
934 val
|= ERST_NUM_SEGS
;
935 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
937 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
939 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
940 /* set the segment table base address */
941 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%llx\n",
942 (unsigned long long)xhci
->erst
.erst_dma_addr
);
943 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
944 val_64
&= ERST_PTR_MASK
;
945 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
946 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
948 /* Set the event ring dequeue address */
949 xhci_set_hc_event_deq(xhci
);
950 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
951 xhci_print_ir_set(xhci
, xhci
->ir_set
, 0);
954 * XXX: Might need to set the Interrupter Moderation Register to
955 * something other than the default (~1ms minimum between interrupts).
956 * See section 5.5.1.2.
958 init_completion(&xhci
->addr_dev
);
959 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
962 if (scratchpad_alloc(xhci
, flags
))
968 xhci_warn(xhci
, "Couldn't initialize memory\n");
969 xhci_mem_cleanup(xhci
);