include/linux/mmc/dw_mmc.h

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef _LINUX_MMC_DW_MMC_H_
  15 #define _LINUX_MMC_DW_MMC_H_
  16
  17 #define MAX_MCI_SLOTS   2
  18
  19 enum dw_mci_state {
  20         STATE_IDLE = 0,
  21         STATE_SENDING_CMD,
  22         STATE_SENDING_DATA,
  23         STATE_DATA_BUSY,
  24         STATE_SENDING_STOP,
  25         STATE_DATA_ERROR,
  26 };
  27
  28 enum {
  29         EVENT_CMD_COMPLETE = 0,
  30         EVENT_XFER_COMPLETE,
  31         EVENT_DATA_COMPLETE,
  32         EVENT_DATA_ERROR,
  33         EVENT_XFER_ERROR
  34 };
  35
  36 struct mmc_data;
  37
  38 /**
  39  * struct dw_mci - MMC controller state shared between all slots
  40  * @lock: Spinlock protecting the queue and associated data.
  41  * @regs: Pointer to MMIO registers.
  42  * @sg: Scatterlist entry currently being processed by PIO code, if any.
  43  * @pio_offset: Offset into the current scatterlist entry.
  44  * @cur_slot: The slot which is currently using the controller.
  45  * @mrq: The request currently being processed on @cur_slot,
  46  *      or NULL if the controller is idle.
  47  * @cmd: The command currently being sent to the card, or NULL.
  48  * @data: The data currently being transferred, or NULL if no data
  49  *      transfer is in progress.
  50  * @use_dma: Whether DMA channel is initialized or not.
  51  * @sg_dma: Bus address of DMA buffer.
  52  * @sg_cpu: Virtual address of DMA buffer.
  53  * @dma_ops: Pointer to platform-specific DMA callbacks.
  54  * @cmd_status: Snapshot of SR taken upon completion of the current
  55  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
  56  * @data_status: Snapshot of SR taken upon completion of the current
  57  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
  58  *      EVENT_DATA_ERROR is pending.
  59  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
  60  *      to be sent.
  61  * @dir_status: Direction of current transfer.
  62  * @tasklet: Tasklet running the request state machine.
  63  * @card_tasklet: Tasklet handling card detect.
  64  * @pending_events: Bitmask of events flagged by the interrupt handler
  65  *      to be processed by the tasklet.
  66  * @completed_events: Bitmask of events which the state machine has
  67  *      processed.
  68  * @state: Tasklet state.
  69  * @queue: List of slots waiting for access to the controller.
  70  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
  71  *      rate and timeout calculations.
  72  * @current_speed: Configured rate of the controller.
  73  * @num_slots: Number of slots available.
  74  * @pdev: Platform device associated with the MMC controller.
  75  * @pdata: Platform data associated with the MMC controller.
  76  * @slot: Slots sharing this MMC controller.
  77  * @data_shift: log2 of FIFO item size.
  78  * @push_data: Pointer to FIFO push function.
  79  * @pull_data: Pointer to FIFO pull function.
  80  * @quirks: Set of quirks that apply to specific versions of the IP.
  81  *
  82  * Locking
  83  * =======
  84  *
  85  * @lock is a softirq-safe spinlock protecting @queue as well as
  86  * @cur_slot, @mrq and @state. These must always be updated
  87  * at the same time while holding @lock.
  88  *
  89  * The @mrq field of struct dw_mci_slot is also protected by @lock,
  90  * and must always be written at the same time as the slot is added to
  91  * @queue.
  92  *
  93  * @pending_events and @completed_events are accessed using atomic bit
  94  * operations, so they don't need any locking.
  95  *
  96  * None of the fields touched by the interrupt handler need any
  97  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
  98  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
  99  * interrupts must be disabled and @data_status updated with a
 100  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 101  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 102  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 103  * bytes_xfered field of @data must be written. This is ensured by
 104  * using barriers.
 105  */
 106 struct dw_mci {
 107         spinlock_t              lock;
 108         void __iomem            *regs;
 109
 110         struct scatterlist      *sg;
 111         unsigned int            pio_offset;
 112
 113         struct dw_mci_slot      *cur_slot;
 114         struct mmc_request      *mrq;
 115         struct mmc_command      *cmd;
 116         struct mmc_data         *data;
 117
 118         /* DMA interface members*/
 119         int                     use_dma;
 120
 121         dma_addr_t              sg_dma;
 122         void                    *sg_cpu;
 123         struct dw_mci_dma_ops   *dma_ops;
 124 #ifdef CONFIG_MMC_DW_IDMAC
 125         unsigned int            ring_size;
 126 #else
 127         struct dw_mci_dma_data  *dma_data;
 128 #endif
 129         u32                     cmd_status;
 130         u32                     data_status;
 131         u32                     stop_cmdr;
 132         u32                     dir_status;
 133         struct tasklet_struct   tasklet;
 134         struct tasklet_struct   card_tasklet;
 135         unsigned long           pending_events;
 136         unsigned long           completed_events;
 137         enum dw_mci_state       state;
 138         struct list_head        queue;
 139
 140         u32                     bus_hz;
 141         u32                     current_speed;
 142         u32                     num_slots;
 143         u32                     fifoth_val;
 144         struct platform_device  *pdev;
 145         struct dw_mci_board     *pdata;
 146         struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
 147
 148         /* FIFO push and pull */
 149         int                     data_shift;
 150         void (*push_data)(struct dw_mci *host, void *buf, int cnt);
 151         void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
 152
 153         /* Workaround flags */
 154         u32                     quirks;
 155
 156         struct regulator        *vmmc;  /* Power regulator */
 157 };
 158
 159 /* DMA ops for Internal/External DMAC interface */
 160 struct dw_mci_dma_ops {
 161         /* DMA Ops */
 162         int (*init)(struct dw_mci *host);
 163         void (*start)(struct dw_mci *host, unsigned int sg_len);
 164         void (*complete)(struct dw_mci *host);
 165         void (*stop)(struct dw_mci *host);
 166         void (*cleanup)(struct dw_mci *host);
 167         void (*exit)(struct dw_mci *host);
 168 };
 169
 170 /* IP Quirks/flags. */
 171 /* DTO fix for command transmission with IDMAC configured */
 172 #define DW_MCI_QUIRK_IDMAC_DTO                  BIT(0)
 173 /* delay needed between retries on some 2.11a implementations */
 174 #define DW_MCI_QUIRK_RETRY_DELAY                BIT(1)
 175 /* High Speed Capable - Supports HS cards (up to 50MHz) */
 176 #define DW_MCI_QUIRK_HIGHSPEED                  BIT(2)
 177 /* Unreliable card detection */
 178 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION      BIT(3)
 179
 180
 181 struct dma_pdata;
 182
 183 struct block_settings {
 184         unsigned short  max_segs;       /* see blk_queue_max_segments */
 185         unsigned int    max_blk_size;   /* maximum size of one mmc block */
 186         unsigned int    max_blk_count;  /* maximum number of blocks in one req*/
 187         unsigned int    max_req_size;   /* maximum number of bytes in one req*/
 188         unsigned int    max_seg_size;   /* see blk_queue_max_segment_size */
 189 };
 190
 191 /* Board platform data */
 192 struct dw_mci_board {
 193         u32 num_slots;
 194
 195         u32 quirks; /* Workaround / Quirk flags */
 196         unsigned int bus_hz; /* Bus speed */
 197
 198         unsigned int caps;      /* Capabilities */
 199
 200         /* delay in mS before detecting cards after interrupt */
 201         u32 detect_delay_ms;
 202
 203         int (*init)(u32 slot_id, irq_handler_t , void *);
 204         int (*get_ro)(u32 slot_id);
 205         int (*get_cd)(u32 slot_id);
 206         int (*get_ocr)(u32 slot_id);
 207         int (*get_bus_wd)(u32 slot_id);
 208         /*
 209          * Enable power to selected slot and set voltage to desired level.
 210          * Voltage levels are specified using MMC_VDD_xxx defines defined
 211          * in linux/mmc/host.h file.
 212          */
 213         void (*setpower)(u32 slot_id, u32 volt);
 214         void (*exit)(u32 slot_id);
 215         void (*select_slot)(u32 slot_id);
 216
 217         struct dw_mci_dma_ops *dma_ops;
 218         struct dma_pdata *data;
 219         struct block_settings *blk_settings;
 220 };
 221
 222 #endif /* _LINUX_MMC_DW_MMC_H_ */