arch/arm/plat-omap/gpio.c

   1 /*
   2  *  linux/arch/arm/plat-omap/gpio.c
   3  *
   4  * Support functions for OMAP GPIO
   5  *
   6  * Copyright (C) 2003-2005 Nokia Corporation
   7  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24
  25 #include <mach/hardware.h>
  26 #include <asm/irq.h>
  27 #include <mach/irqs.h>
  28 #include <mach/gpio.h>
  29 #include <asm/mach/irq.h>
  30
  31 /*
  32  * OMAP1510 GPIO registers
  33  */
  34 #define OMAP1510_GPIO_BASE              IO_ADDRESS(0xfffce000)
  35 #define OMAP1510_GPIO_DATA_INPUT        0x00
  36 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
  37 #define OMAP1510_GPIO_DIR_CONTROL       0x08
  38 #define OMAP1510_GPIO_INT_CONTROL       0x0c
  39 #define OMAP1510_GPIO_INT_MASK          0x10
  40 #define OMAP1510_GPIO_INT_STATUS        0x14
  41 #define OMAP1510_GPIO_PIN_CONTROL       0x18
  42
  43 #define OMAP1510_IH_GPIO_BASE           64
  44
  45 /*
  46  * OMAP1610 specific GPIO registers
  47  */
  48 #define OMAP1610_GPIO1_BASE             IO_ADDRESS(0xfffbe400)
  49 #define OMAP1610_GPIO2_BASE             IO_ADDRESS(0xfffbec00)
  50 #define OMAP1610_GPIO3_BASE             IO_ADDRESS(0xfffbb400)
  51 #define OMAP1610_GPIO4_BASE             IO_ADDRESS(0xfffbbc00)
  52 #define OMAP1610_GPIO_REVISION          0x0000
  53 #define OMAP1610_GPIO_SYSCONFIG         0x0010
  54 #define OMAP1610_GPIO_SYSSTATUS         0x0014
  55 #define OMAP1610_GPIO_IRQSTATUS1        0x0018
  56 #define OMAP1610_GPIO_IRQENABLE1        0x001c
  57 #define OMAP1610_GPIO_WAKEUPENABLE      0x0028
  58 #define OMAP1610_GPIO_DATAIN            0x002c
  59 #define OMAP1610_GPIO_DATAOUT           0x0030
  60 #define OMAP1610_GPIO_DIRECTION         0x0034
  61 #define OMAP1610_GPIO_EDGE_CTRL1        0x0038
  62 #define OMAP1610_GPIO_EDGE_CTRL2        0x003c
  63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
  64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
  65 #define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
  66 #define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
  67 #define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
  68 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
  69
  70 /*
  71  * OMAP730 specific GPIO registers
  72  */
  73 #define OMAP730_GPIO1_BASE              IO_ADDRESS(0xfffbc000)
  74 #define OMAP730_GPIO2_BASE              IO_ADDRESS(0xfffbc800)
  75 #define OMAP730_GPIO3_BASE              IO_ADDRESS(0xfffbd000)
  76 #define OMAP730_GPIO4_BASE              IO_ADDRESS(0xfffbd800)
  77 #define OMAP730_GPIO5_BASE              IO_ADDRESS(0xfffbe000)
  78 #define OMAP730_GPIO6_BASE              IO_ADDRESS(0xfffbe800)
  79 #define OMAP730_GPIO_DATA_INPUT         0x00
  80 #define OMAP730_GPIO_DATA_OUTPUT        0x04
  81 #define OMAP730_GPIO_DIR_CONTROL        0x08
  82 #define OMAP730_GPIO_INT_CONTROL        0x0c
  83 #define OMAP730_GPIO_INT_MASK           0x10
  84 #define OMAP730_GPIO_INT_STATUS         0x14
  85
  86 /*
  87  * OMAP850 specific GPIO registers
  88  */
  89 #define OMAP850_GPIO1_BASE              IO_ADDRESS(0xfffbc000)
  90 #define OMAP850_GPIO2_BASE              IO_ADDRESS(0xfffbc800)
  91 #define OMAP850_GPIO3_BASE              IO_ADDRESS(0xfffbd000)
  92 #define OMAP850_GPIO4_BASE              IO_ADDRESS(0xfffbd800)
  93 #define OMAP850_GPIO5_BASE              IO_ADDRESS(0xfffbe000)
  94 #define OMAP850_GPIO6_BASE              IO_ADDRESS(0xfffbe800)
  95 #define OMAP850_GPIO_DATA_INPUT         0x00
  96 #define OMAP850_GPIO_DATA_OUTPUT        0x04
  97 #define OMAP850_GPIO_DIR_CONTROL        0x08
  98 #define OMAP850_GPIO_INT_CONTROL        0x0c
  99 #define OMAP850_GPIO_INT_MASK           0x10
 100 #define OMAP850_GPIO_INT_STATUS         0x14
 101
 102 /*
 103  * omap24xx specific GPIO registers
 104  */
 105 #define OMAP242X_GPIO1_BASE             IO_ADDRESS(0x48018000)
 106 #define OMAP242X_GPIO2_BASE             IO_ADDRESS(0x4801a000)
 107 #define OMAP242X_GPIO3_BASE             IO_ADDRESS(0x4801c000)
 108 #define OMAP242X_GPIO4_BASE             IO_ADDRESS(0x4801e000)
 109
 110 #define OMAP243X_GPIO1_BASE             IO_ADDRESS(0x4900C000)
 111 #define OMAP243X_GPIO2_BASE             IO_ADDRESS(0x4900E000)
 112 #define OMAP243X_GPIO3_BASE             IO_ADDRESS(0x49010000)
 113 #define OMAP243X_GPIO4_BASE             IO_ADDRESS(0x49012000)
 114 #define OMAP243X_GPIO5_BASE             IO_ADDRESS(0x480B6000)
 115
 116 #define OMAP24XX_GPIO_REVISION          0x0000
 117 #define OMAP24XX_GPIO_SYSCONFIG         0x0010
 118 #define OMAP24XX_GPIO_SYSSTATUS         0x0014
 119 #define OMAP24XX_GPIO_IRQSTATUS1        0x0018
 120 #define OMAP24XX_GPIO_IRQSTATUS2        0x0028
 121 #define OMAP24XX_GPIO_IRQENABLE2        0x002c
 122 #define OMAP24XX_GPIO_IRQENABLE1        0x001c
 123 #define OMAP24XX_GPIO_WAKE_EN           0x0020
 124 #define OMAP24XX_GPIO_CTRL              0x0030
 125 #define OMAP24XX_GPIO_OE                0x0034
 126 #define OMAP24XX_GPIO_DATAIN            0x0038
 127 #define OMAP24XX_GPIO_DATAOUT           0x003c
 128 #define OMAP24XX_GPIO_LEVELDETECT0      0x0040
 129 #define OMAP24XX_GPIO_LEVELDETECT1      0x0044
 130 #define OMAP24XX_GPIO_RISINGDETECT      0x0048
 131 #define OMAP24XX_GPIO_FALLINGDETECT     0x004c
 132 #define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
 133 #define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
 134 #define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
 135 #define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
 136 #define OMAP24XX_GPIO_CLEARWKUENA       0x0080
 137 #define OMAP24XX_GPIO_SETWKUENA         0x0084
 138 #define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
 139 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
 140
 141 /*
 142  * omap34xx specific GPIO registers
 143  */
 144
 145 #define OMAP34XX_GPIO1_BASE             IO_ADDRESS(0x48310000)
 146 #define OMAP34XX_GPIO2_BASE             IO_ADDRESS(0x49050000)
 147 #define OMAP34XX_GPIO3_BASE             IO_ADDRESS(0x49052000)
 148 #define OMAP34XX_GPIO4_BASE             IO_ADDRESS(0x49054000)
 149 #define OMAP34XX_GPIO5_BASE             IO_ADDRESS(0x49056000)
 150 #define OMAP34XX_GPIO6_BASE             IO_ADDRESS(0x49058000)
 151
 152 /*
 153  * OMAP44XX  specific GPIO registers
 154  */
 155 #define OMAP44XX_GPIO1_BASE             IO_ADDRESS(0x4a310000)
 156 #define OMAP44XX_GPIO2_BASE             IO_ADDRESS(0x48055000)
 157 #define OMAP44XX_GPIO3_BASE             IO_ADDRESS(0x48057000)
 158 #define OMAP44XX_GPIO4_BASE             IO_ADDRESS(0x48059000)
 159 #define OMAP44XX_GPIO5_BASE             IO_ADDRESS(0x4805B000)
 160 #define OMAP44XX_GPIO6_BASE             IO_ADDRESS(0x4805D000)
 161
 162 #define OMAP_MPUIO_VBASE                IO_ADDRESS(OMAP_MPUIO_BASE)
 163
 164 struct gpio_bank {
 165         void __iomem *base;
 166         u16 irq;
 167         u16 virtual_irq_start;
 168         int method;
 169 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||  \
 170                 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
 171         u32 suspend_wakeup;
 172         u32 saved_wakeup;
 173 #endif
 174 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 175                         defined(CONFIG_ARCH_OMAP4)
 176         u32 non_wakeup_gpios;
 177         u32 enabled_non_wakeup_gpios;
 178
 179         u32 saved_datain;
 180         u32 saved_fallingdetect;
 181         u32 saved_risingdetect;
 182 #endif
 183         u32 level_mask;
 184         spinlock_t lock;
 185         struct gpio_chip chip;
 186         struct clk *dbck;
 187 };
 188
 189 #define METHOD_MPUIO            0
 190 #define METHOD_GPIO_1510        1
 191 #define METHOD_GPIO_1610        2
 192 #define METHOD_GPIO_730         3
 193 #define METHOD_GPIO_850         4
 194 #define METHOD_GPIO_24XX        5
 195
 196 #ifdef CONFIG_ARCH_OMAP16XX
 197 static struct gpio_bank gpio_bank_1610[5] = {
 198         { OMAP_MPUIO_VBASE,    INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
 199         { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
 200         { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
 201         { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
 202         { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
 203 };
 204 #endif
 205
 206 #ifdef CONFIG_ARCH_OMAP15XX
 207 static struct gpio_bank gpio_bank_1510[2] = {
 208         { OMAP_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
 209         { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
 210 };
 211 #endif
 212
 213 #ifdef CONFIG_ARCH_OMAP730
 214 static struct gpio_bank gpio_bank_730[7] = {
 215         { OMAP_MPUIO_VBASE,    INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
 216         { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
 217         { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
 218         { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
 219         { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
 220         { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
 221         { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
 222 };
 223 #endif
 224
 225 #ifdef CONFIG_ARCH_OMAP850
 226 static struct gpio_bank gpio_bank_850[7] = {
 227         { OMAP_MPUIO_BASE,     INT_850_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
 228         { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
 229         { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
 230         { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
 231         { OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_850 },
 232         { OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
 233         { OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
 234 };
 235 #endif
 236
 237
 238 #ifdef CONFIG_ARCH_OMAP24XX
 239
 240 static struct gpio_bank gpio_bank_242x[4] = {
 241         { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 242         { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 243         { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 244         { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 245 };
 246
 247 static struct gpio_bank gpio_bank_243x[5] = {
 248         { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 249         { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 250         { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 251         { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 252         { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
 253 };
 254
 255 #endif
 256
 257 #ifdef CONFIG_ARCH_OMAP34XX
 258 static struct gpio_bank gpio_bank_34xx[6] = {
 259         { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 260         { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 261         { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 262         { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 263         { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
 264         { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
 265 };
 266
 267 #endif
 268
 269 #ifdef CONFIG_ARCH_OMAP4
 270 static struct gpio_bank gpio_bank_44xx[6] = {
 271         { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,       \
 272                 METHOD_GPIO_24XX },
 273         { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,  \
 274                 METHOD_GPIO_24XX },
 275         { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,  \
 276                 METHOD_GPIO_24XX },
 277         { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,  \
 278                 METHOD_GPIO_24XX },
 279         { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
 280                 METHOD_GPIO_24XX },
 281         { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
 282                 METHOD_GPIO_24XX },
 283 };
 284
 285 #endif
 286
 287 static struct gpio_bank *gpio_bank;
 288 static int gpio_bank_count;
 289
 290 static inline struct gpio_bank *get_gpio_bank(int gpio)
 291 {
 292         if (cpu_is_omap15xx()) {
 293                 if (OMAP_GPIO_IS_MPUIO(gpio))
 294                         return &gpio_bank[0];
 295                 return &gpio_bank[1];
 296         }
 297         if (cpu_is_omap16xx()) {
 298                 if (OMAP_GPIO_IS_MPUIO(gpio))
 299                         return &gpio_bank[0];
 300                 return &gpio_bank[1 + (gpio >> 4)];
 301         }
 302         if (cpu_is_omap7xx()) {
 303                 if (OMAP_GPIO_IS_MPUIO(gpio))
 304                         return &gpio_bank[0];
 305                 return &gpio_bank[1 + (gpio >> 5)];
 306         }
 307         if (cpu_is_omap24xx())
 308                 return &gpio_bank[gpio >> 5];
 309         if (cpu_is_omap34xx() || cpu_is_omap44xx())
 310                 return &gpio_bank[gpio >> 5];
 311         BUG();
 312         return NULL;
 313 }
 314
 315 static inline int get_gpio_index(int gpio)
 316 {
 317         if (cpu_is_omap7xx())
 318                 return gpio & 0x1f;
 319         if (cpu_is_omap24xx())
 320                 return gpio & 0x1f;
 321         if (cpu_is_omap34xx() || cpu_is_omap44xx())
 322                 return gpio & 0x1f;
 323         return gpio & 0x0f;
 324 }
 325
 326 static inline int gpio_valid(int gpio)
 327 {
 328         if (gpio < 0)
 329                 return -1;
 330         if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
 331                 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
 332                         return -1;
 333                 return 0;
 334         }
 335         if (cpu_is_omap15xx() && gpio < 16)
 336                 return 0;
 337         if ((cpu_is_omap16xx()) && gpio < 64)
 338                 return 0;
 339         if (cpu_is_omap7xx() && gpio < 192)
 340                 return 0;
 341         if (cpu_is_omap24xx() && gpio < 128)
 342                 return 0;
 343         if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
 344                 return 0;
 345         return -1;
 346 }
 347
 348 static int check_gpio(int gpio)
 349 {
 350         if (unlikely(gpio_valid(gpio)) < 0) {
 351                 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
 352                 dump_stack();
 353                 return -1;
 354         }
 355         return 0;
 356 }
 357
 358 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 359 {
 360         void __iomem *reg = bank->base;
 361         u32 l;
 362
 363         switch (bank->method) {
 364 #ifdef CONFIG_ARCH_OMAP1
 365         case METHOD_MPUIO:
 366                 reg += OMAP_MPUIO_IO_CNTL;
 367                 break;
 368 #endif
 369 #ifdef CONFIG_ARCH_OMAP15XX
 370         case METHOD_GPIO_1510:
 371                 reg += OMAP1510_GPIO_DIR_CONTROL;
 372                 break;
 373 #endif
 374 #ifdef CONFIG_ARCH_OMAP16XX
 375         case METHOD_GPIO_1610:
 376                 reg += OMAP1610_GPIO_DIRECTION;
 377                 break;
 378 #endif
 379 #ifdef CONFIG_ARCH_OMAP730
 380         case METHOD_GPIO_730:
 381                 reg += OMAP730_GPIO_DIR_CONTROL;
 382                 break;
 383 #endif
 384 #ifdef CONFIG_ARCH_OMAP850
 385         case METHOD_GPIO_850:
 386                 reg += OMAP850_GPIO_DIR_CONTROL;
 387                 break;
 388 #endif
 389 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 390                         defined(CONFIG_ARCH_OMAP4)
 391         case METHOD_GPIO_24XX:
 392                 reg += OMAP24XX_GPIO_OE;
 393                 break;
 394 #endif
 395         default:
 396                 WARN_ON(1);
 397                 return;
 398         }
 399         l = __raw_readl(reg);
 400         if (is_input)
 401                 l |= 1 << gpio;
 402         else
 403                 l &= ~(1 << gpio);
 404         __raw_writel(l, reg);
 405 }
 406
 407 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 408 {
 409         void __iomem *reg = bank->base;
 410         u32 l = 0;
 411
 412         switch (bank->method) {
 413 #ifdef CONFIG_ARCH_OMAP1
 414         case METHOD_MPUIO:
 415                 reg += OMAP_MPUIO_OUTPUT;
 416                 l = __raw_readl(reg);
 417                 if (enable)
 418                         l |= 1 << gpio;
 419                 else
 420                         l &= ~(1 << gpio);
 421                 break;
 422 #endif
 423 #ifdef CONFIG_ARCH_OMAP15XX
 424         case METHOD_GPIO_1510:
 425                 reg += OMAP1510_GPIO_DATA_OUTPUT;
 426                 l = __raw_readl(reg);
 427                 if (enable)
 428                         l |= 1 << gpio;
 429                 else
 430                         l &= ~(1 << gpio);
 431                 break;
 432 #endif
 433 #ifdef CONFIG_ARCH_OMAP16XX
 434         case METHOD_GPIO_1610:
 435                 if (enable)
 436                         reg += OMAP1610_GPIO_SET_DATAOUT;
 437                 else
 438                         reg += OMAP1610_GPIO_CLEAR_DATAOUT;
 439                 l = 1 << gpio;
 440                 break;
 441 #endif
 442 #ifdef CONFIG_ARCH_OMAP730
 443         case METHOD_GPIO_730:
 444                 reg += OMAP730_GPIO_DATA_OUTPUT;
 445                 l = __raw_readl(reg);
 446                 if (enable)
 447                         l |= 1 << gpio;
 448                 else
 449                         l &= ~(1 << gpio);
 450                 break;
 451 #endif
 452 #ifdef CONFIG_ARCH_OMAP850
 453         case METHOD_GPIO_850:
 454                 reg += OMAP850_GPIO_DATA_OUTPUT;
 455                 l = __raw_readl(reg);
 456                 if (enable)
 457                         l |= 1 << gpio;
 458                 else
 459                         l &= ~(1 << gpio);
 460                 break;
 461 #endif
 462 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 463                         defined(CONFIG_ARCH_OMAP4)
 464         case METHOD_GPIO_24XX:
 465                 if (enable)
 466                         reg += OMAP24XX_GPIO_SETDATAOUT;
 467                 else
 468                         reg += OMAP24XX_GPIO_CLEARDATAOUT;
 469                 l = 1 << gpio;
 470                 break;
 471 #endif
 472         default:
 473                 WARN_ON(1);
 474                 return;
 475         }
 476         __raw_writel(l, reg);
 477 }
 478
 479 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
 480 {
 481         void __iomem *reg;
 482
 483         if (check_gpio(gpio) < 0)
 484                 return -EINVAL;
 485         reg = bank->base;
 486         switch (bank->method) {
 487 #ifdef CONFIG_ARCH_OMAP1
 488         case METHOD_MPUIO:
 489                 reg += OMAP_MPUIO_INPUT_LATCH;
 490                 break;
 491 #endif
 492 #ifdef CONFIG_ARCH_OMAP15XX
 493         case METHOD_GPIO_1510:
 494                 reg += OMAP1510_GPIO_DATA_INPUT;
 495                 break;
 496 #endif
 497 #ifdef CONFIG_ARCH_OMAP16XX
 498         case METHOD_GPIO_1610:
 499                 reg += OMAP1610_GPIO_DATAIN;
 500                 break;
 501 #endif
 502 #ifdef CONFIG_ARCH_OMAP730
 503         case METHOD_GPIO_730:
 504                 reg += OMAP730_GPIO_DATA_INPUT;
 505                 break;
 506 #endif
 507 #ifdef CONFIG_ARCH_OMAP850
 508         case METHOD_GPIO_850:
 509                 reg += OMAP850_GPIO_DATA_INPUT;
 510                 break;
 511 #endif
 512 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 513                         defined(CONFIG_ARCH_OMAP4)
 514         case METHOD_GPIO_24XX:
 515                 reg += OMAP24XX_GPIO_DATAIN;
 516                 break;
 517 #endif
 518         default:
 519                 return -EINVAL;
 520         }
 521         return (__raw_readl(reg)
 522                         & (1 << get_gpio_index(gpio))) != 0;
 523 }
 524
 525 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
 526 {
 527         void __iomem *reg;
 528
 529         if (check_gpio(gpio) < 0)
 530                 return -EINVAL;
 531         reg = bank->base;
 532
 533         switch (bank->method) {
 534 #ifdef CONFIG_ARCH_OMAP1
 535         case METHOD_MPUIO:
 536                 reg += OMAP_MPUIO_OUTPUT;
 537                 break;
 538 #endif
 539 #ifdef CONFIG_ARCH_OMAP15XX
 540         case METHOD_GPIO_1510:
 541                 reg += OMAP1510_GPIO_DATA_OUTPUT;
 542                 break;
 543 #endif
 544 #ifdef CONFIG_ARCH_OMAP16XX
 545         case METHOD_GPIO_1610:
 546                 reg += OMAP1610_GPIO_DATAOUT;
 547                 break;
 548 #endif
 549 #ifdef CONFIG_ARCH_OMAP730
 550         case METHOD_GPIO_730:
 551                 reg += OMAP730_GPIO_DATA_OUTPUT;
 552                 break;
 553 #endif
 554 #ifdef CONFIG_ARCH_OMAP850
 555         case METHOD_GPIO_850:
 556                 reg += OMAP850_GPIO_DATA_OUTPUT;
 557                 break;
 558 #endif
 559 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 560                 defined(CONFIG_ARCH_OMAP4)
 561         case METHOD_GPIO_24XX:
 562                 reg += OMAP24XX_GPIO_DATAOUT;
 563                 break;
 564 #endif
 565         default:
 566                 return -EINVAL;
 567         }
 568
 569         return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
 570 }
 571
 572 #define MOD_REG_BIT(reg, bit_mask, set) \
 573 do {    \
 574         int l = __raw_readl(base + reg); \
 575         if (set) l |= bit_mask; \
 576         else l &= ~bit_mask; \
 577         __raw_writel(l, base + reg); \
 578 } while(0)
 579
 580 void omap_set_gpio_debounce(int gpio, int enable)
 581 {
 582         struct gpio_bank *bank;
 583         void __iomem *reg;
 584         unsigned long flags;
 585         u32 val, l = 1 << get_gpio_index(gpio);
 586
 587         if (cpu_class_is_omap1())
 588                 return;
 589
 590         bank = get_gpio_bank(gpio);
 591         reg = bank->base;
 592         reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 593
 594         spin_lock_irqsave(&bank->lock, flags);
 595         val = __raw_readl(reg);
 596
 597         if (enable && !(val & l))
 598                 val |= l;
 599         else if (!enable && (val & l))
 600                 val &= ~l;
 601         else
 602                 goto done;
 603
 604         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 605                 if (enable)
 606                         clk_enable(bank->dbck);
 607                 else
 608                         clk_disable(bank->dbck);
 609         }
 610
 611         __raw_writel(val, reg);
 612 done:
 613         spin_unlock_irqrestore(&bank->lock, flags);
 614 }
 615 EXPORT_SYMBOL(omap_set_gpio_debounce);
 616
 617 void omap_set_gpio_debounce_time(int gpio, int enc_time)
 618 {
 619         struct gpio_bank *bank;
 620         void __iomem *reg;
 621
 622         if (cpu_class_is_omap1())
 623                 return;
 624
 625         bank = get_gpio_bank(gpio);
 626         reg = bank->base;
 627
 628         enc_time &= 0xff;
 629         reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
 630         __raw_writel(enc_time, reg);
 631 }
 632 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
 633
 634 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 635                                 defined(CONFIG_ARCH_OMAP4)
 636 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 637                                                 int trigger)
 638 {
 639         void __iomem *base = bank->base;
 640         u32 gpio_bit = 1 << gpio;
 641
 642         MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
 643                 trigger & IRQ_TYPE_LEVEL_LOW);
 644         MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
 645                 trigger & IRQ_TYPE_LEVEL_HIGH);
 646         MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
 647                 trigger & IRQ_TYPE_EDGE_RISING);
 648         MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
 649                 trigger & IRQ_TYPE_EDGE_FALLING);
 650
 651         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 652                 if (trigger != 0)
 653                         __raw_writel(1 << gpio, bank->base
 654                                         + OMAP24XX_GPIO_SETWKUENA);
 655                 else
 656                         __raw_writel(1 << gpio, bank->base
 657                                         + OMAP24XX_GPIO_CLEARWKUENA);
 658         } else {
 659                 if (trigger != 0)
 660                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 661                 else
 662                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 663         }
 664
 665         bank->level_mask =
 666                 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
 667                 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 668 }
 669 #endif
 670
 671 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 672 {
 673         void __iomem *reg = bank->base;
 674         u32 l = 0;
 675
 676         switch (bank->method) {
 677 #ifdef CONFIG_ARCH_OMAP1
 678         case METHOD_MPUIO:
 679                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
 680                 l = __raw_readl(reg);
 681                 if (trigger & IRQ_TYPE_EDGE_RISING)
 682                         l |= 1 << gpio;
 683                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 684                         l &= ~(1 << gpio);
 685                 else
 686                         goto bad;
 687                 break;
 688 #endif
 689 #ifdef CONFIG_ARCH_OMAP15XX
 690         case METHOD_GPIO_1510:
 691                 reg += OMAP1510_GPIO_INT_CONTROL;
 692                 l = __raw_readl(reg);
 693                 if (trigger & IRQ_TYPE_EDGE_RISING)
 694                         l |= 1 << gpio;
 695                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 696                         l &= ~(1 << gpio);
 697                 else
 698                         goto bad;
 699                 break;
 700 #endif
 701 #ifdef CONFIG_ARCH_OMAP16XX
 702         case METHOD_GPIO_1610:
 703                 if (gpio & 0x08)
 704                         reg += OMAP1610_GPIO_EDGE_CTRL2;
 705                 else
 706                         reg += OMAP1610_GPIO_EDGE_CTRL1;
 707                 gpio &= 0x07;
 708                 l = __raw_readl(reg);
 709                 l &= ~(3 << (gpio << 1));
 710                 if (trigger & IRQ_TYPE_EDGE_RISING)
 711                         l |= 2 << (gpio << 1);
 712                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 713                         l |= 1 << (gpio << 1);
 714                 if (trigger)
 715                         /* Enable wake-up during idle for dynamic tick */
 716                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
 717                 else
 718                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
 719                 break;
 720 #endif
 721 #ifdef CONFIG_ARCH_OMAP730
 722         case METHOD_GPIO_730:
 723                 reg += OMAP730_GPIO_INT_CONTROL;
 724                 l = __raw_readl(reg);
 725                 if (trigger & IRQ_TYPE_EDGE_RISING)
 726                         l |= 1 << gpio;
 727                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 728                         l &= ~(1 << gpio);
 729                 else
 730                         goto bad;
 731                 break;
 732 #endif
 733 #ifdef CONFIG_ARCH_OMAP850
 734         case METHOD_GPIO_850:
 735                 reg += OMAP850_GPIO_INT_CONTROL;
 736                 l = __raw_readl(reg);
 737                 if (trigger & IRQ_TYPE_EDGE_RISING)
 738                         l |= 1 << gpio;
 739                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 740                         l &= ~(1 << gpio);
 741                 else
 742                         goto bad;
 743                 break;
 744 #endif
 745 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 746                                 defined(CONFIG_ARCH_OMAP4)
 747         case METHOD_GPIO_24XX:
 748                 set_24xx_gpio_triggering(bank, gpio, trigger);
 749                 break;
 750 #endif
 751         default:
 752                 goto bad;
 753         }
 754         __raw_writel(l, reg);
 755         return 0;
 756 bad:
 757         return -EINVAL;
 758 }
 759
 760 static int gpio_irq_type(unsigned irq, unsigned type)
 761 {
 762         struct gpio_bank *bank;
 763         unsigned gpio;
 764         int retval;
 765         unsigned long flags;
 766
 767         if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
 768                 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
 769         else
 770                 gpio = irq - IH_GPIO_BASE;
 771
 772         if (check_gpio(gpio) < 0)
 773                 return -EINVAL;
 774
 775         if (type & ~IRQ_TYPE_SENSE_MASK)
 776                 return -EINVAL;
 777
 778         /* OMAP1 allows only only edge triggering */
 779         if (!cpu_class_is_omap2()
 780                         && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 781                 return -EINVAL;
 782
 783         bank = get_irq_chip_data(irq);
 784         spin_lock_irqsave(&bank->lock, flags);
 785         retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
 786         if (retval == 0) {
 787                 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 788                 irq_desc[irq].status |= type;
 789         }
 790         spin_unlock_irqrestore(&bank->lock, flags);
 791
 792         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 793                 __set_irq_handler_unlocked(irq, handle_level_irq);
 794         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 795                 __set_irq_handler_unlocked(irq, handle_edge_irq);
 796
 797         return retval;
 798 }
 799
 800 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 801 {
 802         void __iomem *reg = bank->base;
 803
 804         switch (bank->method) {
 805 #ifdef CONFIG_ARCH_OMAP1
 806         case METHOD_MPUIO:
 807                 /* MPUIO irqstatus is reset by reading the status register,
 808                  * so do nothing here */
 809                 return;
 810 #endif
 811 #ifdef CONFIG_ARCH_OMAP15XX
 812         case METHOD_GPIO_1510:
 813                 reg += OMAP1510_GPIO_INT_STATUS;
 814                 break;
 815 #endif
 816 #ifdef CONFIG_ARCH_OMAP16XX
 817         case METHOD_GPIO_1610:
 818                 reg += OMAP1610_GPIO_IRQSTATUS1;
 819                 break;
 820 #endif
 821 #ifdef CONFIG_ARCH_OMAP730
 822         case METHOD_GPIO_730:
 823                 reg += OMAP730_GPIO_INT_STATUS;
 824                 break;
 825 #endif
 826 #ifdef CONFIG_ARCH_OMAP850
 827         case METHOD_GPIO_850:
 828                 reg += OMAP850_GPIO_INT_STATUS;
 829                 break;
 830 #endif
 831 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 832                                 defined(CONFIG_ARCH_OMAP4)
 833         case METHOD_GPIO_24XX:
 834                 reg += OMAP24XX_GPIO_IRQSTATUS1;
 835                 break;
 836 #endif
 837         default:
 838                 WARN_ON(1);
 839                 return;
 840         }
 841         __raw_writel(gpio_mask, reg);
 842
 843         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 844 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 845         reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
 846         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 847                 __raw_writel(gpio_mask, reg);
 848
 849         /* Flush posted write for the irq status to avoid spurious interrupts */
 850         __raw_readl(reg);
 851 #endif
 852 }
 853
 854 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
 855 {
 856         _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
 857 }
 858
 859 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
 860 {
 861         void __iomem *reg = bank->base;
 862         int inv = 0;
 863         u32 l;
 864         u32 mask;
 865
 866         switch (bank->method) {
 867 #ifdef CONFIG_ARCH_OMAP1
 868         case METHOD_MPUIO:
 869                 reg += OMAP_MPUIO_GPIO_MASKIT;
 870                 mask = 0xffff;
 871                 inv = 1;
 872                 break;
 873 #endif
 874 #ifdef CONFIG_ARCH_OMAP15XX
 875         case METHOD_GPIO_1510:
 876                 reg += OMAP1510_GPIO_INT_MASK;
 877                 mask = 0xffff;
 878                 inv = 1;
 879                 break;
 880 #endif
 881 #ifdef CONFIG_ARCH_OMAP16XX
 882         case METHOD_GPIO_1610:
 883                 reg += OMAP1610_GPIO_IRQENABLE1;
 884                 mask = 0xffff;
 885                 break;
 886 #endif
 887 #ifdef CONFIG_ARCH_OMAP730
 888         case METHOD_GPIO_730:
 889                 reg += OMAP730_GPIO_INT_MASK;
 890                 mask = 0xffffffff;
 891                 inv = 1;
 892                 break;
 893 #endif
 894 #ifdef CONFIG_ARCH_OMAP850
 895         case METHOD_GPIO_850:
 896                 reg += OMAP850_GPIO_INT_MASK;
 897                 mask = 0xffffffff;
 898                 inv = 1;
 899                 break;
 900 #endif
 901 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 902                                 defined(CONFIG_ARCH_OMAP4)
 903         case METHOD_GPIO_24XX:
 904                 reg += OMAP24XX_GPIO_IRQENABLE1;
 905                 mask = 0xffffffff;
 906                 break;
 907 #endif
 908         default:
 909                 WARN_ON(1);
 910                 return 0;
 911         }
 912
 913         l = __raw_readl(reg);
 914         if (inv)
 915                 l = ~l;
 916         l &= mask;
 917         return l;
 918 }
 919
 920 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
 921 {
 922         void __iomem *reg = bank->base;
 923         u32 l;
 924
 925         switch (bank->method) {
 926 #ifdef CONFIG_ARCH_OMAP1
 927         case METHOD_MPUIO:
 928                 reg += OMAP_MPUIO_GPIO_MASKIT;
 929                 l = __raw_readl(reg);
 930                 if (enable)
 931                         l &= ~(gpio_mask);
 932                 else
 933                         l |= gpio_mask;
 934                 break;
 935 #endif
 936 #ifdef CONFIG_ARCH_OMAP15XX
 937         case METHOD_GPIO_1510:
 938                 reg += OMAP1510_GPIO_INT_MASK;
 939                 l = __raw_readl(reg);
 940                 if (enable)
 941                         l &= ~(gpio_mask);
 942                 else
 943                         l |= gpio_mask;
 944                 break;
 945 #endif
 946 #ifdef CONFIG_ARCH_OMAP16XX
 947         case METHOD_GPIO_1610:
 948                 if (enable)
 949                         reg += OMAP1610_GPIO_SET_IRQENABLE1;
 950                 else
 951                         reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
 952                 l = gpio_mask;
 953                 break;
 954 #endif
 955 #ifdef CONFIG_ARCH_OMAP730
 956         case METHOD_GPIO_730:
 957                 reg += OMAP730_GPIO_INT_MASK;
 958                 l = __raw_readl(reg);
 959                 if (enable)
 960                         l &= ~(gpio_mask);
 961                 else
 962                         l |= gpio_mask;
 963                 break;
 964 #endif
 965 #ifdef CONFIG_ARCH_OMAP850
 966         case METHOD_GPIO_850:
 967                 reg += OMAP850_GPIO_INT_MASK;
 968                 l = __raw_readl(reg);
 969                 if (enable)
 970                         l &= ~(gpio_mask);
 971                 else
 972                         l |= gpio_mask;
 973                 break;
 974 #endif
 975 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 976                 defined(CONFIG_ARCH_OMAP4)
 977         case METHOD_GPIO_24XX:
 978                 if (enable)
 979                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
 980                 else
 981                         reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
 982                 l = gpio_mask;
 983                 break;
 984 #endif
 985         default:
 986                 WARN_ON(1);
 987                 return;
 988         }
 989         __raw_writel(l, reg);
 990 }
 991
 992 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 993 {
 994         _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
 995 }
 996
 997 /*
 998  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 999  * 1510 does not seem to have a wake-up register. If JTAG is connected
1000  * to the target, system will wake up always on GPIO events. While
1001  * system is running all registered GPIO interrupts need to have wake-up
1002  * enabled. When system is suspended, only selected GPIO interrupts need
1003  * to have wake-up enabled.
1004  */
1005 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1006 {
1007         unsigned long flags;
1008
1009         switch (bank->method) {
1010 #ifdef CONFIG_ARCH_OMAP16XX
1011         case METHOD_MPUIO:
1012         case METHOD_GPIO_1610:
1013                 spin_lock_irqsave(&bank->lock, flags);
1014                 if (enable)
1015                         bank->suspend_wakeup |= (1 << gpio);
1016                 else
1017                         bank->suspend_wakeup &= ~(1 << gpio);
1018                 spin_unlock_irqrestore(&bank->lock, flags);
1019                 return 0;
1020 #endif
1021 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1022                                 defined(CONFIG_ARCH_OMAP4)
1023         case METHOD_GPIO_24XX:
1024                 if (bank->non_wakeup_gpios & (1 << gpio)) {
1025                         printk(KERN_ERR "Unable to modify wakeup on "
1026                                         "non-wakeup GPIO%d\n",
1027                                         (bank - gpio_bank) * 32 + gpio);
1028                         return -EINVAL;
1029                 }
1030                 spin_lock_irqsave(&bank->lock, flags);
1031                 if (enable)
1032                         bank->suspend_wakeup |= (1 << gpio);
1033                 else
1034                         bank->suspend_wakeup &= ~(1 << gpio);
1035                 spin_unlock_irqrestore(&bank->lock, flags);
1036                 return 0;
1037 #endif
1038         default:
1039                 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1040                        bank->method);
1041                 return -EINVAL;
1042         }
1043 }
1044
1045 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1046 {
1047         _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1048         _set_gpio_irqenable(bank, gpio, 0);
1049         _clear_gpio_irqstatus(bank, gpio);
1050         _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1051 }
1052
1053 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1054 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1055 {
1056         unsigned int gpio = irq - IH_GPIO_BASE;
1057         struct gpio_bank *bank;
1058         int retval;
1059
1060         if (check_gpio(gpio) < 0)
1061                 return -ENODEV;
1062         bank = get_irq_chip_data(irq);
1063         retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1064
1065         return retval;
1066 }
1067
1068 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1069 {
1070         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1071         unsigned long flags;
1072
1073         spin_lock_irqsave(&bank->lock, flags);
1074
1075         /* Set trigger to none. You need to enable the desired trigger with
1076          * request_irq() or set_irq_type().
1077          */
1078         _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1079
1080 #ifdef CONFIG_ARCH_OMAP15XX
1081         if (bank->method == METHOD_GPIO_1510) {
1082                 void __iomem *reg;
1083
1084                 /* Claim the pin for MPU */
1085                 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1086                 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1087         }
1088 #endif
1089         spin_unlock_irqrestore(&bank->lock, flags);
1090
1091         return 0;
1092 }
1093
1094 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1095 {
1096         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1097         unsigned long flags;
1098
1099         spin_lock_irqsave(&bank->lock, flags);
1100 #ifdef CONFIG_ARCH_OMAP16XX
1101         if (bank->method == METHOD_GPIO_1610) {
1102                 /* Disable wake-up during idle for dynamic tick */
1103                 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1104                 __raw_writel(1 << offset, reg);
1105         }
1106 #endif
1107 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1108                                 defined(CONFIG_ARCH_OMAP4)
1109         if (bank->method == METHOD_GPIO_24XX) {
1110                 /* Disable wake-up during idle for dynamic tick */
1111                 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1112                 __raw_writel(1 << offset, reg);
1113         }
1114 #endif
1115         _reset_gpio(bank, bank->chip.base + offset);
1116         spin_unlock_irqrestore(&bank->lock, flags);
1117 }
1118
1119 /*
1120  * We need to unmask the GPIO bank interrupt as soon as possible to
1121  * avoid missing GPIO interrupts for other lines in the bank.
1122  * Then we need to mask-read-clear-unmask the triggered GPIO lines
1123  * in the bank to avoid missing nested interrupts for a GPIO line.
1124  * If we wait to unmask individual GPIO lines in the bank after the
1125  * line's interrupt handler has been run, we may miss some nested
1126  * interrupts.
1127  */
1128 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1129 {
1130         void __iomem *isr_reg = NULL;
1131         u32 isr;
1132         unsigned int gpio_irq;
1133         struct gpio_bank *bank;
1134         u32 retrigger = 0;
1135         int unmasked = 0;
1136
1137         desc->chip->ack(irq);
1138
1139         bank = get_irq_data(irq);
1140 #ifdef CONFIG_ARCH_OMAP1
1141         if (bank->method == METHOD_MPUIO)
1142                 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1143 #endif
1144 #ifdef CONFIG_ARCH_OMAP15XX
1145         if (bank->method == METHOD_GPIO_1510)
1146                 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1147 #endif
1148 #if defined(CONFIG_ARCH_OMAP16XX)
1149         if (bank->method == METHOD_GPIO_1610)
1150                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1151 #endif
1152 #ifdef CONFIG_ARCH_OMAP730
1153         if (bank->method == METHOD_GPIO_730)
1154                 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1155 #endif
1156 #ifdef CONFIG_ARCH_OMAP850
1157         if (bank->method == METHOD_GPIO_850)
1158                 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1159 #endif
1160 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1161                                 defined(CONFIG_ARCH_OMAP4)
1162         if (bank->method == METHOD_GPIO_24XX)
1163                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1164 #endif
1165         while(1) {
1166                 u32 isr_saved, level_mask = 0;
1167                 u32 enabled;
1168
1169                 enabled = _get_gpio_irqbank_mask(bank);
1170                 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1171
1172                 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1173                         isr &= 0x0000ffff;
1174
1175                 if (cpu_class_is_omap2()) {
1176                         level_mask = bank->level_mask & enabled;
1177                 }
1178
1179                 /* clear edge sensitive interrupts before handler(s) are
1180                 called so that we don't miss any interrupt occurred while
1181                 executing them */
1182                 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1183                 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1184                 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1185
1186                 /* if there is only edge sensitive GPIO pin interrupts
1187                 configured, we could unmask GPIO bank interrupt immediately */
1188                 if (!level_mask && !unmasked) {
1189                         unmasked = 1;
1190                         desc->chip->unmask(irq);
1191                 }
1192
1193                 isr |= retrigger;
1194                 retrigger = 0;
1195                 if (!isr)
1196                         break;
1197
1198                 gpio_irq = bank->virtual_irq_start;
1199                 for (; isr != 0; isr >>= 1, gpio_irq++) {
1200                         if (!(isr & 1))
1201                                 continue;
1202
1203                         generic_handle_irq(gpio_irq);
1204                 }
1205         }
1206         /* if bank has any level sensitive GPIO pin interrupt
1207         configured, we must unmask the bank interrupt only after
1208         handler(s) are executed in order to avoid spurious bank
1209         interrupt */
1210         if (!unmasked)
1211                 desc->chip->unmask(irq);
1212
1213 }
1214
1215 static void gpio_irq_shutdown(unsigned int irq)
1216 {
1217         unsigned int gpio = irq - IH_GPIO_BASE;
1218         struct gpio_bank *bank = get_irq_chip_data(irq);
1219
1220         _reset_gpio(bank, gpio);
1221 }
1222
1223 static void gpio_ack_irq(unsigned int irq)
1224 {
1225         unsigned int gpio = irq - IH_GPIO_BASE;
1226         struct gpio_bank *bank = get_irq_chip_data(irq);
1227
1228         _clear_gpio_irqstatus(bank, gpio);
1229 }
1230
1231 static void gpio_mask_irq(unsigned int irq)
1232 {
1233         unsigned int gpio = irq - IH_GPIO_BASE;
1234         struct gpio_bank *bank = get_irq_chip_data(irq);
1235
1236         _set_gpio_irqenable(bank, gpio, 0);
1237         _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1238 }
1239
1240 static void gpio_unmask_irq(unsigned int irq)
1241 {
1242         unsigned int gpio = irq - IH_GPIO_BASE;
1243         struct gpio_bank *bank = get_irq_chip_data(irq);
1244         unsigned int irq_mask = 1 << get_gpio_index(gpio);
1245         struct irq_desc *desc = irq_to_desc(irq);
1246         u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1247
1248         if (trigger)
1249                 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1250
1251         /* For level-triggered GPIOs, the clearing must be done after
1252          * the HW source is cleared, thus after the handler has run */
1253         if (bank->level_mask & irq_mask) {
1254                 _set_gpio_irqenable(bank, gpio, 0);
1255                 _clear_gpio_irqstatus(bank, gpio);
1256         }
1257
1258         _set_gpio_irqenable(bank, gpio, 1);
1259 }
1260
1261 static struct irq_chip gpio_irq_chip = {
1262         .name           = "GPIO",
1263         .shutdown       = gpio_irq_shutdown,
1264         .ack            = gpio_ack_irq,
1265         .mask           = gpio_mask_irq,
1266         .unmask         = gpio_unmask_irq,
1267         .set_type       = gpio_irq_type,
1268         .set_wake       = gpio_wake_enable,
1269 };
1270
1271 /*---------------------------------------------------------------------*/
1272
1273 #ifdef CONFIG_ARCH_OMAP1
1274
1275 /* MPUIO uses the always-on 32k clock */
1276
1277 static void mpuio_ack_irq(unsigned int irq)
1278 {
1279         /* The ISR is reset automatically, so do nothing here. */
1280 }
1281
1282 static void mpuio_mask_irq(unsigned int irq)
1283 {
1284         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1285         struct gpio_bank *bank = get_irq_chip_data(irq);
1286
1287         _set_gpio_irqenable(bank, gpio, 0);
1288 }
1289
1290 static void mpuio_unmask_irq(unsigned int irq)
1291 {
1292         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1293         struct gpio_bank *bank = get_irq_chip_data(irq);
1294
1295         _set_gpio_irqenable(bank, gpio, 1);
1296 }
1297
1298 static struct irq_chip mpuio_irq_chip = {
1299         .name           = "MPUIO",
1300         .ack            = mpuio_ack_irq,
1301         .mask           = mpuio_mask_irq,
1302         .unmask         = mpuio_unmask_irq,
1303         .set_type       = gpio_irq_type,
1304 #ifdef CONFIG_ARCH_OMAP16XX
1305         /* REVISIT: assuming only 16xx supports MPUIO wake events */
1306         .set_wake       = gpio_wake_enable,
1307 #endif
1308 };
1309
1310
1311 #define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
1312
1313
1314 #ifdef CONFIG_ARCH_OMAP16XX
1315
1316 #include <linux/platform_device.h>
1317
1318 static int omap_mpuio_suspend_noirq(struct device *dev)
1319 {
1320         struct platform_device *pdev = to_platform_device(dev);
1321         struct gpio_bank        *bank = platform_get_drvdata(pdev);
1322         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1323         unsigned long           flags;
1324
1325         spin_lock_irqsave(&bank->lock, flags);
1326         bank->saved_wakeup = __raw_readl(mask_reg);
1327         __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1328         spin_unlock_irqrestore(&bank->lock, flags);
1329
1330         return 0;
1331 }
1332
1333 static int omap_mpuio_resume_noirq(struct device *dev)
1334 {
1335         struct platform_device *pdev = to_platform_device(dev);
1336         struct gpio_bank        *bank = platform_get_drvdata(pdev);
1337         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1338         unsigned long           flags;
1339
1340         spin_lock_irqsave(&bank->lock, flags);
1341         __raw_writel(bank->saved_wakeup, mask_reg);
1342         spin_unlock_irqrestore(&bank->lock, flags);
1343
1344         return 0;
1345 }
1346
1347 static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1348         .suspend_noirq = omap_mpuio_suspend_noirq,
1349         .resume_noirq = omap_mpuio_resume_noirq,
1350 };
1351
1352 /* use platform_driver for this, now that there's no longer any
1353  * point to sys_device (other than not disturbing old code).
1354  */
1355 static struct platform_driver omap_mpuio_driver = {
1356         .driver         = {
1357                 .name   = "mpuio",
1358                 .pm     = &omap_mpuio_dev_pm_ops,
1359         },
1360 };
1361
1362 static struct platform_device omap_mpuio_device = {
1363         .name           = "mpuio",
1364         .id             = -1,
1365         .dev = {
1366                 .driver = &omap_mpuio_driver.driver,
1367         }
1368         /* could list the /proc/iomem resources */
1369 };
1370
1371 static inline void mpuio_init(void)
1372 {
1373         platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1374
1375         if (platform_driver_register(&omap_mpuio_driver) == 0)
1376                 (void) platform_device_register(&omap_mpuio_device);
1377 }
1378
1379 #else
1380 static inline void mpuio_init(void) {}
1381 #endif  /* 16xx */
1382
1383 #else
1384
1385 extern struct irq_chip mpuio_irq_chip;
1386
1387 #define bank_is_mpuio(bank)     0
1388 static inline void mpuio_init(void) {}
1389
1390 #endif
1391
1392 /*---------------------------------------------------------------------*/
1393
1394 /* REVISIT these are stupid implementations!  replace by ones that
1395  * don't switch on METHOD_* and which mostly avoid spinlocks
1396  */
1397
1398 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1399 {
1400         struct gpio_bank *bank;
1401         unsigned long flags;
1402
1403         bank = container_of(chip, struct gpio_bank, chip);
1404         spin_lock_irqsave(&bank->lock, flags);
1405         _set_gpio_direction(bank, offset, 1);
1406         spin_unlock_irqrestore(&bank->lock, flags);
1407         return 0;
1408 }
1409
1410 static int gpio_is_input(struct gpio_bank *bank, int mask)
1411 {
1412         void __iomem *reg = bank->base;
1413
1414         switch (bank->method) {
1415         case METHOD_MPUIO:
1416                 reg += OMAP_MPUIO_IO_CNTL;
1417                 break;
1418         case METHOD_GPIO_1510:
1419                 reg += OMAP1510_GPIO_DIR_CONTROL;
1420                 break;
1421         case METHOD_GPIO_1610:
1422                 reg += OMAP1610_GPIO_DIRECTION;
1423                 break;
1424         case METHOD_GPIO_730:
1425                 reg += OMAP730_GPIO_DIR_CONTROL;
1426                 break;
1427         case METHOD_GPIO_850:
1428                 reg += OMAP850_GPIO_DIR_CONTROL;
1429                 break;
1430         case METHOD_GPIO_24XX:
1431                 reg += OMAP24XX_GPIO_OE;
1432                 break;
1433         }
1434         return __raw_readl(reg) & mask;
1435 }
1436
1437 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1438 {
1439         struct gpio_bank *bank;
1440         void __iomem *reg;
1441         int gpio;
1442         u32 mask;
1443
1444         gpio = chip->base + offset;
1445         bank = get_gpio_bank(gpio);
1446         reg = bank->base;
1447         mask = 1 << get_gpio_index(gpio);
1448
1449         if (gpio_is_input(bank, mask))
1450                 return _get_gpio_datain(bank, gpio);
1451         else
1452                 return _get_gpio_dataout(bank, gpio);
1453 }
1454
1455 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1456 {
1457         struct gpio_bank *bank;
1458         unsigned long flags;
1459
1460         bank = container_of(chip, struct gpio_bank, chip);
1461         spin_lock_irqsave(&bank->lock, flags);
1462         _set_gpio_dataout(bank, offset, value);
1463         _set_gpio_direction(bank, offset, 0);
1464         spin_unlock_irqrestore(&bank->lock, flags);
1465         return 0;
1466 }
1467
1468 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1469 {
1470         struct gpio_bank *bank;
1471         unsigned long flags;
1472
1473         bank = container_of(chip, struct gpio_bank, chip);
1474         spin_lock_irqsave(&bank->lock, flags);
1475         _set_gpio_dataout(bank, offset, value);
1476         spin_unlock_irqrestore(&bank->lock, flags);
1477 }
1478
1479 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1480 {
1481         struct gpio_bank *bank;
1482
1483         bank = container_of(chip, struct gpio_bank, chip);
1484         return bank->virtual_irq_start + offset;
1485 }
1486
1487 /*---------------------------------------------------------------------*/
1488
1489 static int initialized;
1490 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1491 static struct clk * gpio_ick;
1492 #endif
1493
1494 #if defined(CONFIG_ARCH_OMAP2)
1495 static struct clk * gpio_fck;
1496 #endif
1497
1498 #if defined(CONFIG_ARCH_OMAP2430)
1499 static struct clk * gpio5_ick;
1500 static struct clk * gpio5_fck;
1501 #endif
1502
1503 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1504 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1505 #endif
1506
1507 /* This lock class tells lockdep that GPIO irqs are in a different
1508  * category than their parents, so it won't report false recursion.
1509  */
1510 static struct lock_class_key gpio_lock_class;
1511
1512 static int __init _omap_gpio_init(void)
1513 {
1514         int i;
1515         int gpio = 0;
1516         struct gpio_bank *bank;
1517         char clk_name[11];
1518
1519         initialized = 1;
1520
1521 #if defined(CONFIG_ARCH_OMAP1)
1522         if (cpu_is_omap15xx()) {
1523                 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1524                 if (IS_ERR(gpio_ick))
1525                         printk("Could not get arm_gpio_ck\n");
1526                 else
1527                         clk_enable(gpio_ick);
1528         }
1529 #endif
1530 #if defined(CONFIG_ARCH_OMAP2)
1531         if (cpu_class_is_omap2()) {
1532                 gpio_ick = clk_get(NULL, "gpios_ick");
1533                 if (IS_ERR(gpio_ick))
1534                         printk("Could not get gpios_ick\n");
1535                 else
1536                         clk_enable(gpio_ick);
1537                 gpio_fck = clk_get(NULL, "gpios_fck");
1538                 if (IS_ERR(gpio_fck))
1539                         printk("Could not get gpios_fck\n");
1540                 else
1541                         clk_enable(gpio_fck);
1542
1543                 /*
1544                  * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1545                  */
1546 #if defined(CONFIG_ARCH_OMAP2430)
1547                 if (cpu_is_omap2430()) {
1548                         gpio5_ick = clk_get(NULL, "gpio5_ick");
1549                         if (IS_ERR(gpio5_ick))
1550                                 printk("Could not get gpio5_ick\n");
1551                         else
1552                                 clk_enable(gpio5_ick);
1553                         gpio5_fck = clk_get(NULL, "gpio5_fck");
1554                         if (IS_ERR(gpio5_fck))
1555                                 printk("Could not get gpio5_fck\n");
1556                         else
1557                                 clk_enable(gpio5_fck);
1558                 }
1559 #endif
1560         }
1561 #endif
1562
1563 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1564         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1565                 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1566                         sprintf(clk_name, "gpio%d_ick", i + 1);
1567                         gpio_iclks[i] = clk_get(NULL, clk_name);
1568                         if (IS_ERR(gpio_iclks[i]))
1569                                 printk(KERN_ERR "Could not get %s\n", clk_name);
1570                         else
1571                                 clk_enable(gpio_iclks[i]);
1572                 }
1573         }
1574 #endif
1575
1576
1577 #ifdef CONFIG_ARCH_OMAP15XX
1578         if (cpu_is_omap15xx()) {
1579                 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1580                 gpio_bank_count = 2;
1581                 gpio_bank = gpio_bank_1510;
1582         }
1583 #endif
1584 #if defined(CONFIG_ARCH_OMAP16XX)
1585         if (cpu_is_omap16xx()) {
1586                 u32 rev;
1587
1588                 gpio_bank_count = 5;
1589                 gpio_bank = gpio_bank_1610;
1590                 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1591                 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1592                        (rev >> 4) & 0x0f, rev & 0x0f);
1593         }
1594 #endif
1595 #ifdef CONFIG_ARCH_OMAP730
1596         if (cpu_is_omap730()) {
1597                 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1598                 gpio_bank_count = 7;
1599                 gpio_bank = gpio_bank_730;
1600         }
1601 #endif
1602 #ifdef CONFIG_ARCH_OMAP850
1603         if (cpu_is_omap850()) {
1604                 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1605                 gpio_bank_count = 7;
1606                 gpio_bank = gpio_bank_850;
1607         }
1608 #endif
1609
1610 #ifdef CONFIG_ARCH_OMAP24XX
1611         if (cpu_is_omap242x()) {
1612                 int rev;
1613
1614                 gpio_bank_count = 4;
1615                 gpio_bank = gpio_bank_242x;
1616                 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1617                 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1618                         (rev >> 4) & 0x0f, rev & 0x0f);
1619         }
1620         if (cpu_is_omap243x()) {
1621                 int rev;
1622
1623                 gpio_bank_count = 5;
1624                 gpio_bank = gpio_bank_243x;
1625                 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1626                 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1627                         (rev >> 4) & 0x0f, rev & 0x0f);
1628         }
1629 #endif
1630 #ifdef CONFIG_ARCH_OMAP34XX
1631         if (cpu_is_omap34xx()) {
1632                 int rev;
1633
1634                 gpio_bank_count = OMAP34XX_NR_GPIOS;
1635                 gpio_bank = gpio_bank_34xx;
1636                 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1637                 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1638                         (rev >> 4) & 0x0f, rev & 0x0f);
1639         }
1640 #endif
1641 #ifdef CONFIG_ARCH_OMAP4
1642         if (cpu_is_omap44xx()) {
1643                 int rev;
1644
1645                 gpio_bank_count = OMAP34XX_NR_GPIOS;
1646                 gpio_bank = gpio_bank_44xx;
1647                 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1648                 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1649                         (rev >> 4) & 0x0f, rev & 0x0f);
1650         }
1651 #endif
1652         for (i = 0; i < gpio_bank_count; i++) {
1653                 int j, gpio_count = 16;
1654
1655                 bank = &gpio_bank[i];
1656                 spin_lock_init(&bank->lock);
1657                 if (bank_is_mpuio(bank))
1658                         __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1659                 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1660                         __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1661                         __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1662                 }
1663                 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1664                         __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1665                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1666                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1667                 }
1668                 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1669                         __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1670                         __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1671
1672                         gpio_count = 32; /* 730 has 32-bit GPIOs */
1673                 }
1674
1675 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1676                                 defined(CONFIG_ARCH_OMAP4)
1677                 if (bank->method == METHOD_GPIO_24XX) {
1678                         static const u32 non_wakeup_gpios[] = {
1679                                 0xe203ffc0, 0x08700040
1680                         };
1681
1682                         __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1683                         __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1684                         __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1685                         __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1686
1687                         /* Initialize interface clock ungated, module enabled */
1688                         __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1689                         if (i < ARRAY_SIZE(non_wakeup_gpios))
1690                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1691                         gpio_count = 32;
1692                 }
1693 #endif
1694
1695                 /* REVISIT eventually switch from OMAP-specific gpio structs
1696                  * over to the generic ones
1697                  */
1698                 bank->chip.request = omap_gpio_request;
1699                 bank->chip.free = omap_gpio_free;
1700                 bank->chip.direction_input = gpio_input;
1701                 bank->chip.get = gpio_get;
1702                 bank->chip.direction_output = gpio_output;
1703                 bank->chip.set = gpio_set;
1704                 bank->chip.to_irq = gpio_2irq;
1705                 if (bank_is_mpuio(bank)) {
1706                         bank->chip.label = "mpuio";
1707 #ifdef CONFIG_ARCH_OMAP16XX
1708                         bank->chip.dev = &omap_mpuio_device.dev;
1709 #endif
1710                         bank->chip.base = OMAP_MPUIO(0);
1711                 } else {
1712                         bank->chip.label = "gpio";
1713                         bank->chip.base = gpio;
1714                         gpio += gpio_count;
1715                 }
1716                 bank->chip.ngpio = gpio_count;
1717
1718                 gpiochip_add(&bank->chip);
1719
1720                 for (j = bank->virtual_irq_start;
1721                      j < bank->virtual_irq_start + gpio_count; j++) {
1722                         lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1723                         set_irq_chip_data(j, bank);
1724                         if (bank_is_mpuio(bank))
1725                                 set_irq_chip(j, &mpuio_irq_chip);
1726                         else
1727                                 set_irq_chip(j, &gpio_irq_chip);
1728                         set_irq_handler(j, handle_simple_irq);
1729                         set_irq_flags(j, IRQF_VALID);
1730                 }
1731                 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1732                 set_irq_data(bank->irq, bank);
1733
1734                 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1735                         sprintf(clk_name, "gpio%d_dbck", i + 1);
1736                         bank->dbck = clk_get(NULL, clk_name);
1737                         if (IS_ERR(bank->dbck))
1738                                 printk(KERN_ERR "Could not get %s\n", clk_name);
1739                 }
1740         }
1741
1742         /* Enable system clock for GPIO module.
1743          * The CAM_CLK_CTRL *is* really the right place. */
1744         if (cpu_is_omap16xx())
1745                 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1746
1747         /* Enable autoidle for the OCP interface */
1748         if (cpu_is_omap24xx())
1749                 omap_writel(1 << 0, 0x48019010);
1750         if (cpu_is_omap34xx())
1751                 omap_writel(1 << 0, 0x48306814);
1752
1753         return 0;
1754 }
1755
1756 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1757                 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1758 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1759 {
1760         int i;
1761
1762         if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1763                 return 0;
1764
1765         for (i = 0; i < gpio_bank_count; i++) {
1766                 struct gpio_bank *bank = &gpio_bank[i];
1767                 void __iomem *wake_status;
1768                 void __iomem *wake_clear;
1769                 void __iomem *wake_set;
1770                 unsigned long flags;
1771
1772                 switch (bank->method) {
1773 #ifdef CONFIG_ARCH_OMAP16XX
1774                 case METHOD_GPIO_1610:
1775                         wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1776                         wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1777                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1778                         break;
1779 #endif
1780 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1781                                 defined(CONFIG_ARCH_OMAP4)
1782                 case METHOD_GPIO_24XX:
1783                         wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1784                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1785                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1786                         break;
1787 #endif
1788                 default:
1789                         continue;
1790                 }
1791
1792                 spin_lock_irqsave(&bank->lock, flags);
1793                 bank->saved_wakeup = __raw_readl(wake_status);
1794                 __raw_writel(0xffffffff, wake_clear);
1795                 __raw_writel(bank->suspend_wakeup, wake_set);
1796                 spin_unlock_irqrestore(&bank->lock, flags);
1797         }
1798
1799         return 0;
1800 }
1801
1802 static int omap_gpio_resume(struct sys_device *dev)
1803 {
1804         int i;
1805
1806         if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1807                 return 0;
1808
1809         for (i = 0; i < gpio_bank_count; i++) {
1810                 struct gpio_bank *bank = &gpio_bank[i];
1811                 void __iomem *wake_clear;
1812                 void __iomem *wake_set;
1813                 unsigned long flags;
1814
1815                 switch (bank->method) {
1816 #ifdef CONFIG_ARCH_OMAP16XX
1817                 case METHOD_GPIO_1610:
1818                         wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1819                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1820                         break;
1821 #endif
1822 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1823                         defined(CONFIG_ARCH_OMAP4)
1824                 case METHOD_GPIO_24XX:
1825                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1826                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1827                         break;
1828 #endif
1829                 default:
1830                         continue;
1831                 }
1832
1833                 spin_lock_irqsave(&bank->lock, flags);
1834                 __raw_writel(0xffffffff, wake_clear);
1835                 __raw_writel(bank->saved_wakeup, wake_set);
1836                 spin_unlock_irqrestore(&bank->lock, flags);
1837         }
1838
1839         return 0;
1840 }
1841
1842 static struct sysdev_class omap_gpio_sysclass = {
1843         .name           = "gpio",
1844         .suspend        = omap_gpio_suspend,
1845         .resume         = omap_gpio_resume,
1846 };
1847
1848 static struct sys_device omap_gpio_device = {
1849         .id             = 0,
1850         .cls            = &omap_gpio_sysclass,
1851 };
1852
1853 #endif
1854
1855 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1856                                 defined(CONFIG_ARCH_OMAP4)
1857
1858 static int workaround_enabled;
1859
1860 void omap2_gpio_prepare_for_retention(void)
1861 {
1862         int i, c = 0;
1863
1864         /* Remove triggering for all non-wakeup GPIOs.  Otherwise spurious
1865          * IRQs will be generated.  See OMAP2420 Errata item 1.101. */
1866         for (i = 0; i < gpio_bank_count; i++) {
1867                 struct gpio_bank *bank = &gpio_bank[i];
1868                 u32 l1, l2;
1869
1870                 if (!(bank->enabled_non_wakeup_gpios))
1871                         continue;
1872 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1873                                 defined(CONFIG_ARCH_OMAP4)
1874                 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1875                 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1876                 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1877 #endif
1878                 bank->saved_fallingdetect = l1;
1879                 bank->saved_risingdetect = l2;
1880                 l1 &= ~bank->enabled_non_wakeup_gpios;
1881                 l2 &= ~bank->enabled_non_wakeup_gpios;
1882 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1883                         defined(CONFIG_ARCH_OMAP4)
1884                 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1885                 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1886 #endif
1887                 c++;
1888         }
1889         if (!c) {
1890                 workaround_enabled = 0;
1891                 return;
1892         }
1893         workaround_enabled = 1;
1894 }
1895
1896 void omap2_gpio_resume_after_retention(void)
1897 {
1898         int i;
1899
1900         if (!workaround_enabled)
1901                 return;
1902         for (i = 0; i < gpio_bank_count; i++) {
1903                 struct gpio_bank *bank = &gpio_bank[i];
1904                 u32 l;
1905
1906                 if (!(bank->enabled_non_wakeup_gpios))
1907                         continue;
1908 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1909                         defined(CONFIG_ARCH_OMAP4)
1910                 __raw_writel(bank->saved_fallingdetect,
1911                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1912                 __raw_writel(bank->saved_risingdetect,
1913                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
1914 #endif
1915                 /* Check if any of the non-wakeup interrupt GPIOs have changed
1916                  * state.  If so, generate an IRQ by software.  This is
1917                  * horribly racy, but it's the best we can do to work around
1918                  * this silicon bug. */
1919 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1920                         defined(CONFIG_ARCH_OMAP4)
1921                 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1922 #endif
1923                 l ^= bank->saved_datain;
1924                 l &= bank->non_wakeup_gpios;
1925                 if (l) {
1926                         u32 old0, old1;
1927 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1928                         defined(CONFIG_ARCH_OMAP4)
1929                         old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1930                         old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1931                         __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1932                         __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1933                         __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1934                         __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1935 #endif
1936                 }
1937         }
1938
1939 }
1940
1941 #endif
1942
1943 /*
1944  * This may get called early from board specific init
1945  * for boards that have interrupts routed via FPGA.
1946  */
1947 int __init omap_gpio_init(void)
1948 {
1949         if (!initialized)
1950                 return _omap_gpio_init();
1951         else
1952                 return 0;
1953 }
1954
1955 static int __init omap_gpio_sysinit(void)
1956 {
1957         int ret = 0;
1958
1959         if (!initialized)
1960                 ret = _omap_gpio_init();
1961
1962         mpuio_init();
1963
1964 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1965                 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1966         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1967                 if (ret == 0) {
1968                         ret = sysdev_class_register(&omap_gpio_sysclass);
1969                         if (ret == 0)
1970                                 ret = sysdev_register(&omap_gpio_device);
1971                 }
1972         }
1973 #endif
1974
1975         return ret;
1976 }
1977
1978 arch_initcall(omap_gpio_sysinit);
1979
1980
1981 #ifdef  CONFIG_DEBUG_FS
1982
1983 #include <linux/debugfs.h>
1984 #include <linux/seq_file.h>
1985
1986 static int dbg_gpio_show(struct seq_file *s, void *unused)
1987 {
1988         unsigned        i, j, gpio;
1989
1990         for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1991                 struct gpio_bank        *bank = gpio_bank + i;
1992                 unsigned                bankwidth = 16;
1993                 u32                     mask = 1;
1994
1995                 if (bank_is_mpuio(bank))
1996                         gpio = OMAP_MPUIO(0);
1997                 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1998                                 cpu_is_omap850())
1999                         bankwidth = 32;
2000
2001                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2002                         unsigned        irq, value, is_in, irqstat;
2003                         const char      *label;
2004
2005                         label = gpiochip_is_requested(&bank->chip, j);
2006                         if (!label)
2007                                 continue;
2008
2009                         irq = bank->virtual_irq_start + j;
2010                         value = gpio_get_value(gpio);
2011                         is_in = gpio_is_input(bank, mask);
2012
2013                         if (bank_is_mpuio(bank))
2014                                 seq_printf(s, "MPUIO %2d ", j);
2015                         else
2016                                 seq_printf(s, "GPIO %3d ", gpio);
2017                         seq_printf(s, "(%-20.20s): %s %s",
2018                                         label,
2019                                         is_in ? "in " : "out",
2020                                         value ? "hi"  : "lo");
2021
2022 /* FIXME for at least omap2, show pullup/pulldown state */
2023
2024                         irqstat = irq_desc[irq].status;
2025 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||   \
2026                 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2027                         if (is_in && ((bank->suspend_wakeup & mask)
2028                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
2029                                 char    *trigger = NULL;
2030
2031                                 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2032                                 case IRQ_TYPE_EDGE_FALLING:
2033                                         trigger = "falling";
2034                                         break;
2035                                 case IRQ_TYPE_EDGE_RISING:
2036                                         trigger = "rising";
2037                                         break;
2038                                 case IRQ_TYPE_EDGE_BOTH:
2039                                         trigger = "bothedge";
2040                                         break;
2041                                 case IRQ_TYPE_LEVEL_LOW:
2042                                         trigger = "low";
2043                                         break;
2044                                 case IRQ_TYPE_LEVEL_HIGH:
2045                                         trigger = "high";
2046                                         break;
2047                                 case IRQ_TYPE_NONE:
2048                                         trigger = "(?)";
2049                                         break;
2050                                 }
2051                                 seq_printf(s, ", irq-%d %-8s%s",
2052                                                 irq, trigger,
2053                                                 (bank->suspend_wakeup & mask)
2054                                                         ? " wakeup" : "");
2055                         }
2056 #endif
2057                         seq_printf(s, "\n");
2058                 }
2059
2060                 if (bank_is_mpuio(bank)) {
2061                         seq_printf(s, "\n");
2062                         gpio = 0;
2063                 }
2064         }
2065         return 0;
2066 }
2067
2068 static int dbg_gpio_open(struct inode *inode, struct file *file)
2069 {
2070         return single_open(file, dbg_gpio_show, &inode->i_private);
2071 }
2072
2073 static const struct file_operations debug_fops = {
2074         .open           = dbg_gpio_open,
2075         .read           = seq_read,
2076         .llseek         = seq_lseek,
2077         .release        = single_release,
2078 };
2079
2080 static int __init omap_gpio_debuginit(void)
2081 {
2082         (void) debugfs_create_file("omap_gpio", S_IRUGO,
2083                                         NULL, NULL, &debug_fops);
2084         return 0;
2085 }
2086 late_initcall(omap_gpio_debuginit);
2087 #endif