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[ALSA] Remove xxx_t typedefs: ARM SA11xx-UDA1341
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / linux / i2o.h
blobd79c8a4bc4f854b872552e6a958d4a22291b7b92
1 /*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18 #ifndef _I2O_H
19 #define _I2O_H
20
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
22
23 #include <linux/i2o-dev.h>
24
25 /* How many different OSM's are we allowing */
26 #define I2O_MAX_DRIVERS 8
27
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/string.h>
31 #include <linux/slab.h>
32 #include <linux/workqueue.h> /* work_struct */
33
34 #include <asm/io.h>
35 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
36
37 /* message queue empty */
38 #define I2O_QUEUE_EMPTY 0xffffffff
39
40 /*
41 * Message structures
42 */
43 struct i2o_message {
44 union {
45 struct {
46 u8 version_offset;
47 u8 flags;
48 u16 size;
49 u32 target_tid:12;
50 u32 init_tid:12;
51 u32 function:8;
52 u32 icntxt; /* initiator context */
53 u32 tcntxt; /* transaction context */
54 } s;
55 u32 head[4];
56 } u;
57 /* List follows */
58 u32 body[0];
59 };
60
61 /*
62 * Each I2O device entity has one of these. There is one per device.
63 */
64 struct i2o_device {
65 i2o_lct_entry lct_data; /* Device LCT information */
66
67 struct i2o_controller *iop; /* Controlling IOP */
68 struct list_head list; /* node in IOP devices list */
69
70 struct device device;
71
72 struct semaphore lock; /* device lock */
73 };
74
75 /*
76 * Event structure provided to the event handling function
77 */
78 struct i2o_event {
79 struct work_struct work;
80 struct i2o_device *i2o_dev; /* I2O device pointer from which the
81 event reply was initiated */
82 u16 size; /* Size of data in 32-bit words */
83 u32 tcntxt; /* Transaction context used at
84 registration */
85 u32 event_indicator; /* Event indicator from reply */
86 u32 data[0]; /* Event data from reply */
87 };
88
89 /*
90 * I2O classes which could be handled by the OSM
91 */
92 struct i2o_class_id {
93 u16 class_id:12;
94 };
95
96 /*
97 * I2O driver structure for OSMs
98 */
99 struct i2o_driver {
100 char *name; /* OSM name */
101 int context; /* Low 8 bits of the transaction info */
102 struct i2o_class_id *classes; /* I2O classes that this OSM handles */
103
104 /* Message reply handler */
105 int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
106
107 /* Event handler */
108 void (*event) (struct i2o_event *);
109
110 struct workqueue_struct *event_queue; /* Event queue */
111
112 struct device_driver driver;
113
114 /* notification of changes */
115 void (*notify_controller_add) (struct i2o_controller *);
116 void (*notify_controller_remove) (struct i2o_controller *);
117 void (*notify_device_add) (struct i2o_device *);
118 void (*notify_device_remove) (struct i2o_device *);
119
120 struct semaphore lock;
121 };
122
123 /*
124 * Contains DMA mapped address information
125 */
126 struct i2o_dma {
127 void *virt;
128 dma_addr_t phys;
129 size_t len;
130 };
131
132 /*
133 * Contains IO mapped address information
134 */
135 struct i2o_io {
136 void __iomem *virt;
137 unsigned long phys;
138 unsigned long len;
139 };
140
141 /*
142 * Context queue entry, used for 32-bit context on 64-bit systems
143 */
144 struct i2o_context_list_element {
145 struct list_head list;
146 u32 context;
147 void *ptr;
148 unsigned long timestamp;
149 };
150
151 /*
152 * Each I2O controller has one of these objects
153 */
154 struct i2o_controller {
155 char name[16];
156 int unit;
157 int type;
158
159 struct pci_dev *pdev; /* PCI device */
160
161 unsigned int promise:1; /* Promise controller */
162 unsigned int adaptec:1; /* DPT / Adaptec controller */
163 unsigned int raptor:1; /* split bar */
164 unsigned int no_quiesce:1; /* dont quiesce before reset */
165 unsigned int short_req:1; /* use small block sizes */
166 unsigned int limit_sectors:1; /* limit number of sectors / request */
167 unsigned int pae_support:1; /* controller has 64-bit SGL support */
168
169 struct list_head devices; /* list of I2O devices */
170 struct list_head list; /* Controller list */
171
172 void __iomem *in_port; /* Inbout port address */
173 void __iomem *out_port; /* Outbound port address */
174 void __iomem *irq_status; /* Interrupt status register address */
175 void __iomem *irq_mask; /* Interrupt mask register address */
176
177 /* Dynamic LCT related data */
178
179 struct i2o_dma status; /* IOP status block */
180
181 struct i2o_dma hrt; /* HW Resource Table */
182 i2o_lct *lct; /* Logical Config Table */
183 struct i2o_dma dlct; /* Temp LCT */
184 struct semaphore lct_lock; /* Lock for LCT updates */
185 struct i2o_dma status_block; /* IOP status block */
186
187 struct i2o_io base; /* controller messaging unit */
188 struct i2o_io in_queue; /* inbound message queue Host->IOP */
189 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
190
191 unsigned int battery:1; /* Has a battery backup */
192 unsigned int io_alloc:1; /* An I/O resource was allocated */
193 unsigned int mem_alloc:1; /* A memory resource was allocated */
194
195 struct resource io_resource; /* I/O resource allocated to the IOP */
196 struct resource mem_resource; /* Mem resource allocated to the IOP */
197
198 struct device device;
199 struct class_device *classdev; /* I2O controller class device */
200 struct i2o_device *exec; /* Executive */
201 #if BITS_PER_LONG == 64
202 spinlock_t context_list_lock; /* lock for context_list */
203 atomic_t context_list_counter; /* needed for unique contexts */
204 struct list_head context_list; /* list of context id's
205 and pointers */
206 #endif
207 spinlock_t lock; /* lock for controller
208 configuration */
209
210 void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
211 };
212
213 /*
214 * I2O System table entry
215 *
216 * The system table contains information about all the IOPs in the
217 * system. It is sent to all IOPs so that they can create peer2peer
218 * connections between them.
219 */
220 struct i2o_sys_tbl_entry {
221 u16 org_id;
222 u16 reserved1;
223 u32 iop_id:12;
224 u32 reserved2:20;
225 u16 seg_num:12;
226 u16 i2o_version:4;
227 u8 iop_state;
228 u8 msg_type;
229 u16 frame_size;
230 u16 reserved3;
231 u32 last_changed;
232 u32 iop_capabilities;
233 u32 inbound_low;
234 u32 inbound_high;
235 };
236
237 struct i2o_sys_tbl {
238 u8 num_entries;
239 u8 version;
240 u16 reserved1;
241 u32 change_ind;
242 u32 reserved2;
243 u32 reserved3;
244 struct i2o_sys_tbl_entry iops[0];
245 };
246
247 extern struct list_head i2o_controllers;
248
249 /* Message functions */
250 static inline u32 i2o_msg_get(struct i2o_controller *,
251 struct i2o_message __iomem **);
252 extern u32 i2o_msg_get_wait(struct i2o_controller *,
253 struct i2o_message __iomem **, int);
254 static inline void i2o_msg_post(struct i2o_controller *, u32);
255 static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
256 unsigned long);
257 extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
258 struct i2o_dma *);
259 extern void i2o_msg_nop(struct i2o_controller *, u32);
260 static inline void i2o_flush_reply(struct i2o_controller *, u32);
261
262 /* IOP functions */
263 extern int i2o_status_get(struct i2o_controller *);
264
265 extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
266 u32);
267 extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
268 extern struct i2o_controller *i2o_find_iop(int);
269
270 /* Functions needed for handling 64-bit pointers in 32-bit context */
271 #if BITS_PER_LONG == 64
272 extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
273 extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
274 extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
275 extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);
276
277 static inline u32 i2o_ptr_low(void *ptr)
278 {
279 return (u32) (u64) ptr;
280 };
281
282 static inline u32 i2o_ptr_high(void *ptr)
283 {
284 return (u32) ((u64) ptr >> 32);
285 };
286
287 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
288 {
289 return (u32) (u64) dma_addr;
290 };
291
292 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
293 {
294 return (u32) ((u64) dma_addr >> 32);
295 };
296 #else
297 static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
298 {
299 return (u32) ptr;
300 };
301
302 static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
303 {
304 return (void *)context;
305 };
306
307 static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
308 {
309 return (u32) ptr;
310 };
311
312 static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
313 {
314 return (u32) ptr;
315 };
316
317 static inline u32 i2o_ptr_low(void *ptr)
318 {
319 return (u32) ptr;
320 };
321
322 static inline u32 i2o_ptr_high(void *ptr)
323 {
324 return 0;
325 };
326
327 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
328 {
329 return (u32) dma_addr;
330 };
331
332 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
333 {
334 return 0;
335 };
336 #endif
337
338 /**
339 * i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
340 * @c: I2O controller for which the calculation should be done
341 * @body_size: maximum body size used for message in 32-bit words.
342 *
343 * Return the maximum number of SG elements in a SG list.
344 */
345 static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
346 {
347 i2o_status_block *sb = c->status_block.virt;
348 u16 sg_count =
349 (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
350 body_size;
351
352 if (c->pae_support) {
353 /*
354 * for 64-bit a SG attribute element must be added and each
355 * SG element needs 12 bytes instead of 8.
356 */
357 sg_count -= 2;
358 sg_count /= 3;
359 } else
360 sg_count /= 2;
361
362 if (c->short_req && (sg_count > 8))
363 sg_count = 8;
364
365 return sg_count;
366 };
367
368 /**
369 * i2o_dma_map_single - Map pointer to controller and fill in I2O message.
370 * @c: I2O controller
371 * @ptr: pointer to the data which should be mapped
372 * @size: size of data in bytes
373 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
374 * @sg_ptr: pointer to the SG list inside the I2O message
375 *
376 * This function does all necessary DMA handling and also writes the I2O
377 * SGL elements into the I2O message. For details on DMA handling see also
378 * dma_map_single(). The pointer sg_ptr will only be set to the end of the
379 * SG list if the allocation was successful.
380 *
381 * Returns DMA address which must be checked for failures using
382 * dma_mapping_error().
383 */
384 static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
385 size_t size,
386 enum dma_data_direction direction,
387 u32 __iomem ** sg_ptr)
388 {
389 u32 sg_flags;
390 u32 __iomem *mptr = *sg_ptr;
391 dma_addr_t dma_addr;
392
393 switch (direction) {
394 case DMA_TO_DEVICE:
395 sg_flags = 0xd4000000;
396 break;
397 case DMA_FROM_DEVICE:
398 sg_flags = 0xd0000000;
399 break;
400 default:
401 return 0;
402 }
403
404 dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
405 if (!dma_mapping_error(dma_addr)) {
406 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
407 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
408 writel(0x7C020002, mptr++);
409 writel(PAGE_SIZE, mptr++);
410 }
411 #endif
412
413 writel(sg_flags | size, mptr++);
414 writel(i2o_dma_low(dma_addr), mptr++);
415 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
416 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
417 writel(i2o_dma_high(dma_addr), mptr++);
418 #endif
419 *sg_ptr = mptr;
420 }
421 return dma_addr;
422 };
423
424 /**
425 * i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
426 * @c: I2O controller
427 * @sg: SG list to be mapped
428 * @sg_count: number of elements in the SG list
429 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
430 * @sg_ptr: pointer to the SG list inside the I2O message
431 *
432 * This function does all necessary DMA handling and also writes the I2O
433 * SGL elements into the I2O message. For details on DMA handling see also
434 * dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
435 * list if the allocation was successful.
436 *
437 * Returns 0 on failure or 1 on success.
438 */
439 static inline int i2o_dma_map_sg(struct i2o_controller *c,
440 struct scatterlist *sg, int sg_count,
441 enum dma_data_direction direction,
442 u32 __iomem ** sg_ptr)
443 {
444 u32 sg_flags;
445 u32 __iomem *mptr = *sg_ptr;
446
447 switch (direction) {
448 case DMA_TO_DEVICE:
449 sg_flags = 0x14000000;
450 break;
451 case DMA_FROM_DEVICE:
452 sg_flags = 0x10000000;
453 break;
454 default:
455 return 0;
456 }
457
458 sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
459 if (!sg_count)
460 return 0;
461
462 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
463 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
464 writel(0x7C020002, mptr++);
465 writel(PAGE_SIZE, mptr++);
466 }
467 #endif
468
469 while (sg_count-- > 0) {
470 if (!sg_count)
471 sg_flags |= 0xC0000000;
472 writel(sg_flags | sg_dma_len(sg), mptr++);
473 writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
474 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
475 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
476 writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
477 #endif
478 sg++;
479 }
480 *sg_ptr = mptr;
481
482 return 1;
483 };
484
485 /**
486 * i2o_dma_alloc - Allocate DMA memory
487 * @dev: struct device pointer to the PCI device of the I2O controller
488 * @addr: i2o_dma struct which should get the DMA buffer
489 * @len: length of the new DMA memory
490 * @gfp_mask: GFP mask
491 *
492 * Allocate a coherent DMA memory and write the pointers into addr.
493 *
494 * Returns 0 on success or -ENOMEM on failure.
495 */
496 static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
497 size_t len, gfp_t gfp_mask)
498 {
499 struct pci_dev *pdev = to_pci_dev(dev);
500 int dma_64 = 0;
501
502 if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
503 dma_64 = 1;
504 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
505 return -ENOMEM;
506 }
507
508 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
509
510 if ((sizeof(dma_addr_t) > 4) && dma_64)
511 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
512 printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
513
514 if (!addr->virt)
515 return -ENOMEM;
516
517 memset(addr->virt, 0, len);
518 addr->len = len;
519
520 return 0;
521 };
522
523 /**
524 * i2o_dma_free - Free DMA memory
525 * @dev: struct device pointer to the PCI device of the I2O controller
526 * @addr: i2o_dma struct which contains the DMA buffer
527 *
528 * Free a coherent DMA memory and set virtual address of addr to NULL.
529 */
530 static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
531 {
532 if (addr->virt) {
533 if (addr->phys)
534 dma_free_coherent(dev, addr->len, addr->virt,
535 addr->phys);
536 else
537 kfree(addr->virt);
538 addr->virt = NULL;
539 }
540 };
541
542 /**
543 * i2o_dma_realloc - Realloc DMA memory
544 * @dev: struct device pointer to the PCI device of the I2O controller
545 * @addr: pointer to a i2o_dma struct DMA buffer
546 * @len: new length of memory
547 * @gfp_mask: GFP mask
548 *
549 * If there was something allocated in the addr, free it first. If len > 0
550 * than try to allocate it and write the addresses back to the addr
551 * structure. If len == 0 set the virtual address to NULL.
552 *
553 * Returns the 0 on success or negative error code on failure.
554 */
555 static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
556 size_t len, gfp_t gfp_mask)
557 {
558 i2o_dma_free(dev, addr);
559
560 if (len)
561 return i2o_dma_alloc(dev, addr, len, gfp_mask);
562
563 return 0;
564 };
565
566 /* I2O driver (OSM) functions */
567 extern int i2o_driver_register(struct i2o_driver *);
568 extern void i2o_driver_unregister(struct i2o_driver *);
569
570 /**
571 * i2o_driver_notify_controller_add - Send notification of added controller
572 * to a single I2O driver
573 *
574 * Send notification of added controller to a single registered driver.
575 */
576 static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv,
577 struct i2o_controller *c)
578 {
579 if (drv->notify_controller_add)
580 drv->notify_controller_add(c);
581 };
582
583 /**
584 * i2o_driver_notify_controller_remove - Send notification of removed
585 * controller to a single I2O driver
586 *
587 * Send notification of removed controller to a single registered driver.
588 */
589 static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv,
590 struct i2o_controller *c)
591 {
592 if (drv->notify_controller_remove)
593 drv->notify_controller_remove(c);
594 };
595
596 /**
597 * i2o_driver_notify_device_add - Send notification of added device to a
598 * single I2O driver
599 *
600 * Send notification of added device to a single registered driver.
601 */
602 static inline void i2o_driver_notify_device_add(struct i2o_driver *drv,
603 struct i2o_device *i2o_dev)
604 {
605 if (drv->notify_device_add)
606 drv->notify_device_add(i2o_dev);
607 };
608
609 /**
610 * i2o_driver_notify_device_remove - Send notification of removed device
611 * to a single I2O driver
612 *
613 * Send notification of removed device to a single registered driver.
614 */
615 static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv,
616 struct i2o_device *i2o_dev)
617 {
618 if (drv->notify_device_remove)
619 drv->notify_device_remove(i2o_dev);
620 };
621
622 extern void i2o_driver_notify_controller_add_all(struct i2o_controller *);
623 extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *);
624 extern void i2o_driver_notify_device_add_all(struct i2o_device *);
625 extern void i2o_driver_notify_device_remove_all(struct i2o_device *);
626
627 /* I2O device functions */
628 extern int i2o_device_claim(struct i2o_device *);
629 extern int i2o_device_claim_release(struct i2o_device *);
630
631 /* Exec OSM functions */
632 extern int i2o_exec_lct_get(struct i2o_controller *);
633
634 /* device / driver / kobject conversion functions */
635 #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
636 #define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
637 #define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
638 #define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
639
640 /**
641 * i2o_msg_get - obtain an I2O message from the IOP
642 * @c: I2O controller
643 * @msg: pointer to a I2O message pointer
644 *
645 * This function tries to get a message slot. If no message slot is
646 * available do not wait until one is availabe (see also i2o_msg_get_wait).
647 *
648 * On a success the message is returned and the pointer to the message is
649 * set in msg. The returned message is the physical page frame offset
650 * address from the read port (see the i2o spec). If no message is
651 * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
652 */
653 static inline u32 i2o_msg_get(struct i2o_controller *c,
654 struct i2o_message __iomem ** msg)
655 {
656 u32 m = readl(c->in_port);
657
658 if (m != I2O_QUEUE_EMPTY)
659 *msg = c->in_queue.virt + m;
660
661 return m;
662 };
663
664 /**
665 * i2o_msg_post - Post I2O message to I2O controller
666 * @c: I2O controller to which the message should be send
667 * @m: the message identifier
668 *
669 * Post the message to the I2O controller.
670 */
671 static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
672 {
673 writel(m, c->in_port);
674 };
675
676 /**
677 * i2o_msg_post_wait - Post and wait a message and wait until return
678 * @c: controller
679 * @m: message to post
680 * @timeout: time in seconds to wait
681 *
682 * This API allows an OSM to post a message and then be told whether or
683 * not the system received a successful reply. If the message times out
684 * then the value '-ETIMEDOUT' is returned.
685 *
686 * Returns 0 on success or negative error code on failure.
687 */
688 static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
689 unsigned long timeout)
690 {
691 return i2o_msg_post_wait_mem(c, m, timeout, NULL);
692 };
693
694 /**
695 * i2o_flush_reply - Flush reply from I2O controller
696 * @c: I2O controller
697 * @m: the message identifier
698 *
699 * The I2O controller must be informed that the reply message is not needed
700 * anymore. If you forget to flush the reply, the message frame can't be
701 * used by the controller anymore and is therefore lost.
702 */
703 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
704 {
705 writel(m, c->out_port);
706 };
707
708 /**
709 * i2o_out_to_virt - Turn an I2O message to a virtual address
710 * @c: controller
711 * @m: message engine value
712 *
713 * Turn a receive message from an I2O controller bus address into
714 * a Linux virtual address. The shared page frame is a linear block
715 * so we simply have to shift the offset. This function does not
716 * work for sender side messages as they are ioremap objects
717 * provided by the I2O controller.
718 */
719 static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
720 u32 m)
721 {
722 BUG_ON(m < c->out_queue.phys
723 || m >= c->out_queue.phys + c->out_queue.len);
724
725 return c->out_queue.virt + (m - c->out_queue.phys);
726 };
727
728 /**
729 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
730 * @c: controller
731 * @m: message engine value
732 *
733 * Turn a send message from an I2O controller bus address into
734 * a Linux virtual address. The shared page frame is a linear block
735 * so we simply have to shift the offset. This function does not
736 * work for receive side messages as they are kmalloc objects
737 * in a different pool.
738 */
739 static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
740 i2o_controller *c,
741 u32 m)
742 {
743 return c->in_queue.virt + m;
744 };
745
746 /*
747 * Endian handling wrapped into the macro - keeps the core code
748 * cleaner.
749 */
750
751 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
752
753 extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int);
754 extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int,
755 void *, int);
756
757 /* debugging and troubleshooting/diagnostic helpers. */
758 #define osm_printk(level, format, arg...) \
759 printk(level "%s: " format, OSM_NAME , ## arg)
760
761 #ifdef DEBUG
762 #define osm_debug(format, arg...) \
763 osm_printk(KERN_DEBUG, format , ## arg)
764 #else
765 #define osm_debug(format, arg...) \
766 do { } while (0)
767 #endif
768
769 #define osm_err(format, arg...) \
770 osm_printk(KERN_ERR, format , ## arg)
771 #define osm_info(format, arg...) \
772 osm_printk(KERN_INFO, format , ## arg)
773 #define osm_warn(format, arg...) \
774 osm_printk(KERN_WARNING, format , ## arg)
775
776 /* debugging functions */
777 extern void i2o_report_status(const char *, const char *, struct i2o_message *);
778 extern void i2o_dump_message(struct i2o_message *);
779 extern void i2o_dump_hrt(struct i2o_controller *c);
780 extern void i2o_debug_state(struct i2o_controller *c);
781
782 /*
783 * Cache strategies
784 */
785
786 /* The NULL strategy leaves everything up to the controller. This tends to be a
787 * pessimal but functional choice.
788 */
789 #define CACHE_NULL 0
790 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
791 * into the controller cache.
792 */
793 #define CACHE_PREFETCH 1
794 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
795 * into the controller cache. When an I/O is less <= 8K we assume its probably
796 * not sequential and don't prefetch (default)
797 */
798 #define CACHE_SMARTFETCH 2
799 /* Data is written to the cache and then out on to the disk. The I/O must be
800 * physically on the medium before the write is acknowledged (default without
801 * NVRAM)
802 */
803 #define CACHE_WRITETHROUGH 17
804 /* Data is written to the cache and then out on to the disk. The controller
805 * is permitted to write back the cache any way it wants. (default if battery
806 * backed NVRAM is present). It can be useful to set this for swap regardless of
807 * battery state.
808 */
809 #define CACHE_WRITEBACK 18
810 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
811 * write large I/O's directly to disk bypassing the cache to avoid the extra
812 * memory copy hits. Small writes are writeback cached
813 */
814 #define CACHE_SMARTBACK 19
815 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
816 * write large I/O's directly to disk bypassing the cache to avoid the extra
817 * memory copy hits. Small writes are writethrough cached. Suitable for devices
818 * lacking battery backup
819 */
820 #define CACHE_SMARTTHROUGH 20
821
822 /*
823 * Ioctl structures
824 */
825
826 #define BLKI2OGRSTRAT _IOR('2', 1, int)
827 #define BLKI2OGWSTRAT _IOR('2', 2, int)
828 #define BLKI2OSRSTRAT _IOW('2', 3, int)
829 #define BLKI2OSWSTRAT _IOW('2', 4, int)
830
831 /*
832 * I2O Function codes
833 */
834
835 /*
836 * Executive Class
837 */
838 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
839 #define I2O_CMD_ADAPTER_READ 0xB2
840 #define I2O_CMD_ADAPTER_RELEASE 0xB5
841 #define I2O_CMD_BIOS_INFO_SET 0xA5
842 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
843 #define I2O_CMD_CONFIG_VALIDATE 0xBB
844 #define I2O_CMD_CONN_SETUP 0xCA
845 #define I2O_CMD_DDM_DESTROY 0xB1
846 #define I2O_CMD_DDM_ENABLE 0xD5
847 #define I2O_CMD_DDM_QUIESCE 0xC7
848 #define I2O_CMD_DDM_RESET 0xD9
849 #define I2O_CMD_DDM_SUSPEND 0xAF
850 #define I2O_CMD_DEVICE_ASSIGN 0xB7
851 #define I2O_CMD_DEVICE_RELEASE 0xB9
852 #define I2O_CMD_HRT_GET 0xA8
853 #define I2O_CMD_ADAPTER_CLEAR 0xBE
854 #define I2O_CMD_ADAPTER_CONNECT 0xC9
855 #define I2O_CMD_ADAPTER_RESET 0xBD
856 #define I2O_CMD_LCT_NOTIFY 0xA2
857 #define I2O_CMD_OUTBOUND_INIT 0xA1
858 #define I2O_CMD_PATH_ENABLE 0xD3
859 #define I2O_CMD_PATH_QUIESCE 0xC5
860 #define I2O_CMD_PATH_RESET 0xD7
861 #define I2O_CMD_STATIC_MF_CREATE 0xDD
862 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
863 #define I2O_CMD_STATUS_GET 0xA0
864 #define I2O_CMD_SW_DOWNLOAD 0xA9
865 #define I2O_CMD_SW_UPLOAD 0xAB
866 #define I2O_CMD_SW_REMOVE 0xAD
867 #define I2O_CMD_SYS_ENABLE 0xD1
868 #define I2O_CMD_SYS_MODIFY 0xC1
869 #define I2O_CMD_SYS_QUIESCE 0xC3
870 #define I2O_CMD_SYS_TAB_SET 0xA3
871
872 /*
873 * Utility Class
874 */
875 #define I2O_CMD_UTIL_NOP 0x00
876 #define I2O_CMD_UTIL_ABORT 0x01
877 #define I2O_CMD_UTIL_CLAIM 0x09
878 #define I2O_CMD_UTIL_RELEASE 0x0B
879 #define I2O_CMD_UTIL_PARAMS_GET 0x06
880 #define I2O_CMD_UTIL_PARAMS_SET 0x05
881 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
882 #define I2O_CMD_UTIL_EVT_ACK 0x14
883 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
884 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
885 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
886 #define I2O_CMD_UTIL_LOCK 0x17
887 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
888 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
889
890 /*
891 * SCSI Host Bus Adapter Class
892 */
893 #define I2O_CMD_SCSI_EXEC 0x81
894 #define I2O_CMD_SCSI_ABORT 0x83
895 #define I2O_CMD_SCSI_BUSRESET 0x27
896
897 /*
898 * Bus Adapter Class
899 */
900 #define I2O_CMD_BUS_ADAPTER_RESET 0x85
901 #define I2O_CMD_BUS_RESET 0x87
902 #define I2O_CMD_BUS_SCAN 0x89
903 #define I2O_CMD_BUS_QUIESCE 0x8b
904
905 /*
906 * Random Block Storage Class
907 */
908 #define I2O_CMD_BLOCK_READ 0x30
909 #define I2O_CMD_BLOCK_WRITE 0x31
910 #define I2O_CMD_BLOCK_CFLUSH 0x37
911 #define I2O_CMD_BLOCK_MLOCK 0x49
912 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
913 #define I2O_CMD_BLOCK_MMOUNT 0x41
914 #define I2O_CMD_BLOCK_MEJECT 0x43
915 #define I2O_CMD_BLOCK_POWER 0x70
916
917 #define I2O_CMD_PRIVATE 0xFF
918
919 /* Command status values */
920
921 #define I2O_CMD_IN_PROGRESS 0x01
922 #define I2O_CMD_REJECTED 0x02
923 #define I2O_CMD_FAILED 0x03
924 #define I2O_CMD_COMPLETED 0x04
925
926 /* I2O API function return values */
927
928 #define I2O_RTN_NO_ERROR 0
929 #define I2O_RTN_NOT_INIT 1
930 #define I2O_RTN_FREE_Q_EMPTY 2
931 #define I2O_RTN_TCB_ERROR 3
932 #define I2O_RTN_TRANSACTION_ERROR 4
933 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
934 #define I2O_RTN_MALLOC_ERROR 6
935 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
936 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
937 #define I2O_RTN_NO_STATUS 9
938 #define I2O_RTN_NO_FIRM_VER 10
939 #define I2O_RTN_NO_LINK_SPEED 11
940
941 /* Reply message status defines for all messages */
942
943 #define I2O_REPLY_STATUS_SUCCESS 0x00
944 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
945 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
946 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
947 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
948 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
949 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
950 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
951 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
952 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
953 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
954 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
955
956 /* Status codes and Error Information for Parameter functions */
957
958 #define I2O_PARAMS_STATUS_SUCCESS 0x00
959 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
960 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
961 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
962 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
963 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
964 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
965 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
966 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
967 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
968 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
969 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
970 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
971 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
972 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
973 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
974 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
975
976 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
977 * messages: Table 3-2 Detailed Status Codes.*/
978
979 #define I2O_DSC_SUCCESS 0x0000
980 #define I2O_DSC_BAD_KEY 0x0002
981 #define I2O_DSC_TCL_ERROR 0x0003
982 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
983 #define I2O_DSC_NO_SUCH_PAGE 0x0005
984 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
985 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
986 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
987 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
988 #define I2O_DSC_DEVICE_LOCKED 0x000B
989 #define I2O_DSC_DEVICE_RESET 0x000C
990 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
991 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
992 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
993 #define I2O_DSC_INVALID_OFFSET 0x0010
994 #define I2O_DSC_INVALID_PARAMETER 0x0011
995 #define I2O_DSC_INVALID_REQUEST 0x0012
996 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
997 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
998 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
999 #define I2O_DSC_MISSING_PARAMETER 0x0016
1000 #define I2O_DSC_TIMEOUT 0x0017
1001 #define I2O_DSC_UNKNOWN_ERROR 0x0018
1002 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
1003 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
1004 #define I2O_DSC_DEVICE_BUSY 0x001B
1005 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
1006
1007 /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
1008 Status Codes.*/
1009
1010 #define I2O_BSA_DSC_SUCCESS 0x0000
1011 #define I2O_BSA_DSC_MEDIA_ERROR 0x0001
1012 #define I2O_BSA_DSC_ACCESS_ERROR 0x0002
1013 #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
1014 #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
1015 #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
1016 #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
1017 #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
1018 #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
1019 #define I2O_BSA_DSC_BUS_FAILURE 0x0009
1020 #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
1021 #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
1022 #define I2O_BSA_DSC_DEVICE_RESET 0x000C
1023 #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
1024 #define I2O_BSA_DSC_TIMEOUT 0x000E
1025
1026 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
1027
1028 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
1029 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
1030 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
1031 #define I2O_FSC_TRANSPORT_FAILURE 0x84
1032 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
1033 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
1034 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
1035 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
1036 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
1037 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
1038 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
1039 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
1040 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
1041 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
1042 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
1043 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
1044
1045 /* Device Claim Types */
1046 #define I2O_CLAIM_PRIMARY 0x01000000
1047 #define I2O_CLAIM_MANAGEMENT 0x02000000
1048 #define I2O_CLAIM_AUTHORIZED 0x03000000
1049 #define I2O_CLAIM_SECONDARY 0x04000000
1050
1051 /* Message header defines for VersionOffset */
1052 #define I2OVER15 0x0001
1053 #define I2OVER20 0x0002
1054
1055 /* Default is 1.5 */
1056 #define I2OVERSION I2OVER15
1057
1058 #define SGL_OFFSET_0 I2OVERSION
1059 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
1060 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
1061 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
1062 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
1063 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
1064 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
1065 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
1066 #define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
1067 #define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
1068 #define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
1069
1070 /* Transaction Reply Lists (TRL) Control Word structure */
1071 #define TRL_SINGLE_FIXED_LENGTH 0x00
1072 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
1073 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
1074
1075 /* msg header defines for MsgFlags */
1076 #define MSG_STATIC 0x0100
1077 #define MSG_64BIT_CNTXT 0x0200
1078 #define MSG_MULTI_TRANS 0x1000
1079 #define MSG_FAIL 0x2000
1080 #define MSG_FINAL 0x4000
1081 #define MSG_REPLY 0x8000
1082
1083 /* minimum size msg */
1084 #define THREE_WORD_MSG_SIZE 0x00030000
1085 #define FOUR_WORD_MSG_SIZE 0x00040000
1086 #define FIVE_WORD_MSG_SIZE 0x00050000
1087 #define SIX_WORD_MSG_SIZE 0x00060000
1088 #define SEVEN_WORD_MSG_SIZE 0x00070000
1089 #define EIGHT_WORD_MSG_SIZE 0x00080000
1090 #define NINE_WORD_MSG_SIZE 0x00090000
1091 #define TEN_WORD_MSG_SIZE 0x000A0000
1092 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
1093 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
1094
1095 /* special TID assignments */
1096 #define ADAPTER_TID 0
1097 #define HOST_TID 1
1098
1099 /* outbound queue defines */
1100 #define I2O_MAX_OUTBOUND_MSG_FRAMES 128
1101 #define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
1102
1103 #define I2O_POST_WAIT_OK 0
1104 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
1105
1106 #define I2O_CONTEXT_LIST_MIN_LENGTH 15
1107 #define I2O_CONTEXT_LIST_USED 0x01
1108 #define I2O_CONTEXT_LIST_DELETED 0x02
1109
1110 /* timeouts */
1111 #define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
1112 #define I2O_TIMEOUT_MESSAGE_GET 5
1113 #define I2O_TIMEOUT_RESET 30
1114 #define I2O_TIMEOUT_STATUS_GET 5
1115 #define I2O_TIMEOUT_LCT_GET 360
1116 #define I2O_TIMEOUT_SCSI_SCB_ABORT 240
1117
1118 /* retries */
1119 #define I2O_HRT_GET_TRIES 3
1120 #define I2O_LCT_GET_TRIES 3
1121
1122 /* defines for max_sectors and max_phys_segments */
1123 #define I2O_MAX_SECTORS 1024
1124 #define I2O_MAX_SECTORS_LIMITED 256
1125 #define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
1126
1127 #endif /* __KERNEL__ */
1128 #endif /* _I2O_H */
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