include/asm-powerpc/synch.h

   1 #ifndef _ASM_POWERPC_SYNCH_H
   2 #define _ASM_POWERPC_SYNCH_H
   3
   4 #include <linux/config.h>
   5
   6 #ifdef __powerpc64__
   7 #define __SUBARCH_HAS_LWSYNC
   8 #endif
   9
  10 #ifdef __SUBARCH_HAS_LWSYNC
  11 #    define LWSYNC      lwsync
  12 #else
  13 #    define LWSYNC      sync
  14 #endif
  15
  16
  17 /*
  18  * Arguably the bitops and *xchg operations don't imply any memory barrier
  19  * or SMP ordering, but in fact a lot of drivers expect them to imply
  20  * both, since they do on x86 cpus.
  21  */
  22 #ifdef CONFIG_SMP
  23 #define EIEIO_ON_SMP    "eieio\n"
  24 #define ISYNC_ON_SMP    "\n\tisync"
  25 #define SYNC_ON_SMP     __stringify(LWSYNC) "\n"
  26 #else
  27 #define EIEIO_ON_SMP
  28 #define ISYNC_ON_SMP
  29 #define SYNC_ON_SMP
  30 #endif
  31
  32 static inline void eieio(void)
  33 {
  34         __asm__ __volatile__ ("eieio" : : : "memory");
  35 }
  36
  37 static inline void isync(void)
  38 {
  39         __asm__ __volatile__ ("isync" : : : "memory");
  40 }
  41
  42 #ifdef CONFIG_SMP
  43 #define eieio_on_smp()  eieio()
  44 #define isync_on_smp()  isync()
  45 #else
  46 #define eieio_on_smp()  __asm__ __volatile__("": : :"memory")
  47 #define isync_on_smp()  __asm__ __volatile__("": : :"memory")
  48 #endif
  49
  50 #endif  /* _ASM_POWERPC_SYNCH_H */
  51