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dpt_i2o: Fix typo of EINVAL
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / et131x / et1310_phy.h
blob080656c6142c18135f08788c19a2196360607b06
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
12 * PHY.
13 *
14 *------------------------------------------------------------------------------
15 *
16 * SOFTWARE LICENSE
17 *
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
22 *
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
25 *
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
28 *
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
32 * distribution.
33 *
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 *
38 * . Neither the name of Agere Systems Inc. nor the names of the contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
41 *
42 * Disclaimer
43 *
44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
55 * DAMAGE.
56 *
57 */
58
59 #ifndef _ET1310_PHY_H_
60 #define _ET1310_PHY_H_
61
62 #include "et1310_address_map.h"
63
64 #define TRUEPHY_SUCCESS 0
65 #define TRUEPHY_FAILURE 1
66
67 /* MI Register Addresses */
68 #define MI_CONTROL_REG 0
69 #define MI_STATUS_REG 1
70 #define MI_PHY_IDENTIFIER_1_REG 2
71 #define MI_PHY_IDENTIFIER_2_REG 3
72 #define MI_AUTONEG_ADVERTISEMENT_REG 4
73 #define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
74 #define MI_AUTONEG_EXPANSION_REG 6
75 #define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7
76 #define MI_LINK_PARTNER_NEXT_PAGE_REG 8
77 #define MI_1000BASET_CONTROL_REG 9
78 #define MI_1000BASET_STATUS_REG 10
79 #define MI_RESERVED11_REG 11
80 #define MI_RESERVED12_REG 12
81 #define MI_RESERVED13_REG 13
82 #define MI_RESERVED14_REG 14
83 #define MI_EXTENDED_STATUS_REG 15
84
85 /* VMI Register Addresses */
86 #define VMI_RESERVED16_REG 16
87 #define VMI_RESERVED17_REG 17
88 #define VMI_RESERVED18_REG 18
89 #define VMI_LOOPBACK_CONTROL_REG 19
90 #define VMI_RESERVED20_REG 20
91 #define VMI_MI_CONTROL_REG 21
92 #define VMI_PHY_CONFIGURATION_REG 22
93 #define VMI_PHY_CONTROL_REG 23
94 #define VMI_INTERRUPT_MASK_REG 24
95 #define VMI_INTERRUPT_STATUS_REG 25
96 #define VMI_PHY_STATUS_REG 26
97 #define VMI_LED_CONTROL_1_REG 27
98 #define VMI_LED_CONTROL_2_REG 28
99 #define VMI_RESERVED29_REG 29
100 #define VMI_RESERVED30_REG 30
101 #define VMI_RESERVED31_REG 31
102
103 /* PHY Register Mapping(MI) Management Interface Regs */
104 typedef struct _MI_REGS_t {
105 u8 bmcr; /* Basic mode control reg(Reg 0x00) */
106 u8 bmsr; /* Basic mode status reg(Reg 0x01) */
107 u8 idr1; /* Phy identifier reg 1(Reg 0x02) */
108 u8 idr2; /* Phy identifier reg 2(Reg 0x03) */
109 u8 anar; /* Auto-Negotiation advertisement(Reg 0x04) */
110 u8 anlpar; /* Auto-Negotiation link Partner Ability(Reg 0x05) */
111 u8 aner; /* Auto-Negotiation expansion reg(Reg 0x06) */
112 u8 annptr; /* Auto-Negotiation next page transmit reg(Reg 0x07) */
113 u8 lpnpr; /* link partner next page reg(Reg 0x08) */
114 u8 gcr; /* Gigabit basic mode control reg(Reg 0x09) */
115 u8 gsr; /* Gigabit basic mode status reg(Reg 0x0A) */
116 u8 mi_res1[4]; /* Future use by MI working group(Reg 0x0B - 0x0E) */
117 u8 esr; /* Extended status reg(Reg 0x0F) */
118 u8 mi_res2[3]; /* Future use by MI working group(Reg 0x10 - 0x12) */
119 u8 loop_ctl; /* Loopback Control Reg(Reg 0x13) */
120 u8 mi_res3; /* Future use by MI working group(Reg 0x14) */
121 u8 mcr; /* MI Control Reg(Reg 0x15) */
122 u8 pcr; /* Configuration Reg(Reg 0x16) */
123 u8 phy_ctl; /* PHY Control Reg(Reg 0x17) */
124 u8 imr; /* Interrupt Mask Reg(Reg 0x18) */
125 u8 isr; /* Interrupt Status Reg(Reg 0x19) */
126 u8 psr; /* PHY Status Reg(Reg 0x1A) */
127 u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */
128 u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */
129 u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
130 } MI_REGS_t, *PMI_REGS_t;
131
132 /* MI Register 0: Basic mode control register */
133 typedef union _MI_BMCR_t {
134 u16 value;
135 struct {
136 #ifdef _BIT_FIELDS_HTOL
137 u16 reset:1; /* bit 15 */
138 u16 loopback:1; /* bit 14 */
139 u16 speed_sel:1; /* bit 13 */
140 u16 enable_autoneg:1; /* bit 12 */
141 u16 power_down:1; /* bit 11 */
142 u16 isolate:1; /* bit 10 */
143 u16 restart_autoneg:1; /* bit 9 */
144 u16 duplex_mode:1; /* bit 8 */
145 u16 col_test:1; /* bit 7 */
146 u16 speed_1000_sel:1; /* bit 6 */
147 u16 res1:6; /* bits 0-5 */
148 #else
149 u16 res1:6; /* bits 0-5 */
150 u16 speed_1000_sel:1; /* bit 6 */
151 u16 col_test:1; /* bit 7 */
152 u16 duplex_mode:1; /* bit 8 */
153 u16 restart_autoneg:1; /* bit 9 */
154 u16 isolate:1; /* bit 10 */
155 u16 power_down:1; /* bit 11 */
156 u16 enable_autoneg:1; /* bit 12 */
157 u16 speed_sel:1; /* bit 13 */
158 u16 loopback:1; /* bit 14 */
159 u16 reset:1; /* bit 15 */
160 #endif
161 } bits;
162 } MI_BMCR_t, *PMI_BMCR_t;
163
164 /* MI Register 1: Basic mode status register */
165 typedef union _MI_BMSR_t {
166 u16 value;
167 struct {
168 #ifdef _BIT_FIELDS_HTOL
169 u16 link_100T4:1; /* bit 15 */
170 u16 link_100fdx:1; /* bit 14 */
171 u16 link_100hdx:1; /* bit 13 */
172 u16 link_10fdx:1; /* bit 12 */
173 u16 link_10hdx:1; /* bit 11 */
174 u16 link_100T2fdx:1; /* bit 10 */
175 u16 link_100T2hdx:1; /* bit 9 */
176 u16 extend_status:1; /* bit 8 */
177 u16 res1:1; /* bit 7 */
178 u16 preamble_supress:1; /* bit 6 */
179 u16 auto_neg_complete:1; /* bit 5 */
180 u16 remote_fault:1; /* bit 4 */
181 u16 auto_neg_able:1; /* bit 3 */
182 u16 link_status:1; /* bit 2 */
183 u16 jabber_detect:1; /* bit 1 */
184 u16 ext_cap:1; /* bit 0 */
185 #else
186 u16 ext_cap:1; /* bit 0 */
187 u16 jabber_detect:1; /* bit 1 */
188 u16 link_status:1; /* bit 2 */
189 u16 auto_neg_able:1; /* bit 3 */
190 u16 remote_fault:1; /* bit 4 */
191 u16 auto_neg_complete:1; /* bit 5 */
192 u16 preamble_supress:1; /* bit 6 */
193 u16 res1:1; /* bit 7 */
194 u16 extend_status:1; /* bit 8 */
195 u16 link_100T2hdx:1; /* bit 9 */
196 u16 link_100T2fdx:1; /* bit 10 */
197 u16 link_10hdx:1; /* bit 11 */
198 u16 link_10fdx:1; /* bit 12 */
199 u16 link_100hdx:1; /* bit 13 */
200 u16 link_100fdx:1; /* bit 14 */
201 u16 link_100T4:1; /* bit 15 */
202 #endif
203 } bits;
204 } MI_BMSR_t, *PMI_BMSR_t;
205
206 /* MI Register 2: Physical Identifier 1 */
207 typedef union _MI_IDR1_t {
208 u16 value;
209 struct {
210 u16 ieee_address:16; /* 0x0282 default(bits 0-15) */
211 } bits;
212 } MI_IDR1_t, *PMI_IDR1_t;
213
214 /* MI Register 3: Physical Identifier 2 */
215 typedef union _MI_IDR2_t {
216 u16 value;
217 struct {
218 #ifdef _BIT_FIELDS_HTOL
219 u16 ieee_address:6; /* 111100 default(bits 10-15) */
220 u16 model_no:6; /* 000001 default(bits 4-9) */
221 u16 rev_no:4; /* 0010 default(bits 0-3) */
222 #else
223 u16 rev_no:4; /* 0010 default(bits 0-3) */
224 u16 model_no:6; /* 000001 default(bits 4-9) */
225 u16 ieee_address:6; /* 111100 default(bits 10-15) */
226 #endif
227 } bits;
228 } MI_IDR2_t, *PMI_IDR2_t;
229
230 /* MI Register 4: Auto-negotiation advertisement register */
231 typedef union _MI_ANAR_t {
232 u16 value;
233 struct {
234 #ifdef _BIT_FIELDS_HTOL
235 u16 np_indication:1; /* bit 15 */
236 u16 res2:1; /* bit 14 */
237 u16 remote_fault:1; /* bit 13 */
238 u16 res1:1; /* bit 12 */
239 u16 cap_asmpause:1; /* bit 11 */
240 u16 cap_pause:1; /* bit 10 */
241 u16 cap_100T4:1; /* bit 9 */
242 u16 cap_100fdx:1; /* bit 8 */
243 u16 cap_100hdx:1; /* bit 7 */
244 u16 cap_10fdx:1; /* bit 6 */
245 u16 cap_10hdx:1; /* bit 5 */
246 u16 selector:5; /* bits 0-4 */
247 #else
248 u16 selector:5; /* bits 0-4 */
249 u16 cap_10hdx:1; /* bit 5 */
250 u16 cap_10fdx:1; /* bit 6 */
251 u16 cap_100hdx:1; /* bit 7 */
252 u16 cap_100fdx:1; /* bit 8 */
253 u16 cap_100T4:1; /* bit 9 */
254 u16 cap_pause:1; /* bit 10 */
255 u16 cap_asmpause:1; /* bit 11 */
256 u16 res1:1; /* bit 12 */
257 u16 remote_fault:1; /* bit 13 */
258 u16 res2:1; /* bit 14 */
259 u16 np_indication:1; /* bit 15 */
260 #endif
261 } bits;
262 } MI_ANAR_t, *PMI_ANAR_t;
263
264 /* MI Register 5: Auto-negotiation link partner advertisement register */
265 typedef struct _MI_ANLPAR_t {
266 u16 value;
267 struct {
268 #ifdef _BIT_FIELDS_HTOL
269 u16 np_indication:1; /* bit 15 */
270 u16 acknowledge:1; /* bit 14 */
271 u16 remote_fault:1; /* bit 13 */
272 u16 res1:1; /* bit 12 */
273 u16 cap_asmpause:1; /* bit 11 */
274 u16 cap_pause:1; /* bit 10 */
275 u16 cap_100T4:1; /* bit 9 */
276 u16 cap_100fdx:1; /* bit 8 */
277 u16 cap_100hdx:1; /* bit 7 */
278 u16 cap_10fdx:1; /* bit 6 */
279 u16 cap_10hdx:1; /* bit 5 */
280 u16 selector:5; /* bits 0-4 */
281 #else
282 u16 selector:5; /* bits 0-4 */
283 u16 cap_10hdx:1; /* bit 5 */
284 u16 cap_10fdx:1; /* bit 6 */
285 u16 cap_100hdx:1; /* bit 7 */
286 u16 cap_100fdx:1; /* bit 8 */
287 u16 cap_100T4:1; /* bit 9 */
288 u16 cap_pause:1; /* bit 10 */
289 u16 cap_asmpause:1; /* bit 11 */
290 u16 res1:1; /* bit 12 */
291 u16 remote_fault:1; /* bit 13 */
292 u16 acknowledge:1; /* bit 14 */
293 u16 np_indication:1; /* bit 15 */
294 #endif
295 } bits;
296 } MI_ANLPAR_t, *PMI_ANLPAR_t;
297
298 /* MI Register 6: Auto-negotiation expansion register */
299 typedef union _MI_ANER_t {
300 u16 value;
301 struct {
302 #ifdef _BIT_FIELDS_HTOL
303 u16 res:11; /* bits 5-15 */
304 u16 pdf:1; /* bit 4 */
305 u16 lp_np_able:1; /* bit 3 */
306 u16 np_able:1; /* bit 2 */
307 u16 page_rx:1; /* bit 1 */
308 u16 lp_an_able:1; /* bit 0 */
309 #else
310 u16 lp_an_able:1; /* bit 0 */
311 u16 page_rx:1; /* bit 1 */
312 u16 np_able:1; /* bit 2 */
313 u16 lp_np_able:1; /* bit 3 */
314 u16 pdf:1; /* bit 4 */
315 u16 res:11; /* bits 5-15 */
316 #endif
317 } bits;
318 } MI_ANER_t, *PMI_ANER_t;
319
320 /* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
321 typedef union _MI_ANNPTR_t {
322 u16 value;
323 struct {
324 #ifdef _BIT_FIELDS_HTOL
325 u16 np:1; /* bit 15 */
326 u16 res1:1; /* bit 14 */
327 u16 msg_page:1; /* bit 13 */
328 u16 ack2:1; /* bit 12 */
329 u16 toggle:1; /* bit 11 */
330 u16 msg:11; /* bits 0-10 */
331 #else
332 u16 msg:11; /* bits 0-10 */
333 u16 toggle:1; /* bit 11 */
334 u16 ack2:1; /* bit 12 */
335 u16 msg_page:1; /* bit 13 */
336 u16 res1:1; /* bit 14 */
337 u16 np:1; /* bit 15 */
338 #endif
339 } bits;
340 } MI_ANNPTR_t, *PMI_ANNPTR_t;
341
342 /* MI Register 8: Link Partner Next Page Reg(0x08) */
343 typedef union _MI_LPNPR_t {
344 u16 value;
345 struct {
346 #ifdef _BIT_FIELDS_HTOL
347 u16 np:1; /* bit 15 */
348 u16 ack:1; /* bit 14 */
349 u16 msg_page:1; /* bit 13 */
350 u16 ack2:1; /* bit 12 */
351 u16 toggle:1; /* bit 11 */
352 u16 msg:11; /* bits 0-10 */
353 #else
354 u16 msg:11; /* bits 0-10 */
355 u16 toggle:1; /* bit 11 */
356 u16 ack2:1; /* bit 12 */
357 u16 msg_page:1; /* bit 13 */
358 u16 ack:1; /* bit 14 */
359 u16 np:1; /* bit 15 */
360 #endif
361 } bits;
362 } MI_LPNPR_t, *PMI_LPNPR_t;
363
364 /* MI Register 9: 1000BaseT Control Reg(0x09) */
365 typedef union _MI_GCR_t {
366 u16 value;
367 struct {
368 #ifdef _BIT_FIELDS_HTOL
369 u16 test_mode:3; /* bits 13-15 */
370 u16 ms_config_en:1; /* bit 12 */
371 u16 ms_value:1; /* bit 11 */
372 u16 port_type:1; /* bit 10 */
373 u16 link_1000fdx:1; /* bit 9 */
374 u16 link_1000hdx:1; /* bit 8 */
375 u16 res:8; /* bit 0-7 */
376 #else
377 u16 res:8; /* bit 0-7 */
378 u16 link_1000hdx:1; /* bit 8 */
379 u16 link_1000fdx:1; /* bit 9 */
380 u16 port_type:1; /* bit 10 */
381 u16 ms_value:1; /* bit 11 */
382 u16 ms_config_en:1; /* bit 12 */
383 u16 test_mode:3; /* bits 13-15 */
384 #endif
385 } bits;
386 } MI_GCR_t, *PMI_GCR_t;
387
388 /* MI Register 10: 1000BaseT Status Reg(0x0A) */
389 typedef union _MI_GSR_t {
390 u16 value;
391 struct {
392 #ifdef _BIT_FIELDS_HTOL
393 u16 ms_config_fault:1; /* bit 15 */
394 u16 ms_resolve:1; /* bit 14 */
395 u16 local_rx_status:1; /* bit 13 */
396 u16 remote_rx_status:1; /* bit 12 */
397 u16 link_1000fdx:1; /* bit 11 */
398 u16 link_1000hdx:1; /* bit 10 */
399 u16 res:2; /* bits 8-9 */
400 u16 idle_err_cnt:8; /* bits 0-7 */
401 #else
402 u16 idle_err_cnt:8; /* bits 0-7 */
403 u16 res:2; /* bits 8-9 */
404 u16 link_1000hdx:1; /* bit 10 */
405 u16 link_1000fdx:1; /* bit 11 */
406 u16 remote_rx_status:1; /* bit 12 */
407 u16 local_rx_status:1; /* bit 13 */
408 u16 ms_resolve:1; /* bit 14 */
409 u16 ms_config_fault:1; /* bit 15 */
410 #endif
411 } bits;
412 } MI_GSR_t, *PMI_GSR_t;
413
414 /* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
415 typedef union _MI_RES_t {
416 u16 value;
417 struct {
418 #ifdef _BIT_FIELDS_HTOL
419 u16 res15:1; /* bit 15 */
420 u16 res14:1; /* bit 14 */
421 u16 res13:1; /* bit 13 */
422 u16 res12:1; /* bit 12 */
423 u16 res11:1; /* bit 11 */
424 u16 res10:1; /* bit 10 */
425 u16 res9:1; /* bit 9 */
426 u16 res8:1; /* bit 8 */
427 u16 res7:1; /* bit 7 */
428 u16 res6:1; /* bit 6 */
429 u16 res5:1; /* bit 5 */
430 u16 res4:1; /* bit 4 */
431 u16 res3:1; /* bit 3 */
432 u16 res2:1; /* bit 2 */
433 u16 res1:1; /* bit 1 */
434 u16 res0:1; /* bit 0 */
435 #else
436 u16 res0:1; /* bit 0 */
437 u16 res1:1; /* bit 1 */
438 u16 res2:1; /* bit 2 */
439 u16 res3:1; /* bit 3 */
440 u16 res4:1; /* bit 4 */
441 u16 res5:1; /* bit 5 */
442 u16 res6:1; /* bit 6 */
443 u16 res7:1; /* bit 7 */
444 u16 res8:1; /* bit 8 */
445 u16 res9:1; /* bit 9 */
446 u16 res10:1; /* bit 10 */
447 u16 res11:1; /* bit 11 */
448 u16 res12:1; /* bit 12 */
449 u16 res13:1; /* bit 13 */
450 u16 res14:1; /* bit 14 */
451 u16 res15:1; /* bit 15 */
452 #endif
453 } bits;
454 } MI_RES_t, *PMI_RES_t;
455
456 /* MI Register 15: Extended status Reg(0x0F) */
457 typedef union _MI_ESR_t {
458 u16 value;
459 struct {
460 #ifdef _BIT_FIELDS_HTOL
461 u16 link_1000Xfdx:1; /* bit 15 */
462 u16 link_1000Xhdx:1; /* bit 14 */
463 u16 link_1000fdx:1; /* bit 13 */
464 u16 link_1000hdx:1; /* bit 12 */
465 u16 res:12; /* bit 0-11 */
466 #else
467 u16 res:12; /* bit 0-11 */
468 u16 link_1000hdx:1; /* bit 12 */
469 u16 link_1000fdx:1; /* bit 13 */
470 u16 link_1000Xhdx:1; /* bit 14 */
471 u16 link_1000Xfdx:1; /* bit 15 */
472 #endif
473 } bits;
474 } MI_ESR_t, *PMI_ESR_t;
475
476 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
477
478 /* MI Register 19: Loopback Control Reg(0x13) */
479 typedef union _MI_LCR_t {
480 u16 value;
481 struct {
482 #ifdef _BIT_FIELDS_HTOL
483 u16 mii_en:1; /* bit 15 */
484 u16 pcs_en:1; /* bit 14 */
485 u16 pmd_en:1; /* bit 13 */
486 u16 all_digital_en:1; /* bit 12 */
487 u16 replica_en:1; /* bit 11 */
488 u16 line_driver_en:1; /* bit 10 */
489 u16 res:10; /* bit 0-9 */
490 #else
491 u16 res:10; /* bit 0-9 */
492 u16 line_driver_en:1; /* bit 10 */
493 u16 replica_en:1; /* bit 11 */
494 u16 all_digital_en:1; /* bit 12 */
495 u16 pmd_en:1; /* bit 13 */
496 u16 pcs_en:1; /* bit 14 */
497 u16 mii_en:1; /* bit 15 */
498 #endif
499 } bits;
500 } MI_LCR_t, *PMI_LCR_t;
501
502 /* MI Register 20: Reserved Reg(0x14) */
503
504 /* MI Register 21: Management Interface Control Reg(0x15) */
505 typedef union _MI_MICR_t {
506 u16 value;
507 struct {
508 #ifdef _BIT_FIELDS_HTOL
509 u16 res1:5; /* bits 11-15 */
510 u16 mi_error_count:7; /* bits 4-10 */
511 u16 res2:1; /* bit 3 */
512 u16 ignore_10g_fr:1; /* bit 2 */
513 u16 res3:1; /* bit 1 */
514 u16 preamble_supress_en:1; /* bit 0 */
515 #else
516 u16 preamble_supress_en:1; /* bit 0 */
517 u16 res3:1; /* bit 1 */
518 u16 ignore_10g_fr:1; /* bit 2 */
519 u16 res2:1; /* bit 3 */
520 u16 mi_error_count:7; /* bits 4-10 */
521 u16 res1:5; /* bits 11-15 */
522 #endif
523 } bits;
524 } MI_MICR_t, *PMI_MICR_t;
525
526 /* MI Register 22: PHY Configuration Reg(0x16) */
527 typedef union _MI_PHY_CONFIG_t {
528 u16 value;
529 struct {
530 #ifdef _BIT_FIELDS_HTOL
531 u16 crs_tx_en:1; /* bit 15 */
532 u16 res1:1; /* bit 14 */
533 u16 tx_fifo_depth:2; /* bits 12-13 */
534 u16 speed_downshift:2; /* bits 10-11 */
535 u16 pbi_detect:1; /* bit 9 */
536 u16 tbi_rate:1; /* bit 8 */
537 u16 alternate_np:1; /* bit 7 */
538 u16 group_mdio_en:1; /* bit 6 */
539 u16 tx_clock_en:1; /* bit 5 */
540 u16 sys_clock_en:1; /* bit 4 */
541 u16 res2:1; /* bit 3 */
542 u16 mac_if_mode:3; /* bits 0-2 */
543 #else
544 u16 mac_if_mode:3; /* bits 0-2 */
545 u16 res2:1; /* bit 3 */
546 u16 sys_clock_en:1; /* bit 4 */
547 u16 tx_clock_en:1; /* bit 5 */
548 u16 group_mdio_en:1; /* bit 6 */
549 u16 alternate_np:1; /* bit 7 */
550 u16 tbi_rate:1; /* bit 8 */
551 u16 pbi_detect:1; /* bit 9 */
552 u16 speed_downshift:2; /* bits 10-11 */
553 u16 tx_fifo_depth:2; /* bits 12-13 */
554 u16 res1:1; /* bit 14 */
555 u16 crs_tx_en:1; /* bit 15 */
556 #endif
557 } bits;
558 } MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
559
560 /* MI Register 23: PHY CONTROL Reg(0x17) */
561 typedef union _MI_PHY_CONTROL_t {
562 u16 value;
563 struct {
564 #ifdef _BIT_FIELDS_HTOL
565 u16 res1:1; /* bit 15 */
566 u16 tdr_en:1; /* bit 14 */
567 u16 res2:1; /* bit 13 */
568 u16 downshift_attempts:2; /* bits 11-12 */
569 u16 res3:5; /* bit 6-10 */
570 u16 jabber_10baseT:1; /* bit 5 */
571 u16 sqe_10baseT:1; /* bit 4 */
572 u16 tp_loopback_10baseT:1; /* bit 3 */
573 u16 preamble_gen_en:1; /* bit 2 */
574 u16 res4:1; /* bit 1 */
575 u16 force_int:1; /* bit 0 */
576 #else
577 u16 force_int:1; /* bit 0 */
578 u16 res4:1; /* bit 1 */
579 u16 preamble_gen_en:1; /* bit 2 */
580 u16 tp_loopback_10baseT:1; /* bit 3 */
581 u16 sqe_10baseT:1; /* bit 4 */
582 u16 jabber_10baseT:1; /* bit 5 */
583 u16 res3:5; /* bit 6-10 */
584 u16 downshift_attempts:2; /* bits 11-12 */
585 u16 res2:1; /* bit 13 */
586 u16 tdr_en:1; /* bit 14 */
587 u16 res1:1; /* bit 15 */
588 #endif
589 } bits;
590 } MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
591
592 /* MI Register 24: Interrupt Mask Reg(0x18) */
593 typedef union _MI_IMR_t {
594 u16 value;
595 struct {
596 #ifdef _BIT_FIELDS_HTOL
597 u16 res1:6; /* bits 10-15 */
598 u16 mdio_sync_lost:1; /* bit 9 */
599 u16 autoneg_status:1; /* bit 8 */
600 u16 hi_bit_err:1; /* bit 7 */
601 u16 np_rx:1; /* bit 6 */
602 u16 err_counter_full:1; /* bit 5 */
603 u16 fifo_over_underflow:1; /* bit 4 */
604 u16 rx_status:1; /* bit 3 */
605 u16 link_status:1; /* bit 2 */
606 u16 automatic_speed:1; /* bit 1 */
607 u16 int_en:1; /* bit 0 */
608 #else
609 u16 int_en:1; /* bit 0 */
610 u16 automatic_speed:1; /* bit 1 */
611 u16 link_status:1; /* bit 2 */
612 u16 rx_status:1; /* bit 3 */
613 u16 fifo_over_underflow:1; /* bit 4 */
614 u16 err_counter_full:1; /* bit 5 */
615 u16 np_rx:1; /* bit 6 */
616 u16 hi_bit_err:1; /* bit 7 */
617 u16 autoneg_status:1; /* bit 8 */
618 u16 mdio_sync_lost:1; /* bit 9 */
619 u16 res1:6; /* bits 10-15 */
620 #endif
621 } bits;
622 } MI_IMR_t, *PMI_IMR_t;
623
624 /* MI Register 25: Interrupt Status Reg(0x19) */
625 typedef union _MI_ISR_t {
626 u16 value;
627 struct {
628 #ifdef _BIT_FIELDS_HTOL
629 u16 res1:6; /* bits 10-15 */
630 u16 mdio_sync_lost:1; /* bit 9 */
631 u16 autoneg_status:1; /* bit 8 */
632 u16 hi_bit_err:1; /* bit 7 */
633 u16 np_rx:1; /* bit 6 */
634 u16 err_counter_full:1; /* bit 5 */
635 u16 fifo_over_underflow:1; /* bit 4 */
636 u16 rx_status:1; /* bit 3 */
637 u16 link_status:1; /* bit 2 */
638 u16 automatic_speed:1; /* bit 1 */
639 u16 int_en:1; /* bit 0 */
640 #else
641 u16 int_en:1; /* bit 0 */
642 u16 automatic_speed:1; /* bit 1 */
643 u16 link_status:1; /* bit 2 */
644 u16 rx_status:1; /* bit 3 */
645 u16 fifo_over_underflow:1; /* bit 4 */
646 u16 err_counter_full:1; /* bit 5 */
647 u16 np_rx:1; /* bit 6 */
648 u16 hi_bit_err:1; /* bit 7 */
649 u16 autoneg_status:1; /* bit 8 */
650 u16 mdio_sync_lost:1; /* bit 9 */
651 u16 res1:6; /* bits 10-15 */
652 #endif
653 } bits;
654 } MI_ISR_t, *PMI_ISR_t;
655
656 /* MI Register 26: PHY Status Reg(0x1A) */
657 typedef union _MI_PSR_t {
658 u16 value;
659 struct {
660 #ifdef _BIT_FIELDS_HTOL
661 u16 res1:1; /* bit 15 */
662 u16 autoneg_fault:2; /* bit 13-14 */
663 u16 autoneg_status:1; /* bit 12 */
664 u16 mdi_x_status:1; /* bit 11 */
665 u16 polarity_status:1; /* bit 10 */
666 u16 speed_status:2; /* bits 8-9 */
667 u16 duplex_status:1; /* bit 7 */
668 u16 link_status:1; /* bit 6 */
669 u16 tx_status:1; /* bit 5 */
670 u16 rx_status:1; /* bit 4 */
671 u16 collision_status:1; /* bit 3 */
672 u16 autoneg_en:1; /* bit 2 */
673 u16 pause_en:1; /* bit 1 */
674 u16 asymmetric_dir:1; /* bit 0 */
675 #else
676 u16 asymmetric_dir:1; /* bit 0 */
677 u16 pause_en:1; /* bit 1 */
678 u16 autoneg_en:1; /* bit 2 */
679 u16 collision_status:1; /* bit 3 */
680 u16 rx_status:1; /* bit 4 */
681 u16 tx_status:1; /* bit 5 */
682 u16 link_status:1; /* bit 6 */
683 u16 duplex_status:1; /* bit 7 */
684 u16 speed_status:2; /* bits 8-9 */
685 u16 polarity_status:1; /* bit 10 */
686 u16 mdi_x_status:1; /* bit 11 */
687 u16 autoneg_status:1; /* bit 12 */
688 u16 autoneg_fault:2; /* bit 13-14 */
689 u16 res1:1; /* bit 15 */
690 #endif
691 } bits;
692 } MI_PSR_t, *PMI_PSR_t;
693
694 /* MI Register 27: LED Control Reg 1(0x1B) */
695 typedef union _MI_LCR1_t {
696 u16 value;
697 struct {
698 #ifdef _BIT_FIELDS_HTOL
699 u16 res1:2; /* bits 14-15 */
700 u16 led_dup_indicate:2; /* bits 12-13 */
701 u16 led_10baseT:2; /* bits 10-11 */
702 u16 led_collision:2; /* bits 8-9 */
703 u16 res2:2; /* bits 6-7 */
704 u16 res3:2; /* bits 4-5 */
705 u16 pulse_dur:2; /* bits 2-3 */
706 u16 pulse_stretch1:1; /* bit 1 */
707 u16 pulse_stretch0:1; /* bit 0 */
708 #else
709 u16 pulse_stretch0:1; /* bit 0 */
710 u16 pulse_stretch1:1; /* bit 1 */
711 u16 pulse_dur:2; /* bits 2-3 */
712 u16 res3:2; /* bits 4-5 */
713 u16 res2:2; /* bits 6-7 */
714 u16 led_collision:2; /* bits 8-9 */
715 u16 led_10baseT:2; /* bits 10-11 */
716 u16 led_dup_indicate:2; /* bits 12-13 */
717 u16 res1:2; /* bits 14-15 */
718 #endif
719 } bits;
720 } MI_LCR1_t, *PMI_LCR1_t;
721
722 /* MI Register 28: LED Control Reg 2(0x1C) */
723 typedef union _MI_LCR2_t {
724 u16 value;
725 struct {
726 #ifdef _BIT_FIELDS_HTOL
727 u16 led_link:4; /* bits 12-15 */
728 u16 led_tx_rx:4; /* bits 8-11 */
729 u16 led_100BaseTX:4; /* bits 4-7 */
730 u16 led_1000BaseT:4; /* bits 0-3 */
731 #else
732 u16 led_1000BaseT:4; /* bits 0-3 */
733 u16 led_100BaseTX:4; /* bits 4-7 */
734 u16 led_tx_rx:4; /* bits 8-11 */
735 u16 led_link:4; /* bits 12-15 */
736 #endif
737 } bits;
738 } MI_LCR2_t, *PMI_LCR2_t;
739
740 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
741
742 /* Forward declaration of the private adapter structure */
743 struct et131x_adapter;
744
745 /* OS Specific Functions*/
746 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *adapter);
747 void TPAL_SetPhy10FullDuplex(struct et131x_adapter *adapter);
748 void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter);
749 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *adapter);
750 void TPAL_SetPhy100FullDuplex(struct et131x_adapter *adapter);
751 void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter);
752 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *adapter);
753 void TPAL_SetPhyAutoNeg(struct et131x_adapter *adapter);
754
755 /* Prototypes for ET1310_phy.c */
756 int et131x_xcvr_find(struct et131x_adapter *adapter);
757 int et131x_setphy_normal(struct et131x_adapter *adapter);
758 int32_t PhyMiRead(struct et131x_adapter *adapter,
759 u8 xcvrAddr, u8 xcvrReg, u16 *value);
760
761 /* static inline function does not work because et131x_adapter is not always
762 * defined
763 */
764 #define MiRead(adapter, xcvrReg, value) \
765 PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
766
767 int32_t MiWrite(struct et131x_adapter *adapter,
768 u8 xcvReg, u16 value);
769 void et131x_Mii_check(struct et131x_adapter *pAdapter,
770 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints);
771
772 /* This last is not strictly required (the driver could call the TPAL
773 * version instead), but this sets the adapter up correctly, and calls the
774 * access routine indirectly. This protects the driver from changes in TPAL.
775 */
776 void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
777
778 /* Defines for PHY access routines */
779
780 /* Define bit operation flags */
781 #define TRUEPHY_BIT_CLEAR 0
782 #define TRUEPHY_BIT_SET 1
783 #define TRUEPHY_BIT_READ 2
784
785 /* Define read/write operation flags */
786 #ifndef TRUEPHY_READ
787 #define TRUEPHY_READ 0
788 #define TRUEPHY_WRITE 1
789 #define TRUEPHY_MASK 2
790 #endif
791
792 /* Define speeds */
793 #define TRUEPHY_SPEED_10MBPS 0
794 #define TRUEPHY_SPEED_100MBPS 1
795 #define TRUEPHY_SPEED_1000MBPS 2
796
797 /* Define duplex modes */
798 #define TRUEPHY_DUPLEX_HALF 0
799 #define TRUEPHY_DUPLEX_FULL 1
800
801 /* Define master/slave configuration values */
802 #define TRUEPHY_CFG_SLAVE 0
803 #define TRUEPHY_CFG_MASTER 1
804
805 /* Define MDI/MDI-X settings */
806 #define TRUEPHY_MDI 0
807 #define TRUEPHY_MDIX 1
808 #define TRUEPHY_AUTO_MDI_MDIX 2
809
810 /* Define 10Base-T link polarities */
811 #define TRUEPHY_POLARITY_NORMAL 0
812 #define TRUEPHY_POLARITY_INVERTED 1
813
814 /* Define auto-negotiation results */
815 #define TRUEPHY_ANEG_NOT_COMPLETE 0
816 #define TRUEPHY_ANEG_COMPLETE 1
817 #define TRUEPHY_ANEG_DISABLED 2
818
819 /* Define duplex advertisment flags */
820 #define TRUEPHY_ADV_DUPLEX_NONE 0x00
821 #define TRUEPHY_ADV_DUPLEX_FULL 0x01
822 #define TRUEPHY_ADV_DUPLEX_HALF 0x02
823 #define TRUEPHY_ADV_DUPLEX_BOTH \
824 (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
825
826 #define PHY_CONTROL 0x00 /* #define TRU_MI_CONTROL_REGISTER 0 */
827 #define PHY_STATUS 0x01 /* #define TRU_MI_STATUS_REGISTER 1 */
828 #define PHY_ID_1 0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2 */
829 #define PHY_ID_2 0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3 */
830 #define PHY_AUTO_ADVERTISEMENT 0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER 4 */
831 #define PHY_AUTO_LINK_PARTNER 0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5 */
832 #define PHY_AUTO_EXPANSION 0x06 /* #define TRU_MI_EXPANSION_REGISTER 6 */
833 #define PHY_AUTO_NEXT_PAGE_TX 0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7 */
834 #define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8 */
835 #define PHY_1000_CONTROL 0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER 9 */
836 #define PHY_1000_STATUS 0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER 10 */
837
838 #define PHY_EXTENDED_STATUS 0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER 15 */
839
840 /* some defines for modem registers that seem to be 'reserved' */
841 #define PHY_INDEX_REG 0x10
842 #define PHY_DATA_REG 0x11
843
844 #define PHY_MPHY_CONTROL_REG 0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER 18 */
845
846 #define PHY_LOOPBACK_CONTROL 0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19 */
847 /* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20 */
848 #define PHY_REGISTER_MGMT_CONTROL 0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21 */
849 #define PHY_CONFIG 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER 22 */
850 #define PHY_PHY_CONTROL 0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER 23 */
851 #define PHY_INTERRUPT_MASK 0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER 24 */
852 #define PHY_INTERRUPT_STATUS 0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER 25 */
853 #define PHY_PHY_STATUS 0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER 26 */
854 #define PHY_LED_1 0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER 27 */
855 #define PHY_LED_2 0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER 28 */
856 /* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */
857 /* #define TRU_VMI_TIMING_CONTROL_REGISTER */
858
859 /* Prototypes for PHY access routines */
860 void ET1310_PhyInit(struct et131x_adapter *adapter);
861 void ET1310_PhyReset(struct et131x_adapter *adapter);
862 void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down);
863 void ET1310_PhyAutoNeg(struct et131x_adapter *adapter, bool enable);
864 void ET1310_PhyDuplexMode(struct et131x_adapter *adapter, u16 duplex);
865 void ET1310_PhySpeedSelect(struct et131x_adapter *adapter, u16 speed);
866 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter,
867 u16 duplex);
868 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
869 u16 duplex);
870 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
871 u16 duplex);
872 void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
873 u8 *Link_status,
874 u32 *autoneg,
875 u32 *linkspeed,
876 u32 *duplex_mode,
877 u32 *mdi_mdix,
878 u32 *masterslave, u32 *polarity);
879 void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
880 u16 regnum, u16 andMask, u16 orMask);
881 void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
882 u16 action,
883 u16 regnum, u16 bitnum, u8 *value);
884
885 #endif /* _ET1310_PHY_H_ */
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