arch/arm/mach-pxa/pxa25x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa25x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA21x/25x/26x variants.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Since this file should be linked before any other machine specific file,
  15  * the __initcall() here will be executed first.  This serves as default
  16  * initialization stuff for PXA machines which can be overridden later if
  17  * need be.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/suspend.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/irq.h>
  26
  27 #include <asm/mach/map.h>
  28 #include <mach/hardware.h>
  29 #include <mach/irqs.h>
  30 #include <mach/gpio.h>
  31 #include <mach/pxa25x.h>
  32 #include <mach/reset.h>
  33 #include <mach/pm.h>
  34 #include <mach/dma.h>
  35 #include <mach/smemc.h>
  36
  37 #include "generic.h"
  38 #include "devices.h"
  39 #include "clock.h"
  40
  41 /*
  42  * Various clock factors driven by the CCCR register.
  43  */
  44
  45 /* Crystal Frequency to Memory Frequency Multiplier (L) */
  46 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
  47
  48 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
  49 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
  50
  51 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
  52 /* Note: we store the value N * 2 here. */
  53 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
  54
  55 /* Crystal clock */
  56 #define BASE_CLK        3686400
  57
  58 /*
  59  * Get the clock frequency as reflected by CCCR and the turbo flag.
  60  * We assume these values have been applied via a fcs.
  61  * If info is not 0 we also display the current settings.
  62  */
  63 unsigned int pxa25x_get_clk_frequency_khz(int info)
  64 {
  65         unsigned long cccr, turbo;
  66         unsigned int l, L, m, M, n2, N;
  67
  68         cccr = CCCR;
  69         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
  70
  71         l  =  L_clk_mult[(cccr >> 0) & 0x1f];
  72         m  =  M_clk_mult[(cccr >> 5) & 0x03];
  73         n2 = N2_clk_mult[(cccr >> 7) & 0x07];
  74
  75         L = l * BASE_CLK;
  76         M = m * L;
  77         N = n2 * M / 2;
  78
  79         if(info)
  80         {
  81                 L += 5000;
  82                 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
  83                         L / 1000000, (L % 1000000) / 10000, l );
  84                 M += 5000;
  85                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  86                         M / 1000000, (M % 1000000) / 10000, m );
  87                 N += 5000;
  88                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  89                         N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
  90                         (turbo & 1) ? "" : "in" );
  91         }
  92
  93         return (turbo & 1) ? (N/1000) : (M/1000);
  94 }
  95
  96 static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
  97 {
  98         return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
  99 }
 100
 101 static const struct clkops clk_pxa25x_mem_ops = {
 102         .enable         = clk_dummy_enable,
 103         .disable        = clk_dummy_disable,
 104         .getrate        = clk_pxa25x_mem_getrate,
 105 };
 106
 107 static const struct clkops clk_pxa25x_lcd_ops = {
 108         .enable         = clk_pxa2xx_cken_enable,
 109         .disable        = clk_pxa2xx_cken_disable,
 110         .getrate        = clk_pxa25x_mem_getrate,
 111 };
 112
 113 static unsigned long gpio12_config_32k[] = {
 114         GPIO12_32KHz,
 115 };
 116
 117 static unsigned long gpio12_config_gpio[] = {
 118         GPIO12_GPIO,
 119 };
 120
 121 static void clk_gpio12_enable(struct clk *clk)
 122 {
 123         pxa2xx_mfp_config(gpio12_config_32k, 1);
 124 }
 125
 126 static void clk_gpio12_disable(struct clk *clk)
 127 {
 128         pxa2xx_mfp_config(gpio12_config_gpio, 1);
 129 }
 130
 131 static const struct clkops clk_pxa25x_gpio12_ops = {
 132         .enable         = clk_gpio12_enable,
 133         .disable        = clk_gpio12_disable,
 134 };
 135
 136 static unsigned long gpio11_config_3m6[] = {
 137         GPIO11_3_6MHz,
 138 };
 139
 140 static unsigned long gpio11_config_gpio[] = {
 141         GPIO11_GPIO,
 142 };
 143
 144 static void clk_gpio11_enable(struct clk *clk)
 145 {
 146         pxa2xx_mfp_config(gpio11_config_3m6, 1);
 147 }
 148
 149 static void clk_gpio11_disable(struct clk *clk)
 150 {
 151         pxa2xx_mfp_config(gpio11_config_gpio, 1);
 152 }
 153
 154 static const struct clkops clk_pxa25x_gpio11_ops = {
 155         .enable         = clk_gpio11_enable,
 156         .disable        = clk_gpio11_disable,
 157 };
 158
 159 /*
 160  * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
 161  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
 162  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
 163  */
 164
 165 /*
 166  * PXA 2xx clock declarations.
 167  */
 168 static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
 169 static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
 170 static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
 171 static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
 172 static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
 173 static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
 174 static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
 175 static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
 176 static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
 177 static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
 178 static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
 179 static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
 180 static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
 181 static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
 182 static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
 183
 184 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
 185 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
 186 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
 187 static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
 188
 189 static struct clk_lookup pxa25x_clkregs[] = {
 190         INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
 191         INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
 192         INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
 193         INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
 194         INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
 195         INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
 196         INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
 197         INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
 198         INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
 199         INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
 200         INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
 201         INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
 202         INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
 203         INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
 204         INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
 205         INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
 206         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
 207         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
 208         INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
 209 };
 210
 211 static struct clk_lookup pxa25x_hwuart_clkreg =
 212         INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
 213
 214 #ifdef CONFIG_PM
 215
 216 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 217 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 218
 219 /*
 220  * List of global PXA peripheral registers to preserve.
 221  * More ones like CP and general purpose register values are preserved
 222  * with the stack pointer in sleep.S.
 223  */
 224 enum {
 225         SLEEP_SAVE_PSTR,
 226         SLEEP_SAVE_COUNT
 227 };
 228
 229
 230 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 231 {
 232         SAVE(PSTR);
 233 }
 234
 235 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 236 {
 237         RESTORE(PSTR);
 238 }
 239
 240 static void pxa25x_cpu_pm_enter(suspend_state_t state)
 241 {
 242         /* Clear reset status */
 243         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 244
 245         switch (state) {
 246         case PM_SUSPEND_MEM:
 247                 pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
 248                 break;
 249         }
 250 }
 251
 252 static int pxa25x_cpu_pm_prepare(void)
 253 {
 254         /* set resume return address */
 255         PSPR = virt_to_phys(cpu_resume);
 256         return 0;
 257 }
 258
 259 static void pxa25x_cpu_pm_finish(void)
 260 {
 261         /* ensure not to come back here if it wasn't intended */
 262         PSPR = 0;
 263 }
 264
 265 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
 266         .save_count     = SLEEP_SAVE_COUNT,
 267         .valid          = suspend_valid_only_mem,
 268         .save           = pxa25x_cpu_pm_save,
 269         .restore        = pxa25x_cpu_pm_restore,
 270         .enter          = pxa25x_cpu_pm_enter,
 271         .prepare        = pxa25x_cpu_pm_prepare,
 272         .finish         = pxa25x_cpu_pm_finish,
 273 };
 274
 275 static void __init pxa25x_init_pm(void)
 276 {
 277         pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
 278 }
 279 #else
 280 static inline void pxa25x_init_pm(void) {}
 281 #endif
 282
 283 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
 284  */
 285
 286 static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
 287 {
 288         int gpio = IRQ_TO_GPIO(d->irq);
 289         uint32_t mask = 0;
 290
 291         if (gpio >= 0 && gpio < 85)
 292                 return gpio_set_wake(gpio, on);
 293
 294         if (d->irq == IRQ_RTCAlrm) {
 295                 mask = PWER_RTC;
 296                 goto set_pwer;
 297         }
 298
 299         return -EINVAL;
 300
 301 set_pwer:
 302         if (on)
 303                 PWER |= mask;
 304         else
 305                 PWER &=~mask;
 306
 307         return 0;
 308 }
 309
 310 void __init pxa25x_init_irq(void)
 311 {
 312         pxa_init_irq(32, pxa25x_set_wake);
 313         pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
 314 }
 315
 316 #ifdef CONFIG_CPU_PXA26x
 317 void __init pxa26x_init_irq(void)
 318 {
 319         pxa_init_irq(32, pxa25x_set_wake);
 320         pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
 321 }
 322 #endif
 323
 324 static struct map_desc pxa25x_io_desc[] __initdata = {
 325         {       /* Mem Ctl */
 326                 .virtual        = SMEMC_VIRT,
 327                 .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
 328                 .length         = 0x00200000,
 329                 .type           = MT_DEVICE
 330         },
 331 };
 332
 333 void __init pxa25x_map_io(void)
 334 {
 335         pxa_map_io();
 336         iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
 337         pxa25x_get_clk_frequency_khz(1);
 338 }
 339
 340 static struct platform_device *pxa25x_devices[] __initdata = {
 341         &pxa25x_device_udc,
 342         &pxa_device_pmu,
 343         &pxa_device_i2s,
 344         &sa1100_device_rtc,
 345         &pxa25x_device_ssp,
 346         &pxa25x_device_nssp,
 347         &pxa25x_device_assp,
 348         &pxa25x_device_pwm0,
 349         &pxa25x_device_pwm1,
 350         &pxa_device_asoc_platform,
 351 };
 352
 353 static struct sys_device pxa25x_sysdev[] = {
 354         {
 355                 .cls    = &pxa_irq_sysclass,
 356         }, {
 357                 .cls    = &pxa2xx_mfp_sysclass,
 358         }, {
 359                 .cls    = &pxa_gpio_sysclass,
 360         }, {
 361                 .cls    = &pxa2xx_clock_sysclass,
 362         }
 363 };
 364
 365 static int __init pxa25x_init(void)
 366 {
 367         int i, ret = 0;
 368
 369         if (cpu_is_pxa25x()) {
 370
 371                 reset_status = RCSR;
 372
 373                 clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 374
 375                 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
 376                         return ret;
 377
 378                 pxa25x_init_pm();
 379
 380                 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
 381                         ret = sysdev_register(&pxa25x_sysdev[i]);
 382                         if (ret)
 383                                 pr_err("failed to register sysdev[%d]\n", i);
 384                 }
 385
 386                 ret = platform_add_devices(pxa25x_devices,
 387                                            ARRAY_SIZE(pxa25x_devices));
 388                 if (ret)
 389                         return ret;
 390         }
 391
 392         /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
 393         if (cpu_is_pxa255())
 394                 clkdev_add(&pxa25x_hwuart_clkreg);
 395
 396         return ret;
 397 }
 398
 399 postcore_initcall(pxa25x_init);