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staging: brcm80211: replace occurrences of __attribute__((packed))
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / brcmsmac / d11.h
blobe7ff0e6f28e0bd5a1641ec1c6e019ceb9f72fd1c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef _BRCM_D11_H_
18 #define _BRCM_D11_H_
19
20 #include <linux/ieee80211.h>
21
22 #include <defs.h>
23 #include "pub.h"
24 #include "dma.h"
25
26 #define BCN_TMPL_LEN 512 /* length of the BCN template area */
27
28 /* RX FIFO numbers */
29 #define RX_FIFO 0 /* data and ctl frames */
30 #define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
31
32 /* TX FIFO numbers using WME Access Classes */
33 #define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
34 #define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
35 #define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
36 #define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
37 #define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
38 #define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
39
40 /* Addr is byte address used by SW; offset is word offset used by uCode */
41
42 /* Per AC TX limit settings */
43 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
44 #define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
45
46 /* Legacy TX FIFO numbers */
47 #define TX_DATA_FIFO TX_AC_BE_FIFO
48 #define TX_CTL_FIFO TX_AC_VO_FIFO
49
50 #ifndef WL_RSSI_ANT_MAX
51 #define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
52 #elif WL_RSSI_ANT_MAX != 4
53 #error "WL_RSSI_ANT_MAX does not match"
54 #endif
55
56 struct intctrlregs {
57 u32 intstatus;
58 u32 intmask;
59 };
60
61 /* PIO structure,
62 * support two PIO format: 2 bytes access and 4 bytes access
63 * basic FIFO register set is per channel(transmit or receive)
64 * a pair of channels is defined for convenience
65 */
66 /* 2byte-wide pio register set per channel(xmt or rcv) */
67 struct pio2regs {
68 u16 fifocontrol;
69 u16 fifodata;
70 u16 fifofree; /* only valid in xmt channel, not in rcv channel */
71 u16 PAD;
72 };
73
74 /* a pair of pio channels(tx and rx) */
75 struct pio2regp {
76 pio2regs_t tx;
77 pio2regs_t rx;
78 };
79
80 /* 4byte-wide pio register set per channel(xmt or rcv) */
81 struct pio4regs {
82 u32 fifocontrol;
83 u32 fifodata;
84 };
85
86 /* a pair of pio channels(tx and rx) */
87 struct pio4regp {
88 pio4regs_t tx;
89 pio4regs_t rx;
90 };
91
92 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
93 * write: only low 16b-it half can be written
94 */
95 union pmqreg {
96 u32 pmqhostdata; /* read only! */
97 struct {
98 u16 pmqctrlstatus; /* read/write */
99 u16 PAD;
100 } w;
101 };
102
103 struct fifo64 {
104 dma64regs_t dmaxmt; /* dma tx */
105 pio4regs_t piotx; /* pio tx */
106 dma64regs_t dmarcv; /* dma rx */
107 pio4regs_t piorx; /* pio rx */
108 };
109
110 /*
111 * Host Interface Registers
112 */
113 struct d11regs {
114 /* Device Control ("semi-standard host registers") */
115 u32 PAD[3]; /* 0x0 - 0x8 */
116 u32 biststatus; /* 0xC */
117 u32 biststatus2; /* 0x10 */
118 u32 PAD; /* 0x14 */
119 u32 gptimer; /* 0x18 */
120 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
121
122 /* Interrupt Control *//* 0x20 */
123 intctrlregs_t intctrlregs[8];
124
125 u32 PAD[40]; /* 0x60 - 0xFC */
126
127 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
128
129 u32 PAD[4]; /* 0x110 - 0x11c */
130
131 u32 maccontrol; /* 0x120 */
132 u32 maccommand; /* 0x124 */
133 u32 macintstatus; /* 0x128 */
134 u32 macintmask; /* 0x12C */
135
136 /* Transmit Template Access */
137 u32 tplatewrptr; /* 0x130 */
138 u32 tplatewrdata; /* 0x134 */
139 u32 PAD[2]; /* 0x138 - 0x13C */
140
141 /* PMQ registers */
142 pmqreg_t pmqreg; /* 0x140 */
143 u32 pmqpatl; /* 0x144 */
144 u32 pmqpath; /* 0x148 */
145 u32 PAD; /* 0x14C */
146
147 u32 chnstatus; /* 0x150 */
148 u32 psmdebug; /* 0x154 */
149 u32 phydebug; /* 0x158 */
150 u32 machwcap; /* 0x15C */
151
152 /* Extended Internal Objects */
153 u32 objaddr; /* 0x160 */
154 u32 objdata; /* 0x164 */
155 u32 PAD[2]; /* 0x168 - 0x16c */
156
157 u32 frmtxstatus; /* 0x170 */
158 u32 frmtxstatus2; /* 0x174 */
159 u32 PAD[2]; /* 0x178 - 0x17c */
160
161 /* TSF host access */
162 u32 tsf_timerlow; /* 0x180 */
163 u32 tsf_timerhigh; /* 0x184 */
164 u32 tsf_cfprep; /* 0x188 */
165 u32 tsf_cfpstart; /* 0x18c */
166 u32 tsf_cfpmaxdur32; /* 0x190 */
167 u32 PAD[3]; /* 0x194 - 0x19c */
168
169 u32 maccontrol1; /* 0x1a0 */
170 u32 machwcap1; /* 0x1a4 */
171 u32 PAD[14]; /* 0x1a8 - 0x1dc */
172
173 /* Clock control and hardware workarounds*/
174 u32 clk_ctl_st; /* 0x1e0 */
175 u32 hw_war;
176 u32 d11_phypllctl; /* the phypll request/avail bits are
177 * moved to clk_ctl_st
178 */
179 u32 PAD[5]; /* 0x1ec - 0x1fc */
180
181 /* 0x200-0x37F dma/pio registers */
182 fifo64_t fifo64regs[6];
183
184 /* FIFO diagnostic port access */
185 dma32diag_t dmafifo; /* 0x380 - 0x38C */
186
187 u32 aggfifocnt; /* 0x390 */
188 u32 aggfifodata; /* 0x394 */
189 u32 PAD[16]; /* 0x398 - 0x3d4 */
190 u16 radioregaddr; /* 0x3d8 */
191 u16 radioregdata; /* 0x3da */
192
193 /*
194 * time delay between the change on rf disable input and
195 * radio shutdown
196 */
197 u32 rfdisabledly; /* 0x3DC */
198
199 /* PHY register access */
200 u16 phyversion; /* 0x3e0 - 0x0 */
201 u16 phybbconfig; /* 0x3e2 - 0x1 */
202 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
203 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
204 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
205 u16 phyrxstatus1; /* 0x3ea - 0x5 */
206 u16 phycrsth; /* 0x3ec - 0x6 */
207 u16 phytxerror; /* 0x3ee - 0x7 */
208 u16 phychannel; /* 0x3f0 - 0x8 */
209 u16 PAD[1]; /* 0x3f2 - 0x9 */
210 u16 phytest; /* 0x3f4 - 0xa */
211 u16 phy4waddr; /* 0x3f6 - 0xb */
212 u16 phy4wdatahi; /* 0x3f8 - 0xc */
213 u16 phy4wdatalo; /* 0x3fa - 0xd */
214 u16 phyregaddr; /* 0x3fc - 0xe */
215 u16 phyregdata; /* 0x3fe - 0xf */
216
217 /* IHR *//* 0x400 - 0x7FE */
218
219 /* RXE Block */
220 u16 PAD[3]; /* 0x400 - 0x406 */
221 u16 rcv_fifo_ctl; /* 0x406 */
222 u16 PAD; /* 0x408 - 0x40a */
223 u16 rcv_frm_cnt; /* 0x40a */
224 u16 PAD[4]; /* 0x40a - 0x414 */
225 u16 rssi; /* 0x414 */
226 u16 PAD[5]; /* 0x414 - 0x420 */
227 u16 rcm_ctl; /* 0x420 */
228 u16 rcm_mat_data; /* 0x422 */
229 u16 rcm_mat_mask; /* 0x424 */
230 u16 rcm_mat_dly; /* 0x426 */
231 u16 rcm_cond_mask_l; /* 0x428 */
232 u16 rcm_cond_mask_h; /* 0x42A */
233 u16 rcm_cond_dly; /* 0x42C */
234 u16 PAD[1]; /* 0x42E */
235 u16 ext_ihr_addr; /* 0x430 */
236 u16 ext_ihr_data; /* 0x432 */
237 u16 rxe_phyrs_2; /* 0x434 */
238 u16 rxe_phyrs_3; /* 0x436 */
239 u16 phy_mode; /* 0x438 */
240 u16 rcmta_ctl; /* 0x43a */
241 u16 rcmta_size; /* 0x43c */
242 u16 rcmta_addr0; /* 0x43e */
243 u16 rcmta_addr1; /* 0x440 */
244 u16 rcmta_addr2; /* 0x442 */
245 u16 PAD[30]; /* 0x444 - 0x480 */
246
247 /* PSM Block *//* 0x480 - 0x500 */
248
249 u16 PAD; /* 0x480 */
250 u16 psm_maccontrol_h; /* 0x482 */
251 u16 psm_macintstatus_l; /* 0x484 */
252 u16 psm_macintstatus_h; /* 0x486 */
253 u16 psm_macintmask_l; /* 0x488 */
254 u16 psm_macintmask_h; /* 0x48A */
255 u16 PAD; /* 0x48C */
256 u16 psm_maccommand; /* 0x48E */
257 u16 psm_brc; /* 0x490 */
258 u16 psm_phy_hdr_param; /* 0x492 */
259 u16 psm_postcard; /* 0x494 */
260 u16 psm_pcard_loc_l; /* 0x496 */
261 u16 psm_pcard_loc_h; /* 0x498 */
262 u16 psm_gpio_in; /* 0x49A */
263 u16 psm_gpio_out; /* 0x49C */
264 u16 psm_gpio_oe; /* 0x49E */
265
266 u16 psm_bred_0; /* 0x4A0 */
267 u16 psm_bred_1; /* 0x4A2 */
268 u16 psm_bred_2; /* 0x4A4 */
269 u16 psm_bred_3; /* 0x4A6 */
270 u16 psm_brcl_0; /* 0x4A8 */
271 u16 psm_brcl_1; /* 0x4AA */
272 u16 psm_brcl_2; /* 0x4AC */
273 u16 psm_brcl_3; /* 0x4AE */
274 u16 psm_brpo_0; /* 0x4B0 */
275 u16 psm_brpo_1; /* 0x4B2 */
276 u16 psm_brpo_2; /* 0x4B4 */
277 u16 psm_brpo_3; /* 0x4B6 */
278 u16 psm_brwk_0; /* 0x4B8 */
279 u16 psm_brwk_1; /* 0x4BA */
280 u16 psm_brwk_2; /* 0x4BC */
281 u16 psm_brwk_3; /* 0x4BE */
282
283 u16 psm_base_0; /* 0x4C0 */
284 u16 psm_base_1; /* 0x4C2 */
285 u16 psm_base_2; /* 0x4C4 */
286 u16 psm_base_3; /* 0x4C6 */
287 u16 psm_base_4; /* 0x4C8 */
288 u16 psm_base_5; /* 0x4CA */
289 u16 psm_base_6; /* 0x4CC */
290 u16 psm_pc_reg_0; /* 0x4CE */
291 u16 psm_pc_reg_1; /* 0x4D0 */
292 u16 psm_pc_reg_2; /* 0x4D2 */
293 u16 psm_pc_reg_3; /* 0x4D4 */
294 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
295 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
296 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
297
298 /* TXE0 Block *//* 0x500 - 0x580 */
299 u16 txe_ctl; /* 0x500 */
300 u16 txe_aux; /* 0x502 */
301 u16 txe_ts_loc; /* 0x504 */
302 u16 txe_time_out; /* 0x506 */
303 u16 txe_wm_0; /* 0x508 */
304 u16 txe_wm_1; /* 0x50A */
305 u16 txe_phyctl; /* 0x50C */
306 u16 txe_status; /* 0x50E */
307 u16 txe_mmplcp0; /* 0x510 */
308 u16 txe_mmplcp1; /* 0x512 */
309 u16 txe_phyctl1; /* 0x514 */
310
311 u16 PAD[0x05]; /* 0x510 - 0x51E */
312
313 /* Transmit control */
314 u16 xmtfifodef; /* 0x520 */
315 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
316 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
317 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
318 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
319 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
320 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
321
322 u16 PAD[0x09]; /* 0x52E - 0x53E */
323
324 u16 xmtfifocmd; /* 0x540 */
325 u16 xmtfifoflush; /* 0x542 */
326 u16 xmtfifothresh; /* 0x544 */
327 u16 xmtfifordy; /* 0x546 */
328 u16 xmtfifoprirdy; /* 0x548 */
329 u16 xmtfiforqpri; /* 0x54A */
330 u16 xmttplatetxptr; /* 0x54C */
331 u16 PAD; /* 0x54E */
332 u16 xmttplateptr; /* 0x550 */
333 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
334 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
335 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
336 u16 PAD[0x04]; /* 0x558 - 0x55E */
337 u16 xmttplatedatalo; /* 0x560 */
338 u16 xmttplatedatahi; /* 0x562 */
339
340 u16 PAD[2]; /* 0x564 - 0x566 */
341
342 u16 xmtsel; /* 0x568 */
343 u16 xmttxcnt; /* 0x56A */
344 u16 xmttxshmaddr; /* 0x56C */
345
346 u16 PAD[0x09]; /* 0x56E - 0x57E */
347
348 /* TXE1 Block */
349 u16 PAD[0x40]; /* 0x580 - 0x5FE */
350
351 /* TSF Block */
352 u16 PAD[0X02]; /* 0x600 - 0x602 */
353 u16 tsf_cfpstrt_l; /* 0x604 */
354 u16 tsf_cfpstrt_h; /* 0x606 */
355 u16 PAD[0X05]; /* 0x608 - 0x610 */
356 u16 tsf_cfppretbtt; /* 0x612 */
357 u16 PAD[0XD]; /* 0x614 - 0x62C */
358 u16 tsf_clk_frac_l; /* 0x62E */
359 u16 tsf_clk_frac_h; /* 0x630 */
360 u16 PAD[0X14]; /* 0x632 - 0x658 */
361 u16 tsf_random; /* 0x65A */
362 u16 PAD[0x05]; /* 0x65C - 0x664 */
363 /* GPTimer 2 registers */
364 u16 tsf_gpt2_stat; /* 0x666 */
365 u16 tsf_gpt2_ctr_l; /* 0x668 */
366 u16 tsf_gpt2_ctr_h; /* 0x66A */
367 u16 tsf_gpt2_val_l; /* 0x66C */
368 u16 tsf_gpt2_val_h; /* 0x66E */
369 u16 tsf_gptall_stat; /* 0x670 */
370 u16 PAD[0x07]; /* 0x672 - 0x67E */
371
372 /* IFS Block */
373 u16 ifs_sifs_rx_tx_tx; /* 0x680 */
374 u16 ifs_sifs_nav_tx; /* 0x682 */
375 u16 ifs_slot; /* 0x684 */
376 u16 PAD; /* 0x686 */
377 u16 ifs_ctl; /* 0x688 */
378 u16 PAD[0x3]; /* 0x68a - 0x68F */
379 u16 ifsstat; /* 0x690 */
380 u16 ifsmedbusyctl; /* 0x692 */
381 u16 iftxdur; /* 0x694 */
382 u16 PAD[0x3]; /* 0x696 - 0x69b */
383 /* EDCF support in dot11macs */
384 u16 ifs_aifsn; /* 0x69c */
385 u16 ifs_ctl1; /* 0x69e */
386
387 /* slow clock registers */
388 u16 scc_ctl; /* 0x6a0 */
389 u16 scc_timer_l; /* 0x6a2 */
390 u16 scc_timer_h; /* 0x6a4 */
391 u16 scc_frac; /* 0x6a6 */
392 u16 scc_fastpwrup_dly; /* 0x6a8 */
393 u16 scc_per; /* 0x6aa */
394 u16 scc_per_frac; /* 0x6ac */
395 u16 scc_cal_timer_l; /* 0x6ae */
396 u16 scc_cal_timer_h; /* 0x6b0 */
397 u16 PAD; /* 0x6b2 */
398
399 u16 PAD[0x26];
400
401 /* NAV Block */
402 u16 nav_ctl; /* 0x700 */
403 u16 navstat; /* 0x702 */
404 u16 PAD[0x3e]; /* 0x702 - 0x77E */
405
406 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
407 u16 PAD[0x20]; /* 0x780 - 0x7BE */
408
409 u16 wepctl; /* 0x7C0 */
410 u16 wepivloc; /* 0x7C2 */
411 u16 wepivkey; /* 0x7C4 */
412 u16 wepwkey; /* 0x7C6 */
413
414 u16 PAD[4]; /* 0x7C8 - 0x7CE */
415 u16 pcmctl; /* 0X7D0 */
416 u16 pcmstat; /* 0X7D2 */
417 u16 PAD[6]; /* 0x7D4 - 0x7DE */
418
419 u16 pmqctl; /* 0x7E0 */
420 u16 pmqstatus; /* 0x7E2 */
421 u16 pmqpat0; /* 0x7E4 */
422 u16 pmqpat1; /* 0x7E6 */
423 u16 pmqpat2; /* 0x7E8 */
424
425 u16 pmqdat; /* 0x7EA */
426 u16 pmqdator; /* 0x7EC */
427 u16 pmqhst; /* 0x7EE */
428 u16 pmqpath0; /* 0x7F0 */
429 u16 pmqpath1; /* 0x7F2 */
430 u16 pmqpath2; /* 0x7F4 */
431 u16 pmqdath; /* 0x7F6 */
432
433 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
434
435 /* SHM *//* 0x800 - 0xEFE */
436 u16 PAD[0x380]; /* 0x800 - 0xEFE */
437 };
438
439 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */
440
441 /* biststatus */
442 #define BT_DONE (1U << 31) /* bist done */
443 #define BT_B2S (1 << 30) /* bist2 ram summary bit */
444
445 /* intstatus and intmask */
446 #define I_PC (1 << 10) /* pci descriptor error */
447 #define I_PD (1 << 11) /* pci data error */
448 #define I_DE (1 << 12) /* descriptor protocol error */
449 #define I_RU (1 << 13) /* receive descriptor underflow */
450 #define I_RO (1 << 14) /* receive fifo overflow */
451 #define I_XU (1 << 15) /* transmit fifo underflow */
452 #define I_RI (1 << 16) /* receive interrupt */
453 #define I_XI (1 << 24) /* transmit interrupt */
454
455 /* interrupt receive lazy */
456 #define IRL_TO_MASK 0x00ffffff /* timeout */
457 #define IRL_FC_MASK 0xff000000 /* frame count */
458 #define IRL_FC_SHIFT 24 /* frame count */
459
460 /* maccontrol register */
461 #define MCTL_GMODE (1U << 31)
462 #define MCTL_DISCARD_PMQ (1 << 30)
463 #define MCTL_WAKE (1 << 26)
464 #define MCTL_HPS (1 << 25)
465 #define MCTL_PROMISC (1 << 24)
466 #define MCTL_KEEPBADFCS (1 << 23)
467 #define MCTL_KEEPCONTROL (1 << 22)
468 #define MCTL_PHYLOCK (1 << 21)
469 #define MCTL_BCNS_PROMISC (1 << 20)
470 #define MCTL_LOCK_RADIO (1 << 19)
471 #define MCTL_AP (1 << 18)
472 #define MCTL_INFRA (1 << 17)
473 #define MCTL_BIGEND (1 << 16)
474 #define MCTL_GPOUT_SEL_MASK (3 << 14)
475 #define MCTL_GPOUT_SEL_SHIFT 14
476 #define MCTL_EN_PSMDBG (1 << 13)
477 #define MCTL_IHR_EN (1 << 10)
478 #define MCTL_SHM_UPPER (1 << 9)
479 #define MCTL_SHM_EN (1 << 8)
480 #define MCTL_PSM_JMP_0 (1 << 2)
481 #define MCTL_PSM_RUN (1 << 1)
482 #define MCTL_EN_MAC (1 << 0)
483
484 /* maccommand register */
485 #define MCMD_BCN0VLD (1 << 0)
486 #define MCMD_BCN1VLD (1 << 1)
487 #define MCMD_DIRFRMQVAL (1 << 2)
488 #define MCMD_CCA (1 << 3)
489 #define MCMD_BG_NOISE (1 << 4)
490 #define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
491 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
492
493 /* macintstatus/macintmask */
494 #define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
495 #define MI_BCNTPL (1 << 1) /* beacon template available */
496 #define MI_TBTT (1 << 2) /* TBTT indication */
497 #define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
498 #define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
499 #define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
500 #define MI_PMQ (1 << 6) /* PMQ entries available */
501 #define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
502 #define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
503 #define MI_MACTXERR (1 << 9) /* MAC level Tx error */
504 #define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
505 #define MI_PHYTXERR (1 << 11) /* PHY Tx error */
506 #define MI_PME (1 << 12) /* Power Management Event */
507 #define MI_GP0 (1 << 13) /* General-purpose timer0 */
508 #define MI_GP1 (1 << 14) /* General-purpose timer1 */
509 #define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
510 #define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
511 #define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
512 #define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
513 #define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
514 #define MI_PRQ (1 << 20) /* Probe response queue needs attention */
515 #define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
516 #define MI_RESERVED3 (1 << 22)
517 #define MI_RESERVED2 (1 << 23)
518 #define MI_RESERVED1 (1 << 25)
519 /* MAC detected change on RF Disable input*/
520 #define MI_RFDISABLE (1 << 28)
521 #define MI_TFS (1 << 29) /* MAC has completed a TX */
522 #define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
523 #define MI_TO (1U << 31) /* general purpose timeout */
524
525 /* Mac capabilities registers */
526 /* machwcap */
527 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
528
529 /* pmqhost data */
530 #define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
531 #define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
532 #define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
533 #define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
534 #define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
535 #define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
536 #define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
537 #define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
538 #define PMQH_OFLO 0x00000004 /* pmq overflow indication */
539 #define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
540
541 /* phydebug */
542 #define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
543 #define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
544 #define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
545 #define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
546 #define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
547 #define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
548 #define PDBG_RXFRG (1 << 6) /* rx start not asserted */
549 #define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
550 #define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
551
552 /* objaddr register */
553 #define OBJADDR_SEL_MASK 0x000F0000
554 #define OBJADDR_UCM_SEL 0x00000000
555 #define OBJADDR_SHM_SEL 0x00010000
556 #define OBJADDR_SCR_SEL 0x00020000
557 #define OBJADDR_IHR_SEL 0x00030000
558 #define OBJADDR_RCMTA_SEL 0x00040000
559 #define OBJADDR_SRCHM_SEL 0x00060000
560 #define OBJADDR_WINC 0x01000000
561 #define OBJADDR_RINC 0x02000000
562 #define OBJADDR_AUTO_INC 0x03000000
563
564 #define WEP_PCMADDR 0x07d4
565 #define WEP_PCMDATA 0x07d6
566
567 /* frmtxstatus */
568 #define TXS_V (1 << 0) /* valid bit */
569 #define TXS_STATUS_MASK 0xffff
570 #define TXS_FID_MASK 0xffff0000
571 #define TXS_FID_SHIFT 16
572
573 /* frmtxstatus2 */
574 #define TXS_SEQ_MASK 0xffff
575 #define TXS_PTX_MASK 0xff0000
576 #define TXS_PTX_SHIFT 16
577 #define TXS_MU_MASK 0x01000000
578 #define TXS_MU_SHIFT 24
579
580 /* clk_ctl_st */
581 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
582 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
583 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
584 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
585
586 /* HT Cloclk Ctrl and Clock Avail for 4313 */
587 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
588 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
589
590 /* tsf_cfprep register */
591 #define CFPREP_CBI_MASK 0xffffffc0
592 #define CFPREP_CBI_SHIFT 6
593 #define CFPREP_CFPP 0x00000001
594
595 /* tx fifo sizes values are in terms of 256 byte blocks */
596 #define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
597 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
598 #define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
599
600 #define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
601 #define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
602 #define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
603 #define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
604
605 /* phy versions, PhyVersion:Revision field */
606 #define PV_AV_MASK 0xf000 /* analog block version */
607 #define PV_AV_SHIFT 12 /* analog block version bitfield offset */
608 #define PV_PT_MASK 0x0f00 /* phy type */
609 #define PV_PT_SHIFT 8 /* phy type bitfield offset */
610 #define PV_PV_MASK 0x000f /* phy version */
611 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
612
613 /* phy types, PhyVersion:PhyType field */
614 #define PHY_TYPE_N 4 /* N-Phy value */
615 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
616 #define PHY_TYPE_LCN 8 /* LCN-Phy value */
617 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
618 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
619
620 /* analog types, PhyVersion:AnalogType field */
621 #define ANA_11N_013 5
622
623 /* 802.11a PLCP header def */
624 struct ofdm_phy_hdr {
625 u8 rlpt[3]; /* rate, length, parity, tail */
626 u16 service;
627 u8 pad;
628 } __packed;
629
630 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
631 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
632 #define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
633 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
634 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
635
636 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */
637 #define D11A_PHY_HDR_SRATE(phdr, rate) \
638 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
639 /* set reserved field to zero */
640 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
641 /* length is number of octets in PSDU */
642 #define D11A_PHY_HDR_SLENGTH(phdr, length) \
643 (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
644 (((length) & 0x0fff) << 5))
645 /* set the tail to all zeros */
646 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
647
648 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
649 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
650
651 #define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
652
653 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
654 #define D11A_PHY_PRE_TIME (16)
655 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
656
657 /* 802.11b PLCP header def */
658 struct cck_phy_hdr {
659 u8 signal;
660 u8 service;
661 u16 length;
662 u16 crc;
663 } __packed;
664
665 #define D11B_PHY_HDR_LEN 6
666
667 #define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
668
669 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
670 #define D11B_PHY_LPRE_TIME (144)
671 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
672
673 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
674 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
675 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
676
677 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
678 #define D11B_PLCP_SIGNAL_LE (1 << 7)
679
680 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
681 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
682 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */
683
684 #define BRCMS_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
685 #define BRCMS_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
686 #define BRCMS_SET_MIMO_PLCP_LEN(plcp, len) \
687 do { \
688 plcp[1] = len & 0xff; \
689 plcp[2] = ((len >> 8) & 0xff); \
690 } while (0);
691
692 #define BRCMS_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
693 #define BRCMS_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
694 #define BRCMS_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
695
696 /* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
697 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
698 * padding added in the ucode.
699 */
700 #define D11_PHY_HDR_LEN 6
701
702 /* TX DMA buffer header */
703 struct d11txh {
704 u16 MacTxControlLow; /* 0x0 */
705 u16 MacTxControlHigh; /* 0x1 */
706 u16 MacFrameControl; /* 0x2 */
707 u16 TxFesTimeNormal; /* 0x3 */
708 u16 PhyTxControlWord; /* 0x4 */
709 u16 PhyTxControlWord_1; /* 0x5 */
710 u16 PhyTxControlWord_1_Fbr; /* 0x6 */
711 u16 PhyTxControlWord_1_Rts; /* 0x7 */
712 u16 PhyTxControlWord_1_FbrRts; /* 0x8 */
713 u16 MainRates; /* 0x9 */
714 u16 XtraFrameTypes; /* 0xa */
715 u8 IV[16]; /* 0x0b - 0x12 */
716 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
717 u16 TxFesTimeFallback; /* 0x16 */
718 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
719 u16 RTSDurFallback; /* 0x1a */
720 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
721 u16 FragDurFallback; /* 0x1e */
722 u16 MModeLen; /* 0x1f */
723 u16 MModeFbrLen; /* 0x20 */
724 u16 TstampLow; /* 0x21 */
725 u16 TstampHigh; /* 0x22 */
726 u16 ABI_MimoAntSel; /* 0x23 */
727 u16 PreloadSize; /* 0x24 */
728 u16 AmpduSeqCtl; /* 0x25 */
729 u16 TxFrameID; /* 0x26 */
730 u16 TxStatus; /* 0x27 */
731 u16 MaxNMpdus; /* 0x28 */
732 u16 MaxABytes_MRT; /* 0x29 */
733 u16 MaxABytes_FBR; /* 0x2a */
734 u16 MinMBytes; /* 0x2b */
735 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
736 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */
737 u16 PAD; /* 0x37 */
738 } __packed;
739
740 #define D11_TXH_LEN 112 /* bytes */
741
742 /* Frame Types */
743 #define FT_CCK 0
744 #define FT_OFDM 1
745 #define FT_HT 2
746 #define FT_N 3
747
748 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
749 #define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
750 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
751 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
752 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
753 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
754
755 /* MacTxControlLow */
756 #define TXC_AMIC 0x8000
757 #define TXC_SENDCTS 0x0800
758 #define TXC_AMPDU_MASK 0x0600
759 #define TXC_BW_40 0x0100
760 #define TXC_FREQBAND_5G 0x0080
761 #define TXC_DFCS 0x0040
762 #define TXC_IGNOREPMQ 0x0020
763 #define TXC_HWSEQ 0x0010
764 #define TXC_STARTMSDU 0x0008
765 #define TXC_SENDRTS 0x0004
766 #define TXC_LONGFRAME 0x0002
767 #define TXC_IMMEDACK 0x0001
768
769 /* MacTxControlHigh */
770 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
771 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
772 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
773 * 1 = SHORT for OFDM/GF for MIMO
774 * 0 = LONG for CCK/MM for MIMO
775 */
776 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
777 #define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
778 #define TXC_SECKEY_MASK 0x0FF0
779 #define TXC_SECKEY_SHIFT 4
780 #define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
781 #define TXC_SECTYPE_MASK 0x0007
782 #define TXC_SECTYPE_SHIFT 0
783
784 /* Null delimiter for Fallback rate */
785 #define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
786
787 /* PhyTxControl for Mimophy */
788 #define PHY_TXC_PWR_MASK 0xFC00
789 #define PHY_TXC_PWR_SHIFT 10
790 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
791 #define PHY_TXC_ANT_SHIFT 6
792 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
793 #define PHY_TXC_LCNPHY_ANT_LAST 0x0000
794 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
795 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
796 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
797 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
798 #define PHY_TXC_SHORT_HDR 0x0010
799
800 #define PHY_TXC_OLD_ANT_0 0x0000
801 #define PHY_TXC_OLD_ANT_1 0x0100
802 #define PHY_TXC_OLD_ANT_LAST 0x0300
803
804 /* PhyTxControl_1 for Mimophy */
805 #define PHY_TXC1_BW_MASK 0x0007
806 #define PHY_TXC1_BW_10MHZ 0
807 #define PHY_TXC1_BW_10MHZ_UP 1
808 #define PHY_TXC1_BW_20MHZ 2
809 #define PHY_TXC1_BW_20MHZ_UP 3
810 #define PHY_TXC1_BW_40MHZ 4
811 #define PHY_TXC1_BW_40MHZ_DUP 5
812 #define PHY_TXC1_MODE_SHIFT 3
813 #define PHY_TXC1_MODE_MASK 0x0038
814 #define PHY_TXC1_MODE_SISO 0
815 #define PHY_TXC1_MODE_CDD 1
816 #define PHY_TXC1_MODE_STBC 2
817 #define PHY_TXC1_MODE_SDM 3
818
819 /* PhyTxControl for HTphy that are different from Mimophy */
820 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
821
822 /* XtraFrameTypes */
823 #define XFTS_RTS_FT_SHIFT 2
824 #define XFTS_FBRRTS_FT_SHIFT 4
825 #define XFTS_CHANNEL_SHIFT 8
826
827 /* Antenna diversity bit in ant_wr_settle */
828 #define PHY_AWS_ANTDIV 0x2000
829
830 /* IFS ctl */
831 #define IFS_USEEDCF (1 << 2)
832
833 /* IFS ctl1 */
834 #define IFS_CTL1_EDCRS (1 << 3)
835 #define IFS_CTL1_EDCRS_20L (1 << 4)
836 #define IFS_CTL1_EDCRS_40 (1 << 5)
837
838 /* ABI_MimoAntSel */
839 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
840 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
841 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
842 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4
843 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
844
845 /* tx status packet */
846 struct tx_status {
847 u16 framelen;
848 u16 PAD;
849 u16 frameid;
850 u16 status;
851 u16 lasttxtime;
852 u16 sequence;
853 u16 phyerr;
854 u16 ackphyrxsh;
855 } __packed;
856
857 #define TXSTATUS_LEN 16
858
859 /* status field bit definitions */
860 #define TX_STATUS_FRM_RTX_MASK 0xF000
861 #define TX_STATUS_FRM_RTX_SHIFT 12
862 #define TX_STATUS_RTS_RTX_MASK 0x0F00
863 #define TX_STATUS_RTS_RTX_SHIFT 8
864 #define TX_STATUS_MASK 0x00FE
865 #define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
866 #define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
867 #define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
868 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
869 #define TX_STATUS_SUPR_SHIFT 2
870 #define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
871 #define TX_STATUS_VALID (1 << 0) /* Tx status valid */
872 #define TX_STATUS_NO_ACK 0
873
874 /* suppress status reason codes */
875 #define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
876 #define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
877 #define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
878 #define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
879 #define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
880 #define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
881 #define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
882
883 /* Unexpected tx status for rate update */
884 #define TX_STATUS_UNEXP(status) \
885 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
886 TX_STATUS_UNEXP_AMPDU(status))
887
888 /* Unexpected tx status for A-MPDU rate update */
889 #define TX_STATUS_UNEXP_AMPDU(status) \
890 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
891 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
892
893 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
894 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
895 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
896 #define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
897
898 /* RXE (Receive Engine) */
899
900 /* RCM_CTL */
901 #define RCM_INC_MASK_H 0x0080
902 #define RCM_INC_MASK_L 0x0040
903 #define RCM_INC_DATA 0x0020
904 #define RCM_INDEX_MASK 0x001F
905 #define RCM_SIZE 15
906
907 #define RCM_MAC_OFFSET 0 /* current MAC address */
908 #define RCM_BSSID_OFFSET 3 /* current BSSID address */
909 #define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
910 #define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
911 #define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
912
913 #define RCM_WEP_TA0_OFFSET 16
914 #define RCM_WEP_TA1_OFFSET 19
915 #define RCM_WEP_TA2_OFFSET 22
916 #define RCM_WEP_TA3_OFFSET 25
917
918 /* PSM Block */
919
920 /* psm_phy_hdr_param bits */
921 #define MAC_PHY_RESET 1
922 #define MAC_PHY_CLOCK_EN 2
923 #define MAC_PHY_FORCE_CLK 4
924
925 /* WEP Block */
926
927 /* WEP_WKEY */
928 #define WKEY_START (1 << 8)
929 #define WKEY_SEL_MASK 0x1F
930
931 /* WEP data formats */
932
933 /* the number of RCMTA entries */
934 #define RCMTA_SIZE 50
935
936 #define M_ADDR_BMP_BLK (0x37e * 2)
937 #define M_ADDR_BMP_BLK_SZ 12
938
939 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
940 #define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
941 #define ADDR_BMP_BSSID (1 << 2) /* BSSID */
942 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
943 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
944 #define ADDR_BMP_RESERVED1 (1 << 5)
945 #define ADDR_BMP_RESERVED2 (1 << 6)
946 #define ADDR_BMP_RESERVED3 (1 << 7)
947 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
948 #define ADDR_BMP_BSS_IDX_SHIFT 8
949
950 #define WSEC_MAX_RCMTA_KEYS 54
951
952 /* max keys in M_TKMICKEYS_BLK */
953 #define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
954
955 /* max RXE match registers */
956 #define WSEC_MAX_RXE_KEYS 4
957
958 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
959 /* SKL (Security Key Lookup) */
960 #define SKL_ALGO_MASK 0x0007
961 #define SKL_ALGO_SHIFT 0
962 #define SKL_KEYID_MASK 0x0008
963 #define SKL_KEYID_SHIFT 3
964 #define SKL_INDEX_MASK 0x03F0
965 #define SKL_INDEX_SHIFT 4
966 #define SKL_GRP_ALGO_MASK 0x1c00
967 #define SKL_GRP_ALGO_SHIFT 10
968
969 /* additional bits defined for IBSS group key support */
970 #define SKL_IBSS_INDEX_MASK 0x01F0
971 #define SKL_IBSS_INDEX_SHIFT 4
972 #define SKL_IBSS_KEYID1_MASK 0x0600
973 #define SKL_IBSS_KEYID1_SHIFT 9
974 #define SKL_IBSS_KEYID2_MASK 0x1800
975 #define SKL_IBSS_KEYID2_SHIFT 11
976 #define SKL_IBSS_KEYALGO_MASK 0xE000
977 #define SKL_IBSS_KEYALGO_SHIFT 13
978
979 #define WSEC_MODE_OFF 0
980 #define WSEC_MODE_HW 1
981 #define WSEC_MODE_SW 2
982
983 #define WSEC_ALGO_OFF 0
984 #define WSEC_ALGO_WEP1 1
985 #define WSEC_ALGO_TKIP 2
986 #define WSEC_ALGO_AES 3
987 #define WSEC_ALGO_WEP128 4
988 #define WSEC_ALGO_AES_LEGACY 5
989 #define WSEC_ALGO_NALG 6
990
991 #define AES_MODE_NONE 0
992 #define AES_MODE_CCM 1
993
994 /* WEP_CTL (Rev 0) */
995 #define WECR0_KEYREG_SHIFT 0
996 #define WECR0_KEYREG_MASK 0x7
997 #define WECR0_DECRYPT (1 << 3)
998 #define WECR0_IVINLINE (1 << 4)
999 #define WECR0_WEPALG_SHIFT 5
1000 #define WECR0_WEPALG_MASK (0x7 << 5)
1001 #define WECR0_WKEYSEL_SHIFT 8
1002 #define WECR0_WKEYSEL_MASK (0x7 << 8)
1003 #define WECR0_WKEYSTART (1 << 11)
1004 #define WECR0_WEPINIT (1 << 14)
1005 #define WECR0_ICVERR (1 << 15)
1006
1007 /* Frame template map byte offsets */
1008 #define T_ACTS_TPL_BASE (0)
1009 #define T_NULL_TPL_BASE (0xc * 2)
1010 #define T_QNULL_TPL_BASE (0x1c * 2)
1011 #define T_RR_TPL_BASE (0x2c * 2)
1012 #define T_BCN0_TPL_BASE (0x34 * 2)
1013 #define T_PRS_TPL_BASE (0x134 * 2)
1014 #define T_BCN1_TPL_BASE (0x234 * 2)
1015 #define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
1016
1017 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1018
1019 #define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1020
1021 /* Shared Mem byte offsets */
1022
1023 /* Location where the ucode expects the corerev */
1024 #define M_MACHW_VER (0x00b * 2)
1025
1026 /* Location where the ucode expects the MAC capabilities */
1027 #define M_MACHW_CAP_L (0x060 * 2)
1028 #define M_MACHW_CAP_H (0x061 * 2)
1029
1030 /* WME shared memory */
1031 #define M_EDCF_STATUS_OFF (0x007 * 2)
1032 #define M_TXF_CUR_INDEX (0x018 * 2)
1033 #define M_EDCF_QINFO (0x120 * 2)
1034
1035 /* PS-mode related parameters */
1036 #define M_DOT11_SLOT (0x008 * 2)
1037 #define M_DOT11_DTIMPERIOD (0x009 * 2)
1038 #define M_NOSLPZNATDTIM (0x026 * 2)
1039
1040 /* Beacon-related parameters */
1041 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1042 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1043 #define M_BCN_TXTSF_OFFSET (0x00e * 2)
1044 #define M_TIMBPOS_INBEACON (0x00f * 2)
1045 #define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1046 #define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1047 #define M_BCN_PCTLWD (0x02a * 2)
1048 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1049
1050 /* MAX Rx Frame len */
1051 #define M_MAXRXFRM_LEN (0x010 * 2)
1052
1053 /* ACK/CTS related params */
1054 #define M_RSP_PCTLWD (0x011 * 2)
1055
1056 /* Hardware Power Control */
1057 #define M_TXPWR_N (0x012 * 2)
1058 #define M_TXPWR_TARGET (0x013 * 2)
1059 #define M_TXPWR_MAX (0x014 * 2)
1060 #define M_TXPWR_CUR (0x019 * 2)
1061
1062 /* Rx-related parameters */
1063 #define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1064
1065 /* WEP Shared mem data */
1066 #define M_SEC_DEFIVLOC (0x01e * 2)
1067 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1068 #define M_PHYVER (0x028 * 2)
1069 #define M_PHYTYPE (0x029 * 2)
1070 #define M_SECRXKEYS_PTR (0x02b * 2)
1071 #define M_TKMICKEYS_PTR (0x059 * 2)
1072 #define M_SECKINDXALGO_BLK (0x2ea * 2)
1073 #define M_SECKINDXALGO_BLK_SZ 54
1074 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1075 #define M_TKIP_TSC_TTAK (0x18c * 2)
1076 #define D11_MAX_KEY_SIZE 16
1077
1078 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1079
1080 /* Probe response related parameters */
1081 #define M_SSIDLEN (0x024 * 2)
1082 #define M_PRB_RESP_FRM_LEN (0x025 * 2)
1083 #define M_PRS_MAXTIME (0x03a * 2)
1084 #define M_SSID (0xb0 * 2)
1085 #define M_CTXPRS_BLK (0xc0 * 2)
1086 #define C_CTX_PCTLWD_POS (0x4 * 2)
1087
1088 /* Delta between OFDM and CCK power in CCK power boost mode */
1089 #define M_OFDM_OFFSET (0x027 * 2)
1090
1091 /* TSSI for last 4 11b/g CCK packets transmitted */
1092 #define M_B_TSSI_0 (0x02c * 2)
1093 #define M_B_TSSI_1 (0x02d * 2)
1094
1095 /* Host flags to turn on ucode options */
1096 #define M_HOST_FLAGS1 (0x02f * 2)
1097 #define M_HOST_FLAGS2 (0x030 * 2)
1098 #define M_HOST_FLAGS3 (0x031 * 2)
1099 #define M_HOST_FLAGS4 (0x03c * 2)
1100 #define M_HOST_FLAGS5 (0x06a * 2)
1101 #define M_HOST_FLAGS_SZ 16
1102
1103 #define M_RADAR_REG (0x033 * 2)
1104
1105 /* TSSI for last 4 11a OFDM packets transmitted */
1106 #define M_A_TSSI_0 (0x034 * 2)
1107 #define M_A_TSSI_1 (0x035 * 2)
1108
1109 /* noise interference measurement */
1110 #define M_NOISE_IF_COUNT (0x034 * 2)
1111 #define M_NOISE_IF_TIMEOUT (0x035 * 2)
1112
1113 #define M_RF_RX_SP_REG1 (0x036 * 2)
1114
1115 /* TSSI for last 4 11g OFDM packets transmitted */
1116 #define M_G_TSSI_0 (0x038 * 2)
1117 #define M_G_TSSI_1 (0x039 * 2)
1118
1119 /* Background noise measure */
1120 #define M_JSSI_0 (0x44 * 2)
1121 #define M_JSSI_1 (0x45 * 2)
1122 #define M_JSSI_AUX (0x46 * 2)
1123
1124 #define M_CUR_2050_RADIOCODE (0x47 * 2)
1125
1126 /* TX fifo sizes */
1127 #define M_FIFOSIZE0 (0x4c * 2)
1128 #define M_FIFOSIZE1 (0x4d * 2)
1129 #define M_FIFOSIZE2 (0x4e * 2)
1130 #define M_FIFOSIZE3 (0x4f * 2)
1131 #define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1132
1133 /* Current channel number plus upper bits */
1134 #define M_CURCHANNEL (0x50 * 2)
1135 #define D11_CURCHANNEL_5G 0x0100;
1136 #define D11_CURCHANNEL_40 0x0200;
1137 #define D11_CURCHANNEL_MAX 0x00FF;
1138
1139 /* last posted frameid on the bcmc fifo */
1140 #define M_BCMC_FID (0x54 * 2)
1141 #define INVALIDFID 0xffff
1142
1143 /* extended beacon phyctl bytes for 11N */
1144 #define M_BCN_PCTL1WD (0x058 * 2)
1145
1146 /* idle busy ratio to duty_cycle requirement */
1147 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1148 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1149
1150 /* CW RSSI for LCNPHY */
1151 #define M_LCN_RSSI_0 0x1332
1152 #define M_LCN_RSSI_1 0x1338
1153 #define M_LCN_RSSI_2 0x133e
1154 #define M_LCN_RSSI_3 0x1344
1155
1156 /* SNR for LCNPHY */
1157 #define M_LCN_SNR_A_0 0x1334
1158 #define M_LCN_SNR_B_0 0x1336
1159
1160 #define M_LCN_SNR_A_1 0x133a
1161 #define M_LCN_SNR_B_1 0x133c
1162
1163 #define M_LCN_SNR_A_2 0x1340
1164 #define M_LCN_SNR_B_2 0x1342
1165
1166 #define M_LCN_SNR_A_3 0x1346
1167 #define M_LCN_SNR_B_3 0x1348
1168
1169 #define M_LCN_LAST_RESET (81*2)
1170 #define M_LCN_LAST_LOC (63*2)
1171 #define M_LCNPHY_RESET_STATUS (4902)
1172 #define M_LCNPHY_DSC_TIME (0x98d*2)
1173 #define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1174 #define M_LCNPHY_RESET_CNT (0x98c*2)
1175
1176 /* Rate table offsets */
1177 #define M_RT_DIRMAP_A (0xe0 * 2)
1178 #define M_RT_BBRSMAP_A (0xf0 * 2)
1179 #define M_RT_DIRMAP_B (0x100 * 2)
1180 #define M_RT_BBRSMAP_B (0x110 * 2)
1181
1182 /* Rate table entry offsets */
1183 #define M_RT_PRS_PLCP_POS 10
1184 #define M_RT_PRS_DUR_POS 16
1185 #define M_RT_OFDM_PCTL1_POS 18
1186
1187 #define M_20IN40_IQ (0x380 * 2)
1188
1189 /* SHM locations where ucode stores the current power index */
1190 #define M_CURR_IDX1 (0x384 * 2)
1191 #define M_CURR_IDX2 (0x387 * 2)
1192
1193 #define M_BSCALE_ANT0 (0x5e * 2)
1194 #define M_BSCALE_ANT1 (0x5f * 2)
1195
1196 /* Antenna Diversity Testing */
1197 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1198 #define M_ANTSEL_CLKDIV (0x61 * 2)
1199 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1200
1201 #define M_MIMO_MAXSYM (0x5d * 2)
1202 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1203 #define MIMO_MAXSYM_MAX 0xffff /* 64k */
1204
1205 #define M_WATCHDOG_8TU (0x1e * 2)
1206 #define WATCHDOG_8TU_DEF 5
1207 #define WATCHDOG_8TU_MAX 10
1208
1209 /* Manufacturing Test Variables */
1210 #define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1211 #define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1212 #define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1213 #define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1214
1215 /* Index variation in vbat ripple */
1216 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1217 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1218
1219 /* M_PKTENG_CTRL bit definitions */
1220 #define M_PKTENG_MODE_TX 0x0001
1221 #define M_PKTENG_MODE_TX_RIFS 0x0004
1222 #define M_PKTENG_MODE_TX_CTS 0x0008
1223 #define M_PKTENG_MODE_RX 0x0002
1224 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1225 #define M_PKTENG_MODE_MASK 0x0003
1226 #define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1227
1228 /* Sample Collect parameters (bitmap and type) */
1229 #define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */
1230 #define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */
1231
1232 #define ANTSEL_CLKDIV_4MHZ 6
1233 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1234 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1235 #define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1236 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1237
1238 struct shm_acparams {
1239 u16 txop;
1240 u16 cwmin;
1241 u16 cwmax;
1242 u16 cwcur;
1243 u16 aifs;
1244 u16 bslots;
1245 u16 reggap;
1246 u16 status;
1247 u16 rsvd[8];
1248 } __packed;
1249 #define M_EDCF_QLEN (16 * 2)
1250
1251 #define WME_STATUS_NEWAC (1 << 8)
1252
1253 /* M_HOST_FLAGS */
1254 #define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
1255 #define MHF1 0 /* Hostflag 1 index */
1256 #define MHF2 1 /* Hostflag 2 index */
1257 #define MHF3 2 /* Hostflag 3 index */
1258 #define MHF4 3 /* Hostflag 4 index */
1259 #define MHF5 4 /* Hostflag 5 index */
1260
1261 /* Flags in M_HOST_FLAGS */
1262 #define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1263 #define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1264 #define MHF1_IQSWAP_WAR 0x0200
1265 #define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1266
1267 /* Flags in M_HOST_FLAGS2 */
1268 #define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1269 #define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1270 #define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */
1271 #define MHF2_NPHY40MHZ_WAR 0x0800
1272
1273 /* Flags in M_HOST_FLAGS3 */
1274 #define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1275 #define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1276 #define MHF3_RESERVED1 0x0004
1277 #define MHF3_RESERVED2 0x0008
1278 #define MHF3_NPHY_MLADV_WAR 0x0010
1279
1280 /* Flags in M_HOST_FLAGS4 */
1281 #define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1282 #define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1283
1284 /* Flags in M_HOST_FLAGS5 */
1285 #define MHF5_4313_GPIOCTRL 0x0001
1286 #define MHF5_RESERVED1 0x0002
1287 #define MHF5_RESERVED2 0x0004
1288 /* Radio power setting for ucode */
1289 #define M_RADIO_PWR (0x32 * 2)
1290
1291 /* phy noise recorded by ucode right after tx */
1292 #define M_PHY_NOISE (0x037 * 2)
1293 #define PHY_NOISE_MASK 0x00ff
1294
1295 /* Receive Frame Data Header for 802.11b DCF-only frames */
1296 struct d11rxhdr {
1297 u16 RxFrameSize; /* Actual byte length of the frame data received */
1298 u16 PAD;
1299 u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1300 u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1301 u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1302 u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1303 u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1304 u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1305 u16 RxStatus1; /* MAC Rx Status */
1306 u16 RxStatus2; /* extended MAC Rx status */
1307 u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1308 u16 RxChan; /* gain code, channel radio code, and phy type */
1309 } __packed;
1310
1311 #define RXHDR_LEN 24 /* sizeof struct d11rxhdr */
1312 #define FRAMELEN(h) ((h)->RxFrameSize)
1313
1314 struct brcms_d11rxhdr {
1315 struct d11rxhdr rxhdr;
1316 u32 tsf_l; /* TSF_L reading */
1317 s8 rssi; /* computed instanteneous rssi in BMAC */
1318 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1319 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1320 s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1321 s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1322 } __packed;
1323
1324 /* PhyRxStatus_0: */
1325 #define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1326 #define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1327 #define PRXS0_CLIP_SHIFT 2
1328 #define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1329 #define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1330 #define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1331 #define PRXS0_SHORTH 0x0080 /* Short Preamble */
1332 #define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1333 #define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1334 #define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1335 #define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1336 #define PRXS0_ANTSEL_SHIFT 0x12
1337
1338 /* subfield PRXS0_FT_MASK */
1339 #define PRXS0_CCK 0x0000
1340 #define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1341 #define PRXS0_PREN 0x0002
1342 #define PRXS0_STDN 0x0003
1343
1344 /* subfield PRXS0_ANTSEL_MASK */
1345 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1346 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1347 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1348 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1349
1350 /* PhyRxStatus_1: */
1351 #define PRXS1_JSSI_MASK 0x00FF
1352 #define PRXS1_JSSI_SHIFT 0
1353 #define PRXS1_SQ_MASK 0xFF00
1354 #define PRXS1_SQ_SHIFT 8
1355
1356 /* nphy PhyRxStatus_1: */
1357 #define PRXS1_nphy_PWR0_MASK 0x00FF
1358 #define PRXS1_nphy_PWR1_MASK 0xFF00
1359
1360 /* HTPHY Rx Status defines */
1361 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1362 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1363 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1364 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1365
1366 /* htphy PhyRxStatus_1: */
1367 #define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1368 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1369 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1370
1371 /* htphy PhyRxStatus_2: */
1372 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1373 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1374 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1375
1376 /* htphy PhyRxStatus_3: */
1377 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1378 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1379
1380 /* htphy PhyRxStatus_4: */
1381 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1382 #define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1383
1384 /* htphy PhyRxStatus_5: */
1385 #define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1386 #define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1387
1388 #define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1389 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1390 /* Get Rx power on core 0 */
1391 #define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1392 /* Get Rx power on core 1 */
1393 #define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1394 /* Get Rx power on core 2 */
1395 #define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1396
1397 /* ucode RxStatus1: */
1398 #define RXS_BCNSENT 0x8000
1399 #define RXS_SECKINDX_MASK 0x07e0
1400 #define RXS_SECKINDX_SHIFT 5
1401 #define RXS_DECERR (1 << 4)
1402 #define RXS_DECATMPT (1 << 3)
1403 #define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1404 #define RXS_RESPFRAMETX (1 << 1)
1405 #define RXS_FCSERR (1 << 0)
1406
1407 /* ucode RxStatus2: */
1408 #define RXS_AMSDU_MASK 1
1409 #define RXS_AGGTYPE_MASK 0x6
1410 #define RXS_AGGTYPE_SHIFT 1
1411 #define RXS_PHYRXST_VALID (1 << 8)
1412 #define RXS_RXANT_MASK 0x3
1413 #define RXS_RXANT_SHIFT 12
1414
1415 /* RxChan */
1416 #define RXS_CHAN_40 0x1000
1417 #define RXS_CHAN_5G 0x0800
1418 #define RXS_CHAN_ID_MASK 0x07f8
1419 #define RXS_CHAN_ID_SHIFT 3
1420 #define RXS_CHAN_PHYTYPE_MASK 0x0007
1421 #define RXS_CHAN_PHYTYPE_SHIFT 0
1422
1423 /* Index of attenuations used during ucode power control. */
1424 #define M_PWRIND_BLKS (0x184 * 2)
1425 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1426 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1427 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1428 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1429 /* M_PWRIND_MAP(core) macro */
1430 #define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1431
1432 /* PSM SHM variable offsets */
1433 #define M_PSM_SOFT_REGS 0x0
1434 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1435 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1436 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1437 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1438
1439 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1440 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1441 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1442 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1443 #define M_PRETBTT (0x4b * 2)
1444
1445 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1446 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1447 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1448 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1449
1450 /* PKTENG Rx Stats Block */
1451 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1452
1453 /* ucode debug status codes */
1454 #define DBGST_INACTIVE 0 /* not valid really */
1455 #define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
1456 #define DBGST_ACTIVE 2 /* "normal" state */
1457 #define DBGST_SUSPENDED 3 /* suspended */
1458 #define DBGST_ASLEEP 4 /* asleep (PS mode) */
1459
1460 /* Scratch Reg defs */
1461 enum _ePsmScratchPadRegDefinitions {
1462 S_RSV0 = 0,
1463 S_RSV1,
1464 S_RSV2,
1465
1466 /* scratch registers for Dot11-contants */
1467 S_DOT11_CWMIN, /* CW-minimum 0x03 */
1468 S_DOT11_CWMAX, /* CW-maximum 0x04 */
1469 S_DOT11_CWCUR, /* CW-current 0x05 */
1470 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
1471 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
1472 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
1473
1474 /* Tx-side scratch registers */
1475 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
1476 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
1477 S_FRMRETX_CNT, /* frame retx count 0x0B */
1478 S_SSRC, /* Station short retry count 0x0C */
1479 S_SLRC, /* Station long retry count 0x0D */
1480 S_EXP_RSP, /* Expected response frame 0x0E */
1481 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
1482 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
1483 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
1484 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
1485
1486 /* Rx-side scratch registers */
1487 S_RXTST, /* Type and subtype in Rxframe 0x13 */
1488
1489 /* Global state register */
1490 S_STREG, /* state storage actual bit maps below 0x14 */
1491
1492 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
1493 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
1494 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
1495 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
1496
1497 S_KEYINDX, /* 0x19 */
1498 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
1499
1500 /* Receive TSF time stored in SCR */
1501 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
1502 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
1503 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
1504 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
1505 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
1506 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
1507
1508 /* Scratch pad regs used in microcode as temp storage */
1509 S_TMP0, /* stmp0 0x21 */
1510 S_TMP1, /* stmp1 0x22 */
1511 S_TMP2, /* stmp2 0x23 */
1512 S_TMP3, /* stmp3 0x24 */
1513 S_TMP4, /* stmp4 0x25 */
1514 S_TMP5, /* stmp5 0x26 */
1515 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
1516 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
1517 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
1518 S_RXTP, /* rx frame type 0x2A */
1519 S_STREG2, /* extra state storage 0x2B */
1520 S_STREG3, /* even more extra state storage 0x2C */
1521 S_STREG4, /* ... 0x2D */
1522 S_STREG5, /* remember to initialize it to zero 0x2E */
1523
1524 S_ADJPWR_IDX,
1525 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
1526 S_REVID4, /* 0x33 */
1527 S_INDX, /* 0x34 */
1528 S_ADDR0, /* 0x35 */
1529 S_ADDR1, /* 0x36 */
1530 S_ADDR2, /* 0x37 */
1531 S_ADDR3, /* 0x38 */
1532 S_ADDR4, /* 0x39 */
1533 S_ADDR5, /* 0x3A */
1534 S_TMP6, /* 0x3B */
1535 S_KEYINDX_BU, /* Backup for Key index 0x3C */
1536 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
1537 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
1538 S_STREG6, /* 0x3F */
1539 };
1540
1541 #define S_BEACON_INDX S_OLD_BREM
1542 #define S_PRS_INDX S_OLD_CWWIN
1543 #define S_PHYTYPE S_SSRC
1544 #define S_PHYVER S_SLRC
1545
1546 /* IHR SLOW_CTRL values */
1547 #define SLOW_CTRL_PDE (1 << 0)
1548 #define SLOW_CTRL_FD (1 << 8)
1549
1550 /* ucode mac statistic counters in shared memory */
1551 struct macstat {
1552 u16 txallfrm; /* 0x80 */
1553 u16 txrtsfrm; /* 0x82 */
1554 u16 txctsfrm; /* 0x84 */
1555 u16 txackfrm; /* 0x86 */
1556 u16 txdnlfrm; /* 0x88 */
1557 u16 txbcnfrm; /* 0x8a */
1558 u16 txfunfl[8]; /* 0x8c - 0x9b */
1559 u16 txtplunfl; /* 0x9c */
1560 u16 txphyerr; /* 0x9e */
1561 u16 pktengrxducast; /* 0xa0 */
1562 u16 pktengrxdmcast; /* 0xa2 */
1563 u16 rxfrmtoolong; /* 0xa4 */
1564 u16 rxfrmtooshrt; /* 0xa6 */
1565 u16 rxinvmachdr; /* 0xa8 */
1566 u16 rxbadfcs; /* 0xaa */
1567 u16 rxbadplcp; /* 0xac */
1568 u16 rxcrsglitch; /* 0xae */
1569 u16 rxstrt; /* 0xb0 */
1570 u16 rxdfrmucastmbss; /* 0xb2 */
1571 u16 rxmfrmucastmbss; /* 0xb4 */
1572 u16 rxcfrmucast; /* 0xb6 */
1573 u16 rxrtsucast; /* 0xb8 */
1574 u16 rxctsucast; /* 0xba */
1575 u16 rxackucast; /* 0xbc */
1576 u16 rxdfrmocast; /* 0xbe */
1577 u16 rxmfrmocast; /* 0xc0 */
1578 u16 rxcfrmocast; /* 0xc2 */
1579 u16 rxrtsocast; /* 0xc4 */
1580 u16 rxctsocast; /* 0xc6 */
1581 u16 rxdfrmmcast; /* 0xc8 */
1582 u16 rxmfrmmcast; /* 0xca */
1583 u16 rxcfrmmcast; /* 0xcc */
1584 u16 rxbeaconmbss; /* 0xce */
1585 u16 rxdfrmucastobss; /* 0xd0 */
1586 u16 rxbeaconobss; /* 0xd2 */
1587 u16 rxrsptmout; /* 0xd4 */
1588 u16 bcntxcancl; /* 0xd6 */
1589 u16 PAD;
1590 u16 rxf0ovfl; /* 0xda */
1591 u16 rxf1ovfl; /* 0xdc */
1592 u16 rxf2ovfl; /* 0xde */
1593 u16 txsfovfl; /* 0xe0 */
1594 u16 pmqovfl; /* 0xe2 */
1595 u16 rxcgprqfrm; /* 0xe4 */
1596 u16 rxcgprsqovfl; /* 0xe6 */
1597 u16 txcgprsfail; /* 0xe8 */
1598 u16 txcgprssuc; /* 0xea */
1599 u16 prs_timeout; /* 0xec */
1600 u16 rxnack;
1601 u16 frmscons;
1602 u16 txnack;
1603 u16 txglitch_nack;
1604 u16 txburst; /* 0xf6 # tx bursts */
1605 u16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1606 u16 phywatchdog; /* 0xfa # of phy watchdog events */
1607 u16 PAD;
1608 u16 bphy_badplcp; /* bphy bad plcp */
1609 };
1610
1611 /* dot11 core-specific control flags */
1612 #define SICF_PCLKE 0x0004 /* PHY clock enable */
1613 #define SICF_PRST 0x0008 /* PHY reset */
1614 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1615 #define SICF_FREF 0x0020 /* PLL FreqRefSelect */
1616 /* NOTE: the following bw bits only apply when the core is attached
1617 * to a NPHY
1618 */
1619 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1620 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1621 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1622 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1623 #define SICF_GMODE 0x2000 /* gmode enable */
1624
1625 /* dot11 core-specific status flags */
1626 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy */
1627 #define SISF_5G_PHY 0x0002 /* 5G capable phy */
1628 #define SISF_FCLKA 0x0004 /* FastClkAvailable */
1629 #define SISF_DB_PHY 0x0008 /* Dualband phy */
1630
1631 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
1632
1633 #define BPHY_REG_OFT_BASE 0x0
1634 /* offsets for indirect access to bphy registers */
1635 #define BPHY_BB_CONFIG 0x01
1636 #define BPHY_ADCBIAS 0x02
1637 #define BPHY_ANACORE 0x03
1638 #define BPHY_PHYCRSTH 0x06
1639 #define BPHY_TEST 0x0a
1640 #define BPHY_PA_TX_TO 0x10
1641 #define BPHY_SYNTH_DC_TO 0x11
1642 #define BPHY_PA_TX_TIME_UP 0x12
1643 #define BPHY_RX_FLTR_TIME_UP 0x13
1644 #define BPHY_TX_POWER_OVERRIDE 0x14
1645 #define BPHY_RF_OVERRIDE 0x15
1646 #define BPHY_RF_TR_LOOKUP1 0x16
1647 #define BPHY_RF_TR_LOOKUP2 0x17
1648 #define BPHY_COEFFS 0x18
1649 #define BPHY_PLL_OUT 0x19
1650 #define BPHY_REFRESH_MAIN 0x1a
1651 #define BPHY_REFRESH_TO0 0x1b
1652 #define BPHY_REFRESH_TO1 0x1c
1653 #define BPHY_RSSI_TRESH 0x20
1654 #define BPHY_IQ_TRESH_HH 0x21
1655 #define BPHY_IQ_TRESH_H 0x22
1656 #define BPHY_IQ_TRESH_L 0x23
1657 #define BPHY_IQ_TRESH_LL 0x24
1658 #define BPHY_GAIN 0x25
1659 #define BPHY_LNA_GAIN_RANGE 0x26
1660 #define BPHY_JSSI 0x27
1661 #define BPHY_TSSI_CTL 0x28
1662 #define BPHY_TSSI 0x29
1663 #define BPHY_TR_LOSS_CTL 0x2a
1664 #define BPHY_LO_LEAKAGE 0x2b
1665 #define BPHY_LO_RSSI_ACC 0x2c
1666 #define BPHY_LO_IQMAG_ACC 0x2d
1667 #define BPHY_TX_DC_OFF1 0x2e
1668 #define BPHY_TX_DC_OFF2 0x2f
1669 #define BPHY_PEAK_CNT_THRESH 0x30
1670 #define BPHY_FREQ_OFFSET 0x31
1671 #define BPHY_DIVERSITY_CTL 0x32
1672 #define BPHY_PEAK_ENERGY_LO 0x33
1673 #define BPHY_PEAK_ENERGY_HI 0x34
1674 #define BPHY_SYNC_CTL 0x35
1675 #define BPHY_TX_PWR_CTRL 0x36
1676 #define BPHY_TX_EST_PWR 0x37
1677 #define BPHY_STEP 0x38
1678 #define BPHY_WARMUP 0x39
1679 #define BPHY_LMS_CFF_READ 0x3a
1680 #define BPHY_LMS_COEFF_I 0x3b
1681 #define BPHY_LMS_COEFF_Q 0x3c
1682 #define BPHY_SIG_POW 0x3d
1683 #define BPHY_RFDC_CANCEL_CTL 0x3e
1684 #define BPHY_HDR_TYPE 0x40
1685 #define BPHY_SFD_TO 0x41
1686 #define BPHY_SFD_CTL 0x42
1687 #define BPHY_DEBUG 0x43
1688 #define BPHY_RX_DELAY_COMP 0x44
1689 #define BPHY_CRS_DROP_TO 0x45
1690 #define BPHY_SHORT_SFD_NZEROS 0x46
1691 #define BPHY_DSSS_COEFF1 0x48
1692 #define BPHY_DSSS_COEFF2 0x49
1693 #define BPHY_CCK_COEFF1 0x4a
1694 #define BPHY_CCK_COEFF2 0x4b
1695 #define BPHY_TR_CORR 0x4c
1696 #define BPHY_ANGLE_SCALE 0x4d
1697 #define BPHY_TX_PWR_BASE_IDX 0x4e
1698 #define BPHY_OPTIONAL_MODES2 0x4f
1699 #define BPHY_CCK_LMS_STEP 0x50
1700 #define BPHY_BYPASS 0x51
1701 #define BPHY_CCK_DELAY_LONG 0x52
1702 #define BPHY_CCK_DELAY_SHORT 0x53
1703 #define BPHY_PPROC_CHAN_DELAY 0x54
1704 #define BPHY_DDFS_ENABLE 0x58
1705 #define BPHY_PHASE_SCALE 0x59
1706 #define BPHY_FREQ_CONTROL 0x5a
1707 #define BPHY_LNA_GAIN_RANGE_10 0x5b
1708 #define BPHY_LNA_GAIN_RANGE_32 0x5c
1709 #define BPHY_OPTIONAL_MODES 0x5d
1710 #define BPHY_RX_STATUS2 0x5e
1711 #define BPHY_RX_STATUS3 0x5f
1712 #define BPHY_DAC_CONTROL 0x60
1713 #define BPHY_ANA11G_FILT_CTRL 0x62
1714 #define BPHY_REFRESH_CTRL 0x64
1715 #define BPHY_RF_OVERRIDE2 0x65
1716 #define BPHY_SPUR_CANCEL_CTRL 0x66
1717 #define BPHY_FINE_DIGIGAIN_CTRL 0x67
1718 #define BPHY_RSSI_LUT 0x88
1719 #define BPHY_RSSI_LUT_END 0xa7
1720 #define BPHY_TSSI_LUT 0xa8
1721 #define BPHY_TSSI_LUT_END 0xc7
1722 #define BPHY_TSSI2PWR_LUT 0x380
1723 #define BPHY_TSSI2PWR_LUT_END 0x39f
1724 #define BPHY_LOCOMP_LUT 0x3a0
1725 #define BPHY_LOCOMP_LUT_END 0x3bf
1726 #define BPHY_TXGAIN_LUT 0x3c0
1727 #define BPHY_TXGAIN_LUT_END 0x3ff
1728
1729 /* Bits in BB_CONFIG: */
1730 #define PHY_BBC_ANT_MASK 0x0180
1731 #define PHY_BBC_ANT_SHIFT 7
1732 #define BB_DARWIN 0x1000
1733 #define BBCFG_RESETCCA 0x4000
1734 #define BBCFG_RESETRX 0x8000
1735
1736 /* Bits in phytest(0x0a): */
1737 #define TST_DDFS 0x2000
1738 #define TST_TXFILT1 0x0800
1739 #define TST_UNSCRAM 0x0400
1740 #define TST_CARR_SUPP 0x0200
1741 #define TST_DC_COMP_LOOP 0x0100
1742 #define TST_LOOPBACK 0x0080
1743 #define TST_TXFILT0 0x0040
1744 #define TST_TXTEST_ENABLE 0x0020
1745 #define TST_TXTEST_RATE 0x0018
1746 #define TST_TXTEST_PHASE 0x0007
1747
1748 /* phytest txTestRate values */
1749 #define TST_TXTEST_RATE_1MBPS 0
1750 #define TST_TXTEST_RATE_2MBPS 1
1751 #define TST_TXTEST_RATE_5_5MBPS 2
1752 #define TST_TXTEST_RATE_11MBPS 3
1753 #define TST_TXTEST_RATE_SHIFT 3
1754
1755 #define SHM_BYT_CNT 0x2 /* IHR location */
1756 #define MAX_BYT_CNT 0x600 /* Maximum frame len */
1757
1758 struct d11cnt {
1759 u32 txfrag;
1760 u32 txmulti;
1761 u32 txfail;
1762 u32 txretry;
1763 u32 txretrie;
1764 u32 rxdup;
1765 u32 txrts;
1766 u32 txnocts;
1767 u32 txnoack;
1768 u32 rxfrag;
1769 u32 rxmulti;
1770 u32 rxcrc;
1771 u32 txfrmsnt;
1772 u32 rxundec;
1773 };
1774
1775 #endif /* _BRCM_D11_H_ */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree