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ahci: RAID mode SATA patch for Intel Ibex Peak DeviceIDs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
bloba0e85a78778b42e30989c0d5e4208f67d01babf8
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64 #define MAX_SLOTS 8
65
66 enum {
67 AHCI_PCI_BAR = 5,
68 AHCI_MAX_PORTS = 32,
69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
71 AHCI_MAX_CMDS = 32,
72 AHCI_CMD_SZ = 32,
73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
74 AHCI_RX_FIS_SZ = 256,
75 AHCI_CMD_TBL_CDB = 0x40,
76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
80 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
84 AHCI_CMD_PREFETCH = (1 << 7),
85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
87
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
91
92 board_ahci = 0,
93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
97 board_ahci_sb700 = 5,
98 board_ahci_mcp65 = 6,
99 board_ahci_nopmp = 7,
100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
166 PORT_IRQ_PHYRDY |
167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
175
176 /* PORT_CMD bits */
177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
184 PORT_CMD_CLO = (1 << 3), /* Command list override */
185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
193
194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
205
206 /* ap->flags bits */
207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
212
213 ICH_MAP = 0x90, /* ICH MAP register */
214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
219 };
220
221 struct ahci_cmd_hdr {
222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
227 };
228
229 struct ahci_sg {
230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
234 };
235
236 struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242 };
243
244 struct ahci_host_priv {
245 unsigned int flags; /* AHCI_HFLAG_* */
246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
250 u32 em_loc; /* enclosure management location */
251 };
252
253 struct ahci_port_priv {
254 struct ata_link *active_link;
255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
261 /* for NCQ spurious interrupt analysis */
262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
264 unsigned int ncq_saw_sdb:1;
265 u32 intr_mask; /* interrupts to enable */
266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
268 };
269
270 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
272 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
273 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
274 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
275 static int ahci_port_start(struct ata_port *ap);
276 static void ahci_port_stop(struct ata_port *ap);
277 static void ahci_qc_prep(struct ata_queued_cmd *qc);
278 static void ahci_freeze(struct ata_port *ap);
279 static void ahci_thaw(struct ata_port *ap);
280 static void ahci_pmp_attach(struct ata_port *ap);
281 static void ahci_pmp_detach(struct ata_port *ap);
282 static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
284 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
286 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292 static void ahci_postreset(struct ata_link *link, unsigned int *class);
293 static void ahci_error_handler(struct ata_port *ap);
294 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
295 static int ahci_port_resume(struct ata_port *ap);
296 static void ahci_dev_config(struct ata_device *dev);
297 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
300 #ifdef CONFIG_PM
301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
302 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303 static int ahci_pci_device_resume(struct pci_dev *pdev);
304 #endif
305 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306 static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308 static void ahci_init_sw_activity(struct ata_link *link);
309
310 static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315 };
316
317 static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
319 NULL
320 };
321
322 static struct scsi_host_template ahci_sht = {
323 ATA_NCQ_SHT(DRV_NAME),
324 .can_queue = AHCI_MAX_CMDS - 1,
325 .sg_tablesize = AHCI_MAX_SG,
326 .dma_boundary = AHCI_DMA_BOUNDARY,
327 .shost_attrs = ahci_shost_attrs,
328 .sdev_attrs = ahci_sdev_attrs,
329 };
330
331 static struct ata_port_operations ahci_ops = {
332 .inherits = &sata_pmp_port_ops,
333
334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337 .qc_fill_rtf = ahci_qc_fill_rtf,
338
339 .freeze = ahci_freeze,
340 .thaw = ahci_thaw,
341 .softreset = ahci_softreset,
342 .hardreset = ahci_hardreset,
343 .postreset = ahci_postreset,
344 .pmp_softreset = ahci_softreset,
345 .error_handler = ahci_error_handler,
346 .post_internal_cmd = ahci_post_internal_cmd,
347 .dev_config = ahci_dev_config,
348
349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
351 .pmp_attach = ahci_pmp_attach,
352 .pmp_detach = ahci_pmp_detach,
353
354 .enable_pm = ahci_enable_alpm,
355 .disable_pm = ahci_disable_alpm,
356 .em_show = ahci_led_show,
357 .em_store = ahci_led_store,
358 .sw_activity_show = ahci_activity_show,
359 .sw_activity_store = ahci_activity_store,
360 #ifdef CONFIG_PM
361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
363 #endif
364 .port_start = ahci_port_start,
365 .port_stop = ahci_port_stop,
366 };
367
368 static struct ata_port_operations ahci_vt8251_ops = {
369 .inherits = &ahci_ops,
370 .hardreset = ahci_vt8251_hardreset,
371 };
372
373 static struct ata_port_operations ahci_p5wdh_ops = {
374 .inherits = &ahci_ops,
375 .hardreset = ahci_p5wdh_hardreset,
376 };
377
378 static struct ata_port_operations ahci_sb600_ops = {
379 .inherits = &ahci_ops,
380 .softreset = ahci_sb600_softreset,
381 .pmp_softreset = ahci_sb600_softreset,
382 };
383
384 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
385
386 static const struct ata_port_info ahci_port_info[] = {
387 /* board_ahci */
388 {
389 .flags = AHCI_FLAG_COMMON,
390 .pio_mask = 0x1f, /* pio0-4 */
391 .udma_mask = ATA_UDMA6,
392 .port_ops = &ahci_ops,
393 },
394 /* board_ahci_vt8251 */
395 {
396 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
397 .flags = AHCI_FLAG_COMMON,
398 .pio_mask = 0x1f, /* pio0-4 */
399 .udma_mask = ATA_UDMA6,
400 .port_ops = &ahci_vt8251_ops,
401 },
402 /* board_ahci_ign_iferr */
403 {
404 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
405 .flags = AHCI_FLAG_COMMON,
406 .pio_mask = 0x1f, /* pio0-4 */
407 .udma_mask = ATA_UDMA6,
408 .port_ops = &ahci_ops,
409 },
410 /* board_ahci_sb600 */
411 {
412 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
413 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
414 AHCI_HFLAG_SECT255),
415 .flags = AHCI_FLAG_COMMON,
416 .pio_mask = 0x1f, /* pio0-4 */
417 .udma_mask = ATA_UDMA6,
418 .port_ops = &ahci_sb600_ops,
419 },
420 /* board_ahci_mv */
421 {
422 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
423 AHCI_HFLAG_MV_PATA),
424 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
425 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
426 .pio_mask = 0x1f, /* pio0-4 */
427 .udma_mask = ATA_UDMA6,
428 .port_ops = &ahci_ops,
429 },
430 /* board_ahci_sb700 */
431 {
432 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
433 .flags = AHCI_FLAG_COMMON,
434 .pio_mask = 0x1f, /* pio0-4 */
435 .udma_mask = ATA_UDMA6,
436 .port_ops = &ahci_sb600_ops,
437 },
438 /* board_ahci_mcp65 */
439 {
440 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
441 .flags = AHCI_FLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
445 },
446 /* board_ahci_nopmp */
447 {
448 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
449 .flags = AHCI_FLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
453 },
454 };
455
456 static const struct pci_device_id ahci_pci_tbl[] = {
457 /* Intel */
458 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
459 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
460 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
461 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
462 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
463 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
464 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
468 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
472 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
486 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
487 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
488 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
489 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
490 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
491
492 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
493 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
495
496 /* ATI */
497 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
498 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
504
505 /* VIA */
506 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
507 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
508
509 /* NVIDIA */
510 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
578
579 /* SiS */
580 { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
581 { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
582 { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
583
584 /* Marvell */
585 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
586 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
587
588 /* Generic, PCI class code for AHCI */
589 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
590 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
591
592 { } /* terminate list */
593 };
594
595
596 static struct pci_driver ahci_pci_driver = {
597 .name = DRV_NAME,
598 .id_table = ahci_pci_tbl,
599 .probe = ahci_init_one,
600 .remove = ata_pci_remove_one,
601 #ifdef CONFIG_PM
602 .suspend = ahci_pci_device_suspend,
603 .resume = ahci_pci_device_resume,
604 #endif
605 };
606
607 static int ahci_em_messages = 1;
608 module_param(ahci_em_messages, int, 0444);
609 /* add other LED protocol types when they become supported */
610 MODULE_PARM_DESC(ahci_em_messages,
611 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
612
613 static inline int ahci_nr_ports(u32 cap)
614 {
615 return (cap & 0x1f) + 1;
616 }
617
618 static inline void __iomem *__ahci_port_base(struct ata_host *host,
619 unsigned int port_no)
620 {
621 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
622
623 return mmio + 0x100 + (port_no * 0x80);
624 }
625
626 static inline void __iomem *ahci_port_base(struct ata_port *ap)
627 {
628 return __ahci_port_base(ap->host, ap->port_no);
629 }
630
631 static void ahci_enable_ahci(void __iomem *mmio)
632 {
633 int i;
634 u32 tmp;
635
636 /* turn on AHCI_EN */
637 tmp = readl(mmio + HOST_CTL);
638 if (tmp & HOST_AHCI_EN)
639 return;
640
641 /* Some controllers need AHCI_EN to be written multiple times.
642 * Try a few times before giving up.
643 */
644 for (i = 0; i < 5; i++) {
645 tmp |= HOST_AHCI_EN;
646 writel(tmp, mmio + HOST_CTL);
647 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
648 if (tmp & HOST_AHCI_EN)
649 return;
650 msleep(10);
651 }
652
653 WARN_ON(1);
654 }
655
656 /**
657 * ahci_save_initial_config - Save and fixup initial config values
658 * @pdev: target PCI device
659 * @hpriv: host private area to store config values
660 *
661 * Some registers containing configuration info might be setup by
662 * BIOS and might be cleared on reset. This function saves the
663 * initial values of those registers into @hpriv such that they
664 * can be restored after controller reset.
665 *
666 * If inconsistent, config values are fixed up by this function.
667 *
668 * LOCKING:
669 * None.
670 */
671 static void ahci_save_initial_config(struct pci_dev *pdev,
672 struct ahci_host_priv *hpriv)
673 {
674 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
675 u32 cap, port_map;
676 int i;
677 int mv;
678
679 /* make sure AHCI mode is enabled before accessing CAP */
680 ahci_enable_ahci(mmio);
681
682 /* Values prefixed with saved_ are written back to host after
683 * reset. Values without are used for driver operation.
684 */
685 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
686 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
687
688 /* some chips have errata preventing 64bit use */
689 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
690 dev_printk(KERN_INFO, &pdev->dev,
691 "controller can't do 64bit DMA, forcing 32bit\n");
692 cap &= ~HOST_CAP_64;
693 }
694
695 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
696 dev_printk(KERN_INFO, &pdev->dev,
697 "controller can't do NCQ, turning off CAP_NCQ\n");
698 cap &= ~HOST_CAP_NCQ;
699 }
700
701 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
702 dev_printk(KERN_INFO, &pdev->dev,
703 "controller can do NCQ, turning on CAP_NCQ\n");
704 cap |= HOST_CAP_NCQ;
705 }
706
707 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
708 dev_printk(KERN_INFO, &pdev->dev,
709 "controller can't do PMP, turning off CAP_PMP\n");
710 cap &= ~HOST_CAP_PMP;
711 }
712
713 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
714 port_map != 1) {
715 dev_printk(KERN_INFO, &pdev->dev,
716 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
717 port_map, 1);
718 port_map = 1;
719 }
720
721 /*
722 * Temporary Marvell 6145 hack: PATA port presence
723 * is asserted through the standard AHCI port
724 * presence register, as bit 4 (counting from 0)
725 */
726 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
727 if (pdev->device == 0x6121)
728 mv = 0x3;
729 else
730 mv = 0xf;
731 dev_printk(KERN_ERR, &pdev->dev,
732 "MV_AHCI HACK: port_map %x -> %x\n",
733 port_map,
734 port_map & mv);
735
736 port_map &= mv;
737 }
738
739 /* cross check port_map and cap.n_ports */
740 if (port_map) {
741 int map_ports = 0;
742
743 for (i = 0; i < AHCI_MAX_PORTS; i++)
744 if (port_map & (1 << i))
745 map_ports++;
746
747 /* If PI has more ports than n_ports, whine, clear
748 * port_map and let it be generated from n_ports.
749 */
750 if (map_ports > ahci_nr_ports(cap)) {
751 dev_printk(KERN_WARNING, &pdev->dev,
752 "implemented port map (0x%x) contains more "
753 "ports than nr_ports (%u), using nr_ports\n",
754 port_map, ahci_nr_ports(cap));
755 port_map = 0;
756 }
757 }
758
759 /* fabricate port_map from cap.nr_ports */
760 if (!port_map) {
761 port_map = (1 << ahci_nr_ports(cap)) - 1;
762 dev_printk(KERN_WARNING, &pdev->dev,
763 "forcing PORTS_IMPL to 0x%x\n", port_map);
764
765 /* write the fixed up value to the PI register */
766 hpriv->saved_port_map = port_map;
767 }
768
769 /* record values to use during operation */
770 hpriv->cap = cap;
771 hpriv->port_map = port_map;
772 }
773
774 /**
775 * ahci_restore_initial_config - Restore initial config
776 * @host: target ATA host
777 *
778 * Restore initial config stored by ahci_save_initial_config().
779 *
780 * LOCKING:
781 * None.
782 */
783 static void ahci_restore_initial_config(struct ata_host *host)
784 {
785 struct ahci_host_priv *hpriv = host->private_data;
786 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
787
788 writel(hpriv->saved_cap, mmio + HOST_CAP);
789 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
790 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
791 }
792
793 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
794 {
795 static const int offset[] = {
796 [SCR_STATUS] = PORT_SCR_STAT,
797 [SCR_CONTROL] = PORT_SCR_CTL,
798 [SCR_ERROR] = PORT_SCR_ERR,
799 [SCR_ACTIVE] = PORT_SCR_ACT,
800 [SCR_NOTIFICATION] = PORT_SCR_NTF,
801 };
802 struct ahci_host_priv *hpriv = ap->host->private_data;
803
804 if (sc_reg < ARRAY_SIZE(offset) &&
805 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
806 return offset[sc_reg];
807 return 0;
808 }
809
810 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
811 {
812 void __iomem *port_mmio = ahci_port_base(ap);
813 int offset = ahci_scr_offset(ap, sc_reg);
814
815 if (offset) {
816 *val = readl(port_mmio + offset);
817 return 0;
818 }
819 return -EINVAL;
820 }
821
822 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
823 {
824 void __iomem *port_mmio = ahci_port_base(ap);
825 int offset = ahci_scr_offset(ap, sc_reg);
826
827 if (offset) {
828 writel(val, port_mmio + offset);
829 return 0;
830 }
831 return -EINVAL;
832 }
833
834 static void ahci_start_engine(struct ata_port *ap)
835 {
836 void __iomem *port_mmio = ahci_port_base(ap);
837 u32 tmp;
838
839 /* start DMA */
840 tmp = readl(port_mmio + PORT_CMD);
841 tmp |= PORT_CMD_START;
842 writel(tmp, port_mmio + PORT_CMD);
843 readl(port_mmio + PORT_CMD); /* flush */
844 }
845
846 static int ahci_stop_engine(struct ata_port *ap)
847 {
848 void __iomem *port_mmio = ahci_port_base(ap);
849 u32 tmp;
850
851 tmp = readl(port_mmio + PORT_CMD);
852
853 /* check if the HBA is idle */
854 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
855 return 0;
856
857 /* setting HBA to idle */
858 tmp &= ~PORT_CMD_START;
859 writel(tmp, port_mmio + PORT_CMD);
860
861 /* wait for engine to stop. This could be as long as 500 msec */
862 tmp = ata_wait_register(port_mmio + PORT_CMD,
863 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
864 if (tmp & PORT_CMD_LIST_ON)
865 return -EIO;
866
867 return 0;
868 }
869
870 static void ahci_start_fis_rx(struct ata_port *ap)
871 {
872 void __iomem *port_mmio = ahci_port_base(ap);
873 struct ahci_host_priv *hpriv = ap->host->private_data;
874 struct ahci_port_priv *pp = ap->private_data;
875 u32 tmp;
876
877 /* set FIS registers */
878 if (hpriv->cap & HOST_CAP_64)
879 writel((pp->cmd_slot_dma >> 16) >> 16,
880 port_mmio + PORT_LST_ADDR_HI);
881 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
882
883 if (hpriv->cap & HOST_CAP_64)
884 writel((pp->rx_fis_dma >> 16) >> 16,
885 port_mmio + PORT_FIS_ADDR_HI);
886 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
887
888 /* enable FIS reception */
889 tmp = readl(port_mmio + PORT_CMD);
890 tmp |= PORT_CMD_FIS_RX;
891 writel(tmp, port_mmio + PORT_CMD);
892
893 /* flush */
894 readl(port_mmio + PORT_CMD);
895 }
896
897 static int ahci_stop_fis_rx(struct ata_port *ap)
898 {
899 void __iomem *port_mmio = ahci_port_base(ap);
900 u32 tmp;
901
902 /* disable FIS reception */
903 tmp = readl(port_mmio + PORT_CMD);
904 tmp &= ~PORT_CMD_FIS_RX;
905 writel(tmp, port_mmio + PORT_CMD);
906
907 /* wait for completion, spec says 500ms, give it 1000 */
908 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
909 PORT_CMD_FIS_ON, 10, 1000);
910 if (tmp & PORT_CMD_FIS_ON)
911 return -EBUSY;
912
913 return 0;
914 }
915
916 static void ahci_power_up(struct ata_port *ap)
917 {
918 struct ahci_host_priv *hpriv = ap->host->private_data;
919 void __iomem *port_mmio = ahci_port_base(ap);
920 u32 cmd;
921
922 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
923
924 /* spin up device */
925 if (hpriv->cap & HOST_CAP_SSS) {
926 cmd |= PORT_CMD_SPIN_UP;
927 writel(cmd, port_mmio + PORT_CMD);
928 }
929
930 /* wake up link */
931 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
932 }
933
934 static void ahci_disable_alpm(struct ata_port *ap)
935 {
936 struct ahci_host_priv *hpriv = ap->host->private_data;
937 void __iomem *port_mmio = ahci_port_base(ap);
938 u32 cmd;
939 struct ahci_port_priv *pp = ap->private_data;
940
941 /* IPM bits should be disabled by libata-core */
942 /* get the existing command bits */
943 cmd = readl(port_mmio + PORT_CMD);
944
945 /* disable ALPM and ASP */
946 cmd &= ~PORT_CMD_ASP;
947 cmd &= ~PORT_CMD_ALPE;
948
949 /* force the interface back to active */
950 cmd |= PORT_CMD_ICC_ACTIVE;
951
952 /* write out new cmd value */
953 writel(cmd, port_mmio + PORT_CMD);
954 cmd = readl(port_mmio + PORT_CMD);
955
956 /* wait 10ms to be sure we've come out of any low power state */
957 msleep(10);
958
959 /* clear out any PhyRdy stuff from interrupt status */
960 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
961
962 /* go ahead and clean out PhyRdy Change from Serror too */
963 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
964
965 /*
966 * Clear flag to indicate that we should ignore all PhyRdy
967 * state changes
968 */
969 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
970
971 /*
972 * Enable interrupts on Phy Ready.
973 */
974 pp->intr_mask |= PORT_IRQ_PHYRDY;
975 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
976
977 /*
978 * don't change the link pm policy - we can be called
979 * just to turn of link pm temporarily
980 */
981 }
982
983 static int ahci_enable_alpm(struct ata_port *ap,
984 enum link_pm policy)
985 {
986 struct ahci_host_priv *hpriv = ap->host->private_data;
987 void __iomem *port_mmio = ahci_port_base(ap);
988 u32 cmd;
989 struct ahci_port_priv *pp = ap->private_data;
990 u32 asp;
991
992 /* Make sure the host is capable of link power management */
993 if (!(hpriv->cap & HOST_CAP_ALPM))
994 return -EINVAL;
995
996 switch (policy) {
997 case MAX_PERFORMANCE:
998 case NOT_AVAILABLE:
999 /*
1000 * if we came here with NOT_AVAILABLE,
1001 * it just means this is the first time we
1002 * have tried to enable - default to max performance,
1003 * and let the user go to lower power modes on request.
1004 */
1005 ahci_disable_alpm(ap);
1006 return 0;
1007 case MIN_POWER:
1008 /* configure HBA to enter SLUMBER */
1009 asp = PORT_CMD_ASP;
1010 break;
1011 case MEDIUM_POWER:
1012 /* configure HBA to enter PARTIAL */
1013 asp = 0;
1014 break;
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 /*
1020 * Disable interrupts on Phy Ready. This keeps us from
1021 * getting woken up due to spurious phy ready interrupts
1022 * TBD - Hot plug should be done via polling now, is
1023 * that even supported?
1024 */
1025 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1026 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1027
1028 /*
1029 * Set a flag to indicate that we should ignore all PhyRdy
1030 * state changes since these can happen now whenever we
1031 * change link state
1032 */
1033 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1034
1035 /* get the existing command bits */
1036 cmd = readl(port_mmio + PORT_CMD);
1037
1038 /*
1039 * Set ASP based on Policy
1040 */
1041 cmd |= asp;
1042
1043 /*
1044 * Setting this bit will instruct the HBA to aggressively
1045 * enter a lower power link state when it's appropriate and
1046 * based on the value set above for ASP
1047 */
1048 cmd |= PORT_CMD_ALPE;
1049
1050 /* write out new cmd value */
1051 writel(cmd, port_mmio + PORT_CMD);
1052 cmd = readl(port_mmio + PORT_CMD);
1053
1054 /* IPM bits should be set by libata-core */
1055 return 0;
1056 }
1057
1058 #ifdef CONFIG_PM
1059 static void ahci_power_down(struct ata_port *ap)
1060 {
1061 struct ahci_host_priv *hpriv = ap->host->private_data;
1062 void __iomem *port_mmio = ahci_port_base(ap);
1063 u32 cmd, scontrol;
1064
1065 if (!(hpriv->cap & HOST_CAP_SSS))
1066 return;
1067
1068 /* put device into listen mode, first set PxSCTL.DET to 0 */
1069 scontrol = readl(port_mmio + PORT_SCR_CTL);
1070 scontrol &= ~0xf;
1071 writel(scontrol, port_mmio + PORT_SCR_CTL);
1072
1073 /* then set PxCMD.SUD to 0 */
1074 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1075 cmd &= ~PORT_CMD_SPIN_UP;
1076 writel(cmd, port_mmio + PORT_CMD);
1077 }
1078 #endif
1079
1080 static void ahci_start_port(struct ata_port *ap)
1081 {
1082 struct ahci_port_priv *pp = ap->private_data;
1083 struct ata_link *link;
1084 struct ahci_em_priv *emp;
1085
1086 /* enable FIS reception */
1087 ahci_start_fis_rx(ap);
1088
1089 /* enable DMA */
1090 ahci_start_engine(ap);
1091
1092 /* turn on LEDs */
1093 if (ap->flags & ATA_FLAG_EM) {
1094 ata_port_for_each_link(link, ap) {
1095 emp = &pp->em_priv[link->pmp];
1096 ahci_transmit_led_message(ap, emp->led_state, 4);
1097 }
1098 }
1099
1100 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1101 ata_port_for_each_link(link, ap)
1102 ahci_init_sw_activity(link);
1103
1104 }
1105
1106 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1107 {
1108 int rc;
1109
1110 /* disable DMA */
1111 rc = ahci_stop_engine(ap);
1112 if (rc) {
1113 *emsg = "failed to stop engine";
1114 return rc;
1115 }
1116
1117 /* disable FIS reception */
1118 rc = ahci_stop_fis_rx(ap);
1119 if (rc) {
1120 *emsg = "failed stop FIS RX";
1121 return rc;
1122 }
1123
1124 return 0;
1125 }
1126
1127 static int ahci_reset_controller(struct ata_host *host)
1128 {
1129 struct pci_dev *pdev = to_pci_dev(host->dev);
1130 struct ahci_host_priv *hpriv = host->private_data;
1131 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1132 u32 tmp;
1133
1134 /* we must be in AHCI mode, before using anything
1135 * AHCI-specific, such as HOST_RESET.
1136 */
1137 ahci_enable_ahci(mmio);
1138
1139 /* global controller reset */
1140 if (!ahci_skip_host_reset) {
1141 tmp = readl(mmio + HOST_CTL);
1142 if ((tmp & HOST_RESET) == 0) {
1143 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1144 readl(mmio + HOST_CTL); /* flush */
1145 }
1146
1147 /*
1148 * to perform host reset, OS should set HOST_RESET
1149 * and poll until this bit is read to be "0".
1150 * reset must complete within 1 second, or
1151 * the hardware should be considered fried.
1152 */
1153 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1154 HOST_RESET, 10, 1000);
1155
1156 if (tmp & HOST_RESET) {
1157 dev_printk(KERN_ERR, host->dev,
1158 "controller reset failed (0x%x)\n", tmp);
1159 return -EIO;
1160 }
1161
1162 /* turn on AHCI mode */
1163 ahci_enable_ahci(mmio);
1164
1165 /* Some registers might be cleared on reset. Restore
1166 * initial values.
1167 */
1168 ahci_restore_initial_config(host);
1169 } else
1170 dev_printk(KERN_INFO, host->dev,
1171 "skipping global host reset\n");
1172
1173 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1174 u16 tmp16;
1175
1176 /* configure PCS */
1177 pci_read_config_word(pdev, 0x92, &tmp16);
1178 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1179 tmp16 |= hpriv->port_map;
1180 pci_write_config_word(pdev, 0x92, tmp16);
1181 }
1182 }
1183
1184 return 0;
1185 }
1186
1187 static void ahci_sw_activity(struct ata_link *link)
1188 {
1189 struct ata_port *ap = link->ap;
1190 struct ahci_port_priv *pp = ap->private_data;
1191 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1192
1193 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1194 return;
1195
1196 emp->activity++;
1197 if (!timer_pending(&emp->timer))
1198 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1199 }
1200
1201 static void ahci_sw_activity_blink(unsigned long arg)
1202 {
1203 struct ata_link *link = (struct ata_link *)arg;
1204 struct ata_port *ap = link->ap;
1205 struct ahci_port_priv *pp = ap->private_data;
1206 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1207 unsigned long led_message = emp->led_state;
1208 u32 activity_led_state;
1209
1210 led_message &= 0xffff0000;
1211 led_message |= ap->port_no | (link->pmp << 8);
1212
1213 /* check to see if we've had activity. If so,
1214 * toggle state of LED and reset timer. If not,
1215 * turn LED to desired idle state.
1216 */
1217 if (emp->saved_activity != emp->activity) {
1218 emp->saved_activity = emp->activity;
1219 /* get the current LED state */
1220 activity_led_state = led_message & 0x00010000;
1221
1222 if (activity_led_state)
1223 activity_led_state = 0;
1224 else
1225 activity_led_state = 1;
1226
1227 /* clear old state */
1228 led_message &= 0xfff8ffff;
1229
1230 /* toggle state */
1231 led_message |= (activity_led_state << 16);
1232 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1233 } else {
1234 /* switch to idle */
1235 led_message &= 0xfff8ffff;
1236 if (emp->blink_policy == BLINK_OFF)
1237 led_message |= (1 << 16);
1238 }
1239 ahci_transmit_led_message(ap, led_message, 4);
1240 }
1241
1242 static void ahci_init_sw_activity(struct ata_link *link)
1243 {
1244 struct ata_port *ap = link->ap;
1245 struct ahci_port_priv *pp = ap->private_data;
1246 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1247
1248 /* init activity stats, setup timer */
1249 emp->saved_activity = emp->activity = 0;
1250 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1251
1252 /* check our blink policy and set flag for link if it's enabled */
1253 if (emp->blink_policy)
1254 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1255 }
1256
1257 static int ahci_reset_em(struct ata_host *host)
1258 {
1259 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1260 u32 em_ctl;
1261
1262 em_ctl = readl(mmio + HOST_EM_CTL);
1263 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1264 return -EINVAL;
1265
1266 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1267 return 0;
1268 }
1269
1270 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1271 ssize_t size)
1272 {
1273 struct ahci_host_priv *hpriv = ap->host->private_data;
1274 struct ahci_port_priv *pp = ap->private_data;
1275 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1276 u32 em_ctl;
1277 u32 message[] = {0, 0};
1278 unsigned long flags;
1279 int pmp;
1280 struct ahci_em_priv *emp;
1281
1282 /* get the slot number from the message */
1283 pmp = (state & 0x0000ff00) >> 8;
1284 if (pmp < MAX_SLOTS)
1285 emp = &pp->em_priv[pmp];
1286 else
1287 return -EINVAL;
1288
1289 spin_lock_irqsave(ap->lock, flags);
1290
1291 /*
1292 * if we are still busy transmitting a previous message,
1293 * do not allow
1294 */
1295 em_ctl = readl(mmio + HOST_EM_CTL);
1296 if (em_ctl & EM_CTL_TM) {
1297 spin_unlock_irqrestore(ap->lock, flags);
1298 return -EINVAL;
1299 }
1300
1301 /*
1302 * create message header - this is all zero except for
1303 * the message size, which is 4 bytes.
1304 */
1305 message[0] |= (4 << 8);
1306
1307 /* ignore 0:4 of byte zero, fill in port info yourself */
1308 message[1] = ((state & 0xfffffff0) | ap->port_no);
1309
1310 /* write message to EM_LOC */
1311 writel(message[0], mmio + hpriv->em_loc);
1312 writel(message[1], mmio + hpriv->em_loc+4);
1313
1314 /* save off new led state for port/slot */
1315 emp->led_state = message[1];
1316
1317 /*
1318 * tell hardware to transmit the message
1319 */
1320 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1321
1322 spin_unlock_irqrestore(ap->lock, flags);
1323 return size;
1324 }
1325
1326 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1327 {
1328 struct ahci_port_priv *pp = ap->private_data;
1329 struct ata_link *link;
1330 struct ahci_em_priv *emp;
1331 int rc = 0;
1332
1333 ata_port_for_each_link(link, ap) {
1334 emp = &pp->em_priv[link->pmp];
1335 rc += sprintf(buf, "%lx\n", emp->led_state);
1336 }
1337 return rc;
1338 }
1339
1340 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1341 size_t size)
1342 {
1343 int state;
1344 int pmp;
1345 struct ahci_port_priv *pp = ap->private_data;
1346 struct ahci_em_priv *emp;
1347
1348 state = simple_strtoul(buf, NULL, 0);
1349
1350 /* get the slot number from the message */
1351 pmp = (state & 0x0000ff00) >> 8;
1352 if (pmp < MAX_SLOTS)
1353 emp = &pp->em_priv[pmp];
1354 else
1355 return -EINVAL;
1356
1357 /* mask off the activity bits if we are in sw_activity
1358 * mode, user should turn off sw_activity before setting
1359 * activity led through em_message
1360 */
1361 if (emp->blink_policy)
1362 state &= 0xfff8ffff;
1363
1364 return ahci_transmit_led_message(ap, state, size);
1365 }
1366
1367 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1368 {
1369 struct ata_link *link = dev->link;
1370 struct ata_port *ap = link->ap;
1371 struct ahci_port_priv *pp = ap->private_data;
1372 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1373 u32 port_led_state = emp->led_state;
1374
1375 /* save the desired Activity LED behavior */
1376 if (val == OFF) {
1377 /* clear LFLAG */
1378 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1379
1380 /* set the LED to OFF */
1381 port_led_state &= 0xfff80000;
1382 port_led_state |= (ap->port_no | (link->pmp << 8));
1383 ahci_transmit_led_message(ap, port_led_state, 4);
1384 } else {
1385 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1386 if (val == BLINK_OFF) {
1387 /* set LED to ON for idle */
1388 port_led_state &= 0xfff80000;
1389 port_led_state |= (ap->port_no | (link->pmp << 8));
1390 port_led_state |= 0x00010000; /* check this */
1391 ahci_transmit_led_message(ap, port_led_state, 4);
1392 }
1393 }
1394 emp->blink_policy = val;
1395 return 0;
1396 }
1397
1398 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1399 {
1400 struct ata_link *link = dev->link;
1401 struct ata_port *ap = link->ap;
1402 struct ahci_port_priv *pp = ap->private_data;
1403 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1404
1405 /* display the saved value of activity behavior for this
1406 * disk.
1407 */
1408 return sprintf(buf, "%d\n", emp->blink_policy);
1409 }
1410
1411 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1412 int port_no, void __iomem *mmio,
1413 void __iomem *port_mmio)
1414 {
1415 const char *emsg = NULL;
1416 int rc;
1417 u32 tmp;
1418
1419 /* make sure port is not active */
1420 rc = ahci_deinit_port(ap, &emsg);
1421 if (rc)
1422 dev_printk(KERN_WARNING, &pdev->dev,
1423 "%s (%d)\n", emsg, rc);
1424
1425 /* clear SError */
1426 tmp = readl(port_mmio + PORT_SCR_ERR);
1427 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1428 writel(tmp, port_mmio + PORT_SCR_ERR);
1429
1430 /* clear port IRQ */
1431 tmp = readl(port_mmio + PORT_IRQ_STAT);
1432 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1433 if (tmp)
1434 writel(tmp, port_mmio + PORT_IRQ_STAT);
1435
1436 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1437 }
1438
1439 static void ahci_init_controller(struct ata_host *host)
1440 {
1441 struct ahci_host_priv *hpriv = host->private_data;
1442 struct pci_dev *pdev = to_pci_dev(host->dev);
1443 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1444 int i;
1445 void __iomem *port_mmio;
1446 u32 tmp;
1447 int mv;
1448
1449 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1450 if (pdev->device == 0x6121)
1451 mv = 2;
1452 else
1453 mv = 4;
1454 port_mmio = __ahci_port_base(host, mv);
1455
1456 writel(0, port_mmio + PORT_IRQ_MASK);
1457
1458 /* clear port IRQ */
1459 tmp = readl(port_mmio + PORT_IRQ_STAT);
1460 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1461 if (tmp)
1462 writel(tmp, port_mmio + PORT_IRQ_STAT);
1463 }
1464
1465 for (i = 0; i < host->n_ports; i++) {
1466 struct ata_port *ap = host->ports[i];
1467
1468 port_mmio = ahci_port_base(ap);
1469 if (ata_port_is_dummy(ap))
1470 continue;
1471
1472 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1473 }
1474
1475 tmp = readl(mmio + HOST_CTL);
1476 VPRINTK("HOST_CTL 0x%x\n", tmp);
1477 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1478 tmp = readl(mmio + HOST_CTL);
1479 VPRINTK("HOST_CTL 0x%x\n", tmp);
1480 }
1481
1482 static void ahci_dev_config(struct ata_device *dev)
1483 {
1484 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1485
1486 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1487 dev->max_sectors = 255;
1488 ata_dev_printk(dev, KERN_INFO,
1489 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1490 }
1491 }
1492
1493 static unsigned int ahci_dev_classify(struct ata_port *ap)
1494 {
1495 void __iomem *port_mmio = ahci_port_base(ap);
1496 struct ata_taskfile tf;
1497 u32 tmp;
1498
1499 tmp = readl(port_mmio + PORT_SIG);
1500 tf.lbah = (tmp >> 24) & 0xff;
1501 tf.lbam = (tmp >> 16) & 0xff;
1502 tf.lbal = (tmp >> 8) & 0xff;
1503 tf.nsect = (tmp) & 0xff;
1504
1505 return ata_dev_classify(&tf);
1506 }
1507
1508 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1509 u32 opts)
1510 {
1511 dma_addr_t cmd_tbl_dma;
1512
1513 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1514
1515 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1516 pp->cmd_slot[tag].status = 0;
1517 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1518 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1519 }
1520
1521 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1522 {
1523 void __iomem *port_mmio = ahci_port_base(ap);
1524 struct ahci_host_priv *hpriv = ap->host->private_data;
1525 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1526 u32 tmp;
1527 int busy, rc;
1528
1529 /* do we need to kick the port? */
1530 busy = status & (ATA_BUSY | ATA_DRQ);
1531 if (!busy && !force_restart)
1532 return 0;
1533
1534 /* stop engine */
1535 rc = ahci_stop_engine(ap);
1536 if (rc)
1537 goto out_restart;
1538
1539 /* need to do CLO? */
1540 if (!busy) {
1541 rc = 0;
1542 goto out_restart;
1543 }
1544
1545 if (!(hpriv->cap & HOST_CAP_CLO)) {
1546 rc = -EOPNOTSUPP;
1547 goto out_restart;
1548 }
1549
1550 /* perform CLO */
1551 tmp = readl(port_mmio + PORT_CMD);
1552 tmp |= PORT_CMD_CLO;
1553 writel(tmp, port_mmio + PORT_CMD);
1554
1555 rc = 0;
1556 tmp = ata_wait_register(port_mmio + PORT_CMD,
1557 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1558 if (tmp & PORT_CMD_CLO)
1559 rc = -EIO;
1560
1561 /* restart engine */
1562 out_restart:
1563 ahci_start_engine(ap);
1564 return rc;
1565 }
1566
1567 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1568 struct ata_taskfile *tf, int is_cmd, u16 flags,
1569 unsigned long timeout_msec)
1570 {
1571 const u32 cmd_fis_len = 5; /* five dwords */
1572 struct ahci_port_priv *pp = ap->private_data;
1573 void __iomem *port_mmio = ahci_port_base(ap);
1574 u8 *fis = pp->cmd_tbl;
1575 u32 tmp;
1576
1577 /* prep the command */
1578 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1579 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1580
1581 /* issue & wait */
1582 writel(1, port_mmio + PORT_CMD_ISSUE);
1583
1584 if (timeout_msec) {
1585 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1586 1, timeout_msec);
1587 if (tmp & 0x1) {
1588 ahci_kick_engine(ap, 1);
1589 return -EBUSY;
1590 }
1591 } else
1592 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1593
1594 return 0;
1595 }
1596
1597 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1598 int pmp, unsigned long deadline,
1599 int (*check_ready)(struct ata_link *link))
1600 {
1601 struct ata_port *ap = link->ap;
1602 const char *reason = NULL;
1603 unsigned long now, msecs;
1604 struct ata_taskfile tf;
1605 int rc;
1606
1607 DPRINTK("ENTER\n");
1608
1609 /* prepare for SRST (AHCI-1.1 10.4.1) */
1610 rc = ahci_kick_engine(ap, 1);
1611 if (rc && rc != -EOPNOTSUPP)
1612 ata_link_printk(link, KERN_WARNING,
1613 "failed to reset engine (errno=%d)\n", rc);
1614
1615 ata_tf_init(link->device, &tf);
1616
1617 /* issue the first D2H Register FIS */
1618 msecs = 0;
1619 now = jiffies;
1620 if (time_after(now, deadline))
1621 msecs = jiffies_to_msecs(deadline - now);
1622
1623 tf.ctl |= ATA_SRST;
1624 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1625 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1626 rc = -EIO;
1627 reason = "1st FIS failed";
1628 goto fail;
1629 }
1630
1631 /* spec says at least 5us, but be generous and sleep for 1ms */
1632 msleep(1);
1633
1634 /* issue the second D2H Register FIS */
1635 tf.ctl &= ~ATA_SRST;
1636 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1637
1638 /* wait for link to become ready */
1639 rc = ata_wait_after_reset(link, deadline, check_ready);
1640 /* link occupied, -ENODEV too is an error */
1641 if (rc) {
1642 reason = "device not ready";
1643 goto fail;
1644 }
1645 *class = ahci_dev_classify(ap);
1646
1647 DPRINTK("EXIT, class=%u\n", *class);
1648 return 0;
1649
1650 fail:
1651 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1652 return rc;
1653 }
1654
1655 static int ahci_check_ready(struct ata_link *link)
1656 {
1657 void __iomem *port_mmio = ahci_port_base(link->ap);
1658 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1659
1660 return ata_check_ready(status);
1661 }
1662
1663 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1664 unsigned long deadline)
1665 {
1666 int pmp = sata_srst_pmp(link);
1667
1668 DPRINTK("ENTER\n");
1669
1670 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1671 }
1672
1673 static int ahci_sb600_check_ready(struct ata_link *link)
1674 {
1675 void __iomem *port_mmio = ahci_port_base(link->ap);
1676 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1677 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1678
1679 /*
1680 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1681 * which can save timeout delay.
1682 */
1683 if (irq_status & PORT_IRQ_BAD_PMP)
1684 return -EIO;
1685
1686 return ata_check_ready(status);
1687 }
1688
1689 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1690 unsigned long deadline)
1691 {
1692 struct ata_port *ap = link->ap;
1693 void __iomem *port_mmio = ahci_port_base(ap);
1694 int pmp = sata_srst_pmp(link);
1695 int rc;
1696 u32 irq_sts;
1697
1698 DPRINTK("ENTER\n");
1699
1700 rc = ahci_do_softreset(link, class, pmp, deadline,
1701 ahci_sb600_check_ready);
1702
1703 /*
1704 * Soft reset fails on some ATI chips with IPMS set when PMP
1705 * is enabled but SATA HDD/ODD is connected to SATA port,
1706 * do soft reset again to port 0.
1707 */
1708 if (rc == -EIO) {
1709 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1710 if (irq_sts & PORT_IRQ_BAD_PMP) {
1711 ata_link_printk(link, KERN_WARNING,
1712 "failed due to HW bug, retry pmp=0\n");
1713 rc = ahci_do_softreset(link, class, 0, deadline,
1714 ahci_check_ready);
1715 }
1716 }
1717
1718 return rc;
1719 }
1720
1721 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1722 unsigned long deadline)
1723 {
1724 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1725 struct ata_port *ap = link->ap;
1726 struct ahci_port_priv *pp = ap->private_data;
1727 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1728 struct ata_taskfile tf;
1729 bool online;
1730 int rc;
1731
1732 DPRINTK("ENTER\n");
1733
1734 ahci_stop_engine(ap);
1735
1736 /* clear D2H reception area to properly wait for D2H FIS */
1737 ata_tf_init(link->device, &tf);
1738 tf.command = 0x80;
1739 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1740
1741 rc = sata_link_hardreset(link, timing, deadline, &online,
1742 ahci_check_ready);
1743
1744 ahci_start_engine(ap);
1745
1746 if (online)
1747 *class = ahci_dev_classify(ap);
1748
1749 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1750 return rc;
1751 }
1752
1753 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1754 unsigned long deadline)
1755 {
1756 struct ata_port *ap = link->ap;
1757 bool online;
1758 int rc;
1759
1760 DPRINTK("ENTER\n");
1761
1762 ahci_stop_engine(ap);
1763
1764 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1765 deadline, &online, NULL);
1766
1767 ahci_start_engine(ap);
1768
1769 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1770
1771 /* vt8251 doesn't clear BSY on signature FIS reception,
1772 * request follow-up softreset.
1773 */
1774 return online ? -EAGAIN : rc;
1775 }
1776
1777 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1778 unsigned long deadline)
1779 {
1780 struct ata_port *ap = link->ap;
1781 struct ahci_port_priv *pp = ap->private_data;
1782 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1783 struct ata_taskfile tf;
1784 bool online;
1785 int rc;
1786
1787 ahci_stop_engine(ap);
1788
1789 /* clear D2H reception area to properly wait for D2H FIS */
1790 ata_tf_init(link->device, &tf);
1791 tf.command = 0x80;
1792 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1793
1794 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1795 deadline, &online, NULL);
1796
1797 ahci_start_engine(ap);
1798
1799 /* The pseudo configuration device on SIMG4726 attached to
1800 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1801 * hardreset if no device is attached to the first downstream
1802 * port && the pseudo device locks up on SRST w/ PMP==0. To
1803 * work around this, wait for !BSY only briefly. If BSY isn't
1804 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1805 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1806 *
1807 * Wait for two seconds. Devices attached to downstream port
1808 * which can't process the following IDENTIFY after this will
1809 * have to be reset again. For most cases, this should
1810 * suffice while making probing snappish enough.
1811 */
1812 if (online) {
1813 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1814 ahci_check_ready);
1815 if (rc)
1816 ahci_kick_engine(ap, 0);
1817 }
1818 return rc;
1819 }
1820
1821 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1822 {
1823 struct ata_port *ap = link->ap;
1824 void __iomem *port_mmio = ahci_port_base(ap);
1825 u32 new_tmp, tmp;
1826
1827 ata_std_postreset(link, class);
1828
1829 /* Make sure port's ATAPI bit is set appropriately */
1830 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1831 if (*class == ATA_DEV_ATAPI)
1832 new_tmp |= PORT_CMD_ATAPI;
1833 else
1834 new_tmp &= ~PORT_CMD_ATAPI;
1835 if (new_tmp != tmp) {
1836 writel(new_tmp, port_mmio + PORT_CMD);
1837 readl(port_mmio + PORT_CMD); /* flush */
1838 }
1839 }
1840
1841 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1842 {
1843 struct scatterlist *sg;
1844 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1845 unsigned int si;
1846
1847 VPRINTK("ENTER\n");
1848
1849 /*
1850 * Next, the S/G list.
1851 */
1852 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1853 dma_addr_t addr = sg_dma_address(sg);
1854 u32 sg_len = sg_dma_len(sg);
1855
1856 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1857 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1858 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1859 }
1860
1861 return si;
1862 }
1863
1864 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1865 {
1866 struct ata_port *ap = qc->ap;
1867 struct ahci_port_priv *pp = ap->private_data;
1868 int is_atapi = ata_is_atapi(qc->tf.protocol);
1869 void *cmd_tbl;
1870 u32 opts;
1871 const u32 cmd_fis_len = 5; /* five dwords */
1872 unsigned int n_elem;
1873
1874 /*
1875 * Fill in command table information. First, the header,
1876 * a SATA Register - Host to Device command FIS.
1877 */
1878 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1879
1880 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1881 if (is_atapi) {
1882 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1883 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1884 }
1885
1886 n_elem = 0;
1887 if (qc->flags & ATA_QCFLAG_DMAMAP)
1888 n_elem = ahci_fill_sg(qc, cmd_tbl);
1889
1890 /*
1891 * Fill in command slot information.
1892 */
1893 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1894 if (qc->tf.flags & ATA_TFLAG_WRITE)
1895 opts |= AHCI_CMD_WRITE;
1896 if (is_atapi)
1897 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1898
1899 ahci_fill_cmd_slot(pp, qc->tag, opts);
1900 }
1901
1902 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1903 {
1904 struct ahci_host_priv *hpriv = ap->host->private_data;
1905 struct ahci_port_priv *pp = ap->private_data;
1906 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1907 struct ata_link *link = NULL;
1908 struct ata_queued_cmd *active_qc;
1909 struct ata_eh_info *active_ehi;
1910 u32 serror;
1911
1912 /* determine active link */
1913 ata_port_for_each_link(link, ap)
1914 if (ata_link_active(link))
1915 break;
1916 if (!link)
1917 link = &ap->link;
1918
1919 active_qc = ata_qc_from_tag(ap, link->active_tag);
1920 active_ehi = &link->eh_info;
1921
1922 /* record irq stat */
1923 ata_ehi_clear_desc(host_ehi);
1924 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1925
1926 /* AHCI needs SError cleared; otherwise, it might lock up */
1927 ahci_scr_read(ap, SCR_ERROR, &serror);
1928 ahci_scr_write(ap, SCR_ERROR, serror);
1929 host_ehi->serror |= serror;
1930
1931 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1932 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1933 irq_stat &= ~PORT_IRQ_IF_ERR;
1934
1935 if (irq_stat & PORT_IRQ_TF_ERR) {
1936 /* If qc is active, charge it; otherwise, the active
1937 * link. There's no active qc on NCQ errors. It will
1938 * be determined by EH by reading log page 10h.
1939 */
1940 if (active_qc)
1941 active_qc->err_mask |= AC_ERR_DEV;
1942 else
1943 active_ehi->err_mask |= AC_ERR_DEV;
1944
1945 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1946 host_ehi->serror &= ~SERR_INTERNAL;
1947 }
1948
1949 if (irq_stat & PORT_IRQ_UNK_FIS) {
1950 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1951
1952 active_ehi->err_mask |= AC_ERR_HSM;
1953 active_ehi->action |= ATA_EH_RESET;
1954 ata_ehi_push_desc(active_ehi,
1955 "unknown FIS %08x %08x %08x %08x" ,
1956 unk[0], unk[1], unk[2], unk[3]);
1957 }
1958
1959 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1960 active_ehi->err_mask |= AC_ERR_HSM;
1961 active_ehi->action |= ATA_EH_RESET;
1962 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1963 }
1964
1965 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1966 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1967 host_ehi->action |= ATA_EH_RESET;
1968 ata_ehi_push_desc(host_ehi, "host bus error");
1969 }
1970
1971 if (irq_stat & PORT_IRQ_IF_ERR) {
1972 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1973 host_ehi->action |= ATA_EH_RESET;
1974 ata_ehi_push_desc(host_ehi, "interface fatal error");
1975 }
1976
1977 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1978 ata_ehi_hotplugged(host_ehi);
1979 ata_ehi_push_desc(host_ehi, "%s",
1980 irq_stat & PORT_IRQ_CONNECT ?
1981 "connection status changed" : "PHY RDY changed");
1982 }
1983
1984 /* okay, let's hand over to EH */
1985
1986 if (irq_stat & PORT_IRQ_FREEZE)
1987 ata_port_freeze(ap);
1988 else
1989 ata_port_abort(ap);
1990 }
1991
1992 static void ahci_port_intr(struct ata_port *ap)
1993 {
1994 void __iomem *port_mmio = ahci_port_base(ap);
1995 struct ata_eh_info *ehi = &ap->link.eh_info;
1996 struct ahci_port_priv *pp = ap->private_data;
1997 struct ahci_host_priv *hpriv = ap->host->private_data;
1998 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1999 u32 status, qc_active;
2000 int rc;
2001
2002 status = readl(port_mmio + PORT_IRQ_STAT);
2003 writel(status, port_mmio + PORT_IRQ_STAT);
2004
2005 /* ignore BAD_PMP while resetting */
2006 if (unlikely(resetting))
2007 status &= ~PORT_IRQ_BAD_PMP;
2008
2009 /* If we are getting PhyRdy, this is
2010 * just a power state change, we should
2011 * clear out this, plus the PhyRdy/Comm
2012 * Wake bits from Serror
2013 */
2014 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2015 (status & PORT_IRQ_PHYRDY)) {
2016 status &= ~PORT_IRQ_PHYRDY;
2017 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2018 }
2019
2020 if (unlikely(status & PORT_IRQ_ERROR)) {
2021 ahci_error_intr(ap, status);
2022 return;
2023 }
2024
2025 if (status & PORT_IRQ_SDB_FIS) {
2026 /* If SNotification is available, leave notification
2027 * handling to sata_async_notification(). If not,
2028 * emulate it by snooping SDB FIS RX area.
2029 *
2030 * Snooping FIS RX area is probably cheaper than
2031 * poking SNotification but some constrollers which
2032 * implement SNotification, ICH9 for example, don't
2033 * store AN SDB FIS into receive area.
2034 */
2035 if (hpriv->cap & HOST_CAP_SNTF)
2036 sata_async_notification(ap);
2037 else {
2038 /* If the 'N' bit in word 0 of the FIS is set,
2039 * we just received asynchronous notification.
2040 * Tell libata about it.
2041 */
2042 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2043 u32 f0 = le32_to_cpu(f[0]);
2044
2045 if (f0 & (1 << 15))
2046 sata_async_notification(ap);
2047 }
2048 }
2049
2050 /* pp->active_link is valid iff any command is in flight */
2051 if (ap->qc_active && pp->active_link->sactive)
2052 qc_active = readl(port_mmio + PORT_SCR_ACT);
2053 else
2054 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2055
2056 rc = ata_qc_complete_multiple(ap, qc_active);
2057
2058 /* while resetting, invalid completions are expected */
2059 if (unlikely(rc < 0 && !resetting)) {
2060 ehi->err_mask |= AC_ERR_HSM;
2061 ehi->action |= ATA_EH_RESET;
2062 ata_port_freeze(ap);
2063 }
2064 }
2065
2066 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2067 {
2068 struct ata_host *host = dev_instance;
2069 struct ahci_host_priv *hpriv;
2070 unsigned int i, handled = 0;
2071 void __iomem *mmio;
2072 u32 irq_stat, irq_masked;
2073
2074 VPRINTK("ENTER\n");
2075
2076 hpriv = host->private_data;
2077 mmio = host->iomap[AHCI_PCI_BAR];
2078
2079 /* sigh. 0xffffffff is a valid return from h/w */
2080 irq_stat = readl(mmio + HOST_IRQ_STAT);
2081 if (!irq_stat)
2082 return IRQ_NONE;
2083
2084 irq_masked = irq_stat & hpriv->port_map;
2085
2086 spin_lock(&host->lock);
2087
2088 for (i = 0; i < host->n_ports; i++) {
2089 struct ata_port *ap;
2090
2091 if (!(irq_masked & (1 << i)))
2092 continue;
2093
2094 ap = host->ports[i];
2095 if (ap) {
2096 ahci_port_intr(ap);
2097 VPRINTK("port %u\n", i);
2098 } else {
2099 VPRINTK("port %u (no irq)\n", i);
2100 if (ata_ratelimit())
2101 dev_printk(KERN_WARNING, host->dev,
2102 "interrupt on disabled port %u\n", i);
2103 }
2104
2105 handled = 1;
2106 }
2107
2108 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2109 * it should be cleared after all the port events are cleared;
2110 * otherwise, it will raise a spurious interrupt after each
2111 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2112 * information.
2113 *
2114 * Also, use the unmasked value to clear interrupt as spurious
2115 * pending event on a dummy port might cause screaming IRQ.
2116 */
2117 writel(irq_stat, mmio + HOST_IRQ_STAT);
2118
2119 spin_unlock(&host->lock);
2120
2121 VPRINTK("EXIT\n");
2122
2123 return IRQ_RETVAL(handled);
2124 }
2125
2126 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2127 {
2128 struct ata_port *ap = qc->ap;
2129 void __iomem *port_mmio = ahci_port_base(ap);
2130 struct ahci_port_priv *pp = ap->private_data;
2131
2132 /* Keep track of the currently active link. It will be used
2133 * in completion path to determine whether NCQ phase is in
2134 * progress.
2135 */
2136 pp->active_link = qc->dev->link;
2137
2138 if (qc->tf.protocol == ATA_PROT_NCQ)
2139 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2140 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2141
2142 ahci_sw_activity(qc->dev->link);
2143
2144 return 0;
2145 }
2146
2147 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2148 {
2149 struct ahci_port_priv *pp = qc->ap->private_data;
2150 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2151
2152 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2153 return true;
2154 }
2155
2156 static void ahci_freeze(struct ata_port *ap)
2157 {
2158 void __iomem *port_mmio = ahci_port_base(ap);
2159
2160 /* turn IRQ off */
2161 writel(0, port_mmio + PORT_IRQ_MASK);
2162 }
2163
2164 static void ahci_thaw(struct ata_port *ap)
2165 {
2166 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2167 void __iomem *port_mmio = ahci_port_base(ap);
2168 u32 tmp;
2169 struct ahci_port_priv *pp = ap->private_data;
2170
2171 /* clear IRQ */
2172 tmp = readl(port_mmio + PORT_IRQ_STAT);
2173 writel(tmp, port_mmio + PORT_IRQ_STAT);
2174 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2175
2176 /* turn IRQ back on */
2177 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2178 }
2179
2180 static void ahci_error_handler(struct ata_port *ap)
2181 {
2182 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2183 /* restart engine */
2184 ahci_stop_engine(ap);
2185 ahci_start_engine(ap);
2186 }
2187
2188 sata_pmp_error_handler(ap);
2189 }
2190
2191 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2192 {
2193 struct ata_port *ap = qc->ap;
2194
2195 /* make DMA engine forget about the failed command */
2196 if (qc->flags & ATA_QCFLAG_FAILED)
2197 ahci_kick_engine(ap, 1);
2198 }
2199
2200 static void ahci_pmp_attach(struct ata_port *ap)
2201 {
2202 void __iomem *port_mmio = ahci_port_base(ap);
2203 struct ahci_port_priv *pp = ap->private_data;
2204 u32 cmd;
2205
2206 cmd = readl(port_mmio + PORT_CMD);
2207 cmd |= PORT_CMD_PMP;
2208 writel(cmd, port_mmio + PORT_CMD);
2209
2210 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2211 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2212 }
2213
2214 static void ahci_pmp_detach(struct ata_port *ap)
2215 {
2216 void __iomem *port_mmio = ahci_port_base(ap);
2217 struct ahci_port_priv *pp = ap->private_data;
2218 u32 cmd;
2219
2220 cmd = readl(port_mmio + PORT_CMD);
2221 cmd &= ~PORT_CMD_PMP;
2222 writel(cmd, port_mmio + PORT_CMD);
2223
2224 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2225 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2226 }
2227
2228 static int ahci_port_resume(struct ata_port *ap)
2229 {
2230 ahci_power_up(ap);
2231 ahci_start_port(ap);
2232
2233 if (sata_pmp_attached(ap))
2234 ahci_pmp_attach(ap);
2235 else
2236 ahci_pmp_detach(ap);
2237
2238 return 0;
2239 }
2240
2241 #ifdef CONFIG_PM
2242 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2243 {
2244 const char *emsg = NULL;
2245 int rc;
2246
2247 rc = ahci_deinit_port(ap, &emsg);
2248 if (rc == 0)
2249 ahci_power_down(ap);
2250 else {
2251 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2252 ahci_start_port(ap);
2253 }
2254
2255 return rc;
2256 }
2257
2258 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2259 {
2260 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2261 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2262 u32 ctl;
2263
2264 if (mesg.event & PM_EVENT_SLEEP) {
2265 /* AHCI spec rev1.1 section 8.3.3:
2266 * Software must disable interrupts prior to requesting a
2267 * transition of the HBA to D3 state.
2268 */
2269 ctl = readl(mmio + HOST_CTL);
2270 ctl &= ~HOST_IRQ_EN;
2271 writel(ctl, mmio + HOST_CTL);
2272 readl(mmio + HOST_CTL); /* flush */
2273 }
2274
2275 return ata_pci_device_suspend(pdev, mesg);
2276 }
2277
2278 static int ahci_pci_device_resume(struct pci_dev *pdev)
2279 {
2280 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2281 int rc;
2282
2283 rc = ata_pci_device_do_resume(pdev);
2284 if (rc)
2285 return rc;
2286
2287 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2288 rc = ahci_reset_controller(host);
2289 if (rc)
2290 return rc;
2291
2292 ahci_init_controller(host);
2293 }
2294
2295 ata_host_resume(host);
2296
2297 return 0;
2298 }
2299 #endif
2300
2301 static int ahci_port_start(struct ata_port *ap)
2302 {
2303 struct device *dev = ap->host->dev;
2304 struct ahci_port_priv *pp;
2305 void *mem;
2306 dma_addr_t mem_dma;
2307
2308 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2309 if (!pp)
2310 return -ENOMEM;
2311
2312 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2313 GFP_KERNEL);
2314 if (!mem)
2315 return -ENOMEM;
2316 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2317
2318 /*
2319 * First item in chunk of DMA memory: 32-slot command table,
2320 * 32 bytes each in size
2321 */
2322 pp->cmd_slot = mem;
2323 pp->cmd_slot_dma = mem_dma;
2324
2325 mem += AHCI_CMD_SLOT_SZ;
2326 mem_dma += AHCI_CMD_SLOT_SZ;
2327
2328 /*
2329 * Second item: Received-FIS area
2330 */
2331 pp->rx_fis = mem;
2332 pp->rx_fis_dma = mem_dma;
2333
2334 mem += AHCI_RX_FIS_SZ;
2335 mem_dma += AHCI_RX_FIS_SZ;
2336
2337 /*
2338 * Third item: data area for storing a single command
2339 * and its scatter-gather table
2340 */
2341 pp->cmd_tbl = mem;
2342 pp->cmd_tbl_dma = mem_dma;
2343
2344 /*
2345 * Save off initial list of interrupts to be enabled.
2346 * This could be changed later
2347 */
2348 pp->intr_mask = DEF_PORT_IRQ;
2349
2350 ap->private_data = pp;
2351
2352 /* engage engines, captain */
2353 return ahci_port_resume(ap);
2354 }
2355
2356 static void ahci_port_stop(struct ata_port *ap)
2357 {
2358 const char *emsg = NULL;
2359 int rc;
2360
2361 /* de-initialize port */
2362 rc = ahci_deinit_port(ap, &emsg);
2363 if (rc)
2364 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2365 }
2366
2367 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2368 {
2369 int rc;
2370
2371 if (using_dac &&
2372 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2373 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2374 if (rc) {
2375 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2376 if (rc) {
2377 dev_printk(KERN_ERR, &pdev->dev,
2378 "64-bit DMA enable failed\n");
2379 return rc;
2380 }
2381 }
2382 } else {
2383 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2384 if (rc) {
2385 dev_printk(KERN_ERR, &pdev->dev,
2386 "32-bit DMA enable failed\n");
2387 return rc;
2388 }
2389 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2390 if (rc) {
2391 dev_printk(KERN_ERR, &pdev->dev,
2392 "32-bit consistent DMA enable failed\n");
2393 return rc;
2394 }
2395 }
2396 return 0;
2397 }
2398
2399 static void ahci_print_info(struct ata_host *host)
2400 {
2401 struct ahci_host_priv *hpriv = host->private_data;
2402 struct pci_dev *pdev = to_pci_dev(host->dev);
2403 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2404 u32 vers, cap, impl, speed;
2405 const char *speed_s;
2406 u16 cc;
2407 const char *scc_s;
2408
2409 vers = readl(mmio + HOST_VERSION);
2410 cap = hpriv->cap;
2411 impl = hpriv->port_map;
2412
2413 speed = (cap >> 20) & 0xf;
2414 if (speed == 1)
2415 speed_s = "1.5";
2416 else if (speed == 2)
2417 speed_s = "3";
2418 else
2419 speed_s = "?";
2420
2421 pci_read_config_word(pdev, 0x0a, &cc);
2422 if (cc == PCI_CLASS_STORAGE_IDE)
2423 scc_s = "IDE";
2424 else if (cc == PCI_CLASS_STORAGE_SATA)
2425 scc_s = "SATA";
2426 else if (cc == PCI_CLASS_STORAGE_RAID)
2427 scc_s = "RAID";
2428 else
2429 scc_s = "unknown";
2430
2431 dev_printk(KERN_INFO, &pdev->dev,
2432 "AHCI %02x%02x.%02x%02x "
2433 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2434 ,
2435
2436 (vers >> 24) & 0xff,
2437 (vers >> 16) & 0xff,
2438 (vers >> 8) & 0xff,
2439 vers & 0xff,
2440
2441 ((cap >> 8) & 0x1f) + 1,
2442 (cap & 0x1f) + 1,
2443 speed_s,
2444 impl,
2445 scc_s);
2446
2447 dev_printk(KERN_INFO, &pdev->dev,
2448 "flags: "
2449 "%s%s%s%s%s%s%s"
2450 "%s%s%s%s%s%s%s"
2451 "%s\n"
2452 ,
2453
2454 cap & (1 << 31) ? "64bit " : "",
2455 cap & (1 << 30) ? "ncq " : "",
2456 cap & (1 << 29) ? "sntf " : "",
2457 cap & (1 << 28) ? "ilck " : "",
2458 cap & (1 << 27) ? "stag " : "",
2459 cap & (1 << 26) ? "pm " : "",
2460 cap & (1 << 25) ? "led " : "",
2461
2462 cap & (1 << 24) ? "clo " : "",
2463 cap & (1 << 19) ? "nz " : "",
2464 cap & (1 << 18) ? "only " : "",
2465 cap & (1 << 17) ? "pmp " : "",
2466 cap & (1 << 15) ? "pio " : "",
2467 cap & (1 << 14) ? "slum " : "",
2468 cap & (1 << 13) ? "part " : "",
2469 cap & (1 << 6) ? "ems ": ""
2470 );
2471 }
2472
2473 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2474 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2475 * support PMP and the 4726 either directly exports the device
2476 * attached to the first downstream port or acts as a hardware storage
2477 * controller and emulate a single ATA device (can be RAID 0/1 or some
2478 * other configuration).
2479 *
2480 * When there's no device attached to the first downstream port of the
2481 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2482 * configure the 4726. However, ATA emulation of the device is very
2483 * lame. It doesn't send signature D2H Reg FIS after the initial
2484 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2485 *
2486 * The following function works around the problem by always using
2487 * hardreset on the port and not depending on receiving signature FIS
2488 * afterward. If signature FIS isn't received soon, ATA class is
2489 * assumed without follow-up softreset.
2490 */
2491 static void ahci_p5wdh_workaround(struct ata_host *host)
2492 {
2493 static struct dmi_system_id sysids[] = {
2494 {
2495 .ident = "P5W DH Deluxe",
2496 .matches = {
2497 DMI_MATCH(DMI_SYS_VENDOR,
2498 "ASUSTEK COMPUTER INC"),
2499 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2500 },
2501 },
2502 { }
2503 };
2504 struct pci_dev *pdev = to_pci_dev(host->dev);
2505
2506 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2507 dmi_check_system(sysids)) {
2508 struct ata_port *ap = host->ports[1];
2509
2510 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2511 "Deluxe on-board SIMG4726 workaround\n");
2512
2513 ap->ops = &ahci_p5wdh_ops;
2514 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2515 }
2516 }
2517
2518 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2519 {
2520 static int printed_version;
2521 unsigned int board_id = ent->driver_data;
2522 struct ata_port_info pi = ahci_port_info[board_id];
2523 const struct ata_port_info *ppi[] = { &pi, NULL };
2524 struct device *dev = &pdev->dev;
2525 struct ahci_host_priv *hpriv;
2526 struct ata_host *host;
2527 int n_ports, i, rc;
2528
2529 VPRINTK("ENTER\n");
2530
2531 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2532
2533 if (!printed_version++)
2534 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2535
2536 /* acquire resources */
2537 rc = pcim_enable_device(pdev);
2538 if (rc)
2539 return rc;
2540
2541 /* AHCI controllers often implement SFF compatible interface.
2542 * Grab all PCI BARs just in case.
2543 */
2544 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2545 if (rc == -EBUSY)
2546 pcim_pin_device(pdev);
2547 if (rc)
2548 return rc;
2549
2550 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2551 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2552 u8 map;
2553
2554 /* ICH6s share the same PCI ID for both piix and ahci
2555 * modes. Enabling ahci mode while MAP indicates
2556 * combined mode is a bad idea. Yield to ata_piix.
2557 */
2558 pci_read_config_byte(pdev, ICH_MAP, &map);
2559 if (map & 0x3) {
2560 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2561 "combined mode, can't enable AHCI mode\n");
2562 return -ENODEV;
2563 }
2564 }
2565
2566 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2567 if (!hpriv)
2568 return -ENOMEM;
2569 hpriv->flags |= (unsigned long)pi.private_data;
2570
2571 /* MCP65 revision A1 and A2 can't do MSI */
2572 if (board_id == board_ahci_mcp65 &&
2573 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2574 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2575
2576 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2577 pci_intx(pdev, 1);
2578
2579 /* save initial config */
2580 ahci_save_initial_config(pdev, hpriv);
2581
2582 /* prepare host */
2583 if (hpriv->cap & HOST_CAP_NCQ)
2584 pi.flags |= ATA_FLAG_NCQ;
2585
2586 if (hpriv->cap & HOST_CAP_PMP)
2587 pi.flags |= ATA_FLAG_PMP;
2588
2589 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2590 u8 messages;
2591 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2592 u32 em_loc = readl(mmio + HOST_EM_LOC);
2593 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2594
2595 messages = (em_ctl & 0x000f0000) >> 16;
2596
2597 /* we only support LED message type right now */
2598 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2599 /* store em_loc */
2600 hpriv->em_loc = ((em_loc >> 16) * 4);
2601 pi.flags |= ATA_FLAG_EM;
2602 if (!(em_ctl & EM_CTL_ALHD))
2603 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2604 }
2605 }
2606
2607 /* CAP.NP sometimes indicate the index of the last enabled
2608 * port, at other times, that of the last possible port, so
2609 * determining the maximum port number requires looking at
2610 * both CAP.NP and port_map.
2611 */
2612 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2613
2614 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2615 if (!host)
2616 return -ENOMEM;
2617 host->iomap = pcim_iomap_table(pdev);
2618 host->private_data = hpriv;
2619
2620 if (pi.flags & ATA_FLAG_EM)
2621 ahci_reset_em(host);
2622
2623 for (i = 0; i < host->n_ports; i++) {
2624 struct ata_port *ap = host->ports[i];
2625
2626 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2627 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2628 0x100 + ap->port_no * 0x80, "port");
2629
2630 /* set initial link pm policy */
2631 ap->pm_policy = NOT_AVAILABLE;
2632
2633 /* set enclosure management message type */
2634 if (ap->flags & ATA_FLAG_EM)
2635 ap->em_message_type = ahci_em_messages;
2636
2637
2638 /* disabled/not-implemented port */
2639 if (!(hpriv->port_map & (1 << i)))
2640 ap->ops = &ata_dummy_port_ops;
2641 }
2642
2643 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2644 ahci_p5wdh_workaround(host);
2645
2646 /* initialize adapter */
2647 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2648 if (rc)
2649 return rc;
2650
2651 rc = ahci_reset_controller(host);
2652 if (rc)
2653 return rc;
2654
2655 ahci_init_controller(host);
2656 ahci_print_info(host);
2657
2658 pci_set_master(pdev);
2659 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2660 &ahci_sht);
2661 }
2662
2663 static int __init ahci_init(void)
2664 {
2665 return pci_register_driver(&ahci_pci_driver);
2666 }
2667
2668 static void __exit ahci_exit(void)
2669 {
2670 pci_unregister_driver(&ahci_pci_driver);
2671 }
2672
2673
2674 MODULE_AUTHOR("Jeff Garzik");
2675 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2676 MODULE_LICENSE("GPL");
2677 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2678 MODULE_VERSION(DRV_VERSION);
2679
2680 module_init(ahci_init);
2681 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree