4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
10 * i8259 parts ripped out of arch/mips/kernel/i8259.c
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial_8250.h>
23 #include <asm/irq_cpu.h>
25 #define RM200_I8259A_IRQ_BASE 32
27 #define MEMPORT(_base,_irq) \
33 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \
36 static struct plat_serial8250_port rm200_data
[] = {
37 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE
+ 4),
38 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE
+ 3),
42 static struct platform_device rm200_serial8250_device
= {
44 .id
= PLAT8250_DEV_PLATFORM
,
46 .platform_data
= rm200_data
,
50 static struct resource rm200_ds1216_rsrc
[] = {
54 .flags
= IORESOURCE_MEM
58 static struct platform_device rm200_ds1216_device
= {
60 .num_resources
= ARRAY_SIZE(rm200_ds1216_rsrc
),
61 .resource
= rm200_ds1216_rsrc
64 static struct resource snirm_82596_rm200_rsrc
[] = {
68 .flags
= IORESOURCE_MEM
73 .flags
= IORESOURCE_MEM
78 .flags
= IORESOURCE_MEM
83 .flags
= IORESOURCE_IRQ
90 static struct platform_device snirm_82596_rm200_pdev
= {
91 .name
= "snirm_82596",
92 .num_resources
= ARRAY_SIZE(snirm_82596_rm200_rsrc
),
93 .resource
= snirm_82596_rm200_rsrc
96 static struct resource snirm_53c710_rm200_rsrc
[] = {
100 .flags
= IORESOURCE_MEM
105 .flags
= IORESOURCE_IRQ
109 static struct platform_device snirm_53c710_rm200_pdev
= {
110 .name
= "snirm_53c710",
111 .num_resources
= ARRAY_SIZE(snirm_53c710_rm200_rsrc
),
112 .resource
= snirm_53c710_rm200_rsrc
115 static int __init
snirm_setup_devinit(void)
117 if (sni_brd_type
== SNI_BRD_RM200
) {
118 platform_device_register(&rm200_serial8250_device
);
119 platform_device_register(&rm200_ds1216_device
);
120 platform_device_register(&snirm_82596_rm200_pdev
);
121 platform_device_register(&snirm_53c710_rm200_pdev
);
122 sni_eisa_root_init();
127 device_initcall(snirm_setup_devinit
);
130 * RM200 has an ISA and an EISA bus. The iSA bus is only used
131 * for onboard devices and also has twi i8259 PICs. Since these
132 * PICs are no accessible via inb/outb the following code uses
133 * readb/writeb to access them
136 static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock
);
139 #define PIC_ISR PIC_CMD
140 #define PIC_POLL PIC_ISR
141 #define PIC_OCW3 PIC_ISR
143 /* i8259A PIC related value */
144 #define PIC_CASCADE_IR 2
145 #define MASTER_ICW4_DEFAULT 0x01
146 #define SLAVE_ICW4_DEFAULT 0x01
149 * This contains the irq mask for both 8259A irq controllers,
151 static unsigned int rm200_cached_irq_mask
= 0xffff;
152 static __iomem u8
*rm200_pic_master
;
153 static __iomem u8
*rm200_pic_slave
;
155 #define cached_master_mask (rm200_cached_irq_mask)
156 #define cached_slave_mask (rm200_cached_irq_mask >> 8)
158 static void sni_rm200_disable_8259A_irq(unsigned int irq
)
163 irq
-= RM200_I8259A_IRQ_BASE
;
165 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock
, flags
);
166 rm200_cached_irq_mask
|= mask
;
168 writeb(cached_slave_mask
, rm200_pic_slave
+ PIC_IMR
);
170 writeb(cached_master_mask
, rm200_pic_master
+ PIC_IMR
);
171 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock
, flags
);
174 static void sni_rm200_enable_8259A_irq(unsigned int irq
)
179 irq
-= RM200_I8259A_IRQ_BASE
;
181 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock
, flags
);
182 rm200_cached_irq_mask
&= mask
;
184 writeb(cached_slave_mask
, rm200_pic_slave
+ PIC_IMR
);
186 writeb(cached_master_mask
, rm200_pic_master
+ PIC_IMR
);
187 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock
, flags
);
190 static inline int sni_rm200_i8259A_irq_real(unsigned int irq
)
193 int irqmask
= 1 << irq
;
196 writeb(0x0B, rm200_pic_master
+ PIC_CMD
);
197 value
= readb(rm200_pic_master
+ PIC_CMD
) & irqmask
;
198 writeb(0x0A, rm200_pic_master
+ PIC_CMD
);
201 writeb(0x0B, rm200_pic_slave
+ PIC_CMD
); /* ISR register */
202 value
= readb(rm200_pic_slave
+ PIC_CMD
) & (irqmask
>> 8);
203 writeb(0x0A, rm200_pic_slave
+ PIC_CMD
);
208 * Careful! The 8259A is a fragile beast, it pretty
209 * much _has_ to be done exactly like this (mask it
210 * first, _then_ send the EOI, and the order of EOI
211 * to the two 8259s is important!
213 void sni_rm200_mask_and_ack_8259A(unsigned int irq
)
215 unsigned int irqmask
;
218 irq
-= RM200_I8259A_IRQ_BASE
;
220 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock
, flags
);
222 * Lightweight spurious IRQ detection. We do not want
223 * to overdo spurious IRQ handling - it's usually a sign
224 * of hardware problems, so we only do the checks we can
225 * do without slowing down good hardware unnecessarily.
227 * Note that IRQ7 and IRQ15 (the two spurious IRQs
228 * usually resulting from the 8259A-1|2 PICs) occur
229 * even if the IRQ is masked in the 8259A. Thus we
230 * can check spurious 8259A IRQs without doing the
231 * quite slow i8259A_irq_real() call for every IRQ.
232 * This does not cover 100% of spurious interrupts,
233 * but should be enough to warn the user that there
234 * is something bad going on ...
236 if (rm200_cached_irq_mask
& irqmask
)
237 goto spurious_8259A_irq
;
238 rm200_cached_irq_mask
|= irqmask
;
242 readb(rm200_pic_slave
+ PIC_IMR
);
243 writeb(cached_slave_mask
, rm200_pic_slave
+ PIC_IMR
);
244 writeb(0x60+(irq
& 7), rm200_pic_slave
+ PIC_CMD
);
245 writeb(0x60+PIC_CASCADE_IR
, rm200_pic_master
+ PIC_CMD
);
247 readb(rm200_pic_master
+ PIC_IMR
);
248 writeb(cached_master_mask
, rm200_pic_master
+ PIC_IMR
);
249 writeb(0x60+irq
, rm200_pic_master
+ PIC_CMD
);
251 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock
, flags
);
256 * this is the slow path - should happen rarely.
258 if (sni_rm200_i8259A_irq_real(irq
))
260 * oops, the IRQ _is_ in service according to the
261 * 8259A - not spurious, go handle it.
263 goto handle_real_irq
;
266 static int spurious_irq_mask
;
268 * At this point we can be sure the IRQ is spurious,
269 * lets ACK and report it. [once per IRQ]
271 if (!(spurious_irq_mask
& irqmask
)) {
273 "spurious RM200 8259A interrupt: IRQ%d.\n", irq
);
274 spurious_irq_mask
|= irqmask
;
276 atomic_inc(&irq_err_count
);
278 * Theoretically we do not have to handle this IRQ,
279 * but in Linux this does not cause problems and is
282 goto handle_real_irq
;
286 static struct irq_chip sni_rm200_i8259A_chip
= {
287 .name
= "RM200-XT-PIC",
288 .mask
= sni_rm200_disable_8259A_irq
,
289 .unmask
= sni_rm200_enable_8259A_irq
,
290 .mask_ack
= sni_rm200_mask_and_ack_8259A
,
294 * Do the traditional i8259 interrupt polling thing. This is for the few
295 * cases where no better interrupt acknowledge method is available and we
296 * absolutely must touch the i8259.
298 static inline int sni_rm200_i8259_irq(void)
302 raw_spin_lock(&sni_rm200_i8259A_lock
);
304 /* Perform an interrupt acknowledge cycle on controller 1. */
305 writeb(0x0C, rm200_pic_master
+ PIC_CMD
); /* prepare for poll */
306 irq
= readb(rm200_pic_master
+ PIC_CMD
) & 7;
307 if (irq
== PIC_CASCADE_IR
) {
309 * Interrupt is cascaded so perform interrupt
310 * acknowledge on controller 2.
312 writeb(0x0C, rm200_pic_slave
+ PIC_CMD
); /* prepare for poll */
313 irq
= (readb(rm200_pic_slave
+ PIC_CMD
) & 7) + 8;
316 if (unlikely(irq
== 7)) {
318 * This may be a spurious interrupt.
320 * Read the interrupt status register (ISR). If the most
321 * significant bit is not set then there is no valid
324 writeb(0x0B, rm200_pic_master
+ PIC_ISR
); /* ISR register */
325 if (~readb(rm200_pic_master
+ PIC_ISR
) & 0x80)
329 raw_spin_unlock(&sni_rm200_i8259A_lock
);
331 return likely(irq
>= 0) ? irq
+ RM200_I8259A_IRQ_BASE
: irq
;
334 void sni_rm200_init_8259A(void)
338 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock
, flags
);
340 writeb(0xff, rm200_pic_master
+ PIC_IMR
);
341 writeb(0xff, rm200_pic_slave
+ PIC_IMR
);
343 writeb(0x11, rm200_pic_master
+ PIC_CMD
);
344 writeb(0, rm200_pic_master
+ PIC_IMR
);
345 writeb(1U << PIC_CASCADE_IR
, rm200_pic_master
+ PIC_IMR
);
346 writeb(MASTER_ICW4_DEFAULT
, rm200_pic_master
+ PIC_IMR
);
347 writeb(0x11, rm200_pic_slave
+ PIC_CMD
);
348 writeb(8, rm200_pic_slave
+ PIC_IMR
);
349 writeb(PIC_CASCADE_IR
, rm200_pic_slave
+ PIC_IMR
);
350 writeb(SLAVE_ICW4_DEFAULT
, rm200_pic_slave
+ PIC_IMR
);
351 udelay(100); /* wait for 8259A to initialize */
353 writeb(cached_master_mask
, rm200_pic_master
+ PIC_IMR
);
354 writeb(cached_slave_mask
, rm200_pic_slave
+ PIC_IMR
);
356 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock
, flags
);
360 * IRQ2 is cascade interrupt to second interrupt controller
362 static struct irqaction sni_rm200_irq2
= {
363 .handler
= no_action
,
367 static struct resource sni_rm200_pic1_resource
= {
368 .name
= "onboard ISA pic1",
371 .flags
= IORESOURCE_BUSY
374 static struct resource sni_rm200_pic2_resource
= {
375 .name
= "onboard ISA pic2",
378 .flags
= IORESOURCE_BUSY
381 /* ISA irq handler */
382 static irqreturn_t
sni_rm200_i8259A_irq_handler(int dummy
, void *p
)
386 irq
= sni_rm200_i8259_irq();
387 if (unlikely(irq
< 0))
394 struct irqaction sni_rm200_i8259A_irq
= {
395 .handler
= sni_rm200_i8259A_irq_handler
,
396 .name
= "onboard ISA",
400 void __init
sni_rm200_i8259_irqs(void)
404 rm200_pic_master
= ioremap_nocache(0x16000020, 4);
405 if (!rm200_pic_master
)
407 rm200_pic_slave
= ioremap_nocache(0x160000a0, 4);
408 if (!rm200_pic_slave
) {
409 iounmap(rm200_pic_master
);
413 insert_resource(&iomem_resource
, &sni_rm200_pic1_resource
);
414 insert_resource(&iomem_resource
, &sni_rm200_pic2_resource
);
416 sni_rm200_init_8259A();
418 for (i
= RM200_I8259A_IRQ_BASE
; i
< RM200_I8259A_IRQ_BASE
+ 16; i
++)
419 set_irq_chip_and_handler(i
, &sni_rm200_i8259A_chip
,
422 setup_irq(RM200_I8259A_IRQ_BASE
+ PIC_CASCADE_IR
, &sni_rm200_irq2
);
426 #define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
427 #define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)
429 #define SNI_RM200_INT_START 24
430 #define SNI_RM200_INT_END 28
432 static void enable_rm200_irq(unsigned int irq
)
434 unsigned int mask
= 1 << (irq
- SNI_RM200_INT_START
);
436 *(volatile u8
*)SNI_RM200_INT_ENA_REG
&= ~mask
;
439 void disable_rm200_irq(unsigned int irq
)
441 unsigned int mask
= 1 << (irq
- SNI_RM200_INT_START
);
443 *(volatile u8
*)SNI_RM200_INT_ENA_REG
|= mask
;
446 void end_rm200_irq(unsigned int irq
)
448 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
449 enable_rm200_irq(irq
);
452 static struct irq_chip rm200_irq_type
= {
454 .ack
= disable_rm200_irq
,
455 .mask
= disable_rm200_irq
,
456 .mask_ack
= disable_rm200_irq
,
457 .unmask
= enable_rm200_irq
,
458 .end
= end_rm200_irq
,
461 static void sni_rm200_hwint(void)
463 u32 pending
= read_c0_cause() & read_c0_status();
468 if (pending
& C_IRQ5
)
469 do_IRQ(MIPS_CPU_IRQ_BASE
+ 7);
470 else if (pending
& C_IRQ0
) {
471 clear_c0_status(IE_IRQ0
);
472 mask
= *(volatile u8
*)SNI_RM200_INT_ENA_REG
^ 0x1f;
473 stat
= *(volatile u8
*)SNI_RM200_INT_STAT_REG
^ 0x14;
474 irq
= ffs(stat
& mask
& 0x1f);
477 do_IRQ(irq
+ SNI_RM200_INT_START
- 1);
478 set_c0_status(IE_IRQ0
);
482 void __init
sni_rm200_irq_init(void)
486 * (volatile u8
*)SNI_RM200_INT_ENA_REG
= 0x1f;
488 sni_rm200_i8259_irqs();
490 /* Actually we've got more interrupts to handle ... */
491 for (i
= SNI_RM200_INT_START
; i
<= SNI_RM200_INT_END
; i
++)
492 set_irq_chip_and_handler(i
, &rm200_irq_type
, handle_level_irq
);
493 sni_hwint
= sni_rm200_hwint
;
494 change_c0_status(ST0_IM
, IE_IRQ0
);
495 setup_irq(SNI_RM200_INT_START
+ 0, &sni_rm200_i8259A_irq
);
496 setup_irq(SNI_RM200_INT_START
+ 1, &sni_isa_irq
);
499 void __init
sni_rm200_init(void)