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USB host: Move AMD PLL quirk to pci-quirks.c
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / lirc / lirc_sir.c
blob76be7b8c620968218822c3216204e14ffdc2250b
1 /*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
36 #include <linux/module.h>
37 #include <linux/sched.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/ioport.h>
43 #include <linux/kernel.h>
44 #include <linux/serial_reg.h>
45 #include <linux/time.h>
46 #include <linux/string.h>
47 #include <linux/types.h>
48 #include <linux/wait.h>
49 #include <linux/mm.h>
50 #include <linux/delay.h>
51 #include <linux/poll.h>
52 #include <asm/system.h>
53 #include <linux/io.h>
54 #include <asm/irq.h>
55 #include <linux/fcntl.h>
56 #ifdef LIRC_ON_SA1100
57 #include <asm/hardware.h>
58 #ifdef CONFIG_SA1100_COLLIE
59 #include <asm/arch/tc35143.h>
60 #include <asm/ucb1200.h>
61 #endif
62 #endif
63
64 #include <linux/timer.h>
65
66 #include <media/lirc.h>
67 #include <media/lirc_dev.h>
68
69 /* SECTION: Definitions */
70
71 /*** Tekram dongle ***/
72 #ifdef LIRC_SIR_TEKRAM
73 /* stolen from kernel source */
74 /* definitions for Tekram dongle */
75 #define TEKRAM_115200 0x00
76 #define TEKRAM_57600 0x01
77 #define TEKRAM_38400 0x02
78 #define TEKRAM_19200 0x03
79 #define TEKRAM_9600 0x04
80 #define TEKRAM_2400 0x08
81
82 #define TEKRAM_PW 0x10 /* Pulse select bit */
83
84 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
85 #define TIME_CONST (10000000ul/115200ul)
86
87 #endif
88
89 #ifdef LIRC_SIR_ACTISYS_ACT200L
90 static void init_act200(void);
91 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
92 static void init_act220(void);
93 #endif
94
95 /*** SA1100 ***/
96 #ifdef LIRC_ON_SA1100
97 struct sa1100_ser2_registers {
98 /* HSSP control register */
99 unsigned char hscr0;
100 /* UART registers */
101 unsigned char utcr0;
102 unsigned char utcr1;
103 unsigned char utcr2;
104 unsigned char utcr3;
105 unsigned char utcr4;
106 unsigned char utdr;
107 unsigned char utsr0;
108 unsigned char utsr1;
109 } sr;
110
111 static int irq = IRQ_Ser2ICP;
112
113 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
114
115 /* pulse/space ratio of 50/50 */
116 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
117 /* 1000000/freq-pulse_width */
118 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
119 static unsigned int freq = 38000; /* modulation frequency */
120 static unsigned int duty_cycle = 50; /* duty cycle of 50% */
121
122 #endif
123
124 #define RBUF_LEN 1024
125 #define WBUF_LEN 1024
126
127 #define LIRC_DRIVER_NAME "lirc_sir"
128
129 #define PULSE '['
130
131 #ifndef LIRC_SIR_TEKRAM
132 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
133 #define TIME_CONST (9000000ul/115200ul)
134 #endif
135
136
137 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
138 #define SIR_TIMEOUT (HZ*5/100)
139
140 #ifndef LIRC_ON_SA1100
141 #ifndef LIRC_IRQ
142 #define LIRC_IRQ 4
143 #endif
144 #ifndef LIRC_PORT
145 /* for external dongles, default to com1 */
146 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
147 defined(LIRC_SIR_ACTISYS_ACT220L) || \
148 defined(LIRC_SIR_TEKRAM)
149 #define LIRC_PORT 0x3f8
150 #else
151 /* onboard sir ports are typically com3 */
152 #define LIRC_PORT 0x3e8
153 #endif
154 #endif
155
156 static int io = LIRC_PORT;
157 static int irq = LIRC_IRQ;
158 static int threshold = 3;
159 #endif
160
161 static DEFINE_SPINLOCK(timer_lock);
162 static struct timer_list timerlist;
163 /* time of last signal change detected */
164 static struct timeval last_tv = {0, 0};
165 /* time of last UART data ready interrupt */
166 static struct timeval last_intr_tv = {0, 0};
167 static int last_value;
168
169 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
170
171 static DEFINE_SPINLOCK(hardware_lock);
172
173 static int rx_buf[RBUF_LEN];
174 static unsigned int rx_tail, rx_head;
175
176 static int debug;
177 #define dprintk(fmt, args...) \
178 do { \
179 if (debug) \
180 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
181 fmt, ## args); \
182 } while (0)
183
184 /* SECTION: Prototypes */
185
186 /* Communication with user-space */
187 static unsigned int lirc_poll(struct file *file, poll_table *wait);
188 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
189 loff_t *ppos);
190 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
191 loff_t *pos);
192 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
193 static void add_read_queue(int flag, unsigned long val);
194 static int init_chrdev(void);
195 static void drop_chrdev(void);
196 /* Hardware */
197 static irqreturn_t sir_interrupt(int irq, void *dev_id);
198 static void send_space(unsigned long len);
199 static void send_pulse(unsigned long len);
200 static int init_hardware(void);
201 static void drop_hardware(void);
202 /* Initialisation */
203 static int init_port(void);
204 static void drop_port(void);
205
206 #ifdef LIRC_ON_SA1100
207 static void on(void)
208 {
209 PPSR |= PPC_TXD2;
210 }
211
212 static void off(void)
213 {
214 PPSR &= ~PPC_TXD2;
215 }
216 #else
217 static inline unsigned int sinp(int offset)
218 {
219 return inb(io + offset);
220 }
221
222 static inline void soutp(int offset, int value)
223 {
224 outb(value, io + offset);
225 }
226 #endif
227
228 #ifndef MAX_UDELAY_MS
229 #define MAX_UDELAY_US 5000
230 #else
231 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
232 #endif
233
234 static void safe_udelay(unsigned long usecs)
235 {
236 while (usecs > MAX_UDELAY_US) {
237 udelay(MAX_UDELAY_US);
238 usecs -= MAX_UDELAY_US;
239 }
240 udelay(usecs);
241 }
242
243 /* SECTION: Communication with user-space */
244
245 static unsigned int lirc_poll(struct file *file, poll_table *wait)
246 {
247 poll_wait(file, &lirc_read_queue, wait);
248 if (rx_head != rx_tail)
249 return POLLIN | POLLRDNORM;
250 return 0;
251 }
252
253 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
254 loff_t *ppos)
255 {
256 int n = 0;
257 int retval = 0;
258 DECLARE_WAITQUEUE(wait, current);
259
260 if (count % sizeof(int))
261 return -EINVAL;
262
263 add_wait_queue(&lirc_read_queue, &wait);
264 set_current_state(TASK_INTERRUPTIBLE);
265 while (n < count) {
266 if (rx_head != rx_tail) {
267 if (copy_to_user((void *) buf + n,
268 (void *) (rx_buf + rx_head),
269 sizeof(int))) {
270 retval = -EFAULT;
271 break;
272 }
273 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
274 n += sizeof(int);
275 } else {
276 if (file->f_flags & O_NONBLOCK) {
277 retval = -EAGAIN;
278 break;
279 }
280 if (signal_pending(current)) {
281 retval = -ERESTARTSYS;
282 break;
283 }
284 schedule();
285 set_current_state(TASK_INTERRUPTIBLE);
286 }
287 }
288 remove_wait_queue(&lirc_read_queue, &wait);
289 set_current_state(TASK_RUNNING);
290 return n ? n : retval;
291 }
292 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
293 loff_t *pos)
294 {
295 unsigned long flags;
296 int i, count;
297 int *tx_buf;
298
299 count = n / sizeof(int);
300 if (n % sizeof(int) || count % 2 == 0)
301 return -EINVAL;
302 tx_buf = memdup_user(buf, n);
303 if (IS_ERR(tx_buf))
304 return PTR_ERR(tx_buf);
305 i = 0;
306 #ifdef LIRC_ON_SA1100
307 /* disable receiver */
308 Ser2UTCR3 = 0;
309 #endif
310 local_irq_save(flags);
311 while (1) {
312 if (i >= count)
313 break;
314 if (tx_buf[i])
315 send_pulse(tx_buf[i]);
316 i++;
317 if (i >= count)
318 break;
319 if (tx_buf[i])
320 send_space(tx_buf[i]);
321 i++;
322 }
323 local_irq_restore(flags);
324 #ifdef LIRC_ON_SA1100
325 off();
326 udelay(1000); /* wait 1ms for IR diode to recover */
327 Ser2UTCR3 = 0;
328 /* clear status register to prevent unwanted interrupts */
329 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
330 /* enable receiver */
331 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
332 #endif
333 kfree(tx_buf);
334 return count;
335 }
336
337 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
338 {
339 int retval = 0;
340 __u32 value = 0;
341 #ifdef LIRC_ON_SA1100
342
343 if (cmd == LIRC_GET_FEATURES)
344 value = LIRC_CAN_SEND_PULSE |
345 LIRC_CAN_SET_SEND_DUTY_CYCLE |
346 LIRC_CAN_SET_SEND_CARRIER |
347 LIRC_CAN_REC_MODE2;
348 else if (cmd == LIRC_GET_SEND_MODE)
349 value = LIRC_MODE_PULSE;
350 else if (cmd == LIRC_GET_REC_MODE)
351 value = LIRC_MODE_MODE2;
352 #else
353 if (cmd == LIRC_GET_FEATURES)
354 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
355 else if (cmd == LIRC_GET_SEND_MODE)
356 value = LIRC_MODE_PULSE;
357 else if (cmd == LIRC_GET_REC_MODE)
358 value = LIRC_MODE_MODE2;
359 #endif
360
361 switch (cmd) {
362 case LIRC_GET_FEATURES:
363 case LIRC_GET_SEND_MODE:
364 case LIRC_GET_REC_MODE:
365 retval = put_user(value, (__u32 *) arg);
366 break;
367
368 case LIRC_SET_SEND_MODE:
369 case LIRC_SET_REC_MODE:
370 retval = get_user(value, (__u32 *) arg);
371 break;
372 #ifdef LIRC_ON_SA1100
373 case LIRC_SET_SEND_DUTY_CYCLE:
374 retval = get_user(value, (__u32 *) arg);
375 if (retval)
376 return retval;
377 if (value <= 0 || value > 100)
378 return -EINVAL;
379 /* (value/100)*(1000000/freq) */
380 duty_cycle = value;
381 pulse_width = (unsigned long) duty_cycle*10000/freq;
382 space_width = (unsigned long) 1000000L/freq-pulse_width;
383 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
384 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
385 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
386 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
387 break;
388 case LIRC_SET_SEND_CARRIER:
389 retval = get_user(value, (__u32 *) arg);
390 if (retval)
391 return retval;
392 if (value > 500000 || value < 20000)
393 return -EINVAL;
394 freq = value;
395 pulse_width = (unsigned long) duty_cycle*10000/freq;
396 space_width = (unsigned long) 1000000L/freq-pulse_width;
397 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
398 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
399 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
400 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
401 break;
402 #endif
403 default:
404 retval = -ENOIOCTLCMD;
405
406 }
407
408 if (retval)
409 return retval;
410 if (cmd == LIRC_SET_REC_MODE) {
411 if (value != LIRC_MODE_MODE2)
412 retval = -ENOSYS;
413 } else if (cmd == LIRC_SET_SEND_MODE) {
414 if (value != LIRC_MODE_PULSE)
415 retval = -ENOSYS;
416 }
417
418 return retval;
419 }
420
421 static void add_read_queue(int flag, unsigned long val)
422 {
423 unsigned int new_rx_tail;
424 int newval;
425
426 dprintk("add flag %d with val %lu\n", flag, val);
427
428 newval = val & PULSE_MASK;
429
430 /*
431 * statistically, pulses are ~TIME_CONST/2 too long. we could
432 * maybe make this more exact, but this is good enough
433 */
434 if (flag) {
435 /* pulse */
436 if (newval > TIME_CONST/2)
437 newval -= TIME_CONST/2;
438 else /* should not ever happen */
439 newval = 1;
440 newval |= PULSE_BIT;
441 } else {
442 newval += TIME_CONST/2;
443 }
444 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
445 if (new_rx_tail == rx_head) {
446 dprintk("Buffer overrun.\n");
447 return;
448 }
449 rx_buf[rx_tail] = newval;
450 rx_tail = new_rx_tail;
451 wake_up_interruptible(&lirc_read_queue);
452 }
453
454 static const struct file_operations lirc_fops = {
455 .owner = THIS_MODULE,
456 .read = lirc_read,
457 .write = lirc_write,
458 .poll = lirc_poll,
459 .unlocked_ioctl = lirc_ioctl,
460 #ifdef CONFIG_COMPAT
461 .compat_ioctl = lirc_ioctl,
462 #endif
463 .open = lirc_dev_fop_open,
464 .release = lirc_dev_fop_close,
465 .llseek = no_llseek,
466 };
467
468 static int set_use_inc(void *data)
469 {
470 return 0;
471 }
472
473 static void set_use_dec(void *data)
474 {
475 }
476
477 static struct lirc_driver driver = {
478 .name = LIRC_DRIVER_NAME,
479 .minor = -1,
480 .code_length = 1,
481 .sample_rate = 0,
482 .data = NULL,
483 .add_to_buf = NULL,
484 .set_use_inc = set_use_inc,
485 .set_use_dec = set_use_dec,
486 .fops = &lirc_fops,
487 .dev = NULL,
488 .owner = THIS_MODULE,
489 };
490
491
492 static int init_chrdev(void)
493 {
494 driver.minor = lirc_register_driver(&driver);
495 if (driver.minor < 0) {
496 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n");
497 return -EIO;
498 }
499 return 0;
500 }
501
502 static void drop_chrdev(void)
503 {
504 lirc_unregister_driver(driver.minor);
505 }
506
507 /* SECTION: Hardware */
508 static long delta(struct timeval *tv1, struct timeval *tv2)
509 {
510 unsigned long deltv;
511
512 deltv = tv2->tv_sec - tv1->tv_sec;
513 if (deltv > 15)
514 deltv = 0xFFFFFF;
515 else
516 deltv = deltv*1000000 +
517 tv2->tv_usec -
518 tv1->tv_usec;
519 return deltv;
520 }
521
522 static void sir_timeout(unsigned long data)
523 {
524 /*
525 * if last received signal was a pulse, but receiving stopped
526 * within the 9 bit frame, we need to finish this pulse and
527 * simulate a signal change to from pulse to space. Otherwise
528 * upper layers will receive two sequences next time.
529 */
530
531 unsigned long flags;
532 unsigned long pulse_end;
533
534 /* avoid interference with interrupt */
535 spin_lock_irqsave(&timer_lock, flags);
536 if (last_value) {
537 #ifndef LIRC_ON_SA1100
538 /* clear unread bits in UART and restart */
539 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
540 #endif
541 /* determine 'virtual' pulse end: */
542 pulse_end = delta(&last_tv, &last_intr_tv);
543 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
544 add_read_queue(last_value, pulse_end);
545 last_value = 0;
546 last_tv = last_intr_tv;
547 }
548 spin_unlock_irqrestore(&timer_lock, flags);
549 }
550
551 static irqreturn_t sir_interrupt(int irq, void *dev_id)
552 {
553 unsigned char data;
554 struct timeval curr_tv;
555 static unsigned long deltv;
556 #ifdef LIRC_ON_SA1100
557 int status;
558 static int n;
559
560 status = Ser2UTSR0;
561 /*
562 * Deal with any receive errors first. The bytes in error may be
563 * the only bytes in the receive FIFO, so we do this first.
564 */
565 while (status & UTSR0_EIF) {
566 int bstat;
567
568 if (debug) {
569 dprintk("EIF\n");
570 bstat = Ser2UTSR1;
571
572 if (bstat & UTSR1_FRE)
573 dprintk("frame error\n");
574 if (bstat & UTSR1_ROR)
575 dprintk("receive fifo overrun\n");
576 if (bstat & UTSR1_PRE)
577 dprintk("parity error\n");
578 }
579
580 bstat = Ser2UTDR;
581 n++;
582 status = Ser2UTSR0;
583 }
584
585 if (status & (UTSR0_RFS | UTSR0_RID)) {
586 do_gettimeofday(&curr_tv);
587 deltv = delta(&last_tv, &curr_tv);
588 do {
589 data = Ser2UTDR;
590 dprintk("%d data: %u\n", n, (unsigned int) data);
591 n++;
592 } while (status & UTSR0_RID && /* do not empty fifo in order to
593 * get UTSR0_RID in any case */
594 Ser2UTSR1 & UTSR1_RNE); /* data ready */
595
596 if (status&UTSR0_RID) {
597 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
598 add_read_queue(1, n * TIME_CONST); /*pulse*/
599 n = 0;
600 last_tv = curr_tv;
601 }
602 }
603
604 if (status & UTSR0_TFS)
605 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n");
606
607 /* We must clear certain bits. */
608 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
609 if (status)
610 Ser2UTSR0 = status;
611 #else
612 unsigned long deltintrtv;
613 unsigned long flags;
614 int iir, lsr;
615
616 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
617 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
618 case UART_IIR_MSI:
619 (void) inb(io + UART_MSR);
620 break;
621 case UART_IIR_RLSI:
622 (void) inb(io + UART_LSR);
623 break;
624 case UART_IIR_THRI:
625 #if 0
626 if (lsr & UART_LSR_THRE) /* FIFO is empty */
627 outb(data, io + UART_TX)
628 #endif
629 break;
630 case UART_IIR_RDI:
631 /* avoid interference with timer */
632 spin_lock_irqsave(&timer_lock, flags);
633 do {
634 del_timer(&timerlist);
635 data = inb(io + UART_RX);
636 do_gettimeofday(&curr_tv);
637 deltv = delta(&last_tv, &curr_tv);
638 deltintrtv = delta(&last_intr_tv, &curr_tv);
639 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
640 /*
641 * if nothing came in last X cycles,
642 * it was gap
643 */
644 if (deltintrtv > TIME_CONST * threshold) {
645 if (last_value) {
646 dprintk("GAP\n");
647 /* simulate signal change */
648 add_read_queue(last_value,
649 deltv -
650 deltintrtv);
651 last_value = 0;
652 last_tv.tv_sec =
653 last_intr_tv.tv_sec;
654 last_tv.tv_usec =
655 last_intr_tv.tv_usec;
656 deltv = deltintrtv;
657 }
658 }
659 data = 1;
660 if (data ^ last_value) {
661 /*
662 * deltintrtv > 2*TIME_CONST, remember?
663 * the other case is timeout
664 */
665 add_read_queue(last_value,
666 deltv-TIME_CONST);
667 last_value = data;
668 last_tv = curr_tv;
669 if (last_tv.tv_usec >= TIME_CONST) {
670 last_tv.tv_usec -= TIME_CONST;
671 } else {
672 last_tv.tv_sec--;
673 last_tv.tv_usec += 1000000 -
674 TIME_CONST;
675 }
676 }
677 last_intr_tv = curr_tv;
678 if (data) {
679 /*
680 * start timer for end of
681 * sequence detection
682 */
683 timerlist.expires = jiffies +
684 SIR_TIMEOUT;
685 add_timer(&timerlist);
686 }
687
688 lsr = inb(io + UART_LSR);
689 } while (lsr & UART_LSR_DR); /* data ready */
690 spin_unlock_irqrestore(&timer_lock, flags);
691 break;
692 default:
693 break;
694 }
695 }
696 #endif
697 return IRQ_RETVAL(IRQ_HANDLED);
698 }
699
700 #ifdef LIRC_ON_SA1100
701 static void send_pulse(unsigned long length)
702 {
703 unsigned long k, delay;
704 int flag;
705
706 if (length == 0)
707 return;
708 /*
709 * this won't give us the carrier frequency we really want
710 * due to integer arithmetic, but we can accept this inaccuracy
711 */
712
713 for (k = flag = 0; k < length; k += delay, flag = !flag) {
714 if (flag) {
715 off();
716 delay = space_width;
717 } else {
718 on();
719 delay = pulse_width;
720 }
721 safe_udelay(delay);
722 }
723 off();
724 }
725
726 static void send_space(unsigned long length)
727 {
728 if (length == 0)
729 return;
730 off();
731 safe_udelay(length);
732 }
733 #else
734 static void send_space(unsigned long len)
735 {
736 safe_udelay(len);
737 }
738
739 static void send_pulse(unsigned long len)
740 {
741 long bytes_out = len / TIME_CONST;
742 long time_left;
743
744 time_left = (long)len - (long)bytes_out * (long)TIME_CONST;
745 if (bytes_out == 0) {
746 bytes_out++;
747 time_left = 0;
748 }
749 while (bytes_out--) {
750 outb(PULSE, io + UART_TX);
751 /* FIXME treba seriozne cakanie z char/serial.c */
752 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
753 ;
754 }
755 #if 0
756 if (time_left > 0)
757 safe_udelay(time_left);
758 #endif
759 }
760 #endif
761
762 #ifdef CONFIG_SA1100_COLLIE
763 static int sa1100_irda_set_power_collie(int state)
764 {
765 if (state) {
766 /*
767 * 0 - off
768 * 1 - short range, lowest power
769 * 2 - medium range, medium power
770 * 3 - maximum range, high power
771 */
772 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
773 TC35143_IODIR_OUTPUT);
774 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
775 udelay(100);
776 } else {
777 /* OFF */
778 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
779 TC35143_IODIR_OUTPUT);
780 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
781 }
782 return 0;
783 }
784 #endif
785
786 static int init_hardware(void)
787 {
788 unsigned long flags;
789
790 spin_lock_irqsave(&hardware_lock, flags);
791 /* reset UART */
792 #ifdef LIRC_ON_SA1100
793 #ifdef CONFIG_SA1100_BITSY
794 if (machine_is_bitsy()) {
795 printk(KERN_INFO "Power on IR module\n");
796 set_bitsy_egpio(EGPIO_BITSY_IR_ON);
797 }
798 #endif
799 #ifdef CONFIG_SA1100_COLLIE
800 sa1100_irda_set_power_collie(3); /* power on */
801 #endif
802 sr.hscr0 = Ser2HSCR0;
803
804 sr.utcr0 = Ser2UTCR0;
805 sr.utcr1 = Ser2UTCR1;
806 sr.utcr2 = Ser2UTCR2;
807 sr.utcr3 = Ser2UTCR3;
808 sr.utcr4 = Ser2UTCR4;
809
810 sr.utdr = Ser2UTDR;
811 sr.utsr0 = Ser2UTSR0;
812 sr.utsr1 = Ser2UTSR1;
813
814 /* configure GPIO */
815 /* output */
816 PPDR |= PPC_TXD2;
817 PSDR |= PPC_TXD2;
818 /* set output to 0 */
819 off();
820
821 /* Enable HP-SIR modulation, and ensure that the port is disabled. */
822 Ser2UTCR3 = 0;
823 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
824
825 /* clear status register to prevent unwanted interrupts */
826 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
827
828 /* 7N1 */
829 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
830 /* 115200 */
831 Ser2UTCR1 = 0;
832 Ser2UTCR2 = 1;
833 /* use HPSIR, 1.6 usec pulses */
834 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
835
836 /* enable receiver, receive fifo interrupt */
837 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
838
839 /* clear status register to prevent unwanted interrupts */
840 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
841
842 #elif defined(LIRC_SIR_TEKRAM)
843 /* disable FIFO */
844 soutp(UART_FCR,
845 UART_FCR_CLEAR_RCVR|
846 UART_FCR_CLEAR_XMIT|
847 UART_FCR_TRIGGER_1);
848
849 /* Set DLAB 0. */
850 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
851
852 /* First of all, disable all interrupts */
853 soutp(UART_IER, sinp(UART_IER) &
854 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
855
856 /* Set DLAB 1. */
857 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
858
859 /* Set divisor to 12 => 9600 Baud */
860 soutp(UART_DLM, 0);
861 soutp(UART_DLL, 12);
862
863 /* Set DLAB 0. */
864 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
865
866 /* power supply */
867 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
868 safe_udelay(50*1000);
869
870 /* -DTR low -> reset PIC */
871 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
872 udelay(1*1000);
873
874 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
875 udelay(100);
876
877
878 /* -RTS low -> send control byte */
879 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
880 udelay(7);
881 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
882
883 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
884 udelay(1500);
885
886 /* back to normal operation */
887 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
888 udelay(50);
889
890 udelay(1500);
891
892 /* read previous control byte */
893 printk(KERN_INFO LIRC_DRIVER_NAME
894 ": 0x%02x\n", sinp(UART_RX));
895
896 /* Set DLAB 1. */
897 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
898
899 /* Set divisor to 1 => 115200 Baud */
900 soutp(UART_DLM, 0);
901 soutp(UART_DLL, 1);
902
903 /* Set DLAB 0, 8 Bit */
904 soutp(UART_LCR, UART_LCR_WLEN8);
905 /* enable interrupts */
906 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
907 #else
908 outb(0, io + UART_MCR);
909 outb(0, io + UART_IER);
910 /* init UART */
911 /* set DLAB, speed = 115200 */
912 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
913 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
914 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
915 outb(UART_LCR_WLEN7, io + UART_LCR);
916 /* FIFO operation */
917 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
918 /* interrupts */
919 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
920 outb(UART_IER_RDI, io + UART_IER);
921 /* turn on UART */
922 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
923 #ifdef LIRC_SIR_ACTISYS_ACT200L
924 init_act200();
925 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
926 init_act220();
927 #endif
928 #endif
929 spin_unlock_irqrestore(&hardware_lock, flags);
930 return 0;
931 }
932
933 static void drop_hardware(void)
934 {
935 unsigned long flags;
936
937 spin_lock_irqsave(&hardware_lock, flags);
938
939 #ifdef LIRC_ON_SA1100
940 Ser2UTCR3 = 0;
941
942 Ser2UTCR0 = sr.utcr0;
943 Ser2UTCR1 = sr.utcr1;
944 Ser2UTCR2 = sr.utcr2;
945 Ser2UTCR4 = sr.utcr4;
946 Ser2UTCR3 = sr.utcr3;
947
948 Ser2HSCR0 = sr.hscr0;
949 #ifdef CONFIG_SA1100_BITSY
950 if (machine_is_bitsy())
951 clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
952 #endif
953 #ifdef CONFIG_SA1100_COLLIE
954 sa1100_irda_set_power_collie(0); /* power off */
955 #endif
956 #else
957 /* turn off interrupts */
958 outb(0, io + UART_IER);
959 #endif
960 spin_unlock_irqrestore(&hardware_lock, flags);
961 }
962
963 /* SECTION: Initialisation */
964
965 static int init_port(void)
966 {
967 int retval;
968
969 /* get I/O port access and IRQ line */
970 #ifndef LIRC_ON_SA1100
971 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
972 printk(KERN_ERR LIRC_DRIVER_NAME
973 ": i/o port 0x%.4x already in use.\n", io);
974 return -EBUSY;
975 }
976 #endif
977 retval = request_irq(irq, sir_interrupt, IRQF_DISABLED,
978 LIRC_DRIVER_NAME, NULL);
979 if (retval < 0) {
980 # ifndef LIRC_ON_SA1100
981 release_region(io, 8);
982 # endif
983 printk(KERN_ERR LIRC_DRIVER_NAME
984 ": IRQ %d already in use.\n",
985 irq);
986 return retval;
987 }
988 #ifndef LIRC_ON_SA1100
989 printk(KERN_INFO LIRC_DRIVER_NAME
990 ": I/O port 0x%.4x, IRQ %d.\n",
991 io, irq);
992 #endif
993
994 init_timer(&timerlist);
995 timerlist.function = sir_timeout;
996 timerlist.data = 0xabadcafe;
997
998 return 0;
999 }
1000
1001 static void drop_port(void)
1002 {
1003 free_irq(irq, NULL);
1004 del_timer_sync(&timerlist);
1005 #ifndef LIRC_ON_SA1100
1006 release_region(io, 8);
1007 #endif
1008 }
1009
1010 #ifdef LIRC_SIR_ACTISYS_ACT200L
1011 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
1012 /* some code borrowed from Linux IRDA driver */
1013
1014 /* Register 0: Control register #1 */
1015 #define ACT200L_REG0 0x00
1016 #define ACT200L_TXEN 0x01 /* Enable transmitter */
1017 #define ACT200L_RXEN 0x02 /* Enable receiver */
1018 #define ACT200L_ECHO 0x08 /* Echo control chars */
1019
1020 /* Register 1: Control register #2 */
1021 #define ACT200L_REG1 0x10
1022 #define ACT200L_LODB 0x01 /* Load new baud rate count value */
1023 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
1024
1025 /* Register 3: Transmit mode register #2 */
1026 #define ACT200L_REG3 0x30
1027 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1028 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1029 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
1030
1031 /* Register 4: Output Power register */
1032 #define ACT200L_REG4 0x40
1033 #define ACT200L_OP0 0x01 /* Enable LED1C output */
1034 #define ACT200L_OP1 0x02 /* Enable LED2C output */
1035 #define ACT200L_BLKR 0x04
1036
1037 /* Register 5: Receive Mode register */
1038 #define ACT200L_REG5 0x50
1039 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
1040 /*.. other various IRDA bit modes, and TV remote modes..*/
1041
1042 /* Register 6: Receive Sensitivity register #1 */
1043 #define ACT200L_REG6 0x60
1044 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
1045 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
1046
1047 /* Register 7: Receive Sensitivity register #2 */
1048 #define ACT200L_REG7 0x70
1049 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
1050
1051 /* Register 8,9: Baud Rate Divider register #1,#2 */
1052 #define ACT200L_REG8 0x80
1053 #define ACT200L_REG9 0x90
1054
1055 #define ACT200L_2400 0x5f
1056 #define ACT200L_9600 0x17
1057 #define ACT200L_19200 0x0b
1058 #define ACT200L_38400 0x05
1059 #define ACT200L_57600 0x03
1060 #define ACT200L_115200 0x01
1061
1062 /* Register 13: Control register #3 */
1063 #define ACT200L_REG13 0xd0
1064 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
1065
1066 /* Register 15: Status register */
1067 #define ACT200L_REG15 0xf0
1068
1069 /* Register 21: Control register #4 */
1070 #define ACT200L_REG21 0x50
1071 #define ACT200L_EXCK 0x02 /* Disable clock output driver */
1072 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
1073
1074 static void init_act200(void)
1075 {
1076 int i;
1077 __u8 control[] = {
1078 ACT200L_REG15,
1079 ACT200L_REG13 | ACT200L_SHDW,
1080 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1081 ACT200L_REG13,
1082 ACT200L_REG7 | ACT200L_ENPOS,
1083 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
1084 ACT200L_REG5 | ACT200L_RWIDL,
1085 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
1086 ACT200L_REG3 | ACT200L_B0,
1087 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
1088 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
1089 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1090 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1091 };
1092
1093 /* Set DLAB 1. */
1094 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1095
1096 /* Set divisor to 12 => 9600 Baud */
1097 soutp(UART_DLM, 0);
1098 soutp(UART_DLL, 12);
1099
1100 /* Set DLAB 0. */
1101 soutp(UART_LCR, UART_LCR_WLEN8);
1102 /* Set divisor to 12 => 9600 Baud */
1103
1104 /* power supply */
1105 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1106 for (i = 0; i < 50; i++)
1107 safe_udelay(1000);
1108
1109 /* Reset the dongle : set RTS low for 25 ms */
1110 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1111 for (i = 0; i < 25; i++)
1112 udelay(1000);
1113
1114 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1115 udelay(100);
1116
1117 /* Clear DTR and set RTS to enter command mode */
1118 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1119 udelay(7);
1120
1121 /* send out the control register settings for 115K 7N1 SIR operation */
1122 for (i = 0; i < sizeof(control); i++) {
1123 soutp(UART_TX, control[i]);
1124 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1125 udelay(1500);
1126 }
1127
1128 /* back to normal operation */
1129 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1130 udelay(50);
1131
1132 udelay(1500);
1133 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1134
1135 /* Set DLAB 1. */
1136 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1137
1138 /* Set divisor to 1 => 115200 Baud */
1139 soutp(UART_DLM, 0);
1140 soutp(UART_DLL, 1);
1141
1142 /* Set DLAB 0. */
1143 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1144
1145 /* Set DLAB 0, 7 Bit */
1146 soutp(UART_LCR, UART_LCR_WLEN7);
1147
1148 /* enable interrupts */
1149 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1150 }
1151 #endif
1152
1153 #ifdef LIRC_SIR_ACTISYS_ACT220L
1154 /*
1155 * Derived from linux IrDA driver (net/irda/actisys.c)
1156 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1157 */
1158
1159 void init_act220(void)
1160 {
1161 int i;
1162
1163 /* DLAB 1 */
1164 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1165
1166 /* 9600 baud */
1167 soutp(UART_DLM, 0);
1168 soutp(UART_DLL, 12);
1169
1170 /* DLAB 0 */
1171 soutp(UART_LCR, UART_LCR_WLEN7);
1172
1173 /* reset the dongle, set DTR low for 10us */
1174 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1175 udelay(10);
1176
1177 /* back to normal (still 9600) */
1178 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1179
1180 /*
1181 * send RTS pulses until we reach 115200
1182 * i hope this is really the same for act220l/act220l+
1183 */
1184 for (i = 0; i < 3; i++) {
1185 udelay(10);
1186 /* set RTS low for 10 us */
1187 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1188 udelay(10);
1189 /* set RTS high for 10 us */
1190 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1191 }
1192
1193 /* back to normal operation */
1194 udelay(1500); /* better safe than sorry ;) */
1195
1196 /* Set DLAB 1. */
1197 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1198
1199 /* Set divisor to 1 => 115200 Baud */
1200 soutp(UART_DLM, 0);
1201 soutp(UART_DLL, 1);
1202
1203 /* Set DLAB 0, 7 Bit */
1204 /* The dongle doesn't seem to have any problems with operation at 7N1 */
1205 soutp(UART_LCR, UART_LCR_WLEN7);
1206
1207 /* enable interrupts */
1208 soutp(UART_IER, UART_IER_RDI);
1209 }
1210 #endif
1211
1212 static int init_lirc_sir(void)
1213 {
1214 int retval;
1215
1216 init_waitqueue_head(&lirc_read_queue);
1217 retval = init_port();
1218 if (retval < 0)
1219 return retval;
1220 init_hardware();
1221 printk(KERN_INFO LIRC_DRIVER_NAME
1222 ": Installed.\n");
1223 return 0;
1224 }
1225
1226
1227 static int __init lirc_sir_init(void)
1228 {
1229 int retval;
1230
1231 retval = init_chrdev();
1232 if (retval < 0)
1233 return retval;
1234 retval = init_lirc_sir();
1235 if (retval) {
1236 drop_chrdev();
1237 return retval;
1238 }
1239 return 0;
1240 }
1241
1242 static void __exit lirc_sir_exit(void)
1243 {
1244 drop_hardware();
1245 drop_chrdev();
1246 drop_port();
1247 printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n");
1248 }
1249
1250 module_init(lirc_sir_init);
1251 module_exit(lirc_sir_exit);
1252
1253 #ifdef LIRC_SIR_TEKRAM
1254 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1255 MODULE_AUTHOR("Christoph Bartelmus");
1256 #elif defined(LIRC_ON_SA1100)
1257 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1258 MODULE_AUTHOR("Christoph Bartelmus");
1259 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
1260 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1261 MODULE_AUTHOR("Karl Bongers");
1262 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
1263 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1264 MODULE_AUTHOR("Jan Roemisch");
1265 #else
1266 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1267 MODULE_AUTHOR("Milan Pikula");
1268 #endif
1269 MODULE_LICENSE("GPL");
1270
1271 #ifdef LIRC_ON_SA1100
1272 module_param(irq, int, S_IRUGO);
1273 MODULE_PARM_DESC(irq, "Interrupt (16)");
1274 #else
1275 module_param(io, int, S_IRUGO);
1276 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1277
1278 module_param(irq, int, S_IRUGO);
1279 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1280
1281 module_param(threshold, int, S_IRUGO);
1282 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1283 #endif
1284
1285 module_param(debug, bool, S_IRUGO | S_IWUSR);
1286 MODULE_PARM_DESC(debug, "Enable debugging messages");
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