x86, cpa: srlz cpa(), global flush tlb after splitting big page and before doing cpa
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / mm / pageattr.c
blobb6374d653d06d01a5bfe347f8f502aeee95b7e44
1 /*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
4 */
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
10 #include <linux/mm.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
15 #include <asm/e820.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/uaccess.h>
20 #include <asm/pgalloc.h>
21 #include <asm/proto.h>
22 #include <asm/pat.h>
25 * The current flushing context - we pass it instead of 5 arguments:
27 struct cpa_data {
28 unsigned long *vaddr;
29 pgprot_t mask_set;
30 pgprot_t mask_clr;
31 int numpages;
32 int flags;
33 unsigned long pfn;
34 unsigned force_split : 1;
35 int curpage;
39 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
40 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
41 * entries change the page attribute in parallel to some other cpu
42 * splitting a large page entry along with changing the attribute.
44 static DEFINE_SPINLOCK(cpa_lock);
46 #define CPA_FLUSHTLB 1
47 #define CPA_ARRAY 2
49 #ifdef CONFIG_PROC_FS
50 static unsigned long direct_pages_count[PG_LEVEL_NUM];
52 void update_page_count(int level, unsigned long pages)
54 unsigned long flags;
56 /* Protect against CPA */
57 spin_lock_irqsave(&pgd_lock, flags);
58 direct_pages_count[level] += pages;
59 spin_unlock_irqrestore(&pgd_lock, flags);
62 static void split_page_count(int level)
64 direct_pages_count[level]--;
65 direct_pages_count[level - 1] += PTRS_PER_PTE;
68 int arch_report_meminfo(char *page)
70 int n = sprintf(page, "DirectMap4k: %8lu kB\n",
71 direct_pages_count[PG_LEVEL_4K] << 2);
72 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
73 n += sprintf(page + n, "DirectMap2M: %8lu kB\n",
74 direct_pages_count[PG_LEVEL_2M] << 11);
75 #else
76 n += sprintf(page + n, "DirectMap4M: %8lu kB\n",
77 direct_pages_count[PG_LEVEL_2M] << 12);
78 #endif
79 #ifdef CONFIG_X86_64
80 if (direct_gbpages)
81 n += sprintf(page + n, "DirectMap1G: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_1G] << 20);
83 #endif
84 return n;
86 #else
87 static inline void split_page_count(int level) { }
88 #endif
90 #ifdef CONFIG_X86_64
92 static inline unsigned long highmap_start_pfn(void)
94 return __pa(_text) >> PAGE_SHIFT;
97 static inline unsigned long highmap_end_pfn(void)
99 return __pa(round_up((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT;
102 #endif
104 #ifdef CONFIG_DEBUG_PAGEALLOC
105 # define debug_pagealloc 1
106 #else
107 # define debug_pagealloc 0
108 #endif
110 static inline int
111 within(unsigned long addr, unsigned long start, unsigned long end)
113 return addr >= start && addr < end;
117 * Flushing functions
121 * clflush_cache_range - flush a cache range with clflush
122 * @addr: virtual start address
123 * @size: number of bytes to flush
125 * clflush is an unordered instruction which needs fencing with mfence
126 * to avoid ordering issues.
128 void clflush_cache_range(void *vaddr, unsigned int size)
130 void *vend = vaddr + size - 1;
132 mb();
134 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
135 clflush(vaddr);
137 * Flush any possible final partial cacheline:
139 clflush(vend);
141 mb();
144 static void __cpa_flush_all(void *arg)
146 unsigned long cache = (unsigned long)arg;
149 * Flush all to work around Errata in early athlons regarding
150 * large page flushing.
152 __flush_tlb_all();
154 if (cache && boot_cpu_data.x86_model >= 4)
155 wbinvd();
158 static void cpa_flush_all(unsigned long cache)
160 BUG_ON(irqs_disabled());
162 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
165 static void __cpa_flush_range(void *arg)
168 * We could optimize that further and do individual per page
169 * tlb invalidates for a low number of pages. Caveat: we must
170 * flush the high aliases on 64bit as well.
172 __flush_tlb_all();
175 static void cpa_flush_range(unsigned long start, int numpages, int cache)
177 unsigned int i, level;
178 unsigned long addr;
180 BUG_ON(irqs_disabled());
181 WARN_ON(PAGE_ALIGN(start) != start);
183 on_each_cpu(__cpa_flush_range, NULL, 1);
185 if (!cache)
186 return;
189 * We only need to flush on one CPU,
190 * clflush is a MESI-coherent instruction that
191 * will cause all other CPUs to flush the same
192 * cachelines:
194 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
195 pte_t *pte = lookup_address(addr, &level);
198 * Only flush present addresses:
200 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
201 clflush_cache_range((void *) addr, PAGE_SIZE);
205 static void cpa_flush_array(unsigned long *start, int numpages, int cache)
207 unsigned int i, level;
208 unsigned long *addr;
210 BUG_ON(irqs_disabled());
212 on_each_cpu(__cpa_flush_range, NULL, 1);
214 if (!cache)
215 return;
217 /* 4M threshold */
218 if (numpages >= 1024) {
219 if (boot_cpu_data.x86_model >= 4)
220 wbinvd();
221 return;
224 * We only need to flush on one CPU,
225 * clflush is a MESI-coherent instruction that
226 * will cause all other CPUs to flush the same
227 * cachelines:
229 for (i = 0, addr = start; i < numpages; i++, addr++) {
230 pte_t *pte = lookup_address(*addr, &level);
233 * Only flush present addresses:
235 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
236 clflush_cache_range((void *) *addr, PAGE_SIZE);
241 * Certain areas of memory on x86 require very specific protection flags,
242 * for example the BIOS area or kernel text. Callers don't always get this
243 * right (again, ioremap() on BIOS memory is not uncommon) so this function
244 * checks and fixes these known static required protection bits.
246 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
247 unsigned long pfn)
249 pgprot_t forbidden = __pgprot(0);
252 * The BIOS area between 640k and 1Mb needs to be executable for
253 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
255 if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
256 pgprot_val(forbidden) |= _PAGE_NX;
259 * The kernel text needs to be executable for obvious reasons
260 * Does not cover __inittext since that is gone later on. On
261 * 64bit we do not enforce !NX on the low mapping
263 if (within(address, (unsigned long)_text, (unsigned long)_etext))
264 pgprot_val(forbidden) |= _PAGE_NX;
267 * The .rodata section needs to be read-only. Using the pfn
268 * catches all aliases.
270 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
271 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
272 pgprot_val(forbidden) |= _PAGE_RW;
274 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
276 return prot;
280 * Lookup the page table entry for a virtual address. Return a pointer
281 * to the entry and the level of the mapping.
283 * Note: We return pud and pmd either when the entry is marked large
284 * or when the present bit is not set. Otherwise we would return a
285 * pointer to a nonexisting mapping.
287 pte_t *lookup_address(unsigned long address, unsigned int *level)
289 pgd_t *pgd = pgd_offset_k(address);
290 pud_t *pud;
291 pmd_t *pmd;
293 *level = PG_LEVEL_NONE;
295 if (pgd_none(*pgd))
296 return NULL;
298 pud = pud_offset(pgd, address);
299 if (pud_none(*pud))
300 return NULL;
302 *level = PG_LEVEL_1G;
303 if (pud_large(*pud) || !pud_present(*pud))
304 return (pte_t *)pud;
306 pmd = pmd_offset(pud, address);
307 if (pmd_none(*pmd))
308 return NULL;
310 *level = PG_LEVEL_2M;
311 if (pmd_large(*pmd) || !pmd_present(*pmd))
312 return (pte_t *)pmd;
314 *level = PG_LEVEL_4K;
316 return pte_offset_kernel(pmd, address);
318 EXPORT_SYMBOL_GPL(lookup_address);
321 * Set the new pmd in all the pgds we know about:
323 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
325 /* change init_mm */
326 set_pte_atomic(kpte, pte);
327 #ifdef CONFIG_X86_32
328 if (!SHARED_KERNEL_PMD) {
329 struct page *page;
331 list_for_each_entry(page, &pgd_list, lru) {
332 pgd_t *pgd;
333 pud_t *pud;
334 pmd_t *pmd;
336 pgd = (pgd_t *)page_address(page) + pgd_index(address);
337 pud = pud_offset(pgd, address);
338 pmd = pmd_offset(pud, address);
339 set_pte_atomic((pte_t *)pmd, pte);
342 #endif
345 static int
346 try_preserve_large_page(pte_t *kpte, unsigned long address,
347 struct cpa_data *cpa)
349 unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
350 pte_t new_pte, old_pte, *tmp;
351 pgprot_t old_prot, new_prot;
352 int i, do_split = 1;
353 unsigned int level;
355 if (cpa->force_split)
356 return 1;
358 spin_lock_irqsave(&pgd_lock, flags);
360 * Check for races, another CPU might have split this page
361 * up already:
363 tmp = lookup_address(address, &level);
364 if (tmp != kpte)
365 goto out_unlock;
367 switch (level) {
368 case PG_LEVEL_2M:
369 psize = PMD_PAGE_SIZE;
370 pmask = PMD_PAGE_MASK;
371 break;
372 #ifdef CONFIG_X86_64
373 case PG_LEVEL_1G:
374 psize = PUD_PAGE_SIZE;
375 pmask = PUD_PAGE_MASK;
376 break;
377 #endif
378 default:
379 do_split = -EINVAL;
380 goto out_unlock;
384 * Calculate the number of pages, which fit into this large
385 * page starting at address:
387 nextpage_addr = (address + psize) & pmask;
388 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
389 if (numpages < cpa->numpages)
390 cpa->numpages = numpages;
393 * We are safe now. Check whether the new pgprot is the same:
395 old_pte = *kpte;
396 old_prot = new_prot = pte_pgprot(old_pte);
398 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
399 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
402 * old_pte points to the large page base address. So we need
403 * to add the offset of the virtual address:
405 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
406 cpa->pfn = pfn;
408 new_prot = static_protections(new_prot, address, pfn);
411 * We need to check the full range, whether
412 * static_protection() requires a different pgprot for one of
413 * the pages in the range we try to preserve:
415 addr = address + PAGE_SIZE;
416 pfn++;
417 for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
418 pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
420 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
421 goto out_unlock;
425 * If there are no changes, return. maxpages has been updated
426 * above:
428 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
429 do_split = 0;
430 goto out_unlock;
434 * We need to change the attributes. Check, whether we can
435 * change the large page in one go. We request a split, when
436 * the address is not aligned and the number of pages is
437 * smaller than the number of pages in the large page. Note
438 * that we limited the number of possible pages already to
439 * the number of pages in the large page.
441 if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
443 * The address is aligned and the number of pages
444 * covers the full page.
446 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
447 __set_pmd_pte(kpte, address, new_pte);
448 cpa->flags |= CPA_FLUSHTLB;
449 do_split = 0;
452 out_unlock:
453 spin_unlock_irqrestore(&pgd_lock, flags);
455 return do_split;
458 static int split_large_page(pte_t *kpte, unsigned long address)
460 unsigned long flags, pfn, pfninc = 1;
461 unsigned int i, level;
462 pte_t *pbase, *tmp;
463 pgprot_t ref_prot;
464 struct page *base;
466 if (!debug_pagealloc)
467 spin_unlock(&cpa_lock);
468 base = alloc_pages(GFP_KERNEL, 0);
469 if (!debug_pagealloc)
470 spin_lock(&cpa_lock);
471 if (!base)
472 return -ENOMEM;
474 spin_lock_irqsave(&pgd_lock, flags);
476 * Check for races, another CPU might have split this page
477 * up for us already:
479 tmp = lookup_address(address, &level);
480 if (tmp != kpte)
481 goto out_unlock;
483 pbase = (pte_t *)page_address(base);
484 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
485 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
487 #ifdef CONFIG_X86_64
488 if (level == PG_LEVEL_1G) {
489 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
490 pgprot_val(ref_prot) |= _PAGE_PSE;
492 #endif
495 * Get the target pfn from the original entry:
497 pfn = pte_pfn(*kpte);
498 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
499 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
501 if (address >= (unsigned long)__va(0) &&
502 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
503 split_page_count(level);
505 #ifdef CONFIG_X86_64
506 if (address >= (unsigned long)__va(1UL<<32) &&
507 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
508 split_page_count(level);
509 #endif
512 * Install the new, split up pagetable. Important details here:
514 * On Intel the NX bit of all levels must be cleared to make a
515 * page executable. See section 4.13.2 of Intel 64 and IA-32
516 * Architectures Software Developer's Manual).
518 * Mark the entry present. The current mapping might be
519 * set to not present, which we preserved above.
521 ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
522 pgprot_val(ref_prot) |= _PAGE_PRESENT;
523 __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
524 base = NULL;
526 out_unlock:
528 * If we dropped out via the lookup_address check under
529 * pgd_lock then stick the page back into the pool:
531 if (base)
532 __free_page(base);
533 spin_unlock_irqrestore(&pgd_lock, flags);
535 return 0;
538 static int __change_page_attr(struct cpa_data *cpa, int primary)
540 unsigned long address;
541 int do_split, err;
542 unsigned int level;
543 pte_t *kpte, old_pte;
545 if (cpa->flags & CPA_ARRAY)
546 address = cpa->vaddr[cpa->curpage];
547 else
548 address = *cpa->vaddr;
550 repeat:
551 kpte = lookup_address(address, &level);
552 if (!kpte)
553 return 0;
555 old_pte = *kpte;
556 if (!pte_val(old_pte)) {
557 if (!primary)
558 return 0;
559 WARN(1, KERN_WARNING "CPA: called for zero pte. "
560 "vaddr = %lx cpa->vaddr = %lx\n", address,
561 *cpa->vaddr);
562 return -EINVAL;
565 if (level == PG_LEVEL_4K) {
566 pte_t new_pte;
567 pgprot_t new_prot = pte_pgprot(old_pte);
568 unsigned long pfn = pte_pfn(old_pte);
570 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
571 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
573 new_prot = static_protections(new_prot, address, pfn);
576 * We need to keep the pfn from the existing PTE,
577 * after all we're only going to change it's attributes
578 * not the memory it points to
580 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
581 cpa->pfn = pfn;
583 * Do we really change anything ?
585 if (pte_val(old_pte) != pte_val(new_pte)) {
586 set_pte_atomic(kpte, new_pte);
587 cpa->flags |= CPA_FLUSHTLB;
589 cpa->numpages = 1;
590 return 0;
594 * Check, whether we can keep the large page intact
595 * and just change the pte:
597 do_split = try_preserve_large_page(kpte, address, cpa);
599 * When the range fits into the existing large page,
600 * return. cp->numpages and cpa->tlbflush have been updated in
601 * try_large_page:
603 if (do_split <= 0)
604 return do_split;
607 * We have to split the large page:
609 err = split_large_page(kpte, address);
610 if (!err) {
612 * Do a global flush tlb after splitting the large page
613 * and before we do the actual change page attribute in the PTE.
615 * With out this, we violate the TLB application note, that says
616 * "The TLBs may contain both ordinary and large-page
617 * translations for a 4-KByte range of linear addresses. This
618 * may occur if software modifies the paging structures so that
619 * the page size used for the address range changes. If the two
620 * translations differ with respect to page frame or attributes
621 * (e.g., permissions), processor behavior is undefined and may
622 * be implementation-specific."
624 * We do this global tlb flush inside the cpa_lock, so that we
625 * don't allow any other cpu, with stale tlb entries change the
626 * page attribute in parallel, that also falls into the
627 * just split large page entry.
629 flush_tlb_all();
630 goto repeat;
633 return err;
636 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
638 static int cpa_process_alias(struct cpa_data *cpa)
640 struct cpa_data alias_cpa;
641 int ret = 0;
642 unsigned long temp_cpa_vaddr, vaddr;
644 if (cpa->pfn >= max_pfn_mapped)
645 return 0;
647 #ifdef CONFIG_X86_64
648 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
649 return 0;
650 #endif
652 * No need to redo, when the primary call touched the direct
653 * mapping already:
655 if (cpa->flags & CPA_ARRAY)
656 vaddr = cpa->vaddr[cpa->curpage];
657 else
658 vaddr = *cpa->vaddr;
660 if (!(within(vaddr, PAGE_OFFSET,
661 PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT))
662 #ifdef CONFIG_X86_64
663 || within(vaddr, PAGE_OFFSET + (1UL<<32),
664 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))
665 #endif
666 )) {
668 alias_cpa = *cpa;
669 temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT);
670 alias_cpa.vaddr = &temp_cpa_vaddr;
671 alias_cpa.flags &= ~CPA_ARRAY;
674 ret = __change_page_attr_set_clr(&alias_cpa, 0);
677 #ifdef CONFIG_X86_64
678 if (ret)
679 return ret;
681 * No need to redo, when the primary call touched the high
682 * mapping already:
684 if (within(vaddr, (unsigned long) _text, (unsigned long) _end))
685 return 0;
688 * If the physical address is inside the kernel map, we need
689 * to touch the high mapped kernel as well:
691 if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn()))
692 return 0;
694 alias_cpa = *cpa;
695 temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base;
696 alias_cpa.vaddr = &temp_cpa_vaddr;
697 alias_cpa.flags &= ~CPA_ARRAY;
700 * The high mapping range is imprecise, so ignore the return value.
702 __change_page_attr_set_clr(&alias_cpa, 0);
703 #endif
704 return ret;
707 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
709 int ret, numpages = cpa->numpages;
711 while (numpages) {
713 * Store the remaining nr of pages for the large page
714 * preservation check.
716 cpa->numpages = numpages;
717 /* for array changes, we can't use large page */
718 if (cpa->flags & CPA_ARRAY)
719 cpa->numpages = 1;
721 if (!debug_pagealloc)
722 spin_lock(&cpa_lock);
723 ret = __change_page_attr(cpa, checkalias);
724 if (!debug_pagealloc)
725 spin_unlock(&cpa_lock);
726 if (ret)
727 return ret;
729 if (checkalias) {
730 ret = cpa_process_alias(cpa);
731 if (ret)
732 return ret;
736 * Adjust the number of pages with the result of the
737 * CPA operation. Either a large page has been
738 * preserved or a single page update happened.
740 BUG_ON(cpa->numpages > numpages);
741 numpages -= cpa->numpages;
742 if (cpa->flags & CPA_ARRAY)
743 cpa->curpage++;
744 else
745 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
748 return 0;
751 static inline int cache_attr(pgprot_t attr)
753 return pgprot_val(attr) &
754 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
757 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
758 pgprot_t mask_set, pgprot_t mask_clr,
759 int force_split, int array)
761 struct cpa_data cpa;
762 int ret, cache, checkalias;
765 * Check, if we are requested to change a not supported
766 * feature:
768 mask_set = canon_pgprot(mask_set);
769 mask_clr = canon_pgprot(mask_clr);
770 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
771 return 0;
773 /* Ensure we are PAGE_SIZE aligned */
774 if (!array) {
775 if (*addr & ~PAGE_MASK) {
776 *addr &= PAGE_MASK;
778 * People should not be passing in unaligned addresses:
780 WARN_ON_ONCE(1);
782 } else {
783 int i;
784 for (i = 0; i < numpages; i++) {
785 if (addr[i] & ~PAGE_MASK) {
786 addr[i] &= PAGE_MASK;
787 WARN_ON_ONCE(1);
792 /* Must avoid aliasing mappings in the highmem code */
793 kmap_flush_unused();
795 cpa.vaddr = addr;
796 cpa.numpages = numpages;
797 cpa.mask_set = mask_set;
798 cpa.mask_clr = mask_clr;
799 cpa.flags = 0;
800 cpa.curpage = 0;
801 cpa.force_split = force_split;
803 if (array)
804 cpa.flags |= CPA_ARRAY;
806 /* No alias checking for _NX bit modifications */
807 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
809 ret = __change_page_attr_set_clr(&cpa, checkalias);
812 * Check whether we really changed something:
814 if (!(cpa.flags & CPA_FLUSHTLB))
815 goto out;
818 * No need to flush, when we did not set any of the caching
819 * attributes:
821 cache = cache_attr(mask_set);
824 * On success we use clflush, when the CPU supports it to
825 * avoid the wbindv. If the CPU does not support it and in the
826 * error case we fall back to cpa_flush_all (which uses
827 * wbindv):
829 if (!ret && cpu_has_clflush) {
830 if (cpa.flags & CPA_ARRAY)
831 cpa_flush_array(addr, numpages, cache);
832 else
833 cpa_flush_range(*addr, numpages, cache);
834 } else
835 cpa_flush_all(cache);
837 out:
838 return ret;
841 static inline int change_page_attr_set(unsigned long *addr, int numpages,
842 pgprot_t mask, int array)
844 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
845 array);
848 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
849 pgprot_t mask, int array)
851 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
852 array);
855 int _set_memory_uc(unsigned long addr, int numpages)
858 * for now UC MINUS. see comments in ioremap_nocache()
860 return change_page_attr_set(&addr, numpages,
861 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
864 int set_memory_uc(unsigned long addr, int numpages)
867 * for now UC MINUS. see comments in ioremap_nocache()
869 if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
870 _PAGE_CACHE_UC_MINUS, NULL))
871 return -EINVAL;
873 return _set_memory_uc(addr, numpages);
875 EXPORT_SYMBOL(set_memory_uc);
877 int set_memory_array_uc(unsigned long *addr, int addrinarray)
879 unsigned long start;
880 unsigned long end;
881 int i;
883 * for now UC MINUS. see comments in ioremap_nocache()
885 for (i = 0; i < addrinarray; i++) {
886 start = __pa(addr[i]);
887 for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
888 if (end != __pa(addr[i + 1]))
889 break;
890 i++;
892 if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL))
893 goto out;
896 return change_page_attr_set(addr, addrinarray,
897 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
898 out:
899 for (i = 0; i < addrinarray; i++) {
900 unsigned long tmp = __pa(addr[i]);
902 if (tmp == start)
903 break;
904 for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
905 if (end != __pa(addr[i + 1]))
906 break;
907 i++;
909 free_memtype(tmp, end);
911 return -EINVAL;
913 EXPORT_SYMBOL(set_memory_array_uc);
915 int _set_memory_wc(unsigned long addr, int numpages)
917 return change_page_attr_set(&addr, numpages,
918 __pgprot(_PAGE_CACHE_WC), 0);
921 int set_memory_wc(unsigned long addr, int numpages)
923 if (!pat_enabled)
924 return set_memory_uc(addr, numpages);
926 if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
927 _PAGE_CACHE_WC, NULL))
928 return -EINVAL;
930 return _set_memory_wc(addr, numpages);
932 EXPORT_SYMBOL(set_memory_wc);
934 int _set_memory_wb(unsigned long addr, int numpages)
936 return change_page_attr_clear(&addr, numpages,
937 __pgprot(_PAGE_CACHE_MASK), 0);
940 int set_memory_wb(unsigned long addr, int numpages)
942 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
944 return _set_memory_wb(addr, numpages);
946 EXPORT_SYMBOL(set_memory_wb);
948 int set_memory_array_wb(unsigned long *addr, int addrinarray)
950 int i;
952 for (i = 0; i < addrinarray; i++) {
953 unsigned long start = __pa(addr[i]);
954 unsigned long end;
956 for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) {
957 if (end != __pa(addr[i + 1]))
958 break;
959 i++;
961 free_memtype(start, end);
963 return change_page_attr_clear(addr, addrinarray,
964 __pgprot(_PAGE_CACHE_MASK), 1);
966 EXPORT_SYMBOL(set_memory_array_wb);
968 int set_memory_x(unsigned long addr, int numpages)
970 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
972 EXPORT_SYMBOL(set_memory_x);
974 int set_memory_nx(unsigned long addr, int numpages)
976 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
978 EXPORT_SYMBOL(set_memory_nx);
980 int set_memory_ro(unsigned long addr, int numpages)
982 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
985 int set_memory_rw(unsigned long addr, int numpages)
987 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
990 int set_memory_np(unsigned long addr, int numpages)
992 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
995 int set_memory_4k(unsigned long addr, int numpages)
997 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
998 __pgprot(0), 1, 0);
1001 int set_pages_uc(struct page *page, int numpages)
1003 unsigned long addr = (unsigned long)page_address(page);
1005 return set_memory_uc(addr, numpages);
1007 EXPORT_SYMBOL(set_pages_uc);
1009 int set_pages_wb(struct page *page, int numpages)
1011 unsigned long addr = (unsigned long)page_address(page);
1013 return set_memory_wb(addr, numpages);
1015 EXPORT_SYMBOL(set_pages_wb);
1017 int set_pages_x(struct page *page, int numpages)
1019 unsigned long addr = (unsigned long)page_address(page);
1021 return set_memory_x(addr, numpages);
1023 EXPORT_SYMBOL(set_pages_x);
1025 int set_pages_nx(struct page *page, int numpages)
1027 unsigned long addr = (unsigned long)page_address(page);
1029 return set_memory_nx(addr, numpages);
1031 EXPORT_SYMBOL(set_pages_nx);
1033 int set_pages_ro(struct page *page, int numpages)
1035 unsigned long addr = (unsigned long)page_address(page);
1037 return set_memory_ro(addr, numpages);
1040 int set_pages_rw(struct page *page, int numpages)
1042 unsigned long addr = (unsigned long)page_address(page);
1044 return set_memory_rw(addr, numpages);
1047 #ifdef CONFIG_DEBUG_PAGEALLOC
1049 static int __set_pages_p(struct page *page, int numpages)
1051 unsigned long tempaddr = (unsigned long) page_address(page);
1052 struct cpa_data cpa = { .vaddr = &tempaddr,
1053 .numpages = numpages,
1054 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1055 .mask_clr = __pgprot(0),
1056 .flags = 0};
1059 * No alias checking needed for setting present flag. otherwise,
1060 * we may need to break large pages for 64-bit kernel text
1061 * mappings (this adds to complexity if we want to do this from
1062 * atomic context especially). Let's keep it simple!
1064 return __change_page_attr_set_clr(&cpa, 0);
1067 static int __set_pages_np(struct page *page, int numpages)
1069 unsigned long tempaddr = (unsigned long) page_address(page);
1070 struct cpa_data cpa = { .vaddr = &tempaddr,
1071 .numpages = numpages,
1072 .mask_set = __pgprot(0),
1073 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1074 .flags = 0};
1077 * No alias checking needed for setting not present flag. otherwise,
1078 * we may need to break large pages for 64-bit kernel text
1079 * mappings (this adds to complexity if we want to do this from
1080 * atomic context especially). Let's keep it simple!
1082 return __change_page_attr_set_clr(&cpa, 0);
1085 void kernel_map_pages(struct page *page, int numpages, int enable)
1087 if (PageHighMem(page))
1088 return;
1089 if (!enable) {
1090 debug_check_no_locks_freed(page_address(page),
1091 numpages * PAGE_SIZE);
1095 * If page allocator is not up yet then do not call c_p_a():
1097 if (!debug_pagealloc_enabled)
1098 return;
1101 * The return value is ignored as the calls cannot fail.
1102 * Large pages for identity mappings are not used at boot time
1103 * and hence no memory allocations during large page split.
1105 if (enable)
1106 __set_pages_p(page, numpages);
1107 else
1108 __set_pages_np(page, numpages);
1111 * We should perform an IPI and flush all tlbs,
1112 * but that can deadlock->flush only current cpu:
1114 __flush_tlb_all();
1117 #ifdef CONFIG_HIBERNATION
1119 bool kernel_page_present(struct page *page)
1121 unsigned int level;
1122 pte_t *pte;
1124 if (PageHighMem(page))
1125 return false;
1127 pte = lookup_address((unsigned long)page_address(page), &level);
1128 return (pte_val(*pte) & _PAGE_PRESENT);
1131 #endif /* CONFIG_HIBERNATION */
1133 #endif /* CONFIG_DEBUG_PAGEALLOC */
1136 * The testcases use internal knowledge of the implementation that shouldn't
1137 * be exposed to the rest of the kernel. Include these directly here.
1139 #ifdef CONFIG_CPA_DEBUG
1140 #include "pageattr-test.c"
1141 #endif