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mlx4_en: Checksum counters per ring
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
blobed452ddfe3426606ac651cf22d6136f77e364857
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
37
38 #include "fw.h"
39 #include "icm.h"
40
41 enum {
42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
45 };
46
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
49
50 static int enable_qos;
51 module_param(enable_qos, bool, 0444);
52 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
54 #define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66 #define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
79 {
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
92 [12] = "DPDP",
93 [15] = "Big LSO headers",
94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support",
102 [30] = "IBoE support",
103 [32] = "Unicast loopback support",
104 [34] = "FCS header control",
105 [38] = "Wake On LAN support",
106 [40] = "UDP RSS support",
107 [41] = "Unicast VEP steering support",
108 [42] = "Multicast VEP steering support",
109 [48] = "Counters support",
110 };
111 int i;
112
113 mlx4_dbg(dev, "DEV_CAP flags:\n");
114 for (i = 0; i < ARRAY_SIZE(fname); ++i)
115 if (fname[i] && (flags & (1LL << i)))
116 mlx4_dbg(dev, " %s\n", fname[i]);
117 }
118
119 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
120 {
121 struct mlx4_cmd_mailbox *mailbox;
122 u32 *inbox;
123 int err = 0;
124
125 #define MOD_STAT_CFG_IN_SIZE 0x100
126
127 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
128 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
129
130 mailbox = mlx4_alloc_cmd_mailbox(dev);
131 if (IS_ERR(mailbox))
132 return PTR_ERR(mailbox);
133 inbox = mailbox->buf;
134
135 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
136
137 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
138 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
139
140 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
141 MLX4_CMD_TIME_CLASS_A);
142
143 mlx4_free_cmd_mailbox(dev, mailbox);
144 return err;
145 }
146
147 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
148 {
149 struct mlx4_cmd_mailbox *mailbox;
150 u32 *outbox;
151 u8 field;
152 u32 field32, flags, ext_flags;
153 u16 size;
154 u16 stat_rate;
155 int err;
156 int i;
157
158 #define QUERY_DEV_CAP_OUT_SIZE 0x100
159 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
160 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
161 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
162 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
163 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
164 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
165 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
166 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
167 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
168 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
169 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
170 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
171 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
172 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
173 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
174 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
175 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
176 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
177 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
178 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
179 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
180 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
181 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
182 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
183 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
184 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
185 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
186 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
187 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
188 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
189 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
190 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
191 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
192 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
193 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
194 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
195 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
196 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
197 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
198 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
199 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
200 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
201 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
202 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
203 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
204 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
205 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
206 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
207 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
208 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
209 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
210 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
211 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
212 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
213 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
214 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
215 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
216 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
217 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
218 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
219 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
220 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
221 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
222
223 mailbox = mlx4_alloc_cmd_mailbox(dev);
224 if (IS_ERR(mailbox))
225 return PTR_ERR(mailbox);
226 outbox = mailbox->buf;
227
228 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
229 MLX4_CMD_TIME_CLASS_A);
230 if (err)
231 goto out;
232
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
234 dev_cap->reserved_qps = 1 << (field & 0xf);
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
236 dev_cap->max_qps = 1 << (field & 0x1f);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
238 dev_cap->reserved_srqs = 1 << (field >> 4);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
240 dev_cap->max_srqs = 1 << (field & 0x1f);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
242 dev_cap->max_cq_sz = 1 << field;
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
244 dev_cap->reserved_cqs = 1 << (field & 0xf);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
246 dev_cap->max_cqs = 1 << (field & 0x1f);
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
248 dev_cap->max_mpts = 1 << (field & 0x3f);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
250 dev_cap->reserved_eqs = field & 0xf;
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
252 dev_cap->max_eqs = 1 << (field & 0xf);
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
254 dev_cap->reserved_mtts = 1 << (field >> 4);
255 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
256 dev_cap->max_mrw_sz = 1 << field;
257 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
258 dev_cap->reserved_mrws = 1 << (field & 0xf);
259 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
260 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
261 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
262 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
263 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
264 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
266 field &= 0x1f;
267 if (!field)
268 dev_cap->max_gso_sz = 0;
269 else
270 dev_cap->max_gso_sz = 1 << field;
271
272 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
273 dev_cap->max_rdma_global = 1 << (field & 0x3f);
274 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
275 dev_cap->local_ca_ack_delay = field & 0x1f;
276 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
277 dev_cap->num_ports = field & 0xf;
278 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
279 dev_cap->max_msg_sz = 1 << (field & 0x1f);
280 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
281 dev_cap->stat_rate_support = stat_rate;
282 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
283 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
284 dev_cap->flags = flags | (u64)ext_flags << 32;
285 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
286 dev_cap->reserved_uars = field >> 4;
287 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
288 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
290 dev_cap->min_page_sz = 1 << field;
291
292 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
293 if (field & 0x80) {
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
295 dev_cap->bf_reg_size = 1 << (field & 0x1f);
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
297 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
298 field = 3;
299 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
300 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
301 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
302 } else {
303 dev_cap->bf_reg_size = 0;
304 mlx4_dbg(dev, "BlueFlame not available\n");
305 }
306
307 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
308 dev_cap->max_sq_sg = field;
309 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
310 dev_cap->max_sq_desc_sz = size;
311
312 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
313 dev_cap->max_qp_per_mcg = 1 << field;
314 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
315 dev_cap->reserved_mgms = field & 0xf;
316 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
317 dev_cap->max_mcgs = 1 << field;
318 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
319 dev_cap->reserved_pds = field >> 4;
320 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
321 dev_cap->max_pds = 1 << (field & 0x3f);
322
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
324 dev_cap->rdmarc_entry_sz = size;
325 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
326 dev_cap->qpc_entry_sz = size;
327 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
328 dev_cap->aux_entry_sz = size;
329 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
330 dev_cap->altc_entry_sz = size;
331 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
332 dev_cap->eqc_entry_sz = size;
333 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
334 dev_cap->cqc_entry_sz = size;
335 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
336 dev_cap->srq_entry_sz = size;
337 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
338 dev_cap->cmpt_entry_sz = size;
339 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
340 dev_cap->mtt_entry_sz = size;
341 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
342 dev_cap->dmpt_entry_sz = size;
343
344 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
345 dev_cap->max_srq_sz = 1 << field;
346 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
347 dev_cap->max_qp_sz = 1 << field;
348 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
349 dev_cap->resize_srq = field & 1;
350 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
351 dev_cap->max_rq_sg = field;
352 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
353 dev_cap->max_rq_desc_sz = size;
354
355 MLX4_GET(dev_cap->bmme_flags, outbox,
356 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
357 MLX4_GET(dev_cap->reserved_lkey, outbox,
358 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
359 MLX4_GET(dev_cap->max_icm_sz, outbox,
360 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
361 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
362 MLX4_GET(dev_cap->max_counters, outbox,
363 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
364
365 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
366 for (i = 1; i <= dev_cap->num_ports; ++i) {
367 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
368 dev_cap->max_vl[i] = field >> 4;
369 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
370 dev_cap->ib_mtu[i] = field >> 4;
371 dev_cap->max_port_width[i] = field & 0xf;
372 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
373 dev_cap->max_gids[i] = 1 << (field & 0xf);
374 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
375 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
376 }
377 } else {
378 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
379 #define QUERY_PORT_MTU_OFFSET 0x01
380 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
381 #define QUERY_PORT_WIDTH_OFFSET 0x06
382 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
383 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
384 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
385 #define QUERY_PORT_MAC_OFFSET 0x10
386 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
387 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
388 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
389
390 for (i = 1; i <= dev_cap->num_ports; ++i) {
391 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
392 MLX4_CMD_TIME_CLASS_B);
393 if (err)
394 goto out;
395
396 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
397 dev_cap->supported_port_types[i] = field & 3;
398 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
399 dev_cap->ib_mtu[i] = field & 0xf;
400 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
401 dev_cap->max_port_width[i] = field & 0xf;
402 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
403 dev_cap->max_gids[i] = 1 << (field >> 4);
404 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
405 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
406 dev_cap->max_vl[i] = field & 0xf;
407 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
408 dev_cap->log_max_macs[i] = field & 0xf;
409 dev_cap->log_max_vlans[i] = field >> 4;
410 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
411 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
412 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
413 dev_cap->trans_type[i] = field32 >> 24;
414 dev_cap->vendor_oui[i] = field32 & 0xffffff;
415 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
416 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
417 }
418 }
419
420 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
421 dev_cap->bmme_flags, dev_cap->reserved_lkey);
422
423 /*
424 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
425 * we can't use any EQs whose doorbell falls on that page,
426 * even if the EQ itself isn't reserved.
427 */
428 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
429 dev_cap->reserved_eqs);
430
431 mlx4_dbg(dev, "Max ICM size %lld MB\n",
432 (unsigned long long) dev_cap->max_icm_sz >> 20);
433 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
434 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
435 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
436 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
437 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
438 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
439 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
440 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
441 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
442 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
443 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
444 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
445 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
446 dev_cap->max_pds, dev_cap->reserved_mgms);
447 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
448 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
449 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
450 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
451 dev_cap->max_port_width[1]);
452 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
453 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
454 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
455 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
456 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
457 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
458
459 dump_dev_cap_flags(dev, dev_cap->flags);
460
461 out:
462 mlx4_free_cmd_mailbox(dev, mailbox);
463 return err;
464 }
465
466 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
467 {
468 struct mlx4_cmd_mailbox *mailbox;
469 struct mlx4_icm_iter iter;
470 __be64 *pages;
471 int lg;
472 int nent = 0;
473 int i;
474 int err = 0;
475 int ts = 0, tc = 0;
476
477 mailbox = mlx4_alloc_cmd_mailbox(dev);
478 if (IS_ERR(mailbox))
479 return PTR_ERR(mailbox);
480 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
481 pages = mailbox->buf;
482
483 for (mlx4_icm_first(icm, &iter);
484 !mlx4_icm_last(&iter);
485 mlx4_icm_next(&iter)) {
486 /*
487 * We have to pass pages that are aligned to their
488 * size, so find the least significant 1 in the
489 * address or size and use that as our log2 size.
490 */
491 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
492 if (lg < MLX4_ICM_PAGE_SHIFT) {
493 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
494 MLX4_ICM_PAGE_SIZE,
495 (unsigned long long) mlx4_icm_addr(&iter),
496 mlx4_icm_size(&iter));
497 err = -EINVAL;
498 goto out;
499 }
500
501 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
502 if (virt != -1) {
503 pages[nent * 2] = cpu_to_be64(virt);
504 virt += 1 << lg;
505 }
506
507 pages[nent * 2 + 1] =
508 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
509 (lg - MLX4_ICM_PAGE_SHIFT));
510 ts += 1 << (lg - 10);
511 ++tc;
512
513 if (++nent == MLX4_MAILBOX_SIZE / 16) {
514 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
515 MLX4_CMD_TIME_CLASS_B);
516 if (err)
517 goto out;
518 nent = 0;
519 }
520 }
521 }
522
523 if (nent)
524 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
525 if (err)
526 goto out;
527
528 switch (op) {
529 case MLX4_CMD_MAP_FA:
530 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
531 break;
532 case MLX4_CMD_MAP_ICM_AUX:
533 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
534 break;
535 case MLX4_CMD_MAP_ICM:
536 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
537 tc, ts, (unsigned long long) virt - (ts << 10));
538 break;
539 }
540
541 out:
542 mlx4_free_cmd_mailbox(dev, mailbox);
543 return err;
544 }
545
546 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
547 {
548 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
549 }
550
551 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
552 {
553 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
554 }
555
556
557 int mlx4_RUN_FW(struct mlx4_dev *dev)
558 {
559 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
560 }
561
562 int mlx4_QUERY_FW(struct mlx4_dev *dev)
563 {
564 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
565 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
566 struct mlx4_cmd_mailbox *mailbox;
567 u32 *outbox;
568 int err = 0;
569 u64 fw_ver;
570 u16 cmd_if_rev;
571 u8 lg;
572
573 #define QUERY_FW_OUT_SIZE 0x100
574 #define QUERY_FW_VER_OFFSET 0x00
575 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
576 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
577 #define QUERY_FW_ERR_START_OFFSET 0x30
578 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
579 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
580
581 #define QUERY_FW_SIZE_OFFSET 0x00
582 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
583 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
584
585 mailbox = mlx4_alloc_cmd_mailbox(dev);
586 if (IS_ERR(mailbox))
587 return PTR_ERR(mailbox);
588 outbox = mailbox->buf;
589
590 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
591 MLX4_CMD_TIME_CLASS_A);
592 if (err)
593 goto out;
594
595 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
596 /*
597 * FW subminor version is at more significant bits than minor
598 * version, so swap here.
599 */
600 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
601 ((fw_ver & 0xffff0000ull) >> 16) |
602 ((fw_ver & 0x0000ffffull) << 16);
603
604 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
605 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
606 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
607 mlx4_err(dev, "Installed FW has unsupported "
608 "command interface revision %d.\n",
609 cmd_if_rev);
610 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
611 (int) (dev->caps.fw_ver >> 32),
612 (int) (dev->caps.fw_ver >> 16) & 0xffff,
613 (int) dev->caps.fw_ver & 0xffff);
614 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
615 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
616 err = -ENODEV;
617 goto out;
618 }
619
620 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
621 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
622
623 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
624 cmd->max_cmds = 1 << lg;
625
626 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
627 (int) (dev->caps.fw_ver >> 32),
628 (int) (dev->caps.fw_ver >> 16) & 0xffff,
629 (int) dev->caps.fw_ver & 0xffff,
630 cmd_if_rev, cmd->max_cmds);
631
632 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
633 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
634 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
635 fw->catas_bar = (fw->catas_bar >> 6) * 2;
636
637 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
638 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
639
640 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
641 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
642 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
643 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
644
645 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
646
647 /*
648 * Round up number of system pages needed in case
649 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
650 */
651 fw->fw_pages =
652 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
653 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
654
655 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
656 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
657
658 out:
659 mlx4_free_cmd_mailbox(dev, mailbox);
660 return err;
661 }
662
663 static void get_board_id(void *vsd, char *board_id)
664 {
665 int i;
666
667 #define VSD_OFFSET_SIG1 0x00
668 #define VSD_OFFSET_SIG2 0xde
669 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
670 #define VSD_OFFSET_TS_BOARD_ID 0x20
671
672 #define VSD_SIGNATURE_TOPSPIN 0x5ad
673
674 memset(board_id, 0, MLX4_BOARD_ID_LEN);
675
676 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
677 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
678 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
679 } else {
680 /*
681 * The board ID is a string but the firmware byte
682 * swaps each 4-byte word before passing it back to
683 * us. Therefore we need to swab it before printing.
684 */
685 for (i = 0; i < 4; ++i)
686 ((u32 *) board_id)[i] =
687 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
688 }
689 }
690
691 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
692 {
693 struct mlx4_cmd_mailbox *mailbox;
694 u32 *outbox;
695 int err;
696
697 #define QUERY_ADAPTER_OUT_SIZE 0x100
698 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
699 #define QUERY_ADAPTER_VSD_OFFSET 0x20
700
701 mailbox = mlx4_alloc_cmd_mailbox(dev);
702 if (IS_ERR(mailbox))
703 return PTR_ERR(mailbox);
704 outbox = mailbox->buf;
705
706 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
707 MLX4_CMD_TIME_CLASS_A);
708 if (err)
709 goto out;
710
711 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
712
713 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
714 adapter->board_id);
715
716 out:
717 mlx4_free_cmd_mailbox(dev, mailbox);
718 return err;
719 }
720
721 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
722 {
723 struct mlx4_cmd_mailbox *mailbox;
724 __be32 *inbox;
725 int err;
726
727 #define INIT_HCA_IN_SIZE 0x200
728 #define INIT_HCA_VERSION_OFFSET 0x000
729 #define INIT_HCA_VERSION 2
730 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
731 #define INIT_HCA_FLAGS_OFFSET 0x014
732 #define INIT_HCA_QPC_OFFSET 0x020
733 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
734 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
735 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
736 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
737 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
738 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
739 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
740 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
741 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
742 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
743 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
744 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
745 #define INIT_HCA_MCAST_OFFSET 0x0c0
746 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
747 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
748 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
749 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
750 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
751 #define INIT_HCA_TPT_OFFSET 0x0f0
752 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
753 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
754 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
755 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
756 #define INIT_HCA_UAR_OFFSET 0x120
757 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
758 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
759
760 mailbox = mlx4_alloc_cmd_mailbox(dev);
761 if (IS_ERR(mailbox))
762 return PTR_ERR(mailbox);
763 inbox = mailbox->buf;
764
765 memset(inbox, 0, INIT_HCA_IN_SIZE);
766
767 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
768
769 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
770 (ilog2(cache_line_size()) - 4) << 5;
771
772 #if defined(__LITTLE_ENDIAN)
773 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
774 #elif defined(__BIG_ENDIAN)
775 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
776 #else
777 #error Host endianness not defined
778 #endif
779 /* Check port for UD address vector: */
780 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
781
782 /* Enable IPoIB checksumming if we can: */
783 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
784 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
785
786 /* Enable QoS support if module parameter set */
787 if (enable_qos)
788 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
789
790 /* enable counters */
791 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
792 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
793
794 /* QPC/EEC/CQC/EQC/RDMARC attributes */
795
796 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
797 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
798 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
799 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
800 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
801 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
802 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
803 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
804 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
805 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
806 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
807 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
808
809 /* multicast attributes */
810
811 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
812 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
813 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
814 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
815 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
816 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
817
818 /* TPT attributes */
819
820 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
821 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
822 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
823 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
824
825 /* UAR attributes */
826
827 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
828 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
829
830 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
831
832 if (err)
833 mlx4_err(dev, "INIT_HCA returns %d\n", err);
834
835 mlx4_free_cmd_mailbox(dev, mailbox);
836 return err;
837 }
838
839 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
840 {
841 struct mlx4_cmd_mailbox *mailbox;
842 u32 *inbox;
843 int err;
844 u32 flags;
845 u16 field;
846
847 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
848 #define INIT_PORT_IN_SIZE 256
849 #define INIT_PORT_FLAGS_OFFSET 0x00
850 #define INIT_PORT_FLAG_SIG (1 << 18)
851 #define INIT_PORT_FLAG_NG (1 << 17)
852 #define INIT_PORT_FLAG_G0 (1 << 16)
853 #define INIT_PORT_VL_SHIFT 4
854 #define INIT_PORT_PORT_WIDTH_SHIFT 8
855 #define INIT_PORT_MTU_OFFSET 0x04
856 #define INIT_PORT_MAX_GID_OFFSET 0x06
857 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
858 #define INIT_PORT_GUID0_OFFSET 0x10
859 #define INIT_PORT_NODE_GUID_OFFSET 0x18
860 #define INIT_PORT_SI_GUID_OFFSET 0x20
861
862 mailbox = mlx4_alloc_cmd_mailbox(dev);
863 if (IS_ERR(mailbox))
864 return PTR_ERR(mailbox);
865 inbox = mailbox->buf;
866
867 memset(inbox, 0, INIT_PORT_IN_SIZE);
868
869 flags = 0;
870 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
871 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
872 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
873
874 field = 128 << dev->caps.ib_mtu_cap[port];
875 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
876 field = dev->caps.gid_table_len[port];
877 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
878 field = dev->caps.pkey_table_len[port];
879 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
880
881 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
882 MLX4_CMD_TIME_CLASS_A);
883
884 mlx4_free_cmd_mailbox(dev, mailbox);
885 } else
886 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
887 MLX4_CMD_TIME_CLASS_A);
888
889 return err;
890 }
891 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
892
893 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
894 {
895 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
896 }
897 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
898
899 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
900 {
901 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
902 }
903
904 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
905 {
906 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
907 MLX4_CMD_SET_ICM_SIZE,
908 MLX4_CMD_TIME_CLASS_A);
909 if (ret)
910 return ret;
911
912 /*
913 * Round up number of system pages needed in case
914 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
915 */
916 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
917 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
918
919 return 0;
920 }
921
922 int mlx4_NOP(struct mlx4_dev *dev)
923 {
924 /* Input modifier of 0x1f means "finish as soon as possible." */
925 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
926 }
927
928 #define MLX4_WOL_SETUP_MODE (5 << 28)
929 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
930 {
931 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
932
933 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
934 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
935 }
936 EXPORT_SYMBOL_GPL(mlx4_wol_read);
937
938 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
939 {
940 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
941
942 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
943 MLX4_CMD_TIME_CLASS_A);
944 }
945 EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree