drivers/net/ethernet/mellanox/mlx4/en_port.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/mlx4/device.h>
  38 #include <linux/mlx4/cmd.h>
  39
  40 #include "en_port.h"
  41 #include "mlx4_en.h"
  42
  43
  44 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
  45                         u64 mac, u64 clear, u8 mode)
  46 {
  47         return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
  48                         MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
  49 }
  50
  51 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
  52 {
  53         struct mlx4_cmd_mailbox *mailbox;
  54         struct mlx4_set_vlan_fltr_mbox *filter;
  55         int i;
  56         int j;
  57         int index = 0;
  58         u32 entry;
  59         int err = 0;
  60
  61         mailbox = mlx4_alloc_cmd_mailbox(dev);
  62         if (IS_ERR(mailbox))
  63                 return PTR_ERR(mailbox);
  64
  65         filter = mailbox->buf;
  66         memset(filter, 0, sizeof(*filter));
  67         for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
  68                 entry = 0;
  69                 for (j = 0; j < 32; j++)
  70                         if (test_bit(index++, priv->active_vlans))
  71                                 entry |= 1 << j;
  72                 filter->entry[i] = cpu_to_be32(entry);
  73         }
  74         err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
  75                        MLX4_CMD_TIME_CLASS_B);
  76         mlx4_free_cmd_mailbox(dev, mailbox);
  77         return err;
  78 }
  79
  80
  81 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  82                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
  83 {
  84         struct mlx4_cmd_mailbox *mailbox;
  85         struct mlx4_set_port_general_context *context;
  86         int err;
  87         u32 in_mod;
  88
  89         mailbox = mlx4_alloc_cmd_mailbox(dev);
  90         if (IS_ERR(mailbox))
  91                 return PTR_ERR(mailbox);
  92         context = mailbox->buf;
  93         memset(context, 0, sizeof *context);
  94
  95         context->flags = SET_PORT_GEN_ALL_VALID;
  96         context->mtu = cpu_to_be16(mtu);
  97         context->pptx = (pptx * (!pfctx)) << 7;
  98         context->pfctx = pfctx;
  99         context->pprx = (pprx * (!pfcrx)) << 7;
 100         context->pfcrx = pfcrx;
 101
 102         in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
 103         err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
 104                        MLX4_CMD_TIME_CLASS_B);
 105
 106         mlx4_free_cmd_mailbox(dev, mailbox);
 107         return err;
 108 }
 109
 110 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 111                            u8 promisc)
 112 {
 113         struct mlx4_cmd_mailbox *mailbox;
 114         struct mlx4_set_port_rqp_calc_context *context;
 115         int err;
 116         u32 in_mod;
 117         u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
 118                                                 MCAST_DIRECT : MCAST_DEFAULT;
 119
 120         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER  &&
 121                         dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)
 122                 return 0;
 123
 124         mailbox = mlx4_alloc_cmd_mailbox(dev);
 125         if (IS_ERR(mailbox))
 126                 return PTR_ERR(mailbox);
 127         context = mailbox->buf;
 128         memset(context, 0, sizeof *context);
 129
 130         context->base_qpn = cpu_to_be32(base_qpn);
 131         context->n_mac = dev->caps.log_num_macs;
 132         context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
 133                                        base_qpn);
 134         context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
 135                                      base_qpn);
 136         context->intra_no_vlan = 0;
 137         context->no_vlan = MLX4_NO_VLAN_IDX;
 138         context->intra_vlan_miss = 0;
 139         context->vlan_miss = MLX4_VLAN_MISS_IDX;
 140
 141         in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
 142         err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
 143                        MLX4_CMD_TIME_CLASS_B);
 144
 145         mlx4_free_cmd_mailbox(dev, mailbox);
 146         return err;
 147 }
 148
 149 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
 150 {
 151         struct mlx4_en_query_port_context *qport_context;
 152         struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
 153         struct mlx4_en_port_state *state = &priv->port_state;
 154         struct mlx4_cmd_mailbox *mailbox;
 155         int err;
 156
 157         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
 158         if (IS_ERR(mailbox))
 159                 return PTR_ERR(mailbox);
 160         memset(mailbox->buf, 0, sizeof(*qport_context));
 161         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
 162                            MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B);
 163         if (err)
 164                 goto out;
 165         qport_context = mailbox->buf;
 166
 167         /* This command is always accessed from Ethtool context
 168          * already synchronized, no need in locking */
 169         state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
 170         switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
 171         case MLX4_EN_1G_SPEED:
 172                 state->link_speed = 1000;
 173                 break;
 174         case MLX4_EN_10G_SPEED_XAUI:
 175         case MLX4_EN_10G_SPEED_XFI:
 176                 state->link_speed = 10000;
 177                 break;
 178         case MLX4_EN_40G_SPEED:
 179                 state->link_speed = 40000;
 180                 break;
 181         default:
 182                 state->link_speed = -1;
 183                 break;
 184         }
 185         state->transciver = qport_context->transceiver;
 186
 187 out:
 188         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
 189         return err;
 190 }
 191
 192 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
 193 {
 194         struct mlx4_en_stat_out_mbox *mlx4_en_stats;
 195         struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
 196         struct net_device_stats *stats = &priv->stats;
 197         struct mlx4_cmd_mailbox *mailbox;
 198         u64 in_mod = reset << 8 | port;
 199         int err;
 200         int i;
 201
 202         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
 203         if (IS_ERR(mailbox))
 204                 return PTR_ERR(mailbox);
 205         memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
 206         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
 207                            MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
 208         if (err)
 209                 goto out;
 210
 211         mlx4_en_stats = mailbox->buf;
 212
 213         spin_lock_bh(&priv->stats_lock);
 214
 215         stats->rx_packets = 0;
 216         stats->rx_bytes = 0;
 217         priv->port_stats.rx_chksum_good = 0;
 218         priv->port_stats.rx_chksum_none = 0;
 219         for (i = 0; i < priv->rx_ring_num; i++) {
 220                 stats->rx_packets += priv->rx_ring[i].packets;
 221                 stats->rx_bytes += priv->rx_ring[i].bytes;
 222                 priv->port_stats.rx_chksum_good += priv->rx_ring[i].csum_ok;
 223                 priv->port_stats.rx_chksum_none += priv->rx_ring[i].csum_none;
 224         }
 225         stats->tx_packets = 0;
 226         stats->tx_bytes = 0;
 227         priv->port_stats.tx_chksum_offload = 0;
 228         for (i = 0; i < priv->tx_ring_num; i++) {
 229                 stats->tx_packets += priv->tx_ring[i].packets;
 230                 stats->tx_bytes += priv->tx_ring[i].bytes;
 231                 priv->port_stats.tx_chksum_offload += priv->tx_ring[i].tx_csum;
 232         }
 233
 234         stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
 235                            be32_to_cpu(mlx4_en_stats->RdropLength) +
 236                            be32_to_cpu(mlx4_en_stats->RJBBR) +
 237                            be32_to_cpu(mlx4_en_stats->RCRC) +
 238                            be32_to_cpu(mlx4_en_stats->RRUNT);
 239         stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
 240         stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
 241                            be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
 242                            be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
 243                            be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
 244                            be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
 245                            be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
 246                            be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
 247                            be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
 248                            be64_to_cpu(mlx4_en_stats->MCAST_novlan);
 249         stats->collisions = 0;
 250         stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
 251         stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
 252         stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
 253         stats->rx_frame_errors = 0;
 254         stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
 255         stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
 256         stats->tx_aborted_errors = 0;
 257         stats->tx_carrier_errors = 0;
 258         stats->tx_fifo_errors = 0;
 259         stats->tx_heartbeat_errors = 0;
 260         stats->tx_window_errors = 0;
 261
 262         priv->pkstats.broadcast =
 263                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
 264                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
 265                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
 266                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
 267                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
 268                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
 269                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
 270                                 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
 271                                 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
 272         priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
 273         priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
 274         priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
 275         priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
 276         priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
 277         priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
 278         priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
 279         priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
 280         priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
 281         priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
 282         priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
 283         priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
 284         priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
 285         priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
 286         priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
 287         priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
 288         spin_unlock_bh(&priv->stats_lock);
 289
 290 out:
 291         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
 292         return err;
 293 }
 294