include/asm-mips/mach-au1x00/au1xxx_psc.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Include file for Alchemy Semiconductor's Au1k CPU.
   5  *
   6  * Copyright 2004 Embedded Edge, LLC
   7  *      dan@embeddededge.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 /* Specifics for the Au1xxx Programmable Serial Controllers, first
  31  * seen in the AU1550 part.
  32  */
  33 #ifndef _AU1000_PSC_H_
  34 #define _AU1000_PSC_H_
  35
  36 #include <linux/config.h>
  37
  38 /* The PSC base addresses.  */
  39 #ifdef CONFIG_SOC_AU1550
  40 #define PSC0_BASE_ADDR          0xb1a00000
  41 #define PSC1_BASE_ADDR          0xb1b00000
  42 #define PSC2_BASE_ADDR          0xb0a00000
  43 #define PSC3_BASE_ADDR          0xb0d00000
  44 #endif
  45
  46 /* The PSC select and control registers are common to
  47  * all protocols.
  48  */
  49 #define PSC_SEL_OFFSET          0x00000000
  50 #define PSC_CTRL_OFFSET         0x00000004
  51
  52 #define PSC_SEL_CLK_MASK        (3 << 4)
  53 #define PSC_SEL_CLK_INTCLK      (0 << 4)
  54 #define PSC_SEL_CLK_EXTCLK      (1 << 4)
  55 #define PSC_SEL_CLK_SERCLK      (2 << 4)
  56
  57 #define PSC_SEL_PS_MASK         0x00000007
  58 #define PSC_SEL_PS_DISABLED     (0)
  59 #define PSC_SEL_PS_SPIMODE      (2)
  60 #define PSC_SEL_PS_I2SMODE      (3)
  61 #define PSC_SEL_PS_AC97MODE     (4)
  62 #define PSC_SEL_PS_SMBUSMODE    (5)
  63
  64 #define PSC_CTRL_DISABLE        (0)
  65 #define PSC_CTRL_SUSPEND        (2)
  66 #define PSC_CTRL_ENABLE         (3)
  67
  68 /* AC97 Registers.
  69 */
  70 #define PSC_AC97CFG_OFFSET      0x00000008
  71 #define PSC_AC97MSK_OFFSET      0x0000000c
  72 #define PSC_AC97PCR_OFFSET      0x00000010
  73 #define PSC_AC97STAT_OFFSET     0x00000014
  74 #define PSC_AC97EVNT_OFFSET     0x00000018
  75 #define PSC_AC97TXRX_OFFSET     0x0000001c
  76 #define PSC_AC97CDC_OFFSET      0x00000020
  77 #define PSC_AC97RST_OFFSET      0x00000024
  78 #define PSC_AC97GPO_OFFSET      0x00000028
  79 #define PSC_AC97GPI_OFFSET      0x0000002c
  80
  81 #define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
  82 #define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
  83 #define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
  84 #define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
  85 #define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
  86 #define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
  87 #define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
  88 #define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
  89 #define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
  90 #define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
  91 #define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
  92 #define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
  93
  94 /* AC97 Config Register.
  95 */
  96 #define PSC_AC97CFG_RT_MASK     (3 << 30)
  97 #define PSC_AC97CFG_RT_FIFO1    (0 << 30)
  98 #define PSC_AC97CFG_RT_FIFO2    (1 << 30)
  99 #define PSC_AC97CFG_RT_FIFO4    (2 << 30)
 100 #define PSC_AC97CFG_RT_FIFO8    (3 << 30)
 101
 102 #define PSC_AC97CFG_TT_MASK     (3 << 28)
 103 #define PSC_AC97CFG_TT_FIFO1    (0 << 28)
 104 #define PSC_AC97CFG_TT_FIFO2    (1 << 28)
 105 #define PSC_AC97CFG_TT_FIFO4    (2 << 28)
 106 #define PSC_AC97CFG_TT_FIFO8    (3 << 28)
 107
 108 #define PSC_AC97CFG_DD_DISABLE  (1 << 27)
 109 #define PSC_AC97CFG_DE_ENABLE   (1 << 26)
 110 #define PSC_AC97CFG_SE_ENABLE   (1 << 25)
 111
 112 #define PSC_AC97CFG_LEN_MASK    (0xf << 21)
 113 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
 114 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
 115 #define PSC_AC97CFG_GE_ENABLE   (1)
 116
 117 /* Enable slots 3-12.
 118 */
 119 #define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
 120 #define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
 121
 122 /* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
 123  * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
 124  * arithmetic in the macro.
 125  */
 126 #define PSC_AC97CFG_SET_LEN(x)  (((((x)-2)/2) & 0xf) << 21)
 127 #define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
 128
 129 /* AC97 Mask Register.
 130 */
 131 #define PSC_AC97MSK_GR          (1 << 25)
 132 #define PSC_AC97MSK_CD          (1 << 24)
 133 #define PSC_AC97MSK_RR          (1 << 13)
 134 #define PSC_AC97MSK_RO          (1 << 12)
 135 #define PSC_AC97MSK_RU          (1 << 11)
 136 #define PSC_AC97MSK_TR          (1 << 10)
 137 #define PSC_AC97MSK_TO          (1 << 9)
 138 #define PSC_AC97MSK_TU          (1 << 8)
 139 #define PSC_AC97MSK_RD          (1 << 5)
 140 #define PSC_AC97MSK_TD          (1 << 4)
 141 #define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
 142                                  PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
 143                                  PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
 144                                  PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
 145                                  PSC_AC97MSK_RD | PSC_AC97MSK_TD)
 146
 147 /* AC97 Protocol Control Register.
 148 */
 149 #define PSC_AC97PCR_RC          (1 << 6)
 150 #define PSC_AC97PCR_RP          (1 << 5)
 151 #define PSC_AC97PCR_RS          (1 << 4)
 152 #define PSC_AC97PCR_TC          (1 << 2)
 153 #define PSC_AC97PCR_TP          (1 << 1)
 154 #define PSC_AC97PCR_TS          (1 << 0)
 155
 156 /* AC97 Status register (read only).
 157 */
 158 #define PSC_AC97STAT_CB         (1 << 26)
 159 #define PSC_AC97STAT_CP         (1 << 25)
 160 #define PSC_AC97STAT_CR         (1 << 24)
 161 #define PSC_AC97STAT_RF         (1 << 13)
 162 #define PSC_AC97STAT_RE         (1 << 12)
 163 #define PSC_AC97STAT_RR         (1 << 11)
 164 #define PSC_AC97STAT_TF         (1 << 10)
 165 #define PSC_AC97STAT_TE         (1 << 9)
 166 #define PSC_AC97STAT_TR         (1 << 8)
 167 #define PSC_AC97STAT_RB         (1 << 5)
 168 #define PSC_AC97STAT_TB         (1 << 4)
 169 #define PSC_AC97STAT_DI         (1 << 2)
 170 #define PSC_AC97STAT_DR         (1 << 1)
 171 #define PSC_AC97STAT_SR         (1 << 0)
 172
 173 /* AC97 Event Register.
 174 */
 175 #define PSC_AC97EVNT_GR         (1 << 25)
 176 #define PSC_AC97EVNT_CD         (1 << 24)
 177 #define PSC_AC97EVNT_RR         (1 << 13)
 178 #define PSC_AC97EVNT_RO         (1 << 12)
 179 #define PSC_AC97EVNT_RU         (1 << 11)
 180 #define PSC_AC97EVNT_TR         (1 << 10)
 181 #define PSC_AC97EVNT_TO         (1 << 9)
 182 #define PSC_AC97EVNT_TU         (1 << 8)
 183 #define PSC_AC97EVNT_RD         (1 << 5)
 184 #define PSC_AC97EVNT_TD         (1 << 4)
 185
 186 /* CODEC Command Register.
 187 */
 188 #define PSC_AC97CDC_RD          (1 << 25)
 189 #define PSC_AC97CDC_ID_MASK     (3 << 23)
 190 #define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
 191 #define PSC_AC97CDC_ID(x)       (((x) & 0x3) << 23)
 192 #define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
 193
 194 /* AC97 Reset Control Register.
 195 */
 196 #define PSC_AC97RST_RST         (1 << 1)
 197 #define PSC_AC97RST_SNC         (1 << 0)
 198
 199
 200 /* PSC in I2S Mode.
 201 */
 202 typedef struct  psc_i2s {
 203         u32     psc_sel;
 204         u32     psc_ctrl;
 205         u32     psc_i2scfg;
 206         u32     psc_i2smsk;
 207         u32     psc_i2spcr;
 208         u32     psc_i2sstat;
 209         u32     psc_i2sevent;
 210         u32     psc_i2stxrx;
 211         u32     psc_i2sudf;
 212 } psc_i2s_t;
 213
 214 /* I2S Config Register.
 215 */
 216 #define PSC_I2SCFG_RT_MASK      (3 << 30)
 217 #define PSC_I2SCFG_RT_FIFO1     (0 << 30)
 218 #define PSC_I2SCFG_RT_FIFO2     (1 << 30)
 219 #define PSC_I2SCFG_RT_FIFO4     (2 << 30)
 220 #define PSC_I2SCFG_RT_FIFO8     (3 << 30)
 221
 222 #define PSC_I2SCFG_TT_MASK      (3 << 28)
 223 #define PSC_I2SCFG_TT_FIFO1     (0 << 28)
 224 #define PSC_I2SCFG_TT_FIFO2     (1 << 28)
 225 #define PSC_I2SCFG_TT_FIFO4     (2 << 28)
 226 #define PSC_I2SCFG_TT_FIFO8     (3 << 28)
 227
 228 #define PSC_I2SCFG_DD_DISABLE   (1 << 27)
 229 #define PSC_I2SCFG_DE_ENABLE    (1 << 26)
 230 #define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
 231 #define PSC_I2SCFG_WI           (1 << 15)
 232
 233 #define PSC_I2SCFG_DIV_MASK     (3 << 13)
 234 #define PSC_I2SCFG_DIV2         (0 << 13)
 235 #define PSC_I2SCFG_DIV4         (1 << 13)
 236 #define PSC_I2SCFG_DIV8         (2 << 13)
 237 #define PSC_I2SCFG_DIV16        (3 << 13)
 238
 239 #define PSC_I2SCFG_BI           (1 << 12)
 240 #define PSC_I2SCFG_BUF          (1 << 11)
 241 #define PSC_I2SCFG_MLJ          (1 << 10)
 242 #define PSC_I2SCFG_XM           (1 << 9)
 243
 244 /* The word length equation is simply LEN+1.
 245  */
 246 #define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
 247 #define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
 248
 249 #define PSC_I2SCFG_LB           (1 << 2)
 250 #define PSC_I2SCFG_MLF          (1 << 1)
 251 #define PSC_I2SCFG_MS           (1 << 0)
 252
 253 /* I2S Mask Register.
 254 */
 255 #define PSC_I2SMSK_RR           (1 << 13)
 256 #define PSC_I2SMSK_RO           (1 << 12)
 257 #define PSC_I2SMSK_RU           (1 << 11)
 258 #define PSC_I2SMSK_TR           (1 << 10)
 259 #define PSC_I2SMSK_TO           (1 << 9)
 260 #define PSC_I2SMSK_TU           (1 << 8)
 261 #define PSC_I2SMSK_RD           (1 << 5)
 262 #define PSC_I2SMSK_TD           (1 << 4)
 263 #define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
 264                                  PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
 265                                  PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
 266                                  PSC_I2SMSK_RD | PSC_I2SMSK_TD)
 267
 268 /* I2S Protocol Control Register.
 269 */
 270 #define PSC_I2SPCR_RC           (1 << 6)
 271 #define PSC_I2SPCR_RP           (1 << 5)
 272 #define PSC_I2SPCR_RS           (1 << 4)
 273 #define PSC_I2SPCR_TC           (1 << 2)
 274 #define PSC_I2SPCR_TP           (1 << 1)
 275 #define PSC_I2SPCR_TS           (1 << 0)
 276
 277 /* I2S Status register (read only).
 278 */
 279 #define PSC_I2SSTAT_RF          (1 << 13)
 280 #define PSC_I2SSTAT_RE          (1 << 12)
 281 #define PSC_I2SSTAT_RR          (1 << 11)
 282 #define PSC_I2SSTAT_TF          (1 << 10)
 283 #define PSC_I2SSTAT_TE          (1 << 9)
 284 #define PSC_I2SSTAT_TR          (1 << 8)
 285 #define PSC_I2SSTAT_RB          (1 << 5)
 286 #define PSC_I2SSTAT_TB          (1 << 4)
 287 #define PSC_I2SSTAT_DI          (1 << 2)
 288 #define PSC_I2SSTAT_DR          (1 << 1)
 289 #define PSC_I2SSTAT_SR          (1 << 0)
 290
 291 /* I2S Event Register.
 292 */
 293 #define PSC_I2SEVNT_RR          (1 << 13)
 294 #define PSC_I2SEVNT_RO          (1 << 12)
 295 #define PSC_I2SEVNT_RU          (1 << 11)
 296 #define PSC_I2SEVNT_TR          (1 << 10)
 297 #define PSC_I2SEVNT_TO          (1 << 9)
 298 #define PSC_I2SEVNT_TU          (1 << 8)
 299 #define PSC_I2SEVNT_RD          (1 << 5)
 300 #define PSC_I2SEVNT_TD          (1 << 4)
 301
 302 /* PSC in SPI Mode.
 303 */
 304 typedef struct  psc_spi {
 305         u32     psc_sel;
 306         u32     psc_ctrl;
 307         u32     psc_spicfg;
 308         u32     psc_spimsk;
 309         u32     psc_spipcr;
 310         u32     psc_spistat;
 311         u32     psc_spievent;
 312         u32     psc_spitxrx;
 313 } psc_spi_t;
 314
 315 /* SPI Config Register.
 316 */
 317 #define PSC_SPICFG_RT_MASK      (3 << 30)
 318 #define PSC_SPICFG_RT_FIFO1     (0 << 30)
 319 #define PSC_SPICFG_RT_FIFO2     (1 << 30)
 320 #define PSC_SPICFG_RT_FIFO4     (2 << 30)
 321 #define PSC_SPICFG_RT_FIFO8     (3 << 30)
 322
 323 #define PSC_SPICFG_TT_MASK      (3 << 28)
 324 #define PSC_SPICFG_TT_FIFO1     (0 << 28)
 325 #define PSC_SPICFG_TT_FIFO2     (1 << 28)
 326 #define PSC_SPICFG_TT_FIFO4     (2 << 28)
 327 #define PSC_SPICFG_TT_FIFO8     (3 << 28)
 328
 329 #define PSC_SPICFG_DD_DISABLE   (1 << 27)
 330 #define PSC_SPICFG_DE_ENABLE    (1 << 26)
 331 #define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
 332 #define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
 333
 334 #define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
 335 #define PSC_SPICFG_DIV2         0
 336 #define PSC_SPICFG_DIV4         1
 337 #define PSC_SPICFG_DIV8         2
 338 #define PSC_SPICFG_DIV16        3
 339
 340 #define PSC_SPICFG_BI           (1 << 12)
 341 #define PSC_SPICFG_PSE          (1 << 11)
 342 #define PSC_SPICFG_CGE          (1 << 10)
 343 #define PSC_SPICFG_CDE          (1 << 9)
 344
 345 #define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
 346 #define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
 347
 348 #define PSC_SPICFG_LB           (1 << 3)
 349 #define PSC_SPICFG_MLF          (1 << 1)
 350 #define PSC_SPICFG_MO           (1 << 0)
 351
 352 /* SPI Mask Register.
 353 */
 354 #define PSC_SPIMSK_MM           (1 << 16)
 355 #define PSC_SPIMSK_RR           (1 << 13)
 356 #define PSC_SPIMSK_RO           (1 << 12)
 357 #define PSC_SPIMSK_RU           (1 << 11)
 358 #define PSC_SPIMSK_TR           (1 << 10)
 359 #define PSC_SPIMSK_TO           (1 << 9)
 360 #define PSC_SPIMSK_TU           (1 << 8)
 361 #define PSC_SPIMSK_SD           (1 << 5)
 362 #define PSC_SPIMSK_MD           (1 << 4)
 363 #define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
 364                                  PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
 365                                  PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
 366                                  PSC_SPIMSK_MD)
 367
 368 /* SPI Protocol Control Register.
 369 */
 370 #define PSC_SPIPCR_RC           (1 << 6)
 371 #define PSC_SPIPCR_SP           (1 << 5)
 372 #define PSC_SPIPCR_SS           (1 << 4)
 373 #define PSC_SPIPCR_TC           (1 << 2)
 374 #define PSC_SPIPCR_MS           (1 << 0)
 375
 376 /* SPI Status register (read only).
 377 */
 378 #define PSC_SPISTAT_RF          (1 << 13)
 379 #define PSC_SPISTAT_RE          (1 << 12)
 380 #define PSC_SPISTAT_RR          (1 << 11)
 381 #define PSC_SPISTAT_TF          (1 << 10)
 382 #define PSC_SPISTAT_TE          (1 << 9)
 383 #define PSC_SPISTAT_TR          (1 << 8)
 384 #define PSC_SPISTAT_SB          (1 << 5)
 385 #define PSC_SPISTAT_MB          (1 << 4)
 386 #define PSC_SPISTAT_DI          (1 << 2)
 387 #define PSC_SPISTAT_DR          (1 << 1)
 388 #define PSC_SPISTAT_SR          (1 << 0)
 389
 390 /* SPI Event Register.
 391 */
 392 #define PSC_SPIEVNT_MM          (1 << 16)
 393 #define PSC_SPIEVNT_RR          (1 << 13)
 394 #define PSC_SPIEVNT_RO          (1 << 12)
 395 #define PSC_SPIEVNT_RU          (1 << 11)
 396 #define PSC_SPIEVNT_TR          (1 << 10)
 397 #define PSC_SPIEVNT_TO          (1 << 9)
 398 #define PSC_SPIEVNT_TU          (1 << 8)
 399 #define PSC_SPIEVNT_SD          (1 << 5)
 400 #define PSC_SPIEVNT_MD          (1 << 4)
 401
 402 /* Transmit register control.
 403 */
 404 #define PSC_SPITXRX_LC          (1 << 29)
 405 #define PSC_SPITXRX_SR          (1 << 28)
 406
 407 /* PSC in SMBus (I2C) Mode.
 408 */
 409 typedef struct  psc_smb {
 410         u32     psc_sel;
 411         u32     psc_ctrl;
 412         u32     psc_smbcfg;
 413         u32     psc_smbmsk;
 414         u32     psc_smbpcr;
 415         u32     psc_smbstat;
 416         u32     psc_smbevnt;
 417         u32     psc_smbtxrx;
 418         u32     psc_smbtmr;
 419 } psc_smb_t;
 420
 421 /* SMBus Config Register.
 422 */
 423 #define PSC_SMBCFG_RT_MASK      (3 << 30)
 424 #define PSC_SMBCFG_RT_FIFO1     (0 << 30)
 425 #define PSC_SMBCFG_RT_FIFO2     (1 << 30)
 426 #define PSC_SMBCFG_RT_FIFO4     (2 << 30)
 427 #define PSC_SMBCFG_RT_FIFO8     (3 << 30)
 428
 429 #define PSC_SMBCFG_TT_MASK      (3 << 28)
 430 #define PSC_SMBCFG_TT_FIFO1     (0 << 28)
 431 #define PSC_SMBCFG_TT_FIFO2     (1 << 28)
 432 #define PSC_SMBCFG_TT_FIFO4     (2 << 28)
 433 #define PSC_SMBCFG_TT_FIFO8     (3 << 28)
 434
 435 #define PSC_SMBCFG_DD_DISABLE   (1 << 27)
 436 #define PSC_SMBCFG_DE_ENABLE    (1 << 26)
 437
 438 #define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
 439 #define PSC_SMBCFG_DIV2         0
 440 #define PSC_SMBCFG_DIV4         1
 441 #define PSC_SMBCFG_DIV8         2
 442 #define PSC_SMBCFG_DIV16        3
 443
 444 #define PSC_SMBCFG_GCE          (1 << 9)
 445 #define PSC_SMBCFG_SFM          (1 << 8)
 446
 447 #define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
 448
 449 /* SMBus Mask Register.
 450 */
 451 #define PSC_SMBMSK_DN           (1 << 30)
 452 #define PSC_SMBMSK_AN           (1 << 29)
 453 #define PSC_SMBMSK_AL           (1 << 28)
 454 #define PSC_SMBMSK_RR           (1 << 13)
 455 #define PSC_SMBMSK_RO           (1 << 12)
 456 #define PSC_SMBMSK_RU           (1 << 11)
 457 #define PSC_SMBMSK_TR           (1 << 10)
 458 #define PSC_SMBMSK_TO           (1 << 9)
 459 #define PSC_SMBMSK_TU           (1 << 8)
 460 #define PSC_SMBMSK_SD           (1 << 5)
 461 #define PSC_SMBMSK_MD           (1 << 4)
 462 #define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
 463                                  PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
 464                                  PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
 465                                  PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
 466                                  PSC_SMBMSK_MD)
 467
 468 /* SMBus Protocol Control Register.
 469 */
 470 #define PSC_SMBPCR_DC           (1 << 2)
 471 #define PSC_SMBPCR_MS           (1 << 0)
 472
 473 /* SMBus Status register (read only).
 474 */
 475 #define PSC_SMBSTAT_BB          (1 << 28)
 476 #define PSC_SMBSTAT_RF          (1 << 13)
 477 #define PSC_SMBSTAT_RE          (1 << 12)
 478 #define PSC_SMBSTAT_RR          (1 << 11)
 479 #define PSC_SMBSTAT_TF          (1 << 10)
 480 #define PSC_SMBSTAT_TE          (1 << 9)
 481 #define PSC_SMBSTAT_TR          (1 << 8)
 482 #define PSC_SMBSTAT_SB          (1 << 5)
 483 #define PSC_SMBSTAT_MB          (1 << 4)
 484 #define PSC_SMBSTAT_DI          (1 << 2)
 485 #define PSC_SMBSTAT_DR          (1 << 1)
 486 #define PSC_SMBSTAT_SR          (1 << 0)
 487
 488 /* SMBus Event Register.
 489 */
 490 #define PSC_SMBEVNT_DN          (1 << 30)
 491 #define PSC_SMBEVNT_AN          (1 << 29)
 492 #define PSC_SMBEVNT_AL          (1 << 28)
 493 #define PSC_SMBEVNT_RR          (1 << 13)
 494 #define PSC_SMBEVNT_RO          (1 << 12)
 495 #define PSC_SMBEVNT_RU          (1 << 11)
 496 #define PSC_SMBEVNT_TR          (1 << 10)
 497 #define PSC_SMBEVNT_TO          (1 << 9)
 498 #define PSC_SMBEVNT_TU          (1 << 8)
 499 #define PSC_SMBEVNT_SD          (1 << 5)
 500 #define PSC_SMBEVNT_MD          (1 << 4)
 501 #define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
 502                                  PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
 503                                  PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
 504                                  PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
 505                                  PSC_SMBEVNT_MD)
 506
 507 /* Transmit register control.
 508 */
 509 #define PSC_SMBTXRX_RSR         (1 << 30)
 510 #define PSC_SMBTXRX_STP         (1 << 29)
 511 #define PSC_SMBTXRX_DATAMASK    (0xff)
 512
 513 /* SMBus protocol timers register.
 514 */
 515 #define PSC_SMBTMR_SET_TH(x)    (((x) & 0x3) << 30)
 516 #define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
 517 #define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
 518 #define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
 519 #define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
 520 #define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
 521 #define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
 522
 523
 524 #endif /* _AU1000_PSC_H_ */