include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 #include "drm.h"
  31
  32 /* Please note that modifications to all structs defined here are
  33  * subject to backwards-compatibility constraints.
  34  */
  35
  36 #ifdef __KERNEL__
  37 /* For use by IPS driver */
  38 extern unsigned long i915_read_mch_val(void);
  39 extern bool i915_gpu_raise(void);
  40 extern bool i915_gpu_lower(void);
  41 extern bool i915_gpu_busy(void);
  42 extern bool i915_gpu_turbo_disable(void);
  43 #endif
  44
  45 /* Each region is a minimum of 16k, and there are at most 255 of them.
  46  */
  47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  48                                  * of chars for next/prev indices */
  49 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  50
  51 typedef struct _drm_i915_init {
  52         enum {
  53                 I915_INIT_DMA = 0x01,
  54                 I915_CLEANUP_DMA = 0x02,
  55                 I915_RESUME_DMA = 0x03
  56         } func;
  57         unsigned int mmio_offset;
  58         int sarea_priv_offset;
  59         unsigned int ring_start;
  60         unsigned int ring_end;
  61         unsigned int ring_size;
  62         unsigned int front_offset;
  63         unsigned int back_offset;
  64         unsigned int depth_offset;
  65         unsigned int w;
  66         unsigned int h;
  67         unsigned int pitch;
  68         unsigned int pitch_bits;
  69         unsigned int back_pitch;
  70         unsigned int depth_pitch;
  71         unsigned int cpp;
  72         unsigned int chipset;
  73 } drm_i915_init_t;
  74
  75 typedef struct _drm_i915_sarea {
  76         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  77         int last_upload;        /* last time texture was uploaded */
  78         int last_enqueue;       /* last time a buffer was enqueued */
  79         int last_dispatch;      /* age of the most recently dispatched buffer */
  80         int ctxOwner;           /* last context to upload state */
  81         int texAge;
  82         int pf_enabled;         /* is pageflipping allowed? */
  83         int pf_active;
  84         int pf_current_page;    /* which buffer is being displayed? */
  85         int perf_boxes;         /* performance boxes to be displayed */
  86         int width, height;      /* screen size in pixels */
  87
  88         drm_handle_t front_handle;
  89         int front_offset;
  90         int front_size;
  91
  92         drm_handle_t back_handle;
  93         int back_offset;
  94         int back_size;
  95
  96         drm_handle_t depth_handle;
  97         int depth_offset;
  98         int depth_size;
  99
 100         drm_handle_t tex_handle;
 101         int tex_offset;
 102         int tex_size;
 103         int log_tex_granularity;
 104         int pitch;
 105         int rotation;           /* 0, 90, 180 or 270 */
 106         int rotated_offset;
 107         int rotated_size;
 108         int rotated_pitch;
 109         int virtualX, virtualY;
 110
 111         unsigned int front_tiled;
 112         unsigned int back_tiled;
 113         unsigned int depth_tiled;
 114         unsigned int rotated_tiled;
 115         unsigned int rotated2_tiled;
 116
 117         int pipeA_x;
 118         int pipeA_y;
 119         int pipeA_w;
 120         int pipeA_h;
 121         int pipeB_x;
 122         int pipeB_y;
 123         int pipeB_w;
 124         int pipeB_h;
 125
 126         /* fill out some space for old userspace triple buffer */
 127         drm_handle_t unused_handle;
 128         __u32 unused1, unused2, unused3;
 129
 130         /* buffer object handles for static buffers. May change
 131          * over the lifetime of the client.
 132          */
 133         __u32 front_bo_handle;
 134         __u32 back_bo_handle;
 135         __u32 unused_bo_handle;
 136         __u32 depth_bo_handle;
 137
 138 } drm_i915_sarea_t;
 139
 140 /* due to userspace building against these headers we need some compat here */
 141 #define planeA_x pipeA_x
 142 #define planeA_y pipeA_y
 143 #define planeA_w pipeA_w
 144 #define planeA_h pipeA_h
 145 #define planeB_x pipeB_x
 146 #define planeB_y pipeB_y
 147 #define planeB_w pipeB_w
 148 #define planeB_h pipeB_h
 149
 150 /* Flags for perf_boxes
 151  */
 152 #define I915_BOX_RING_EMPTY    0x1
 153 #define I915_BOX_FLIP          0x2
 154 #define I915_BOX_WAIT          0x4
 155 #define I915_BOX_TEXTURE_LOAD  0x8
 156 #define I915_BOX_LOST_CONTEXT  0x10
 157
 158 /* I915 specific ioctls
 159  * The device specific ioctl range is 0x40 to 0x79.
 160  */
 161 #define DRM_I915_INIT           0x00
 162 #define DRM_I915_FLUSH          0x01
 163 #define DRM_I915_FLIP           0x02
 164 #define DRM_I915_BATCHBUFFER    0x03
 165 #define DRM_I915_IRQ_EMIT       0x04
 166 #define DRM_I915_IRQ_WAIT       0x05
 167 #define DRM_I915_GETPARAM       0x06
 168 #define DRM_I915_SETPARAM       0x07
 169 #define DRM_I915_ALLOC          0x08
 170 #define DRM_I915_FREE           0x09
 171 #define DRM_I915_INIT_HEAP      0x0a
 172 #define DRM_I915_CMDBUFFER      0x0b
 173 #define DRM_I915_DESTROY_HEAP   0x0c
 174 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 175 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 176 #define DRM_I915_VBLANK_SWAP    0x0f
 177 #define DRM_I915_HWS_ADDR       0x11
 178 #define DRM_I915_GEM_INIT       0x13
 179 #define DRM_I915_GEM_EXECBUFFER 0x14
 180 #define DRM_I915_GEM_PIN        0x15
 181 #define DRM_I915_GEM_UNPIN      0x16
 182 #define DRM_I915_GEM_BUSY       0x17
 183 #define DRM_I915_GEM_THROTTLE   0x18
 184 #define DRM_I915_GEM_ENTERVT    0x19
 185 #define DRM_I915_GEM_LEAVEVT    0x1a
 186 #define DRM_I915_GEM_CREATE     0x1b
 187 #define DRM_I915_GEM_PREAD      0x1c
 188 #define DRM_I915_GEM_PWRITE     0x1d
 189 #define DRM_I915_GEM_MMAP       0x1e
 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 191 #define DRM_I915_GEM_SW_FINISH  0x20
 192 #define DRM_I915_GEM_SET_TILING 0x21
 193 #define DRM_I915_GEM_GET_TILING 0x22
 194 #define DRM_I915_GEM_GET_APERTURE 0x23
 195 #define DRM_I915_GEM_MMAP_GTT   0x24
 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
 197 #define DRM_I915_GEM_MADVISE    0x26
 198 #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
 199 #define DRM_I915_OVERLAY_ATTRS  0x28
 200 #define DRM_I915_GEM_EXECBUFFER2        0x29
 201
 202 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 203 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 204 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 205 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 206 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 207 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 208 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 209 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 210 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 211 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 212 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 213 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 214 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 217 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 218 #define DRM_IOCTL_I915_HWS_ADDR         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
 219 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 220 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
 222 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 223 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 224 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 225 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 226 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 227 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 228 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 229 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 230 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 231 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 232 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
 233 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 234 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 235 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 236 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 237 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 238 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 239 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
 240 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
 241 #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 242
 243 /* Allow drivers to submit batchbuffers directly to hardware, relying
 244  * on the security mechanisms provided by hardware.
 245  */
 246 typedef struct drm_i915_batchbuffer {
 247         int start;              /* agp offset */
 248         int used;               /* nr bytes in use */
 249         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 250         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 251         int num_cliprects;      /* mulitpass with multiple cliprects? */
 252         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 253 } drm_i915_batchbuffer_t;
 254
 255 /* As above, but pass a pointer to userspace buffer which can be
 256  * validated by the kernel prior to sending to hardware.
 257  */
 258 typedef struct _drm_i915_cmdbuffer {
 259         char __user *buf;       /* pointer to userspace command buffer */
 260         int sz;                 /* nr bytes in buf */
 261         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 262         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 263         int num_cliprects;      /* mulitpass with multiple cliprects? */
 264         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 265 } drm_i915_cmdbuffer_t;
 266
 267 /* Userspace can request & wait on irq's:
 268  */
 269 typedef struct drm_i915_irq_emit {
 270         int __user *irq_seq;
 271 } drm_i915_irq_emit_t;
 272
 273 typedef struct drm_i915_irq_wait {
 274         int irq_seq;
 275 } drm_i915_irq_wait_t;
 276
 277 /* Ioctl to query kernel params:
 278  */
 279 #define I915_PARAM_IRQ_ACTIVE            1
 280 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 281 #define I915_PARAM_LAST_DISPATCH         3
 282 #define I915_PARAM_CHIPSET_ID            4
 283 #define I915_PARAM_HAS_GEM               5
 284 #define I915_PARAM_NUM_FENCES_AVAIL      6
 285 #define I915_PARAM_HAS_OVERLAY           7
 286 #define I915_PARAM_HAS_PAGEFLIPPING      8
 287 #define I915_PARAM_HAS_EXECBUF2          9
 288 #define I915_PARAM_HAS_BSD               10
 289 #define I915_PARAM_HAS_BLT               11
 290 #define I915_PARAM_HAS_RELAXED_FENCING   12
 291 #define I915_PARAM_HAS_COHERENT_RINGS    13
 292
 293 typedef struct drm_i915_getparam {
 294         int param;
 295         int __user *value;
 296 } drm_i915_getparam_t;
 297
 298 /* Ioctl to set kernel params:
 299  */
 300 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 301 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 302 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 303 #define I915_SETPARAM_NUM_USED_FENCES                     4
 304
 305 typedef struct drm_i915_setparam {
 306         int param;
 307         int value;
 308 } drm_i915_setparam_t;
 309
 310 /* A memory manager for regions of shared memory:
 311  */
 312 #define I915_MEM_REGION_AGP 1
 313
 314 typedef struct drm_i915_mem_alloc {
 315         int region;
 316         int alignment;
 317         int size;
 318         int __user *region_offset;      /* offset from start of fb or agp */
 319 } drm_i915_mem_alloc_t;
 320
 321 typedef struct drm_i915_mem_free {
 322         int region;
 323         int region_offset;
 324 } drm_i915_mem_free_t;
 325
 326 typedef struct drm_i915_mem_init_heap {
 327         int region;
 328         int size;
 329         int start;
 330 } drm_i915_mem_init_heap_t;
 331
 332 /* Allow memory manager to be torn down and re-initialized (eg on
 333  * rotate):
 334  */
 335 typedef struct drm_i915_mem_destroy_heap {
 336         int region;
 337 } drm_i915_mem_destroy_heap_t;
 338
 339 /* Allow X server to configure which pipes to monitor for vblank signals
 340  */
 341 #define DRM_I915_VBLANK_PIPE_A  1
 342 #define DRM_I915_VBLANK_PIPE_B  2
 343
 344 typedef struct drm_i915_vblank_pipe {
 345         int pipe;
 346 } drm_i915_vblank_pipe_t;
 347
 348 /* Schedule buffer swap at given vertical blank:
 349  */
 350 typedef struct drm_i915_vblank_swap {
 351         drm_drawable_t drawable;
 352         enum drm_vblank_seq_type seqtype;
 353         unsigned int sequence;
 354 } drm_i915_vblank_swap_t;
 355
 356 typedef struct drm_i915_hws_addr {
 357         __u64 addr;
 358 } drm_i915_hws_addr_t;
 359
 360 struct drm_i915_gem_init {
 361         /**
 362          * Beginning offset in the GTT to be managed by the DRM memory
 363          * manager.
 364          */
 365         __u64 gtt_start;
 366         /**
 367          * Ending offset in the GTT to be managed by the DRM memory
 368          * manager.
 369          */
 370         __u64 gtt_end;
 371 };
 372
 373 struct drm_i915_gem_create {
 374         /**
 375          * Requested size for the object.
 376          *
 377          * The (page-aligned) allocated size for the object will be returned.
 378          */
 379         __u64 size;
 380         /**
 381          * Returned handle for the object.
 382          *
 383          * Object handles are nonzero.
 384          */
 385         __u32 handle;
 386         __u32 pad;
 387 };
 388
 389 struct drm_i915_gem_pread {
 390         /** Handle for the object being read. */
 391         __u32 handle;
 392         __u32 pad;
 393         /** Offset into the object to read from */
 394         __u64 offset;
 395         /** Length of data to read */
 396         __u64 size;
 397         /**
 398          * Pointer to write the data into.
 399          *
 400          * This is a fixed-size type for 32/64 compatibility.
 401          */
 402         __u64 data_ptr;
 403 };
 404
 405 struct drm_i915_gem_pwrite {
 406         /** Handle for the object being written to. */
 407         __u32 handle;
 408         __u32 pad;
 409         /** Offset into the object to write to */
 410         __u64 offset;
 411         /** Length of data to write */
 412         __u64 size;
 413         /**
 414          * Pointer to read the data from.
 415          *
 416          * This is a fixed-size type for 32/64 compatibility.
 417          */
 418         __u64 data_ptr;
 419 };
 420
 421 struct drm_i915_gem_mmap {
 422         /** Handle for the object being mapped. */
 423         __u32 handle;
 424         __u32 pad;
 425         /** Offset in the object to map. */
 426         __u64 offset;
 427         /**
 428          * Length of data to map.
 429          *
 430          * The value will be page-aligned.
 431          */
 432         __u64 size;
 433         /**
 434          * Returned pointer the data was mapped at.
 435          *
 436          * This is a fixed-size type for 32/64 compatibility.
 437          */
 438         __u64 addr_ptr;
 439 };
 440
 441 struct drm_i915_gem_mmap_gtt {
 442         /** Handle for the object being mapped. */
 443         __u32 handle;
 444         __u32 pad;
 445         /**
 446          * Fake offset to use for subsequent mmap call
 447          *
 448          * This is a fixed-size type for 32/64 compatibility.
 449          */
 450         __u64 offset;
 451 };
 452
 453 struct drm_i915_gem_set_domain {
 454         /** Handle for the object */
 455         __u32 handle;
 456
 457         /** New read domains */
 458         __u32 read_domains;
 459
 460         /** New write domain */
 461         __u32 write_domain;
 462 };
 463
 464 struct drm_i915_gem_sw_finish {
 465         /** Handle for the object */
 466         __u32 handle;
 467 };
 468
 469 struct drm_i915_gem_relocation_entry {
 470         /**
 471          * Handle of the buffer being pointed to by this relocation entry.
 472          *
 473          * It's appealing to make this be an index into the mm_validate_entry
 474          * list to refer to the buffer, but this allows the driver to create
 475          * a relocation list for state buffers and not re-write it per
 476          * exec using the buffer.
 477          */
 478         __u32 target_handle;
 479
 480         /**
 481          * Value to be added to the offset of the target buffer to make up
 482          * the relocation entry.
 483          */
 484         __u32 delta;
 485
 486         /** Offset in the buffer the relocation entry will be written into */
 487         __u64 offset;
 488
 489         /**
 490          * Offset value of the target buffer that the relocation entry was last
 491          * written as.
 492          *
 493          * If the buffer has the same offset as last time, we can skip syncing
 494          * and writing the relocation.  This value is written back out by
 495          * the execbuffer ioctl when the relocation is written.
 496          */
 497         __u64 presumed_offset;
 498
 499         /**
 500          * Target memory domains read by this operation.
 501          */
 502         __u32 read_domains;
 503
 504         /**
 505          * Target memory domains written by this operation.
 506          *
 507          * Note that only one domain may be written by the whole
 508          * execbuffer operation, so that where there are conflicts,
 509          * the application will get -EINVAL back.
 510          */
 511         __u32 write_domain;
 512 };
 513
 514 /** @{
 515  * Intel memory domains
 516  *
 517  * Most of these just align with the various caches in
 518  * the system and are used to flush and invalidate as
 519  * objects end up cached in different domains.
 520  */
 521 /** CPU cache */
 522 #define I915_GEM_DOMAIN_CPU             0x00000001
 523 /** Render cache, used by 2D and 3D drawing */
 524 #define I915_GEM_DOMAIN_RENDER          0x00000002
 525 /** Sampler cache, used by texture engine */
 526 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 527 /** Command queue, used to load batch buffers */
 528 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 529 /** Instruction cache, used by shader programs */
 530 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 531 /** Vertex address cache */
 532 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 533 /** GTT domain - aperture and scanout */
 534 #define I915_GEM_DOMAIN_GTT             0x00000040
 535 /** @} */
 536
 537 struct drm_i915_gem_exec_object {
 538         /**
 539          * User's handle for a buffer to be bound into the GTT for this
 540          * operation.
 541          */
 542         __u32 handle;
 543
 544         /** Number of relocations to be performed on this buffer */
 545         __u32 relocation_count;
 546         /**
 547          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 548          * the relocations to be performed in this buffer.
 549          */
 550         __u64 relocs_ptr;
 551
 552         /** Required alignment in graphics aperture */
 553         __u64 alignment;
 554
 555         /**
 556          * Returned value of the updated offset of the object, for future
 557          * presumed_offset writes.
 558          */
 559         __u64 offset;
 560 };
 561
 562 struct drm_i915_gem_execbuffer {
 563         /**
 564          * List of buffers to be validated with their relocations to be
 565          * performend on them.
 566          *
 567          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 568          *
 569          * These buffers must be listed in an order such that all relocations
 570          * a buffer is performing refer to buffers that have already appeared
 571          * in the validate list.
 572          */
 573         __u64 buffers_ptr;
 574         __u32 buffer_count;
 575
 576         /** Offset in the batchbuffer to start execution from. */
 577         __u32 batch_start_offset;
 578         /** Bytes used in batchbuffer from batch_start_offset */
 579         __u32 batch_len;
 580         __u32 DR1;
 581         __u32 DR4;
 582         __u32 num_cliprects;
 583         /** This is a struct drm_clip_rect *cliprects */
 584         __u64 cliprects_ptr;
 585 };
 586
 587 struct drm_i915_gem_exec_object2 {
 588         /**
 589          * User's handle for a buffer to be bound into the GTT for this
 590          * operation.
 591          */
 592         __u32 handle;
 593
 594         /** Number of relocations to be performed on this buffer */
 595         __u32 relocation_count;
 596         /**
 597          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 598          * the relocations to be performed in this buffer.
 599          */
 600         __u64 relocs_ptr;
 601
 602         /** Required alignment in graphics aperture */
 603         __u64 alignment;
 604
 605         /**
 606          * Returned value of the updated offset of the object, for future
 607          * presumed_offset writes.
 608          */
 609         __u64 offset;
 610
 611 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
 612         __u64 flags;
 613         __u64 rsvd1;
 614         __u64 rsvd2;
 615 };
 616
 617 struct drm_i915_gem_execbuffer2 {
 618         /**
 619          * List of gem_exec_object2 structs
 620          */
 621         __u64 buffers_ptr;
 622         __u32 buffer_count;
 623
 624         /** Offset in the batchbuffer to start execution from. */
 625         __u32 batch_start_offset;
 626         /** Bytes used in batchbuffer from batch_start_offset */
 627         __u32 batch_len;
 628         __u32 DR1;
 629         __u32 DR4;
 630         __u32 num_cliprects;
 631         /** This is a struct drm_clip_rect *cliprects */
 632         __u64 cliprects_ptr;
 633 #define I915_EXEC_RING_MASK              (7<<0)
 634 #define I915_EXEC_DEFAULT                (0<<0)
 635 #define I915_EXEC_RENDER                 (1<<0)
 636 #define I915_EXEC_BSD                    (2<<0)
 637 #define I915_EXEC_BLT                    (3<<0)
 638         __u64 flags;
 639         __u64 rsvd1;
 640         __u64 rsvd2;
 641 };
 642
 643 struct drm_i915_gem_pin {
 644         /** Handle of the buffer to be pinned. */
 645         __u32 handle;
 646         __u32 pad;
 647
 648         /** alignment required within the aperture */
 649         __u64 alignment;
 650
 651         /** Returned GTT offset of the buffer. */
 652         __u64 offset;
 653 };
 654
 655 struct drm_i915_gem_unpin {
 656         /** Handle of the buffer to be unpinned. */
 657         __u32 handle;
 658         __u32 pad;
 659 };
 660
 661 struct drm_i915_gem_busy {
 662         /** Handle of the buffer to check for busy */
 663         __u32 handle;
 664
 665         /** Return busy status (1 if busy, 0 if idle) */
 666         __u32 busy;
 667 };
 668
 669 #define I915_TILING_NONE        0
 670 #define I915_TILING_X           1
 671 #define I915_TILING_Y           2
 672
 673 #define I915_BIT_6_SWIZZLE_NONE         0
 674 #define I915_BIT_6_SWIZZLE_9            1
 675 #define I915_BIT_6_SWIZZLE_9_10         2
 676 #define I915_BIT_6_SWIZZLE_9_11         3
 677 #define I915_BIT_6_SWIZZLE_9_10_11      4
 678 /* Not seen by userland */
 679 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 680 /* Seen by userland. */
 681 #define I915_BIT_6_SWIZZLE_9_17         6
 682 #define I915_BIT_6_SWIZZLE_9_10_17      7
 683
 684 struct drm_i915_gem_set_tiling {
 685         /** Handle of the buffer to have its tiling state updated */
 686         __u32 handle;
 687
 688         /**
 689          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 690          * I915_TILING_Y).
 691          *
 692          * This value is to be set on request, and will be updated by the
 693          * kernel on successful return with the actual chosen tiling layout.
 694          *
 695          * The tiling mode may be demoted to I915_TILING_NONE when the system
 696          * has bit 6 swizzling that can't be managed correctly by GEM.
 697          *
 698          * Buffer contents become undefined when changing tiling_mode.
 699          */
 700         __u32 tiling_mode;
 701
 702         /**
 703          * Stride in bytes for the object when in I915_TILING_X or
 704          * I915_TILING_Y.
 705          */
 706         __u32 stride;
 707
 708         /**
 709          * Returned address bit 6 swizzling required for CPU access through
 710          * mmap mapping.
 711          */
 712         __u32 swizzle_mode;
 713 };
 714
 715 struct drm_i915_gem_get_tiling {
 716         /** Handle of the buffer to get tiling state for. */
 717         __u32 handle;
 718
 719         /**
 720          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 721          * I915_TILING_Y).
 722          */
 723         __u32 tiling_mode;
 724
 725         /**
 726          * Returned address bit 6 swizzling required for CPU access through
 727          * mmap mapping.
 728          */
 729         __u32 swizzle_mode;
 730 };
 731
 732 struct drm_i915_gem_get_aperture {
 733         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
 734         __u64 aper_size;
 735
 736         /**
 737          * Available space in the aperture used by i915_gem_execbuffer, in
 738          * bytes
 739          */
 740         __u64 aper_available_size;
 741 };
 742
 743 struct drm_i915_get_pipe_from_crtc_id {
 744         /** ID of CRTC being requested **/
 745         __u32 crtc_id;
 746
 747         /** pipe of requested CRTC **/
 748         __u32 pipe;
 749 };
 750
 751 #define I915_MADV_WILLNEED 0
 752 #define I915_MADV_DONTNEED 1
 753 #define __I915_MADV_PURGED 2 /* internal state */
 754
 755 struct drm_i915_gem_madvise {
 756         /** Handle of the buffer to change the backing store advice */
 757         __u32 handle;
 758
 759         /* Advice: either the buffer will be needed again in the near future,
 760          *         or wont be and could be discarded under memory pressure.
 761          */
 762         __u32 madv;
 763
 764         /** Whether the backing store still exists. */
 765         __u32 retained;
 766 };
 767
 768 /* flags */
 769 #define I915_OVERLAY_TYPE_MASK          0xff
 770 #define I915_OVERLAY_YUV_PLANAR         0x01
 771 #define I915_OVERLAY_YUV_PACKED         0x02
 772 #define I915_OVERLAY_RGB                0x03
 773
 774 #define I915_OVERLAY_DEPTH_MASK         0xff00
 775 #define I915_OVERLAY_RGB24              0x1000
 776 #define I915_OVERLAY_RGB16              0x2000
 777 #define I915_OVERLAY_RGB15              0x3000
 778 #define I915_OVERLAY_YUV422             0x0100
 779 #define I915_OVERLAY_YUV411             0x0200
 780 #define I915_OVERLAY_YUV420             0x0300
 781 #define I915_OVERLAY_YUV410             0x0400
 782
 783 #define I915_OVERLAY_SWAP_MASK          0xff0000
 784 #define I915_OVERLAY_NO_SWAP            0x000000
 785 #define I915_OVERLAY_UV_SWAP            0x010000
 786 #define I915_OVERLAY_Y_SWAP             0x020000
 787 #define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
 788
 789 #define I915_OVERLAY_FLAGS_MASK         0xff000000
 790 #define I915_OVERLAY_ENABLE             0x01000000
 791
 792 struct drm_intel_overlay_put_image {
 793         /* various flags and src format description */
 794         __u32 flags;
 795         /* source picture description */
 796         __u32 bo_handle;
 797         /* stride values and offsets are in bytes, buffer relative */
 798         __u16 stride_Y; /* stride for packed formats */
 799         __u16 stride_UV;
 800         __u32 offset_Y; /* offset for packet formats */
 801         __u32 offset_U;
 802         __u32 offset_V;
 803         /* in pixels */
 804         __u16 src_width;
 805         __u16 src_height;
 806         /* to compensate the scaling factors for partially covered surfaces */
 807         __u16 src_scan_width;
 808         __u16 src_scan_height;
 809         /* output crtc description */
 810         __u32 crtc_id;
 811         __u16 dst_x;
 812         __u16 dst_y;
 813         __u16 dst_width;
 814         __u16 dst_height;
 815 };
 816
 817 /* flags */
 818 #define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
 819 #define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
 820 struct drm_intel_overlay_attrs {
 821         __u32 flags;
 822         __u32 color_key;
 823         __s32 brightness;
 824         __u32 contrast;
 825         __u32 saturation;
 826         __u32 gamma0;
 827         __u32 gamma1;
 828         __u32 gamma2;
 829         __u32 gamma3;
 830         __u32 gamma4;
 831         __u32 gamma5;
 832 };
 833
 834 #endif                          /* _I915_DRM_H_ */