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Merge git://git.infradead.org/mtd-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / synclink.c
blobafded3a2379c592082e85e373236addce5d9fcd3
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/module.h>
67 #include <linux/errno.h>
68 #include <linux/signal.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/pci.h>
73 #include <linux/tty.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/major.h>
77 #include <linux/string.h>
78 #include <linux/fcntl.h>
79 #include <linux/ptrace.h>
80 #include <linux/ioport.h>
81 #include <linux/mm.h>
82 #include <linux/seq_file.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
85 #include <linux/netdevice.h>
86 #include <linux/vmalloc.h>
87 #include <linux/init.h>
88 #include <linux/ioctl.h>
89 #include <linux/synclink.h>
90
91 #include <asm/system.h>
92 #include <asm/io.h>
93 #include <asm/irq.h>
94 #include <asm/dma.h>
95 #include <linux/bitops.h>
96 #include <asm/types.h>
97 #include <linux/termios.h>
98 #include <linux/workqueue.h>
99 #include <linux/hdlc.h>
100 #include <linux/dma-mapping.h>
101
102 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
103 #define SYNCLINK_GENERIC_HDLC 1
104 #else
105 #define SYNCLINK_GENERIC_HDLC 0
106 #endif
107
108 #define GET_USER(error,value,addr) error = get_user(value,addr)
109 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
110 #define PUT_USER(error,value,addr) error = put_user(value,addr)
111 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
112
113 #include <asm/uaccess.h>
114
115 #define RCLRVALUE 0xffff
116
117 static MGSL_PARAMS default_params = {
118 MGSL_MODE_HDLC, /* unsigned long mode */
119 0, /* unsigned char loopback; */
120 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
121 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
122 0, /* unsigned long clock_speed; */
123 0xff, /* unsigned char addr_filter; */
124 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
125 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
126 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
127 9600, /* unsigned long data_rate; */
128 8, /* unsigned char data_bits; */
129 1, /* unsigned char stop_bits; */
130 ASYNC_PARITY_NONE /* unsigned char parity; */
131 };
132
133 #define SHARED_MEM_ADDRESS_SIZE 0x40000
134 #define BUFFERLISTSIZE 4096
135 #define DMABUFFERSIZE 4096
136 #define MAXRXFRAMES 7
137
138 typedef struct _DMABUFFERENTRY
139 {
140 u32 phys_addr; /* 32-bit flat physical address of data buffer */
141 volatile u16 count; /* buffer size/data count */
142 volatile u16 status; /* Control/status field */
143 volatile u16 rcc; /* character count field */
144 u16 reserved; /* padding required by 16C32 */
145 u32 link; /* 32-bit flat link to next buffer entry */
146 char *virt_addr; /* virtual address of data buffer */
147 u32 phys_entry; /* physical address of this buffer entry */
148 dma_addr_t dma_addr;
149 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
150
151 /* The queue of BH actions to be performed */
152
153 #define BH_RECEIVE 1
154 #define BH_TRANSMIT 2
155 #define BH_STATUS 4
156
157 #define IO_PIN_SHUTDOWN_LIMIT 100
158
159 struct _input_signal_events {
160 int ri_up;
161 int ri_down;
162 int dsr_up;
163 int dsr_down;
164 int dcd_up;
165 int dcd_down;
166 int cts_up;
167 int cts_down;
168 };
169
170 /* transmit holding buffer definitions*/
171 #define MAX_TX_HOLDING_BUFFERS 5
172 struct tx_holding_buffer {
173 int buffer_size;
174 unsigned char * buffer;
175 };
176
177
178 /*
179 * Device instance data structure
180 */
181
182 struct mgsl_struct {
183 int magic;
184 struct tty_port port;
185 int line;
186 int hw_version;
187
188 struct mgsl_icount icount;
189
190 int timeout;
191 int x_char; /* xon/xoff character */
192 u16 read_status_mask;
193 u16 ignore_status_mask;
194 unsigned char *xmit_buf;
195 int xmit_head;
196 int xmit_tail;
197 int xmit_cnt;
198
199 wait_queue_head_t status_event_wait_q;
200 wait_queue_head_t event_wait_q;
201 struct timer_list tx_timer; /* HDLC transmit timeout timer */
202 struct mgsl_struct *next_device; /* device list link */
203
204 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
205 struct work_struct task; /* task structure for scheduling bh */
206
207 u32 EventMask; /* event trigger mask */
208 u32 RecordedEvents; /* pending events */
209
210 u32 max_frame_size; /* as set by device config */
211
212 u32 pending_bh;
213
214 bool bh_running; /* Protection from multiple */
215 int isr_overflow;
216 bool bh_requested;
217
218 int dcd_chkcount; /* check counts to prevent */
219 int cts_chkcount; /* too many IRQs if a signal */
220 int dsr_chkcount; /* is floating */
221 int ri_chkcount;
222
223 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
224 u32 buffer_list_phys;
225 dma_addr_t buffer_list_dma_addr;
226
227 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
228 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
229 unsigned int current_rx_buffer;
230
231 int num_tx_dma_buffers; /* number of tx dma frames required */
232 int tx_dma_buffers_used;
233 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
234 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
235 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
236 int current_tx_buffer; /* next tx dma buffer to be loaded */
237
238 unsigned char *intermediate_rxbuffer;
239
240 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
241 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
242 int put_tx_holding_index; /* next tx holding buffer to store user request */
243 int tx_holding_count; /* number of tx holding buffers waiting */
244 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
245
246 bool rx_enabled;
247 bool rx_overflow;
248 bool rx_rcc_underrun;
249
250 bool tx_enabled;
251 bool tx_active;
252 u32 idle_mode;
253
254 u16 cmr_value;
255 u16 tcsr_value;
256
257 char device_name[25]; /* device instance name */
258
259 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
260 unsigned char bus; /* expansion bus number (zero based) */
261 unsigned char function; /* PCI device number */
262
263 unsigned int io_base; /* base I/O address of adapter */
264 unsigned int io_addr_size; /* size of the I/O address range */
265 bool io_addr_requested; /* true if I/O address requested */
266
267 unsigned int irq_level; /* interrupt level */
268 unsigned long irq_flags;
269 bool irq_requested; /* true if IRQ requested */
270
271 unsigned int dma_level; /* DMA channel */
272 bool dma_requested; /* true if dma channel requested */
273
274 u16 mbre_bit;
275 u16 loopback_bits;
276 u16 usc_idle_mode;
277
278 MGSL_PARAMS params; /* communications parameters */
279
280 unsigned char serial_signals; /* current serial signal states */
281
282 bool irq_occurred; /* for diagnostics use */
283 unsigned int init_error; /* Initialization startup error (DIAGS) */
284 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
285
286 u32 last_mem_alloc;
287 unsigned char* memory_base; /* shared memory address (PCI only) */
288 u32 phys_memory_base;
289 bool shared_mem_requested;
290
291 unsigned char* lcr_base; /* local config registers (PCI only) */
292 u32 phys_lcr_base;
293 u32 lcr_offset;
294 bool lcr_mem_requested;
295
296 u32 misc_ctrl_value;
297 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
298 char char_buf[MAX_ASYNC_BUFFER_SIZE];
299 bool drop_rts_on_tx_done;
300
301 bool loopmode_insert_requested;
302 bool loopmode_send_done_requested;
303
304 struct _input_signal_events input_signal_events;
305
306 /* generic HDLC device parts */
307 int netcount;
308 spinlock_t netlock;
309
310 #if SYNCLINK_GENERIC_HDLC
311 struct net_device *netdev;
312 #endif
313 };
314
315 #define MGSL_MAGIC 0x5401
316
317 /*
318 * The size of the serial xmit buffer is 1 page, or 4096 bytes
319 */
320 #ifndef SERIAL_XMIT_SIZE
321 #define SERIAL_XMIT_SIZE 4096
322 #endif
323
324 /*
325 * These macros define the offsets used in calculating the
326 * I/O address of the specified USC registers.
327 */
328
329
330 #define DCPIN 2 /* Bit 1 of I/O address */
331 #define SDPIN 4 /* Bit 2 of I/O address */
332
333 #define DCAR 0 /* DMA command/address register */
334 #define CCAR SDPIN /* channel command/address register */
335 #define DATAREG DCPIN + SDPIN /* serial data register */
336 #define MSBONLY 0x41
337 #define LSBONLY 0x40
338
339 /*
340 * These macros define the register address (ordinal number)
341 * used for writing address/value pairs to the USC.
342 */
343
344 #define CMR 0x02 /* Channel mode Register */
345 #define CCSR 0x04 /* Channel Command/status Register */
346 #define CCR 0x06 /* Channel Control Register */
347 #define PSR 0x08 /* Port status Register */
348 #define PCR 0x0a /* Port Control Register */
349 #define TMDR 0x0c /* Test mode Data Register */
350 #define TMCR 0x0e /* Test mode Control Register */
351 #define CMCR 0x10 /* Clock mode Control Register */
352 #define HCR 0x12 /* Hardware Configuration Register */
353 #define IVR 0x14 /* Interrupt Vector Register */
354 #define IOCR 0x16 /* Input/Output Control Register */
355 #define ICR 0x18 /* Interrupt Control Register */
356 #define DCCR 0x1a /* Daisy Chain Control Register */
357 #define MISR 0x1c /* Misc Interrupt status Register */
358 #define SICR 0x1e /* status Interrupt Control Register */
359 #define RDR 0x20 /* Receive Data Register */
360 #define RMR 0x22 /* Receive mode Register */
361 #define RCSR 0x24 /* Receive Command/status Register */
362 #define RICR 0x26 /* Receive Interrupt Control Register */
363 #define RSR 0x28 /* Receive Sync Register */
364 #define RCLR 0x2a /* Receive count Limit Register */
365 #define RCCR 0x2c /* Receive Character count Register */
366 #define TC0R 0x2e /* Time Constant 0 Register */
367 #define TDR 0x30 /* Transmit Data Register */
368 #define TMR 0x32 /* Transmit mode Register */
369 #define TCSR 0x34 /* Transmit Command/status Register */
370 #define TICR 0x36 /* Transmit Interrupt Control Register */
371 #define TSR 0x38 /* Transmit Sync Register */
372 #define TCLR 0x3a /* Transmit count Limit Register */
373 #define TCCR 0x3c /* Transmit Character count Register */
374 #define TC1R 0x3e /* Time Constant 1 Register */
375
376
377 /*
378 * MACRO DEFINITIONS FOR DMA REGISTERS
379 */
380
381 #define DCR 0x06 /* DMA Control Register (shared) */
382 #define DACR 0x08 /* DMA Array count Register (shared) */
383 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
384 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
385 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
386 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
387 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
388
389 #define TDMR 0x02 /* Transmit DMA mode Register */
390 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
391 #define TBCR 0x2a /* Transmit Byte count Register */
392 #define TARL 0x2c /* Transmit Address Register (low) */
393 #define TARU 0x2e /* Transmit Address Register (high) */
394 #define NTBCR 0x3a /* Next Transmit Byte count Register */
395 #define NTARL 0x3c /* Next Transmit Address Register (low) */
396 #define NTARU 0x3e /* Next Transmit Address Register (high) */
397
398 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
399 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
400 #define RBCR 0xaa /* Receive Byte count Register */
401 #define RARL 0xac /* Receive Address Register (low) */
402 #define RARU 0xae /* Receive Address Register (high) */
403 #define NRBCR 0xba /* Next Receive Byte count Register */
404 #define NRARL 0xbc /* Next Receive Address Register (low) */
405 #define NRARU 0xbe /* Next Receive Address Register (high) */
406
407
408 /*
409 * MACRO DEFINITIONS FOR MODEM STATUS BITS
410 */
411
412 #define MODEMSTATUS_DTR 0x80
413 #define MODEMSTATUS_DSR 0x40
414 #define MODEMSTATUS_RTS 0x20
415 #define MODEMSTATUS_CTS 0x10
416 #define MODEMSTATUS_RI 0x04
417 #define MODEMSTATUS_DCD 0x01
418
419
420 /*
421 * Channel Command/Address Register (CCAR) Command Codes
422 */
423
424 #define RTCmd_Null 0x0000
425 #define RTCmd_ResetHighestIus 0x1000
426 #define RTCmd_TriggerChannelLoadDma 0x2000
427 #define RTCmd_TriggerRxDma 0x2800
428 #define RTCmd_TriggerTxDma 0x3000
429 #define RTCmd_TriggerRxAndTxDma 0x3800
430 #define RTCmd_PurgeRxFifo 0x4800
431 #define RTCmd_PurgeTxFifo 0x5000
432 #define RTCmd_PurgeRxAndTxFifo 0x5800
433 #define RTCmd_LoadRcc 0x6800
434 #define RTCmd_LoadTcc 0x7000
435 #define RTCmd_LoadRccAndTcc 0x7800
436 #define RTCmd_LoadTC0 0x8800
437 #define RTCmd_LoadTC1 0x9000
438 #define RTCmd_LoadTC0AndTC1 0x9800
439 #define RTCmd_SerialDataLSBFirst 0xa000
440 #define RTCmd_SerialDataMSBFirst 0xa800
441 #define RTCmd_SelectBigEndian 0xb000
442 #define RTCmd_SelectLittleEndian 0xb800
443
444
445 /*
446 * DMA Command/Address Register (DCAR) Command Codes
447 */
448
449 #define DmaCmd_Null 0x0000
450 #define DmaCmd_ResetTxChannel 0x1000
451 #define DmaCmd_ResetRxChannel 0x1200
452 #define DmaCmd_StartTxChannel 0x2000
453 #define DmaCmd_StartRxChannel 0x2200
454 #define DmaCmd_ContinueTxChannel 0x3000
455 #define DmaCmd_ContinueRxChannel 0x3200
456 #define DmaCmd_PauseTxChannel 0x4000
457 #define DmaCmd_PauseRxChannel 0x4200
458 #define DmaCmd_AbortTxChannel 0x5000
459 #define DmaCmd_AbortRxChannel 0x5200
460 #define DmaCmd_InitTxChannel 0x7000
461 #define DmaCmd_InitRxChannel 0x7200
462 #define DmaCmd_ResetHighestDmaIus 0x8000
463 #define DmaCmd_ResetAllChannels 0x9000
464 #define DmaCmd_StartAllChannels 0xa000
465 #define DmaCmd_ContinueAllChannels 0xb000
466 #define DmaCmd_PauseAllChannels 0xc000
467 #define DmaCmd_AbortAllChannels 0xd000
468 #define DmaCmd_InitAllChannels 0xf000
469
470 #define TCmd_Null 0x0000
471 #define TCmd_ClearTxCRC 0x2000
472 #define TCmd_SelectTicrTtsaData 0x4000
473 #define TCmd_SelectTicrTxFifostatus 0x5000
474 #define TCmd_SelectTicrIntLevel 0x6000
475 #define TCmd_SelectTicrdma_level 0x7000
476 #define TCmd_SendFrame 0x8000
477 #define TCmd_SendAbort 0x9000
478 #define TCmd_EnableDleInsertion 0xc000
479 #define TCmd_DisableDleInsertion 0xd000
480 #define TCmd_ClearEofEom 0xe000
481 #define TCmd_SetEofEom 0xf000
482
483 #define RCmd_Null 0x0000
484 #define RCmd_ClearRxCRC 0x2000
485 #define RCmd_EnterHuntmode 0x3000
486 #define RCmd_SelectRicrRtsaData 0x4000
487 #define RCmd_SelectRicrRxFifostatus 0x5000
488 #define RCmd_SelectRicrIntLevel 0x6000
489 #define RCmd_SelectRicrdma_level 0x7000
490
491 /*
492 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
493 */
494
495 #define RECEIVE_STATUS BIT5
496 #define RECEIVE_DATA BIT4
497 #define TRANSMIT_STATUS BIT3
498 #define TRANSMIT_DATA BIT2
499 #define IO_PIN BIT1
500 #define MISC BIT0
501
502
503 /*
504 * Receive status Bits in Receive Command/status Register RCSR
505 */
506
507 #define RXSTATUS_SHORT_FRAME BIT8
508 #define RXSTATUS_CODE_VIOLATION BIT8
509 #define RXSTATUS_EXITED_HUNT BIT7
510 #define RXSTATUS_IDLE_RECEIVED BIT6
511 #define RXSTATUS_BREAK_RECEIVED BIT5
512 #define RXSTATUS_ABORT_RECEIVED BIT5
513 #define RXSTATUS_RXBOUND BIT4
514 #define RXSTATUS_CRC_ERROR BIT3
515 #define RXSTATUS_FRAMING_ERROR BIT3
516 #define RXSTATUS_ABORT BIT2
517 #define RXSTATUS_PARITY_ERROR BIT2
518 #define RXSTATUS_OVERRUN BIT1
519 #define RXSTATUS_DATA_AVAILABLE BIT0
520 #define RXSTATUS_ALL 0x01f6
521 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
522
523 /*
524 * Values for setting transmit idle mode in
525 * Transmit Control/status Register (TCSR)
526 */
527 #define IDLEMODE_FLAGS 0x0000
528 #define IDLEMODE_ALT_ONE_ZERO 0x0100
529 #define IDLEMODE_ZERO 0x0200
530 #define IDLEMODE_ONE 0x0300
531 #define IDLEMODE_ALT_MARK_SPACE 0x0500
532 #define IDLEMODE_SPACE 0x0600
533 #define IDLEMODE_MARK 0x0700
534 #define IDLEMODE_MASK 0x0700
535
536 /*
537 * IUSC revision identifiers
538 */
539 #define IUSC_SL1660 0x4d44
540 #define IUSC_PRE_SL1660 0x4553
541
542 /*
543 * Transmit status Bits in Transmit Command/status Register (TCSR)
544 */
545
546 #define TCSR_PRESERVE 0x0F00
547
548 #define TCSR_UNDERWAIT BIT11
549 #define TXSTATUS_PREAMBLE_SENT BIT7
550 #define TXSTATUS_IDLE_SENT BIT6
551 #define TXSTATUS_ABORT_SENT BIT5
552 #define TXSTATUS_EOF_SENT BIT4
553 #define TXSTATUS_EOM_SENT BIT4
554 #define TXSTATUS_CRC_SENT BIT3
555 #define TXSTATUS_ALL_SENT BIT2
556 #define TXSTATUS_UNDERRUN BIT1
557 #define TXSTATUS_FIFO_EMPTY BIT0
558 #define TXSTATUS_ALL 0x00fa
559 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
560
561
562 #define MISCSTATUS_RXC_LATCHED BIT15
563 #define MISCSTATUS_RXC BIT14
564 #define MISCSTATUS_TXC_LATCHED BIT13
565 #define MISCSTATUS_TXC BIT12
566 #define MISCSTATUS_RI_LATCHED BIT11
567 #define MISCSTATUS_RI BIT10
568 #define MISCSTATUS_DSR_LATCHED BIT9
569 #define MISCSTATUS_DSR BIT8
570 #define MISCSTATUS_DCD_LATCHED BIT7
571 #define MISCSTATUS_DCD BIT6
572 #define MISCSTATUS_CTS_LATCHED BIT5
573 #define MISCSTATUS_CTS BIT4
574 #define MISCSTATUS_RCC_UNDERRUN BIT3
575 #define MISCSTATUS_DPLL_NO_SYNC BIT2
576 #define MISCSTATUS_BRG1_ZERO BIT1
577 #define MISCSTATUS_BRG0_ZERO BIT0
578
579 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
580 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
581
582 #define SICR_RXC_ACTIVE BIT15
583 #define SICR_RXC_INACTIVE BIT14
584 #define SICR_RXC (BIT15+BIT14)
585 #define SICR_TXC_ACTIVE BIT13
586 #define SICR_TXC_INACTIVE BIT12
587 #define SICR_TXC (BIT13+BIT12)
588 #define SICR_RI_ACTIVE BIT11
589 #define SICR_RI_INACTIVE BIT10
590 #define SICR_RI (BIT11+BIT10)
591 #define SICR_DSR_ACTIVE BIT9
592 #define SICR_DSR_INACTIVE BIT8
593 #define SICR_DSR (BIT9+BIT8)
594 #define SICR_DCD_ACTIVE BIT7
595 #define SICR_DCD_INACTIVE BIT6
596 #define SICR_DCD (BIT7+BIT6)
597 #define SICR_CTS_ACTIVE BIT5
598 #define SICR_CTS_INACTIVE BIT4
599 #define SICR_CTS (BIT5+BIT4)
600 #define SICR_RCC_UNDERFLOW BIT3
601 #define SICR_DPLL_NO_SYNC BIT2
602 #define SICR_BRG1_ZERO BIT1
603 #define SICR_BRG0_ZERO BIT0
604
605 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
606 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
607 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
608 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
609 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
610
611 #define usc_EnableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
613
614 #define usc_DisableInterrupts( a, b ) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
616
617 #define usc_EnableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
619
620 #define usc_DisableMasterIrqBit(a) \
621 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
622
623 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
624
625 /*
626 * Transmit status Bits in Transmit Control status Register (TCSR)
627 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
628 */
629
630 #define TXSTATUS_PREAMBLE_SENT BIT7
631 #define TXSTATUS_IDLE_SENT BIT6
632 #define TXSTATUS_ABORT_SENT BIT5
633 #define TXSTATUS_EOF BIT4
634 #define TXSTATUS_CRC_SENT BIT3
635 #define TXSTATUS_ALL_SENT BIT2
636 #define TXSTATUS_UNDERRUN BIT1
637 #define TXSTATUS_FIFO_EMPTY BIT0
638
639 #define DICR_MASTER BIT15
640 #define DICR_TRANSMIT BIT0
641 #define DICR_RECEIVE BIT1
642
643 #define usc_EnableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
645
646 #define usc_DisableDmaInterrupts(a,b) \
647 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
648
649 #define usc_EnableStatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
651
652 #define usc_DisablestatusIrqs(a,b) \
653 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
654
655 /* Transmit status Bits in Transmit Control status Register (TCSR) */
656 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
657
658
659 #define DISABLE_UNCONDITIONAL 0
660 #define DISABLE_END_OF_FRAME 1
661 #define ENABLE_UNCONDITIONAL 2
662 #define ENABLE_AUTO_CTS 3
663 #define ENABLE_AUTO_DCD 3
664 #define usc_EnableTransmitter(a,b) \
665 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
666 #define usc_EnableReceiver(a,b) \
667 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668
669 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
670 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
671 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
672
673 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
674 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
675 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
676 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
677 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
678
679 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
680 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
681
682 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
683
684 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
685 static void usc_start_receiver( struct mgsl_struct *info );
686 static void usc_stop_receiver( struct mgsl_struct *info );
687
688 static void usc_start_transmitter( struct mgsl_struct *info );
689 static void usc_stop_transmitter( struct mgsl_struct *info );
690 static void usc_set_txidle( struct mgsl_struct *info );
691 static void usc_load_txfifo( struct mgsl_struct *info );
692
693 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
694 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
695
696 static void usc_get_serial_signals( struct mgsl_struct *info );
697 static void usc_set_serial_signals( struct mgsl_struct *info );
698
699 static void usc_reset( struct mgsl_struct *info );
700
701 static void usc_set_sync_mode( struct mgsl_struct *info );
702 static void usc_set_sdlc_mode( struct mgsl_struct *info );
703 static void usc_set_async_mode( struct mgsl_struct *info );
704 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705
706 static void usc_loopback_frame( struct mgsl_struct *info );
707
708 static void mgsl_tx_timeout(unsigned long context);
709
710
711 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
712 static void usc_loopmode_insert_request( struct mgsl_struct * info );
713 static int usc_loopmode_active( struct mgsl_struct * info);
714 static void usc_loopmode_send_done( struct mgsl_struct * info );
715
716 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
717
718 #if SYNCLINK_GENERIC_HDLC
719 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
720 static void hdlcdev_tx_done(struct mgsl_struct *info);
721 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
722 static int hdlcdev_init(struct mgsl_struct *info);
723 static void hdlcdev_exit(struct mgsl_struct *info);
724 #endif
725
726 /*
727 * Defines a BUS descriptor value for the PCI adapter
728 * local bus address ranges.
729 */
730
731 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
732 (0x00400020 + \
733 ((WrHold) << 30) + \
734 ((WrDly) << 28) + \
735 ((RdDly) << 26) + \
736 ((Nwdd) << 20) + \
737 ((Nwad) << 15) + \
738 ((Nxda) << 13) + \
739 ((Nrdd) << 11) + \
740 ((Nrad) << 6) )
741
742 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
743
744 /*
745 * Adapter diagnostic routines
746 */
747 static bool mgsl_register_test( struct mgsl_struct *info );
748 static bool mgsl_irq_test( struct mgsl_struct *info );
749 static bool mgsl_dma_test( struct mgsl_struct *info );
750 static bool mgsl_memory_test( struct mgsl_struct *info );
751 static int mgsl_adapter_test( struct mgsl_struct *info );
752
753 /*
754 * device and resource management routines
755 */
756 static int mgsl_claim_resources(struct mgsl_struct *info);
757 static void mgsl_release_resources(struct mgsl_struct *info);
758 static void mgsl_add_device(struct mgsl_struct *info);
759 static struct mgsl_struct* mgsl_allocate_device(void);
760
761 /*
762 * DMA buffer manupulation functions.
763 */
764 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
765 static bool mgsl_get_rx_frame( struct mgsl_struct *info );
766 static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
767 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
768 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
769 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
770 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
771 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
772
773 /*
774 * DMA and Shared Memory buffer allocation and formatting
775 */
776 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
777 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
778 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
779 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
780 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
781 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
782 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
783 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
784 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
785 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
786 static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
787 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
788
789 /*
790 * Bottom half interrupt handlers
791 */
792 static void mgsl_bh_handler(struct work_struct *work);
793 static void mgsl_bh_receive(struct mgsl_struct *info);
794 static void mgsl_bh_transmit(struct mgsl_struct *info);
795 static void mgsl_bh_status(struct mgsl_struct *info);
796
797 /*
798 * Interrupt handler routines and dispatch table.
799 */
800 static void mgsl_isr_null( struct mgsl_struct *info );
801 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
802 static void mgsl_isr_receive_data( struct mgsl_struct *info );
803 static void mgsl_isr_receive_status( struct mgsl_struct *info );
804 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
805 static void mgsl_isr_io_pin( struct mgsl_struct *info );
806 static void mgsl_isr_misc( struct mgsl_struct *info );
807 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
808 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
809
810 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811
812 static isr_dispatch_func UscIsrTable[7] =
813 {
814 mgsl_isr_null,
815 mgsl_isr_misc,
816 mgsl_isr_io_pin,
817 mgsl_isr_transmit_data,
818 mgsl_isr_transmit_status,
819 mgsl_isr_receive_data,
820 mgsl_isr_receive_status
821 };
822
823 /*
824 * ioctl call handlers
825 */
826 static int tiocmget(struct tty_struct *tty, struct file *file);
827 static int tiocmset(struct tty_struct *tty, struct file *file,
828 unsigned int set, unsigned int clear);
829 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
830 __user *user_icount);
831 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
832 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
833 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
834 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
835 static int mgsl_txenable(struct mgsl_struct * info, int enable);
836 static int mgsl_txabort(struct mgsl_struct * info);
837 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
838 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
839 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840
841 /* set non-zero on successful registration with PCI subsystem */
842 static bool pci_registered;
843
844 /*
845 * Global linked list of SyncLink devices
846 */
847 static struct mgsl_struct *mgsl_device_list;
848 static int mgsl_device_count;
849
850 /*
851 * Set this param to non-zero to load eax with the
852 * .text section address and breakpoint on module load.
853 * This is useful for use with gdb and add-symbol-file command.
854 */
855 static int break_on_load;
856
857 /*
858 * Driver major number, defaults to zero to get auto
859 * assigned major number. May be forced as module parameter.
860 */
861 static int ttymajor;
862
863 /*
864 * Array of user specified options for ISA adapters.
865 */
866 static int io[MAX_ISA_DEVICES];
867 static int irq[MAX_ISA_DEVICES];
868 static int dma[MAX_ISA_DEVICES];
869 static int debug_level;
870 static int maxframe[MAX_TOTAL_DEVICES];
871 static int txdmabufs[MAX_TOTAL_DEVICES];
872 static int txholdbufs[MAX_TOTAL_DEVICES];
873
874 module_param(break_on_load, bool, 0);
875 module_param(ttymajor, int, 0);
876 module_param_array(io, int, NULL, 0);
877 module_param_array(irq, int, NULL, 0);
878 module_param_array(dma, int, NULL, 0);
879 module_param(debug_level, int, 0);
880 module_param_array(maxframe, int, NULL, 0);
881 module_param_array(txdmabufs, int, NULL, 0);
882 module_param_array(txholdbufs, int, NULL, 0);
883
884 static char *driver_name = "SyncLink serial driver";
885 static char *driver_version = "$Revision: 4.38 $";
886
887 static int synclink_init_one (struct pci_dev *dev,
888 const struct pci_device_id *ent);
889 static void synclink_remove_one (struct pci_dev *dev);
890
891 static struct pci_device_id synclink_pci_tbl[] = {
892 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
893 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
894 { 0, }, /* terminate list */
895 };
896 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
897
898 MODULE_LICENSE("GPL");
899
900 static struct pci_driver synclink_pci_driver = {
901 .name = "synclink",
902 .id_table = synclink_pci_tbl,
903 .probe = synclink_init_one,
904 .remove = __devexit_p(synclink_remove_one),
905 };
906
907 static struct tty_driver *serial_driver;
908
909 /* number of characters left in xmit buffer before we ask for more */
910 #define WAKEUP_CHARS 256
911
912
913 static void mgsl_change_params(struct mgsl_struct *info);
914 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
915
916 /*
917 * 1st function defined in .text section. Calling this function in
918 * init_module() followed by a breakpoint allows a remote debugger
919 * (gdb) to get the .text address for the add-symbol-file command.
920 * This allows remote debugging of dynamically loadable modules.
921 */
922 static void* mgsl_get_text_ptr(void)
923 {
924 return mgsl_get_text_ptr;
925 }
926
927 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
928 char *name, const char *routine)
929 {
930 #ifdef MGSL_PARANOIA_CHECK
931 static const char *badmagic =
932 "Warning: bad magic number for mgsl struct (%s) in %s\n";
933 static const char *badinfo =
934 "Warning: null mgsl_struct for (%s) in %s\n";
935
936 if (!info) {
937 printk(badinfo, name, routine);
938 return 1;
939 }
940 if (info->magic != MGSL_MAGIC) {
941 printk(badmagic, name, routine);
942 return 1;
943 }
944 #else
945 if (!info)
946 return 1;
947 #endif
948 return 0;
949 }
950
951 /**
952 * line discipline callback wrappers
953 *
954 * The wrappers maintain line discipline references
955 * while calling into the line discipline.
956 *
957 * ldisc_receive_buf - pass receive data to line discipline
958 */
959
960 static void ldisc_receive_buf(struct tty_struct *tty,
961 const __u8 *data, char *flags, int count)
962 {
963 struct tty_ldisc *ld;
964 if (!tty)
965 return;
966 ld = tty_ldisc_ref(tty);
967 if (ld) {
968 if (ld->ops->receive_buf)
969 ld->ops->receive_buf(tty, data, flags, count);
970 tty_ldisc_deref(ld);
971 }
972 }
973
974 /* mgsl_stop() throttle (stop) transmitter
975 *
976 * Arguments: tty pointer to tty info structure
977 * Return Value: None
978 */
979 static void mgsl_stop(struct tty_struct *tty)
980 {
981 struct mgsl_struct *info = tty->driver_data;
982 unsigned long flags;
983
984 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
985 return;
986
987 if ( debug_level >= DEBUG_LEVEL_INFO )
988 printk("mgsl_stop(%s)\n",info->device_name);
989
990 spin_lock_irqsave(&info->irq_spinlock,flags);
991 if (info->tx_enabled)
992 usc_stop_transmitter(info);
993 spin_unlock_irqrestore(&info->irq_spinlock,flags);
994
995 } /* end of mgsl_stop() */
996
997 /* mgsl_start() release (start) transmitter
998 *
999 * Arguments: tty pointer to tty info structure
1000 * Return Value: None
1001 */
1002 static void mgsl_start(struct tty_struct *tty)
1003 {
1004 struct mgsl_struct *info = tty->driver_data;
1005 unsigned long flags;
1006
1007 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1008 return;
1009
1010 if ( debug_level >= DEBUG_LEVEL_INFO )
1011 printk("mgsl_start(%s)\n",info->device_name);
1012
1013 spin_lock_irqsave(&info->irq_spinlock,flags);
1014 if (!info->tx_enabled)
1015 usc_start_transmitter(info);
1016 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1017
1018 } /* end of mgsl_start() */
1019
1020 /*
1021 * Bottom half work queue access functions
1022 */
1023
1024 /* mgsl_bh_action() Return next bottom half action to perform.
1025 * Return Value: BH action code or 0 if nothing to do.
1026 */
1027 static int mgsl_bh_action(struct mgsl_struct *info)
1028 {
1029 unsigned long flags;
1030 int rc = 0;
1031
1032 spin_lock_irqsave(&info->irq_spinlock,flags);
1033
1034 if (info->pending_bh & BH_RECEIVE) {
1035 info->pending_bh &= ~BH_RECEIVE;
1036 rc = BH_RECEIVE;
1037 } else if (info->pending_bh & BH_TRANSMIT) {
1038 info->pending_bh &= ~BH_TRANSMIT;
1039 rc = BH_TRANSMIT;
1040 } else if (info->pending_bh & BH_STATUS) {
1041 info->pending_bh &= ~BH_STATUS;
1042 rc = BH_STATUS;
1043 }
1044
1045 if (!rc) {
1046 /* Mark BH routine as complete */
1047 info->bh_running = false;
1048 info->bh_requested = false;
1049 }
1050
1051 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1052
1053 return rc;
1054 }
1055
1056 /*
1057 * Perform bottom half processing of work items queued by ISR.
1058 */
1059 static void mgsl_bh_handler(struct work_struct *work)
1060 {
1061 struct mgsl_struct *info =
1062 container_of(work, struct mgsl_struct, task);
1063 int action;
1064
1065 if (!info)
1066 return;
1067
1068 if ( debug_level >= DEBUG_LEVEL_BH )
1069 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1070 __FILE__,__LINE__,info->device_name);
1071
1072 info->bh_running = true;
1073
1074 while((action = mgsl_bh_action(info)) != 0) {
1075
1076 /* Process work item */
1077 if ( debug_level >= DEBUG_LEVEL_BH )
1078 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1079 __FILE__,__LINE__,action);
1080
1081 switch (action) {
1082
1083 case BH_RECEIVE:
1084 mgsl_bh_receive(info);
1085 break;
1086 case BH_TRANSMIT:
1087 mgsl_bh_transmit(info);
1088 break;
1089 case BH_STATUS:
1090 mgsl_bh_status(info);
1091 break;
1092 default:
1093 /* unknown work item ID */
1094 printk("Unknown work item ID=%08X!\n", action);
1095 break;
1096 }
1097 }
1098
1099 if ( debug_level >= DEBUG_LEVEL_BH )
1100 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1101 __FILE__,__LINE__,info->device_name);
1102 }
1103
1104 static void mgsl_bh_receive(struct mgsl_struct *info)
1105 {
1106 bool (*get_rx_frame)(struct mgsl_struct *info) =
1107 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1108
1109 if ( debug_level >= DEBUG_LEVEL_BH )
1110 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1111 __FILE__,__LINE__,info->device_name);
1112
1113 do
1114 {
1115 if (info->rx_rcc_underrun) {
1116 unsigned long flags;
1117 spin_lock_irqsave(&info->irq_spinlock,flags);
1118 usc_start_receiver(info);
1119 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1120 return;
1121 }
1122 } while(get_rx_frame(info));
1123 }
1124
1125 static void mgsl_bh_transmit(struct mgsl_struct *info)
1126 {
1127 struct tty_struct *tty = info->port.tty;
1128 unsigned long flags;
1129
1130 if ( debug_level >= DEBUG_LEVEL_BH )
1131 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1132 __FILE__,__LINE__,info->device_name);
1133
1134 if (tty)
1135 tty_wakeup(tty);
1136
1137 /* if transmitter idle and loopmode_send_done_requested
1138 * then start echoing RxD to TxD
1139 */
1140 spin_lock_irqsave(&info->irq_spinlock,flags);
1141 if ( !info->tx_active && info->loopmode_send_done_requested )
1142 usc_loopmode_send_done( info );
1143 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1144 }
1145
1146 static void mgsl_bh_status(struct mgsl_struct *info)
1147 {
1148 if ( debug_level >= DEBUG_LEVEL_BH )
1149 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1150 __FILE__,__LINE__,info->device_name);
1151
1152 info->ri_chkcount = 0;
1153 info->dsr_chkcount = 0;
1154 info->dcd_chkcount = 0;
1155 info->cts_chkcount = 0;
1156 }
1157
1158 /* mgsl_isr_receive_status()
1159 *
1160 * Service a receive status interrupt. The type of status
1161 * interrupt is indicated by the state of the RCSR.
1162 * This is only used for HDLC mode.
1163 *
1164 * Arguments: info pointer to device instance data
1165 * Return Value: None
1166 */
1167 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1168 {
1169 u16 status = usc_InReg( info, RCSR );
1170
1171 if ( debug_level >= DEBUG_LEVEL_ISR )
1172 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1173 __FILE__,__LINE__,status);
1174
1175 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1176 info->loopmode_insert_requested &&
1177 usc_loopmode_active(info) )
1178 {
1179 ++info->icount.rxabort;
1180 info->loopmode_insert_requested = false;
1181
1182 /* clear CMR:13 to start echoing RxD to TxD */
1183 info->cmr_value &= ~BIT13;
1184 usc_OutReg(info, CMR, info->cmr_value);
1185
1186 /* disable received abort irq (no longer required) */
1187 usc_OutReg(info, RICR,
1188 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1189 }
1190
1191 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1192 if (status & RXSTATUS_EXITED_HUNT)
1193 info->icount.exithunt++;
1194 if (status & RXSTATUS_IDLE_RECEIVED)
1195 info->icount.rxidle++;
1196 wake_up_interruptible(&info->event_wait_q);
1197 }
1198
1199 if (status & RXSTATUS_OVERRUN){
1200 info->icount.rxover++;
1201 usc_process_rxoverrun_sync( info );
1202 }
1203
1204 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1205 usc_UnlatchRxstatusBits( info, status );
1206
1207 } /* end of mgsl_isr_receive_status() */
1208
1209 /* mgsl_isr_transmit_status()
1210 *
1211 * Service a transmit status interrupt
1212 * HDLC mode :end of transmit frame
1213 * Async mode:all data is sent
1214 * transmit status is indicated by bits in the TCSR.
1215 *
1216 * Arguments: info pointer to device instance data
1217 * Return Value: None
1218 */
1219 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1220 {
1221 u16 status = usc_InReg( info, TCSR );
1222
1223 if ( debug_level >= DEBUG_LEVEL_ISR )
1224 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1225 __FILE__,__LINE__,status);
1226
1227 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1228 usc_UnlatchTxstatusBits( info, status );
1229
1230 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1231 {
1232 /* finished sending HDLC abort. This may leave */
1233 /* the TxFifo with data from the aborted frame */
1234 /* so purge the TxFifo. Also shutdown the DMA */
1235 /* channel in case there is data remaining in */
1236 /* the DMA buffer */
1237 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1238 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1239 }
1240
1241 if ( status & TXSTATUS_EOF_SENT )
1242 info->icount.txok++;
1243 else if ( status & TXSTATUS_UNDERRUN )
1244 info->icount.txunder++;
1245 else if ( status & TXSTATUS_ABORT_SENT )
1246 info->icount.txabort++;
1247 else
1248 info->icount.txunder++;
1249
1250 info->tx_active = false;
1251 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1252 del_timer(&info->tx_timer);
1253
1254 if ( info->drop_rts_on_tx_done ) {
1255 usc_get_serial_signals( info );
1256 if ( info->serial_signals & SerialSignal_RTS ) {
1257 info->serial_signals &= ~SerialSignal_RTS;
1258 usc_set_serial_signals( info );
1259 }
1260 info->drop_rts_on_tx_done = false;
1261 }
1262
1263 #if SYNCLINK_GENERIC_HDLC
1264 if (info->netcount)
1265 hdlcdev_tx_done(info);
1266 else
1267 #endif
1268 {
1269 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1270 usc_stop_transmitter(info);
1271 return;
1272 }
1273 info->pending_bh |= BH_TRANSMIT;
1274 }
1275
1276 } /* end of mgsl_isr_transmit_status() */
1277
1278 /* mgsl_isr_io_pin()
1279 *
1280 * Service an Input/Output pin interrupt. The type of
1281 * interrupt is indicated by bits in the MISR
1282 *
1283 * Arguments: info pointer to device instance data
1284 * Return Value: None
1285 */
1286 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1287 {
1288 struct mgsl_icount *icount;
1289 u16 status = usc_InReg( info, MISR );
1290
1291 if ( debug_level >= DEBUG_LEVEL_ISR )
1292 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1293 __FILE__,__LINE__,status);
1294
1295 usc_ClearIrqPendingBits( info, IO_PIN );
1296 usc_UnlatchIostatusBits( info, status );
1297
1298 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1299 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1300 icount = &info->icount;
1301 /* update input line counters */
1302 if (status & MISCSTATUS_RI_LATCHED) {
1303 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1304 usc_DisablestatusIrqs(info,SICR_RI);
1305 icount->rng++;
1306 if ( status & MISCSTATUS_RI )
1307 info->input_signal_events.ri_up++;
1308 else
1309 info->input_signal_events.ri_down++;
1310 }
1311 if (status & MISCSTATUS_DSR_LATCHED) {
1312 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1313 usc_DisablestatusIrqs(info,SICR_DSR);
1314 icount->dsr++;
1315 if ( status & MISCSTATUS_DSR )
1316 info->input_signal_events.dsr_up++;
1317 else
1318 info->input_signal_events.dsr_down++;
1319 }
1320 if (status & MISCSTATUS_DCD_LATCHED) {
1321 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1322 usc_DisablestatusIrqs(info,SICR_DCD);
1323 icount->dcd++;
1324 if (status & MISCSTATUS_DCD) {
1325 info->input_signal_events.dcd_up++;
1326 } else
1327 info->input_signal_events.dcd_down++;
1328 #if SYNCLINK_GENERIC_HDLC
1329 if (info->netcount) {
1330 if (status & MISCSTATUS_DCD)
1331 netif_carrier_on(info->netdev);
1332 else
1333 netif_carrier_off(info->netdev);
1334 }
1335 #endif
1336 }
1337 if (status & MISCSTATUS_CTS_LATCHED)
1338 {
1339 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340 usc_DisablestatusIrqs(info,SICR_CTS);
1341 icount->cts++;
1342 if ( status & MISCSTATUS_CTS )
1343 info->input_signal_events.cts_up++;
1344 else
1345 info->input_signal_events.cts_down++;
1346 }
1347 wake_up_interruptible(&info->status_event_wait_q);
1348 wake_up_interruptible(&info->event_wait_q);
1349
1350 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1351 (status & MISCSTATUS_DCD_LATCHED) ) {
1352 if ( debug_level >= DEBUG_LEVEL_ISR )
1353 printk("%s CD now %s...", info->device_name,
1354 (status & MISCSTATUS_DCD) ? "on" : "off");
1355 if (status & MISCSTATUS_DCD)
1356 wake_up_interruptible(&info->port.open_wait);
1357 else {
1358 if ( debug_level >= DEBUG_LEVEL_ISR )
1359 printk("doing serial hangup...");
1360 if (info->port.tty)
1361 tty_hangup(info->port.tty);
1362 }
1363 }
1364
1365 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
1366 (status & MISCSTATUS_CTS_LATCHED) ) {
1367 if (info->port.tty->hw_stopped) {
1368 if (status & MISCSTATUS_CTS) {
1369 if ( debug_level >= DEBUG_LEVEL_ISR )
1370 printk("CTS tx start...");
1371 if (info->port.tty)
1372 info->port.tty->hw_stopped = 0;
1373 usc_start_transmitter(info);
1374 info->pending_bh |= BH_TRANSMIT;
1375 return;
1376 }
1377 } else {
1378 if (!(status & MISCSTATUS_CTS)) {
1379 if ( debug_level >= DEBUG_LEVEL_ISR )
1380 printk("CTS tx stop...");
1381 if (info->port.tty)
1382 info->port.tty->hw_stopped = 1;
1383 usc_stop_transmitter(info);
1384 }
1385 }
1386 }
1387 }
1388
1389 info->pending_bh |= BH_STATUS;
1390
1391 /* for diagnostics set IRQ flag */
1392 if ( status & MISCSTATUS_TXC_LATCHED ){
1393 usc_OutReg( info, SICR,
1394 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1395 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1396 info->irq_occurred = true;
1397 }
1398
1399 } /* end of mgsl_isr_io_pin() */
1400
1401 /* mgsl_isr_transmit_data()
1402 *
1403 * Service a transmit data interrupt (async mode only).
1404 *
1405 * Arguments: info pointer to device instance data
1406 * Return Value: None
1407 */
1408 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1409 {
1410 if ( debug_level >= DEBUG_LEVEL_ISR )
1411 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1412 __FILE__,__LINE__,info->xmit_cnt);
1413
1414 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1415
1416 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1417 usc_stop_transmitter(info);
1418 return;
1419 }
1420
1421 if ( info->xmit_cnt )
1422 usc_load_txfifo( info );
1423 else
1424 info->tx_active = false;
1425
1426 if (info->xmit_cnt < WAKEUP_CHARS)
1427 info->pending_bh |= BH_TRANSMIT;
1428
1429 } /* end of mgsl_isr_transmit_data() */
1430
1431 /* mgsl_isr_receive_data()
1432 *
1433 * Service a receive data interrupt. This occurs
1434 * when operating in asynchronous interrupt transfer mode.
1435 * The receive data FIFO is flushed to the receive data buffers.
1436 *
1437 * Arguments: info pointer to device instance data
1438 * Return Value: None
1439 */
1440 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1441 {
1442 int Fifocount;
1443 u16 status;
1444 int work = 0;
1445 unsigned char DataByte;
1446 struct tty_struct *tty = info->port.tty;
1447 struct mgsl_icount *icount = &info->icount;
1448
1449 if ( debug_level >= DEBUG_LEVEL_ISR )
1450 printk("%s(%d):mgsl_isr_receive_data\n",
1451 __FILE__,__LINE__);
1452
1453 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1454
1455 /* select FIFO status for RICR readback */
1456 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1457
1458 /* clear the Wordstatus bit so that status readback */
1459 /* only reflects the status of this byte */
1460 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1461
1462 /* flush the receive FIFO */
1463
1464 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1465 int flag;
1466
1467 /* read one byte from RxFIFO */
1468 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1469 info->io_base + CCAR );
1470 DataByte = inb( info->io_base + CCAR );
1471
1472 /* get the status of the received byte */
1473 status = usc_InReg(info, RCSR);
1474 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1475 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1476 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1477
1478 icount->rx++;
1479
1480 flag = 0;
1481 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1482 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1483 printk("rxerr=%04X\n",status);
1484 /* update error statistics */
1485 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1486 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1487 icount->brk++;
1488 } else if (status & RXSTATUS_PARITY_ERROR)
1489 icount->parity++;
1490 else if (status & RXSTATUS_FRAMING_ERROR)
1491 icount->frame++;
1492 else if (status & RXSTATUS_OVERRUN) {
1493 /* must issue purge fifo cmd before */
1494 /* 16C32 accepts more receive chars */
1495 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1496 icount->overrun++;
1497 }
1498
1499 /* discard char if tty control flags say so */
1500 if (status & info->ignore_status_mask)
1501 continue;
1502
1503 status &= info->read_status_mask;
1504
1505 if (status & RXSTATUS_BREAK_RECEIVED) {
1506 flag = TTY_BREAK;
1507 if (info->port.flags & ASYNC_SAK)
1508 do_SAK(tty);
1509 } else if (status & RXSTATUS_PARITY_ERROR)
1510 flag = TTY_PARITY;
1511 else if (status & RXSTATUS_FRAMING_ERROR)
1512 flag = TTY_FRAME;
1513 } /* end of if (error) */
1514 tty_insert_flip_char(tty, DataByte, flag);
1515 if (status & RXSTATUS_OVERRUN) {
1516 /* Overrun is special, since it's
1517 * reported immediately, and doesn't
1518 * affect the current character
1519 */
1520 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1521 }
1522 }
1523
1524 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1525 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1526 __FILE__,__LINE__,icount->rx,icount->brk,
1527 icount->parity,icount->frame,icount->overrun);
1528 }
1529
1530 if(work)
1531 tty_flip_buffer_push(tty);
1532 }
1533
1534 /* mgsl_isr_misc()
1535 *
1536 * Service a miscellaneous interrupt source.
1537 *
1538 * Arguments: info pointer to device extension (instance data)
1539 * Return Value: None
1540 */
1541 static void mgsl_isr_misc( struct mgsl_struct *info )
1542 {
1543 u16 status = usc_InReg( info, MISR );
1544
1545 if ( debug_level >= DEBUG_LEVEL_ISR )
1546 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1547 __FILE__,__LINE__,status);
1548
1549 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1550 (info->params.mode == MGSL_MODE_HDLC)) {
1551
1552 /* turn off receiver and rx DMA */
1553 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1554 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1555 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1556 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1557 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1558
1559 /* schedule BH handler to restart receiver */
1560 info->pending_bh |= BH_RECEIVE;
1561 info->rx_rcc_underrun = true;
1562 }
1563
1564 usc_ClearIrqPendingBits( info, MISC );
1565 usc_UnlatchMiscstatusBits( info, status );
1566
1567 } /* end of mgsl_isr_misc() */
1568
1569 /* mgsl_isr_null()
1570 *
1571 * Services undefined interrupt vectors from the
1572 * USC. (hence this function SHOULD never be called)
1573 *
1574 * Arguments: info pointer to device extension (instance data)
1575 * Return Value: None
1576 */
1577 static void mgsl_isr_null( struct mgsl_struct *info )
1578 {
1579
1580 } /* end of mgsl_isr_null() */
1581
1582 /* mgsl_isr_receive_dma()
1583 *
1584 * Service a receive DMA channel interrupt.
1585 * For this driver there are two sources of receive DMA interrupts
1586 * as identified in the Receive DMA mode Register (RDMR):
1587 *
1588 * BIT3 EOA/EOL End of List, all receive buffers in receive
1589 * buffer list have been filled (no more free buffers
1590 * available). The DMA controller has shut down.
1591 *
1592 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1593 * DMA buffer is terminated in response to completion
1594 * of a good frame or a frame with errors. The status
1595 * of the frame is stored in the buffer entry in the
1596 * list of receive buffer entries.
1597 *
1598 * Arguments: info pointer to device instance data
1599 * Return Value: None
1600 */
1601 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1602 {
1603 u16 status;
1604
1605 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1606 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1607
1608 /* Read the receive DMA status to identify interrupt type. */
1609 /* This also clears the status bits. */
1610 status = usc_InDmaReg( info, RDMR );
1611
1612 if ( debug_level >= DEBUG_LEVEL_ISR )
1613 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1614 __FILE__,__LINE__,info->device_name,status);
1615
1616 info->pending_bh |= BH_RECEIVE;
1617
1618 if ( status & BIT3 ) {
1619 info->rx_overflow = true;
1620 info->icount.buf_overrun++;
1621 }
1622
1623 } /* end of mgsl_isr_receive_dma() */
1624
1625 /* mgsl_isr_transmit_dma()
1626 *
1627 * This function services a transmit DMA channel interrupt.
1628 *
1629 * For this driver there is one source of transmit DMA interrupts
1630 * as identified in the Transmit DMA Mode Register (TDMR):
1631 *
1632 * BIT2 EOB End of Buffer. This interrupt occurs when a
1633 * transmit DMA buffer has been emptied.
1634 *
1635 * The driver maintains enough transmit DMA buffers to hold at least
1636 * one max frame size transmit frame. When operating in a buffered
1637 * transmit mode, there may be enough transmit DMA buffers to hold at
1638 * least two or more max frame size frames. On an EOB condition,
1639 * determine if there are any queued transmit buffers and copy into
1640 * transmit DMA buffers if we have room.
1641 *
1642 * Arguments: info pointer to device instance data
1643 * Return Value: None
1644 */
1645 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1646 {
1647 u16 status;
1648
1649 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1650 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1651
1652 /* Read the transmit DMA status to identify interrupt type. */
1653 /* This also clears the status bits. */
1654
1655 status = usc_InDmaReg( info, TDMR );
1656
1657 if ( debug_level >= DEBUG_LEVEL_ISR )
1658 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1659 __FILE__,__LINE__,info->device_name,status);
1660
1661 if ( status & BIT2 ) {
1662 --info->tx_dma_buffers_used;
1663
1664 /* if there are transmit frames queued,
1665 * try to load the next one
1666 */
1667 if ( load_next_tx_holding_buffer(info) ) {
1668 /* if call returns non-zero value, we have
1669 * at least one free tx holding buffer
1670 */
1671 info->pending_bh |= BH_TRANSMIT;
1672 }
1673 }
1674
1675 } /* end of mgsl_isr_transmit_dma() */
1676
1677 /* mgsl_interrupt()
1678 *
1679 * Interrupt service routine entry point.
1680 *
1681 * Arguments:
1682 *
1683 * irq interrupt number that caused interrupt
1684 * dev_id device ID supplied during interrupt registration
1685 *
1686 * Return Value: None
1687 */
1688 static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1689 {
1690 struct mgsl_struct *info = dev_id;
1691 u16 UscVector;
1692 u16 DmaVector;
1693
1694 if ( debug_level >= DEBUG_LEVEL_ISR )
1695 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1696 __FILE__, __LINE__, info->irq_level);
1697
1698 spin_lock(&info->irq_spinlock);
1699
1700 for(;;) {
1701 /* Read the interrupt vectors from hardware. */
1702 UscVector = usc_InReg(info, IVR) >> 9;
1703 DmaVector = usc_InDmaReg(info, DIVR);
1704
1705 if ( debug_level >= DEBUG_LEVEL_ISR )
1706 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1707 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1708
1709 if ( !UscVector && !DmaVector )
1710 break;
1711
1712 /* Dispatch interrupt vector */
1713 if ( UscVector )
1714 (*UscIsrTable[UscVector])(info);
1715 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1716 mgsl_isr_transmit_dma(info);
1717 else
1718 mgsl_isr_receive_dma(info);
1719
1720 if ( info->isr_overflow ) {
1721 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1722 __FILE__, __LINE__, info->device_name, info->irq_level);
1723 usc_DisableMasterIrqBit(info);
1724 usc_DisableDmaInterrupts(info,DICR_MASTER);
1725 break;
1726 }
1727 }
1728
1729 /* Request bottom half processing if there's something
1730 * for it to do and the bh is not already running
1731 */
1732
1733 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1734 if ( debug_level >= DEBUG_LEVEL_ISR )
1735 printk("%s(%d):%s queueing bh task.\n",
1736 __FILE__,__LINE__,info->device_name);
1737 schedule_work(&info->task);
1738 info->bh_requested = true;
1739 }
1740
1741 spin_unlock(&info->irq_spinlock);
1742
1743 if ( debug_level >= DEBUG_LEVEL_ISR )
1744 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1745 __FILE__, __LINE__, info->irq_level);
1746
1747 return IRQ_HANDLED;
1748 } /* end of mgsl_interrupt() */
1749
1750 /* startup()
1751 *
1752 * Initialize and start device.
1753 *
1754 * Arguments: info pointer to device instance data
1755 * Return Value: 0 if success, otherwise error code
1756 */
1757 static int startup(struct mgsl_struct * info)
1758 {
1759 int retval = 0;
1760
1761 if ( debug_level >= DEBUG_LEVEL_INFO )
1762 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1763
1764 if (info->port.flags & ASYNC_INITIALIZED)
1765 return 0;
1766
1767 if (!info->xmit_buf) {
1768 /* allocate a page of memory for a transmit buffer */
1769 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1770 if (!info->xmit_buf) {
1771 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1772 __FILE__,__LINE__,info->device_name);
1773 return -ENOMEM;
1774 }
1775 }
1776
1777 info->pending_bh = 0;
1778
1779 memset(&info->icount, 0, sizeof(info->icount));
1780
1781 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1782
1783 /* Allocate and claim adapter resources */
1784 retval = mgsl_claim_resources(info);
1785
1786 /* perform existence check and diagnostics */
1787 if ( !retval )
1788 retval = mgsl_adapter_test(info);
1789
1790 if ( retval ) {
1791 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1792 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1793 mgsl_release_resources(info);
1794 return retval;
1795 }
1796
1797 /* program hardware for current parameters */
1798 mgsl_change_params(info);
1799
1800 if (info->port.tty)
1801 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1802
1803 info->port.flags |= ASYNC_INITIALIZED;
1804
1805 return 0;
1806
1807 } /* end of startup() */
1808
1809 /* shutdown()
1810 *
1811 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1812 *
1813 * Arguments: info pointer to device instance data
1814 * Return Value: None
1815 */
1816 static void shutdown(struct mgsl_struct * info)
1817 {
1818 unsigned long flags;
1819
1820 if (!(info->port.flags & ASYNC_INITIALIZED))
1821 return;
1822
1823 if (debug_level >= DEBUG_LEVEL_INFO)
1824 printk("%s(%d):mgsl_shutdown(%s)\n",
1825 __FILE__,__LINE__, info->device_name );
1826
1827 /* clear status wait queue because status changes */
1828 /* can't happen after shutting down the hardware */
1829 wake_up_interruptible(&info->status_event_wait_q);
1830 wake_up_interruptible(&info->event_wait_q);
1831
1832 del_timer_sync(&info->tx_timer);
1833
1834 if (info->xmit_buf) {
1835 free_page((unsigned long) info->xmit_buf);
1836 info->xmit_buf = NULL;
1837 }
1838
1839 spin_lock_irqsave(&info->irq_spinlock,flags);
1840 usc_DisableMasterIrqBit(info);
1841 usc_stop_receiver(info);
1842 usc_stop_transmitter(info);
1843 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1844 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1845 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1846
1847 /* Disable DMAEN (Port 7, Bit 14) */
1848 /* This disconnects the DMA request signal from the ISA bus */
1849 /* on the ISA adapter. This has no effect for the PCI adapter */
1850 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1851
1852 /* Disable INTEN (Port 6, Bit12) */
1853 /* This disconnects the IRQ request signal to the ISA bus */
1854 /* on the ISA adapter. This has no effect for the PCI adapter */
1855 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1856
1857 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
1858 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1859 usc_set_serial_signals(info);
1860 }
1861
1862 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1863
1864 mgsl_release_resources(info);
1865
1866 if (info->port.tty)
1867 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1868
1869 info->port.flags &= ~ASYNC_INITIALIZED;
1870
1871 } /* end of shutdown() */
1872
1873 static void mgsl_program_hw(struct mgsl_struct *info)
1874 {
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&info->irq_spinlock,flags);
1878
1879 usc_stop_receiver(info);
1880 usc_stop_transmitter(info);
1881 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1882
1883 if (info->params.mode == MGSL_MODE_HDLC ||
1884 info->params.mode == MGSL_MODE_RAW ||
1885 info->netcount)
1886 usc_set_sync_mode(info);
1887 else
1888 usc_set_async_mode(info);
1889
1890 usc_set_serial_signals(info);
1891
1892 info->dcd_chkcount = 0;
1893 info->cts_chkcount = 0;
1894 info->ri_chkcount = 0;
1895 info->dsr_chkcount = 0;
1896
1897 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1898 usc_EnableInterrupts(info, IO_PIN);
1899 usc_get_serial_signals(info);
1900
1901 if (info->netcount || info->port.tty->termios->c_cflag & CREAD)
1902 usc_start_receiver(info);
1903
1904 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1905 }
1906
1907 /* Reconfigure adapter based on new parameters
1908 */
1909 static void mgsl_change_params(struct mgsl_struct *info)
1910 {
1911 unsigned cflag;
1912 int bits_per_char;
1913
1914 if (!info->port.tty || !info->port.tty->termios)
1915 return;
1916
1917 if (debug_level >= DEBUG_LEVEL_INFO)
1918 printk("%s(%d):mgsl_change_params(%s)\n",
1919 __FILE__,__LINE__, info->device_name );
1920
1921 cflag = info->port.tty->termios->c_cflag;
1922
1923 /* if B0 rate (hangup) specified then negate DTR and RTS */
1924 /* otherwise assert DTR and RTS */
1925 if (cflag & CBAUD)
1926 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1927 else
1928 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1929
1930 /* byte size and parity */
1931
1932 switch (cflag & CSIZE) {
1933 case CS5: info->params.data_bits = 5; break;
1934 case CS6: info->params.data_bits = 6; break;
1935 case CS7: info->params.data_bits = 7; break;
1936 case CS8: info->params.data_bits = 8; break;
1937 /* Never happens, but GCC is too dumb to figure it out */
1938 default: info->params.data_bits = 7; break;
1939 }
1940
1941 if (cflag & CSTOPB)
1942 info->params.stop_bits = 2;
1943 else
1944 info->params.stop_bits = 1;
1945
1946 info->params.parity = ASYNC_PARITY_NONE;
1947 if (cflag & PARENB) {
1948 if (cflag & PARODD)
1949 info->params.parity = ASYNC_PARITY_ODD;
1950 else
1951 info->params.parity = ASYNC_PARITY_EVEN;
1952 #ifdef CMSPAR
1953 if (cflag & CMSPAR)
1954 info->params.parity = ASYNC_PARITY_SPACE;
1955 #endif
1956 }
1957
1958 /* calculate number of jiffies to transmit a full
1959 * FIFO (32 bytes) at specified data rate
1960 */
1961 bits_per_char = info->params.data_bits +
1962 info->params.stop_bits + 1;
1963
1964 /* if port data rate is set to 460800 or less then
1965 * allow tty settings to override, otherwise keep the
1966 * current data rate.
1967 */
1968 if (info->params.data_rate <= 460800)
1969 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1970
1971 if ( info->params.data_rate ) {
1972 info->timeout = (32*HZ*bits_per_char) /
1973 info->params.data_rate;
1974 }
1975 info->timeout += HZ/50; /* Add .02 seconds of slop */
1976
1977 if (cflag & CRTSCTS)
1978 info->port.flags |= ASYNC_CTS_FLOW;
1979 else
1980 info->port.flags &= ~ASYNC_CTS_FLOW;
1981
1982 if (cflag & CLOCAL)
1983 info->port.flags &= ~ASYNC_CHECK_CD;
1984 else
1985 info->port.flags |= ASYNC_CHECK_CD;
1986
1987 /* process tty input control flags */
1988
1989 info->read_status_mask = RXSTATUS_OVERRUN;
1990 if (I_INPCK(info->port.tty))
1991 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1992 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1993 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1994
1995 if (I_IGNPAR(info->port.tty))
1996 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1997 if (I_IGNBRK(info->port.tty)) {
1998 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1999 /* If ignoring parity and break indicators, ignore
2000 * overruns too. (For real raw support).
2001 */
2002 if (I_IGNPAR(info->port.tty))
2003 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2004 }
2005
2006 mgsl_program_hw(info);
2007
2008 } /* end of mgsl_change_params() */
2009
2010 /* mgsl_put_char()
2011 *
2012 * Add a character to the transmit buffer.
2013 *
2014 * Arguments: tty pointer to tty information structure
2015 * ch character to add to transmit buffer
2016 *
2017 * Return Value: None
2018 */
2019 static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2020 {
2021 struct mgsl_struct *info = tty->driver_data;
2022 unsigned long flags;
2023 int ret = 0;
2024
2025 if (debug_level >= DEBUG_LEVEL_INFO) {
2026 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2027 __FILE__, __LINE__, ch, info->device_name);
2028 }
2029
2030 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2031 return 0;
2032
2033 if (!tty || !info->xmit_buf)
2034 return 0;
2035
2036 spin_lock_irqsave(&info->irq_spinlock, flags);
2037
2038 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2039 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2040 info->xmit_buf[info->xmit_head++] = ch;
2041 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2042 info->xmit_cnt++;
2043 ret = 1;
2044 }
2045 }
2046 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2047 return ret;
2048
2049 } /* end of mgsl_put_char() */
2050
2051 /* mgsl_flush_chars()
2052 *
2053 * Enable transmitter so remaining characters in the
2054 * transmit buffer are sent.
2055 *
2056 * Arguments: tty pointer to tty information structure
2057 * Return Value: None
2058 */
2059 static void mgsl_flush_chars(struct tty_struct *tty)
2060 {
2061 struct mgsl_struct *info = tty->driver_data;
2062 unsigned long flags;
2063
2064 if ( debug_level >= DEBUG_LEVEL_INFO )
2065 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2066 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2067
2068 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2069 return;
2070
2071 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2072 !info->xmit_buf)
2073 return;
2074
2075 if ( debug_level >= DEBUG_LEVEL_INFO )
2076 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2077 __FILE__,__LINE__,info->device_name );
2078
2079 spin_lock_irqsave(&info->irq_spinlock,flags);
2080
2081 if (!info->tx_active) {
2082 if ( (info->params.mode == MGSL_MODE_HDLC ||
2083 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2084 /* operating in synchronous (frame oriented) mode */
2085 /* copy data from circular xmit_buf to */
2086 /* transmit DMA buffer. */
2087 mgsl_load_tx_dma_buffer(info,
2088 info->xmit_buf,info->xmit_cnt);
2089 }
2090 usc_start_transmitter(info);
2091 }
2092
2093 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2094
2095 } /* end of mgsl_flush_chars() */
2096
2097 /* mgsl_write()
2098 *
2099 * Send a block of data
2100 *
2101 * Arguments:
2102 *
2103 * tty pointer to tty information structure
2104 * buf pointer to buffer containing send data
2105 * count size of send data in bytes
2106 *
2107 * Return Value: number of characters written
2108 */
2109 static int mgsl_write(struct tty_struct * tty,
2110 const unsigned char *buf, int count)
2111 {
2112 int c, ret = 0;
2113 struct mgsl_struct *info = tty->driver_data;
2114 unsigned long flags;
2115
2116 if ( debug_level >= DEBUG_LEVEL_INFO )
2117 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2118 __FILE__,__LINE__,info->device_name,count);
2119
2120 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2121 goto cleanup;
2122
2123 if (!tty || !info->xmit_buf)
2124 goto cleanup;
2125
2126 if ( info->params.mode == MGSL_MODE_HDLC ||
2127 info->params.mode == MGSL_MODE_RAW ) {
2128 /* operating in synchronous (frame oriented) mode */
2129 /* operating in synchronous (frame oriented) mode */
2130 if (info->tx_active) {
2131
2132 if ( info->params.mode == MGSL_MODE_HDLC ) {
2133 ret = 0;
2134 goto cleanup;
2135 }
2136 /* transmitter is actively sending data -
2137 * if we have multiple transmit dma and
2138 * holding buffers, attempt to queue this
2139 * frame for transmission at a later time.
2140 */
2141 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2142 /* no tx holding buffers available */
2143 ret = 0;
2144 goto cleanup;
2145 }
2146
2147 /* queue transmit frame request */
2148 ret = count;
2149 save_tx_buffer_request(info,buf,count);
2150
2151 /* if we have sufficient tx dma buffers,
2152 * load the next buffered tx request
2153 */
2154 spin_lock_irqsave(&info->irq_spinlock,flags);
2155 load_next_tx_holding_buffer(info);
2156 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2157 goto cleanup;
2158 }
2159
2160 /* if operating in HDLC LoopMode and the adapter */
2161 /* has yet to be inserted into the loop, we can't */
2162 /* transmit */
2163
2164 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2165 !usc_loopmode_active(info) )
2166 {
2167 ret = 0;
2168 goto cleanup;
2169 }
2170
2171 if ( info->xmit_cnt ) {
2172 /* Send accumulated from send_char() calls */
2173 /* as frame and wait before accepting more data. */
2174 ret = 0;
2175
2176 /* copy data from circular xmit_buf to */
2177 /* transmit DMA buffer. */
2178 mgsl_load_tx_dma_buffer(info,
2179 info->xmit_buf,info->xmit_cnt);
2180 if ( debug_level >= DEBUG_LEVEL_INFO )
2181 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2182 __FILE__,__LINE__,info->device_name);
2183 } else {
2184 if ( debug_level >= DEBUG_LEVEL_INFO )
2185 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2186 __FILE__,__LINE__,info->device_name);
2187 ret = count;
2188 info->xmit_cnt = count;
2189 mgsl_load_tx_dma_buffer(info,buf,count);
2190 }
2191 } else {
2192 while (1) {
2193 spin_lock_irqsave(&info->irq_spinlock,flags);
2194 c = min_t(int, count,
2195 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2196 SERIAL_XMIT_SIZE - info->xmit_head));
2197 if (c <= 0) {
2198 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2199 break;
2200 }
2201 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2202 info->xmit_head = ((info->xmit_head + c) &
2203 (SERIAL_XMIT_SIZE-1));
2204 info->xmit_cnt += c;
2205 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2206 buf += c;
2207 count -= c;
2208 ret += c;
2209 }
2210 }
2211
2212 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2213 spin_lock_irqsave(&info->irq_spinlock,flags);
2214 if (!info->tx_active)
2215 usc_start_transmitter(info);
2216 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2217 }
2218 cleanup:
2219 if ( debug_level >= DEBUG_LEVEL_INFO )
2220 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2221 __FILE__,__LINE__,info->device_name,ret);
2222
2223 return ret;
2224
2225 } /* end of mgsl_write() */
2226
2227 /* mgsl_write_room()
2228 *
2229 * Return the count of free bytes in transmit buffer
2230 *
2231 * Arguments: tty pointer to tty info structure
2232 * Return Value: None
2233 */
2234 static int mgsl_write_room(struct tty_struct *tty)
2235 {
2236 struct mgsl_struct *info = tty->driver_data;
2237 int ret;
2238
2239 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2240 return 0;
2241 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2242 if (ret < 0)
2243 ret = 0;
2244
2245 if (debug_level >= DEBUG_LEVEL_INFO)
2246 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2247 __FILE__,__LINE__, info->device_name,ret );
2248
2249 if ( info->params.mode == MGSL_MODE_HDLC ||
2250 info->params.mode == MGSL_MODE_RAW ) {
2251 /* operating in synchronous (frame oriented) mode */
2252 if ( info->tx_active )
2253 return 0;
2254 else
2255 return HDLC_MAX_FRAME_SIZE;
2256 }
2257
2258 return ret;
2259
2260 } /* end of mgsl_write_room() */
2261
2262 /* mgsl_chars_in_buffer()
2263 *
2264 * Return the count of bytes in transmit buffer
2265 *
2266 * Arguments: tty pointer to tty info structure
2267 * Return Value: None
2268 */
2269 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2270 {
2271 struct mgsl_struct *info = tty->driver_data;
2272
2273 if (debug_level >= DEBUG_LEVEL_INFO)
2274 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2275 __FILE__,__LINE__, info->device_name );
2276
2277 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2278 return 0;
2279
2280 if (debug_level >= DEBUG_LEVEL_INFO)
2281 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2282 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2283
2284 if ( info->params.mode == MGSL_MODE_HDLC ||
2285 info->params.mode == MGSL_MODE_RAW ) {
2286 /* operating in synchronous (frame oriented) mode */
2287 if ( info->tx_active )
2288 return info->max_frame_size;
2289 else
2290 return 0;
2291 }
2292
2293 return info->xmit_cnt;
2294 } /* end of mgsl_chars_in_buffer() */
2295
2296 /* mgsl_flush_buffer()
2297 *
2298 * Discard all data in the send buffer
2299 *
2300 * Arguments: tty pointer to tty info structure
2301 * Return Value: None
2302 */
2303 static void mgsl_flush_buffer(struct tty_struct *tty)
2304 {
2305 struct mgsl_struct *info = tty->driver_data;
2306 unsigned long flags;
2307
2308 if (debug_level >= DEBUG_LEVEL_INFO)
2309 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2310 __FILE__,__LINE__, info->device_name );
2311
2312 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2313 return;
2314
2315 spin_lock_irqsave(&info->irq_spinlock,flags);
2316 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2317 del_timer(&info->tx_timer);
2318 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2319
2320 tty_wakeup(tty);
2321 }
2322
2323 /* mgsl_send_xchar()
2324 *
2325 * Send a high-priority XON/XOFF character
2326 *
2327 * Arguments: tty pointer to tty info structure
2328 * ch character to send
2329 * Return Value: None
2330 */
2331 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2332 {
2333 struct mgsl_struct *info = tty->driver_data;
2334 unsigned long flags;
2335
2336 if (debug_level >= DEBUG_LEVEL_INFO)
2337 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2338 __FILE__,__LINE__, info->device_name, ch );
2339
2340 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2341 return;
2342
2343 info->x_char = ch;
2344 if (ch) {
2345 /* Make sure transmit interrupts are on */
2346 spin_lock_irqsave(&info->irq_spinlock,flags);
2347 if (!info->tx_enabled)
2348 usc_start_transmitter(info);
2349 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2350 }
2351 } /* end of mgsl_send_xchar() */
2352
2353 /* mgsl_throttle()
2354 *
2355 * Signal remote device to throttle send data (our receive data)
2356 *
2357 * Arguments: tty pointer to tty info structure
2358 * Return Value: None
2359 */
2360 static void mgsl_throttle(struct tty_struct * tty)
2361 {
2362 struct mgsl_struct *info = tty->driver_data;
2363 unsigned long flags;
2364
2365 if (debug_level >= DEBUG_LEVEL_INFO)
2366 printk("%s(%d):mgsl_throttle(%s) entry\n",
2367 __FILE__,__LINE__, info->device_name );
2368
2369 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2370 return;
2371
2372 if (I_IXOFF(tty))
2373 mgsl_send_xchar(tty, STOP_CHAR(tty));
2374
2375 if (tty->termios->c_cflag & CRTSCTS) {
2376 spin_lock_irqsave(&info->irq_spinlock,flags);
2377 info->serial_signals &= ~SerialSignal_RTS;
2378 usc_set_serial_signals(info);
2379 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2380 }
2381 } /* end of mgsl_throttle() */
2382
2383 /* mgsl_unthrottle()
2384 *
2385 * Signal remote device to stop throttling send data (our receive data)
2386 *
2387 * Arguments: tty pointer to tty info structure
2388 * Return Value: None
2389 */
2390 static void mgsl_unthrottle(struct tty_struct * tty)
2391 {
2392 struct mgsl_struct *info = tty->driver_data;
2393 unsigned long flags;
2394
2395 if (debug_level >= DEBUG_LEVEL_INFO)
2396 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2397 __FILE__,__LINE__, info->device_name );
2398
2399 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2400 return;
2401
2402 if (I_IXOFF(tty)) {
2403 if (info->x_char)
2404 info->x_char = 0;
2405 else
2406 mgsl_send_xchar(tty, START_CHAR(tty));
2407 }
2408
2409 if (tty->termios->c_cflag & CRTSCTS) {
2410 spin_lock_irqsave(&info->irq_spinlock,flags);
2411 info->serial_signals |= SerialSignal_RTS;
2412 usc_set_serial_signals(info);
2413 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2414 }
2415
2416 } /* end of mgsl_unthrottle() */
2417
2418 /* mgsl_get_stats()
2419 *
2420 * get the current serial parameters information
2421 *
2422 * Arguments: info pointer to device instance data
2423 * user_icount pointer to buffer to hold returned stats
2424 *
2425 * Return Value: 0 if success, otherwise error code
2426 */
2427 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2428 {
2429 int err;
2430
2431 if (debug_level >= DEBUG_LEVEL_INFO)
2432 printk("%s(%d):mgsl_get_params(%s)\n",
2433 __FILE__,__LINE__, info->device_name);
2434
2435 if (!user_icount) {
2436 memset(&info->icount, 0, sizeof(info->icount));
2437 } else {
2438 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2439 if (err)
2440 return -EFAULT;
2441 }
2442
2443 return 0;
2444
2445 } /* end of mgsl_get_stats() */
2446
2447 /* mgsl_get_params()
2448 *
2449 * get the current serial parameters information
2450 *
2451 * Arguments: info pointer to device instance data
2452 * user_params pointer to buffer to hold returned params
2453 *
2454 * Return Value: 0 if success, otherwise error code
2455 */
2456 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2457 {
2458 int err;
2459 if (debug_level >= DEBUG_LEVEL_INFO)
2460 printk("%s(%d):mgsl_get_params(%s)\n",
2461 __FILE__,__LINE__, info->device_name);
2462
2463 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2464 if (err) {
2465 if ( debug_level >= DEBUG_LEVEL_INFO )
2466 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2467 __FILE__,__LINE__,info->device_name);
2468 return -EFAULT;
2469 }
2470
2471 return 0;
2472
2473 } /* end of mgsl_get_params() */
2474
2475 /* mgsl_set_params()
2476 *
2477 * set the serial parameters
2478 *
2479 * Arguments:
2480 *
2481 * info pointer to device instance data
2482 * new_params user buffer containing new serial params
2483 *
2484 * Return Value: 0 if success, otherwise error code
2485 */
2486 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2487 {
2488 unsigned long flags;
2489 MGSL_PARAMS tmp_params;
2490 int err;
2491
2492 if (debug_level >= DEBUG_LEVEL_INFO)
2493 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2494 info->device_name );
2495 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2496 if (err) {
2497 if ( debug_level >= DEBUG_LEVEL_INFO )
2498 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2499 __FILE__,__LINE__,info->device_name);
2500 return -EFAULT;
2501 }
2502
2503 spin_lock_irqsave(&info->irq_spinlock,flags);
2504 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2505 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2506
2507 mgsl_change_params(info);
2508
2509 return 0;
2510
2511 } /* end of mgsl_set_params() */
2512
2513 /* mgsl_get_txidle()
2514 *
2515 * get the current transmit idle mode
2516 *
2517 * Arguments: info pointer to device instance data
2518 * idle_mode pointer to buffer to hold returned idle mode
2519 *
2520 * Return Value: 0 if success, otherwise error code
2521 */
2522 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2523 {
2524 int err;
2525
2526 if (debug_level >= DEBUG_LEVEL_INFO)
2527 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2528 __FILE__,__LINE__, info->device_name, info->idle_mode);
2529
2530 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2531 if (err) {
2532 if ( debug_level >= DEBUG_LEVEL_INFO )
2533 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2534 __FILE__,__LINE__,info->device_name);
2535 return -EFAULT;
2536 }
2537
2538 return 0;
2539
2540 } /* end of mgsl_get_txidle() */
2541
2542 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2543 *
2544 * Arguments: info pointer to device instance data
2545 * idle_mode new idle mode
2546 *
2547 * Return Value: 0 if success, otherwise error code
2548 */
2549 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2550 {
2551 unsigned long flags;
2552
2553 if (debug_level >= DEBUG_LEVEL_INFO)
2554 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2555 info->device_name, idle_mode );
2556
2557 spin_lock_irqsave(&info->irq_spinlock,flags);
2558 info->idle_mode = idle_mode;
2559 usc_set_txidle( info );
2560 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2561 return 0;
2562
2563 } /* end of mgsl_set_txidle() */
2564
2565 /* mgsl_txenable()
2566 *
2567 * enable or disable the transmitter
2568 *
2569 * Arguments:
2570 *
2571 * info pointer to device instance data
2572 * enable 1 = enable, 0 = disable
2573 *
2574 * Return Value: 0 if success, otherwise error code
2575 */
2576 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2577 {
2578 unsigned long flags;
2579
2580 if (debug_level >= DEBUG_LEVEL_INFO)
2581 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2582 info->device_name, enable);
2583
2584 spin_lock_irqsave(&info->irq_spinlock,flags);
2585 if ( enable ) {
2586 if ( !info->tx_enabled ) {
2587
2588 usc_start_transmitter(info);
2589 /*--------------------------------------------------
2590 * if HDLC/SDLC Loop mode, attempt to insert the
2591 * station in the 'loop' by setting CMR:13. Upon
2592 * receipt of the next GoAhead (RxAbort) sequence,
2593 * the OnLoop indicator (CCSR:7) should go active
2594 * to indicate that we are on the loop
2595 *--------------------------------------------------*/
2596 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2597 usc_loopmode_insert_request( info );
2598 }
2599 } else {
2600 if ( info->tx_enabled )
2601 usc_stop_transmitter(info);
2602 }
2603 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2604 return 0;
2605
2606 } /* end of mgsl_txenable() */
2607
2608 /* mgsl_txabort() abort send HDLC frame
2609 *
2610 * Arguments: info pointer to device instance data
2611 * Return Value: 0 if success, otherwise error code
2612 */
2613 static int mgsl_txabort(struct mgsl_struct * info)
2614 {
2615 unsigned long flags;
2616
2617 if (debug_level >= DEBUG_LEVEL_INFO)
2618 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2619 info->device_name);
2620
2621 spin_lock_irqsave(&info->irq_spinlock,flags);
2622 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2623 {
2624 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2625 usc_loopmode_cancel_transmit( info );
2626 else
2627 usc_TCmd(info,TCmd_SendAbort);
2628 }
2629 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2630 return 0;
2631
2632 } /* end of mgsl_txabort() */
2633
2634 /* mgsl_rxenable() enable or disable the receiver
2635 *
2636 * Arguments: info pointer to device instance data
2637 * enable 1 = enable, 0 = disable
2638 * Return Value: 0 if success, otherwise error code
2639 */
2640 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2641 {
2642 unsigned long flags;
2643
2644 if (debug_level >= DEBUG_LEVEL_INFO)
2645 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2646 info->device_name, enable);
2647
2648 spin_lock_irqsave(&info->irq_spinlock,flags);
2649 if ( enable ) {
2650 if ( !info->rx_enabled )
2651 usc_start_receiver(info);
2652 } else {
2653 if ( info->rx_enabled )
2654 usc_stop_receiver(info);
2655 }
2656 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2657 return 0;
2658
2659 } /* end of mgsl_rxenable() */
2660
2661 /* mgsl_wait_event() wait for specified event to occur
2662 *
2663 * Arguments: info pointer to device instance data
2664 * mask pointer to bitmask of events to wait for
2665 * Return Value: 0 if successful and bit mask updated with
2666 * of events triggerred,
2667 * otherwise error code
2668 */
2669 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2670 {
2671 unsigned long flags;
2672 int s;
2673 int rc=0;
2674 struct mgsl_icount cprev, cnow;
2675 int events;
2676 int mask;
2677 struct _input_signal_events oldsigs, newsigs;
2678 DECLARE_WAITQUEUE(wait, current);
2679
2680 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2681 if (rc) {
2682 return -EFAULT;
2683 }
2684
2685 if (debug_level >= DEBUG_LEVEL_INFO)
2686 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2687 info->device_name, mask);
2688
2689 spin_lock_irqsave(&info->irq_spinlock,flags);
2690
2691 /* return immediately if state matches requested events */
2692 usc_get_serial_signals(info);
2693 s = info->serial_signals;
2694 events = mask &
2695 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2696 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2697 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2698 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2699 if (events) {
2700 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2701 goto exit;
2702 }
2703
2704 /* save current irq counts */
2705 cprev = info->icount;
2706 oldsigs = info->input_signal_events;
2707
2708 /* enable hunt and idle irqs if needed */
2709 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2710 u16 oldreg = usc_InReg(info,RICR);
2711 u16 newreg = oldreg +
2712 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2713 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2714 if (oldreg != newreg)
2715 usc_OutReg(info, RICR, newreg);
2716 }
2717
2718 set_current_state(TASK_INTERRUPTIBLE);
2719 add_wait_queue(&info->event_wait_q, &wait);
2720
2721 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2722
2723
2724 for(;;) {
2725 schedule();
2726 if (signal_pending(current)) {
2727 rc = -ERESTARTSYS;
2728 break;
2729 }
2730
2731 /* get current irq counts */
2732 spin_lock_irqsave(&info->irq_spinlock,flags);
2733 cnow = info->icount;
2734 newsigs = info->input_signal_events;
2735 set_current_state(TASK_INTERRUPTIBLE);
2736 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2737
2738 /* if no change, wait aborted for some reason */
2739 if (newsigs.dsr_up == oldsigs.dsr_up &&
2740 newsigs.dsr_down == oldsigs.dsr_down &&
2741 newsigs.dcd_up == oldsigs.dcd_up &&
2742 newsigs.dcd_down == oldsigs.dcd_down &&
2743 newsigs.cts_up == oldsigs.cts_up &&
2744 newsigs.cts_down == oldsigs.cts_down &&
2745 newsigs.ri_up == oldsigs.ri_up &&
2746 newsigs.ri_down == oldsigs.ri_down &&
2747 cnow.exithunt == cprev.exithunt &&
2748 cnow.rxidle == cprev.rxidle) {
2749 rc = -EIO;
2750 break;
2751 }
2752
2753 events = mask &
2754 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2755 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2756 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2757 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2758 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2759 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2760 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2761 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2762 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2763 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2764 if (events)
2765 break;
2766
2767 cprev = cnow;
2768 oldsigs = newsigs;
2769 }
2770
2771 remove_wait_queue(&info->event_wait_q, &wait);
2772 set_current_state(TASK_RUNNING);
2773
2774 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2775 spin_lock_irqsave(&info->irq_spinlock,flags);
2776 if (!waitqueue_active(&info->event_wait_q)) {
2777 /* disable enable exit hunt mode/idle rcvd IRQs */
2778 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2779 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2780 }
2781 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2782 }
2783 exit:
2784 if ( rc == 0 )
2785 PUT_USER(rc, events, mask_ptr);
2786
2787 return rc;
2788
2789 } /* end of mgsl_wait_event() */
2790
2791 static int modem_input_wait(struct mgsl_struct *info,int arg)
2792 {
2793 unsigned long flags;
2794 int rc;
2795 struct mgsl_icount cprev, cnow;
2796 DECLARE_WAITQUEUE(wait, current);
2797
2798 /* save current irq counts */
2799 spin_lock_irqsave(&info->irq_spinlock,flags);
2800 cprev = info->icount;
2801 add_wait_queue(&info->status_event_wait_q, &wait);
2802 set_current_state(TASK_INTERRUPTIBLE);
2803 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2804
2805 for(;;) {
2806 schedule();
2807 if (signal_pending(current)) {
2808 rc = -ERESTARTSYS;
2809 break;
2810 }
2811
2812 /* get new irq counts */
2813 spin_lock_irqsave(&info->irq_spinlock,flags);
2814 cnow = info->icount;
2815 set_current_state(TASK_INTERRUPTIBLE);
2816 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2817
2818 /* if no change, wait aborted for some reason */
2819 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2820 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2821 rc = -EIO;
2822 break;
2823 }
2824
2825 /* check for change in caller specified modem input */
2826 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2827 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2828 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2829 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2830 rc = 0;
2831 break;
2832 }
2833
2834 cprev = cnow;
2835 }
2836 remove_wait_queue(&info->status_event_wait_q, &wait);
2837 set_current_state(TASK_RUNNING);
2838 return rc;
2839 }
2840
2841 /* return the state of the serial control and status signals
2842 */
2843 static int tiocmget(struct tty_struct *tty, struct file *file)
2844 {
2845 struct mgsl_struct *info = tty->driver_data;
2846 unsigned int result;
2847 unsigned long flags;
2848
2849 spin_lock_irqsave(&info->irq_spinlock,flags);
2850 usc_get_serial_signals(info);
2851 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2852
2853 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2854 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2855 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2856 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2857 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2858 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2859
2860 if (debug_level >= DEBUG_LEVEL_INFO)
2861 printk("%s(%d):%s tiocmget() value=%08X\n",
2862 __FILE__,__LINE__, info->device_name, result );
2863 return result;
2864 }
2865
2866 /* set modem control signals (DTR/RTS)
2867 */
2868 static int tiocmset(struct tty_struct *tty, struct file *file,
2869 unsigned int set, unsigned int clear)
2870 {
2871 struct mgsl_struct *info = tty->driver_data;
2872 unsigned long flags;
2873
2874 if (debug_level >= DEBUG_LEVEL_INFO)
2875 printk("%s(%d):%s tiocmset(%x,%x)\n",
2876 __FILE__,__LINE__,info->device_name, set, clear);
2877
2878 if (set & TIOCM_RTS)
2879 info->serial_signals |= SerialSignal_RTS;
2880 if (set & TIOCM_DTR)
2881 info->serial_signals |= SerialSignal_DTR;
2882 if (clear & TIOCM_RTS)
2883 info->serial_signals &= ~SerialSignal_RTS;
2884 if (clear & TIOCM_DTR)
2885 info->serial_signals &= ~SerialSignal_DTR;
2886
2887 spin_lock_irqsave(&info->irq_spinlock,flags);
2888 usc_set_serial_signals(info);
2889 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2890
2891 return 0;
2892 }
2893
2894 /* mgsl_break() Set or clear transmit break condition
2895 *
2896 * Arguments: tty pointer to tty instance data
2897 * break_state -1=set break condition, 0=clear
2898 * Return Value: error code
2899 */
2900 static int mgsl_break(struct tty_struct *tty, int break_state)
2901 {
2902 struct mgsl_struct * info = tty->driver_data;
2903 unsigned long flags;
2904
2905 if (debug_level >= DEBUG_LEVEL_INFO)
2906 printk("%s(%d):mgsl_break(%s,%d)\n",
2907 __FILE__,__LINE__, info->device_name, break_state);
2908
2909 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2910 return -EINVAL;
2911
2912 spin_lock_irqsave(&info->irq_spinlock,flags);
2913 if (break_state == -1)
2914 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2915 else
2916 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2917 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2918 return 0;
2919
2920 } /* end of mgsl_break() */
2921
2922 /* mgsl_ioctl() Service an IOCTL request
2923 *
2924 * Arguments:
2925 *
2926 * tty pointer to tty instance data
2927 * file pointer to associated file object for device
2928 * cmd IOCTL command code
2929 * arg command argument/context
2930 *
2931 * Return Value: 0 if success, otherwise error code
2932 */
2933 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2934 unsigned int cmd, unsigned long arg)
2935 {
2936 struct mgsl_struct * info = tty->driver_data;
2937 int ret;
2938
2939 if (debug_level >= DEBUG_LEVEL_INFO)
2940 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2941 info->device_name, cmd );
2942
2943 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2944 return -ENODEV;
2945
2946 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2947 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2948 if (tty->flags & (1 << TTY_IO_ERROR))
2949 return -EIO;
2950 }
2951
2952 lock_kernel();
2953 ret = mgsl_ioctl_common(info, cmd, arg);
2954 unlock_kernel();
2955 return ret;
2956 }
2957
2958 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2959 {
2960 int error;
2961 struct mgsl_icount cnow; /* kernel counter temps */
2962 void __user *argp = (void __user *)arg;
2963 struct serial_icounter_struct __user *p_cuser; /* user space */
2964 unsigned long flags;
2965
2966 switch (cmd) {
2967 case MGSL_IOCGPARAMS:
2968 return mgsl_get_params(info, argp);
2969 case MGSL_IOCSPARAMS:
2970 return mgsl_set_params(info, argp);
2971 case MGSL_IOCGTXIDLE:
2972 return mgsl_get_txidle(info, argp);
2973 case MGSL_IOCSTXIDLE:
2974 return mgsl_set_txidle(info,(int)arg);
2975 case MGSL_IOCTXENABLE:
2976 return mgsl_txenable(info,(int)arg);
2977 case MGSL_IOCRXENABLE:
2978 return mgsl_rxenable(info,(int)arg);
2979 case MGSL_IOCTXABORT:
2980 return mgsl_txabort(info);
2981 case MGSL_IOCGSTATS:
2982 return mgsl_get_stats(info, argp);
2983 case MGSL_IOCWAITEVENT:
2984 return mgsl_wait_event(info, argp);
2985 case MGSL_IOCLOOPTXDONE:
2986 return mgsl_loopmode_send_done(info);
2987 /* Wait for modem input (DCD,RI,DSR,CTS) change
2988 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2989 */
2990 case TIOCMIWAIT:
2991 return modem_input_wait(info,(int)arg);
2992
2993 /*
2994 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2995 * Return: write counters to the user passed counter struct
2996 * NB: both 1->0 and 0->1 transitions are counted except for
2997 * RI where only 0->1 is counted.
2998 */
2999 case TIOCGICOUNT:
3000 spin_lock_irqsave(&info->irq_spinlock,flags);
3001 cnow = info->icount;
3002 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3003 p_cuser = argp;
3004 PUT_USER(error,cnow.cts, &p_cuser->cts);
3005 if (error) return error;
3006 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3007 if (error) return error;
3008 PUT_USER(error,cnow.rng, &p_cuser->rng);
3009 if (error) return error;
3010 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3011 if (error) return error;
3012 PUT_USER(error,cnow.rx, &p_cuser->rx);
3013 if (error) return error;
3014 PUT_USER(error,cnow.tx, &p_cuser->tx);
3015 if (error) return error;
3016 PUT_USER(error,cnow.frame, &p_cuser->frame);
3017 if (error) return error;
3018 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3019 if (error) return error;
3020 PUT_USER(error,cnow.parity, &p_cuser->parity);
3021 if (error) return error;
3022 PUT_USER(error,cnow.brk, &p_cuser->brk);
3023 if (error) return error;
3024 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3025 if (error) return error;
3026 return 0;
3027 default:
3028 return -ENOIOCTLCMD;
3029 }
3030 return 0;
3031 }
3032
3033 /* mgsl_set_termios()
3034 *
3035 * Set new termios settings
3036 *
3037 * Arguments:
3038 *
3039 * tty pointer to tty structure
3040 * termios pointer to buffer to hold returned old termios
3041 *
3042 * Return Value: None
3043 */
3044 static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3045 {
3046 struct mgsl_struct *info = tty->driver_data;
3047 unsigned long flags;
3048
3049 if (debug_level >= DEBUG_LEVEL_INFO)
3050 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3051 tty->driver->name );
3052
3053 mgsl_change_params(info);
3054
3055 /* Handle transition to B0 status */
3056 if (old_termios->c_cflag & CBAUD &&
3057 !(tty->termios->c_cflag & CBAUD)) {
3058 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3059 spin_lock_irqsave(&info->irq_spinlock,flags);
3060 usc_set_serial_signals(info);
3061 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3062 }
3063
3064 /* Handle transition away from B0 status */
3065 if (!(old_termios->c_cflag & CBAUD) &&
3066 tty->termios->c_cflag & CBAUD) {
3067 info->serial_signals |= SerialSignal_DTR;
3068 if (!(tty->termios->c_cflag & CRTSCTS) ||
3069 !test_bit(TTY_THROTTLED, &tty->flags)) {
3070 info->serial_signals |= SerialSignal_RTS;
3071 }
3072 spin_lock_irqsave(&info->irq_spinlock,flags);
3073 usc_set_serial_signals(info);
3074 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3075 }
3076
3077 /* Handle turning off CRTSCTS */
3078 if (old_termios->c_cflag & CRTSCTS &&
3079 !(tty->termios->c_cflag & CRTSCTS)) {
3080 tty->hw_stopped = 0;
3081 mgsl_start(tty);
3082 }
3083
3084 } /* end of mgsl_set_termios() */
3085
3086 /* mgsl_close()
3087 *
3088 * Called when port is closed. Wait for remaining data to be
3089 * sent. Disable port and free resources.
3090 *
3091 * Arguments:
3092 *
3093 * tty pointer to open tty structure
3094 * filp pointer to open file object
3095 *
3096 * Return Value: None
3097 */
3098 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3099 {
3100 struct mgsl_struct * info = tty->driver_data;
3101
3102 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3103 return;
3104
3105 if (debug_level >= DEBUG_LEVEL_INFO)
3106 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3107 __FILE__,__LINE__, info->device_name, info->port.count);
3108
3109 if (tty_port_close_start(&info->port, tty, filp) == 0)
3110 goto cleanup;
3111
3112 if (info->port.flags & ASYNC_INITIALIZED)
3113 mgsl_wait_until_sent(tty, info->timeout);
3114 mgsl_flush_buffer(tty);
3115 tty_ldisc_flush(tty);
3116 shutdown(info);
3117
3118 tty_port_close_end(&info->port, tty);
3119 info->port.tty = NULL;
3120 cleanup:
3121 if (debug_level >= DEBUG_LEVEL_INFO)
3122 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3123 tty->driver->name, info->port.count);
3124
3125 } /* end of mgsl_close() */
3126
3127 /* mgsl_wait_until_sent()
3128 *
3129 * Wait until the transmitter is empty.
3130 *
3131 * Arguments:
3132 *
3133 * tty pointer to tty info structure
3134 * timeout time to wait for send completion
3135 *
3136 * Return Value: None
3137 */
3138 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3139 {
3140 struct mgsl_struct * info = tty->driver_data;
3141 unsigned long orig_jiffies, char_time;
3142
3143 if (!info )
3144 return;
3145
3146 if (debug_level >= DEBUG_LEVEL_INFO)
3147 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3148 __FILE__,__LINE__, info->device_name );
3149
3150 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3151 return;
3152
3153 if (!(info->port.flags & ASYNC_INITIALIZED))
3154 goto exit;
3155
3156 orig_jiffies = jiffies;
3157
3158 /* Set check interval to 1/5 of estimated time to
3159 * send a character, and make it at least 1. The check
3160 * interval should also be less than the timeout.
3161 * Note: use tight timings here to satisfy the NIST-PCTS.
3162 */
3163
3164 lock_kernel();
3165 if ( info->params.data_rate ) {
3166 char_time = info->timeout/(32 * 5);
3167 if (!char_time)
3168 char_time++;
3169 } else
3170 char_time = 1;
3171
3172 if (timeout)
3173 char_time = min_t(unsigned long, char_time, timeout);
3174
3175 if ( info->params.mode == MGSL_MODE_HDLC ||
3176 info->params.mode == MGSL_MODE_RAW ) {
3177 while (info->tx_active) {
3178 msleep_interruptible(jiffies_to_msecs(char_time));
3179 if (signal_pending(current))
3180 break;
3181 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3182 break;
3183 }
3184 } else {
3185 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3186 info->tx_enabled) {
3187 msleep_interruptible(jiffies_to_msecs(char_time));
3188 if (signal_pending(current))
3189 break;
3190 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3191 break;
3192 }
3193 }
3194 unlock_kernel();
3195
3196 exit:
3197 if (debug_level >= DEBUG_LEVEL_INFO)
3198 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3199 __FILE__,__LINE__, info->device_name );
3200
3201 } /* end of mgsl_wait_until_sent() */
3202
3203 /* mgsl_hangup()
3204 *
3205 * Called by tty_hangup() when a hangup is signaled.
3206 * This is the same as to closing all open files for the port.
3207 *
3208 * Arguments: tty pointer to associated tty object
3209 * Return Value: None
3210 */
3211 static void mgsl_hangup(struct tty_struct *tty)
3212 {
3213 struct mgsl_struct * info = tty->driver_data;
3214
3215 if (debug_level >= DEBUG_LEVEL_INFO)
3216 printk("%s(%d):mgsl_hangup(%s)\n",
3217 __FILE__,__LINE__, info->device_name );
3218
3219 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3220 return;
3221
3222 mgsl_flush_buffer(tty);
3223 shutdown(info);
3224
3225 info->port.count = 0;
3226 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3227 info->port.tty = NULL;
3228
3229 wake_up_interruptible(&info->port.open_wait);
3230
3231 } /* end of mgsl_hangup() */
3232
3233 /*
3234 * carrier_raised()
3235 *
3236 * Return true if carrier is raised
3237 */
3238
3239 static int carrier_raised(struct tty_port *port)
3240 {
3241 unsigned long flags;
3242 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3243
3244 spin_lock_irqsave(&info->irq_spinlock, flags);
3245 usc_get_serial_signals(info);
3246 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3247 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3248 }
3249
3250 static void dtr_rts(struct tty_port *port, int on)
3251 {
3252 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3253 unsigned long flags;
3254
3255 spin_lock_irqsave(&info->irq_spinlock,flags);
3256 if (on)
3257 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3258 else
3259 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3260 usc_set_serial_signals(info);
3261 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3262 }
3263
3264
3265 /* block_til_ready()
3266 *
3267 * Block the current process until the specified port
3268 * is ready to be opened.
3269 *
3270 * Arguments:
3271 *
3272 * tty pointer to tty info structure
3273 * filp pointer to open file object
3274 * info pointer to device instance data
3275 *
3276 * Return Value: 0 if success, otherwise error code
3277 */
3278 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3279 struct mgsl_struct *info)
3280 {
3281 DECLARE_WAITQUEUE(wait, current);
3282 int retval;
3283 bool do_clocal = false;
3284 bool extra_count = false;
3285 unsigned long flags;
3286 int dcd;
3287 struct tty_port *port = &info->port;
3288
3289 if (debug_level >= DEBUG_LEVEL_INFO)
3290 printk("%s(%d):block_til_ready on %s\n",
3291 __FILE__,__LINE__, tty->driver->name );
3292
3293 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3294 /* nonblock mode is set or port is not enabled */
3295 port->flags |= ASYNC_NORMAL_ACTIVE;
3296 return 0;
3297 }
3298
3299 if (tty->termios->c_cflag & CLOCAL)
3300 do_clocal = true;
3301
3302 /* Wait for carrier detect and the line to become
3303 * free (i.e., not in use by the callout). While we are in
3304 * this loop, port->count is dropped by one, so that
3305 * mgsl_close() knows when to free things. We restore it upon
3306 * exit, either normal or abnormal.
3307 */
3308
3309 retval = 0;
3310 add_wait_queue(&port->open_wait, &wait);
3311
3312 if (debug_level >= DEBUG_LEVEL_INFO)
3313 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3314 __FILE__,__LINE__, tty->driver->name, port->count );
3315
3316 spin_lock_irqsave(&info->irq_spinlock, flags);
3317 if (!tty_hung_up_p(filp)) {
3318 extra_count = true;
3319 port->count--;
3320 }
3321 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3322 port->blocked_open++;
3323
3324 while (1) {
3325 if (tty->termios->c_cflag & CBAUD)
3326 tty_port_raise_dtr_rts(port);
3327
3328 set_current_state(TASK_INTERRUPTIBLE);
3329
3330 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3331 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3332 -EAGAIN : -ERESTARTSYS;
3333 break;
3334 }
3335
3336 dcd = tty_port_carrier_raised(&info->port);
3337
3338 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3339 break;
3340
3341 if (signal_pending(current)) {
3342 retval = -ERESTARTSYS;
3343 break;
3344 }
3345
3346 if (debug_level >= DEBUG_LEVEL_INFO)
3347 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3348 __FILE__,__LINE__, tty->driver->name, port->count );
3349
3350 schedule();
3351 }
3352
3353 set_current_state(TASK_RUNNING);
3354 remove_wait_queue(&port->open_wait, &wait);
3355
3356 /* FIXME: Racy on hangup during close wait */
3357 if (extra_count)
3358 port->count++;
3359 port->blocked_open--;
3360
3361 if (debug_level >= DEBUG_LEVEL_INFO)
3362 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3363 __FILE__,__LINE__, tty->driver->name, port->count );
3364
3365 if (!retval)
3366 port->flags |= ASYNC_NORMAL_ACTIVE;
3367
3368 return retval;
3369
3370 } /* end of block_til_ready() */
3371
3372 /* mgsl_open()
3373 *
3374 * Called when a port is opened. Init and enable port.
3375 * Perform serial-specific initialization for the tty structure.
3376 *
3377 * Arguments: tty pointer to tty info structure
3378 * filp associated file pointer
3379 *
3380 * Return Value: 0 if success, otherwise error code
3381 */
3382 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3383 {
3384 struct mgsl_struct *info;
3385 int retval, line;
3386 unsigned long flags;
3387
3388 /* verify range of specified line number */
3389 line = tty->index;
3390 if ((line < 0) || (line >= mgsl_device_count)) {
3391 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3392 __FILE__,__LINE__,line);
3393 return -ENODEV;
3394 }
3395
3396 /* find the info structure for the specified line */
3397 info = mgsl_device_list;
3398 while(info && info->line != line)
3399 info = info->next_device;
3400 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3401 return -ENODEV;
3402
3403 tty->driver_data = info;
3404 info->port.tty = tty;
3405
3406 if (debug_level >= DEBUG_LEVEL_INFO)
3407 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3408 __FILE__,__LINE__,tty->driver->name, info->port.count);
3409
3410 /* If port is closing, signal caller to try again */
3411 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3412 if (info->port.flags & ASYNC_CLOSING)
3413 interruptible_sleep_on(&info->port.close_wait);
3414 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3415 -EAGAIN : -ERESTARTSYS);
3416 goto cleanup;
3417 }
3418
3419 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3420
3421 spin_lock_irqsave(&info->netlock, flags);
3422 if (info->netcount) {
3423 retval = -EBUSY;
3424 spin_unlock_irqrestore(&info->netlock, flags);
3425 goto cleanup;
3426 }
3427 info->port.count++;
3428 spin_unlock_irqrestore(&info->netlock, flags);
3429
3430 if (info->port.count == 1) {
3431 /* 1st open on this device, init hardware */
3432 retval = startup(info);
3433 if (retval < 0)
3434 goto cleanup;
3435 }
3436
3437 retval = block_til_ready(tty, filp, info);
3438 if (retval) {
3439 if (debug_level >= DEBUG_LEVEL_INFO)
3440 printk("%s(%d):block_til_ready(%s) returned %d\n",
3441 __FILE__,__LINE__, info->device_name, retval);
3442 goto cleanup;
3443 }
3444
3445 if (debug_level >= DEBUG_LEVEL_INFO)
3446 printk("%s(%d):mgsl_open(%s) success\n",
3447 __FILE__,__LINE__, info->device_name);
3448 retval = 0;
3449
3450 cleanup:
3451 if (retval) {
3452 if (tty->count == 1)
3453 info->port.tty = NULL; /* tty layer will release tty struct */
3454 if(info->port.count)
3455 info->port.count--;
3456 }
3457
3458 return retval;
3459
3460 } /* end of mgsl_open() */
3461
3462 /*
3463 * /proc fs routines....
3464 */
3465
3466 static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3467 {
3468 char stat_buf[30];
3469 unsigned long flags;
3470
3471 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3472 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3473 info->device_name, info->io_base, info->irq_level,
3474 info->phys_memory_base, info->phys_lcr_base);
3475 } else {
3476 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3477 info->device_name, info->io_base,
3478 info->irq_level, info->dma_level);
3479 }
3480
3481 /* output current serial signal states */
3482 spin_lock_irqsave(&info->irq_spinlock,flags);
3483 usc_get_serial_signals(info);
3484 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3485
3486 stat_buf[0] = 0;
3487 stat_buf[1] = 0;
3488 if (info->serial_signals & SerialSignal_RTS)
3489 strcat(stat_buf, "|RTS");
3490 if (info->serial_signals & SerialSignal_CTS)
3491 strcat(stat_buf, "|CTS");
3492 if (info->serial_signals & SerialSignal_DTR)
3493 strcat(stat_buf, "|DTR");
3494 if (info->serial_signals & SerialSignal_DSR)
3495 strcat(stat_buf, "|DSR");
3496 if (info->serial_signals & SerialSignal_DCD)
3497 strcat(stat_buf, "|CD");
3498 if (info->serial_signals & SerialSignal_RI)
3499 strcat(stat_buf, "|RI");
3500
3501 if (info->params.mode == MGSL_MODE_HDLC ||
3502 info->params.mode == MGSL_MODE_RAW ) {
3503 seq_printf(m, " HDLC txok:%d rxok:%d",
3504 info->icount.txok, info->icount.rxok);
3505 if (info->icount.txunder)
3506 seq_printf(m, " txunder:%d", info->icount.txunder);
3507 if (info->icount.txabort)
3508 seq_printf(m, " txabort:%d", info->icount.txabort);
3509 if (info->icount.rxshort)
3510 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3511 if (info->icount.rxlong)
3512 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3513 if (info->icount.rxover)
3514 seq_printf(m, " rxover:%d", info->icount.rxover);
3515 if (info->icount.rxcrc)
3516 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3517 } else {
3518 seq_printf(m, " ASYNC tx:%d rx:%d",
3519 info->icount.tx, info->icount.rx);
3520 if (info->icount.frame)
3521 seq_printf(m, " fe:%d", info->icount.frame);
3522 if (info->icount.parity)
3523 seq_printf(m, " pe:%d", info->icount.parity);
3524 if (info->icount.brk)
3525 seq_printf(m, " brk:%d", info->icount.brk);
3526 if (info->icount.overrun)
3527 seq_printf(m, " oe:%d", info->icount.overrun);
3528 }
3529
3530 /* Append serial signal status to end */
3531 seq_printf(m, " %s\n", stat_buf+1);
3532
3533 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3534 info->tx_active,info->bh_requested,info->bh_running,
3535 info->pending_bh);
3536
3537 spin_lock_irqsave(&info->irq_spinlock,flags);
3538 {
3539 u16 Tcsr = usc_InReg( info, TCSR );
3540 u16 Tdmr = usc_InDmaReg( info, TDMR );
3541 u16 Ticr = usc_InReg( info, TICR );
3542 u16 Rscr = usc_InReg( info, RCSR );
3543 u16 Rdmr = usc_InDmaReg( info, RDMR );
3544 u16 Ricr = usc_InReg( info, RICR );
3545 u16 Icr = usc_InReg( info, ICR );
3546 u16 Dccr = usc_InReg( info, DCCR );
3547 u16 Tmr = usc_InReg( info, TMR );
3548 u16 Tccr = usc_InReg( info, TCCR );
3549 u16 Ccar = inw( info->io_base + CCAR );
3550 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3551 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3552 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3553 }
3554 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3555 }
3556
3557 /* Called to print information about devices */
3558 static int mgsl_proc_show(struct seq_file *m, void *v)
3559 {
3560 struct mgsl_struct *info;
3561
3562 seq_printf(m, "synclink driver:%s\n", driver_version);
3563
3564 info = mgsl_device_list;
3565 while( info ) {
3566 line_info(m, info);
3567 info = info->next_device;
3568 }
3569 return 0;
3570 }
3571
3572 static int mgsl_proc_open(struct inode *inode, struct file *file)
3573 {
3574 return single_open(file, mgsl_proc_show, NULL);
3575 }
3576
3577 static const struct file_operations mgsl_proc_fops = {
3578 .owner = THIS_MODULE,
3579 .open = mgsl_proc_open,
3580 .read = seq_read,
3581 .llseek = seq_lseek,
3582 .release = single_release,
3583 };
3584
3585 /* mgsl_allocate_dma_buffers()
3586 *
3587 * Allocate and format DMA buffers (ISA adapter)
3588 * or format shared memory buffers (PCI adapter).
3589 *
3590 * Arguments: info pointer to device instance data
3591 * Return Value: 0 if success, otherwise error
3592 */
3593 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3594 {
3595 unsigned short BuffersPerFrame;
3596
3597 info->last_mem_alloc = 0;
3598
3599 /* Calculate the number of DMA buffers necessary to hold the */
3600 /* largest allowable frame size. Note: If the max frame size is */
3601 /* not an even multiple of the DMA buffer size then we need to */
3602 /* round the buffer count per frame up one. */
3603
3604 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3605 if ( info->max_frame_size % DMABUFFERSIZE )
3606 BuffersPerFrame++;
3607
3608 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3609 /*
3610 * The PCI adapter has 256KBytes of shared memory to use.
3611 * This is 64 PAGE_SIZE buffers.
3612 *
3613 * The first page is used for padding at this time so the
3614 * buffer list does not begin at offset 0 of the PCI
3615 * adapter's shared memory.
3616 *
3617 * The 2nd page is used for the buffer list. A 4K buffer
3618 * list can hold 128 DMA_BUFFER structures at 32 bytes
3619 * each.
3620 *
3621 * This leaves 62 4K pages.
3622 *
3623 * The next N pages are used for transmit frame(s). We
3624 * reserve enough 4K page blocks to hold the required
3625 * number of transmit dma buffers (num_tx_dma_buffers),
3626 * each of MaxFrameSize size.
3627 *
3628 * Of the remaining pages (62-N), determine how many can
3629 * be used to receive full MaxFrameSize inbound frames
3630 */
3631 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3632 info->rx_buffer_count = 62 - info->tx_buffer_count;
3633 } else {
3634 /* Calculate the number of PAGE_SIZE buffers needed for */
3635 /* receive and transmit DMA buffers. */
3636
3637
3638 /* Calculate the number of DMA buffers necessary to */
3639 /* hold 7 max size receive frames and one max size transmit frame. */
3640 /* The receive buffer count is bumped by one so we avoid an */
3641 /* End of List condition if all receive buffers are used when */
3642 /* using linked list DMA buffers. */
3643
3644 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3645 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3646
3647 /*
3648 * limit total TxBuffers & RxBuffers to 62 4K total
3649 * (ala PCI Allocation)
3650 */
3651
3652 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3653 info->rx_buffer_count = 62 - info->tx_buffer_count;
3654
3655 }
3656
3657 if ( debug_level >= DEBUG_LEVEL_INFO )
3658 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3659 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3660
3661 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3662 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3663 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3664 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3665 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3666 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3667 return -ENOMEM;
3668 }
3669
3670 mgsl_reset_rx_dma_buffers( info );
3671 mgsl_reset_tx_dma_buffers( info );
3672
3673 return 0;
3674
3675 } /* end of mgsl_allocate_dma_buffers() */
3676
3677 /*
3678 * mgsl_alloc_buffer_list_memory()
3679 *
3680 * Allocate a common DMA buffer for use as the
3681 * receive and transmit buffer lists.
3682 *
3683 * A buffer list is a set of buffer entries where each entry contains
3684 * a pointer to an actual buffer and a pointer to the next buffer entry
3685 * (plus some other info about the buffer).
3686 *
3687 * The buffer entries for a list are built to form a circular list so
3688 * that when the entire list has been traversed you start back at the
3689 * beginning.
3690 *
3691 * This function allocates memory for just the buffer entries.
3692 * The links (pointer to next entry) are filled in with the physical
3693 * address of the next entry so the adapter can navigate the list
3694 * using bus master DMA. The pointers to the actual buffers are filled
3695 * out later when the actual buffers are allocated.
3696 *
3697 * Arguments: info pointer to device instance data
3698 * Return Value: 0 if success, otherwise error
3699 */
3700 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3701 {
3702 unsigned int i;
3703
3704 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3705 /* PCI adapter uses shared memory. */
3706 info->buffer_list = info->memory_base + info->last_mem_alloc;
3707 info->buffer_list_phys = info->last_mem_alloc;
3708 info->last_mem_alloc += BUFFERLISTSIZE;
3709 } else {
3710 /* ISA adapter uses system memory. */
3711 /* The buffer lists are allocated as a common buffer that both */
3712 /* the processor and adapter can access. This allows the driver to */
3713 /* inspect portions of the buffer while other portions are being */
3714 /* updated by the adapter using Bus Master DMA. */
3715
3716 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3717 if (info->buffer_list == NULL)
3718 return -ENOMEM;
3719 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3720 }
3721
3722 /* We got the memory for the buffer entry lists. */
3723 /* Initialize the memory block to all zeros. */
3724 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3725
3726 /* Save virtual address pointers to the receive and */
3727 /* transmit buffer lists. (Receive 1st). These pointers will */
3728 /* be used by the processor to access the lists. */
3729 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3730 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3731 info->tx_buffer_list += info->rx_buffer_count;
3732
3733 /*
3734 * Build the links for the buffer entry lists such that
3735 * two circular lists are built. (Transmit and Receive).
3736 *
3737 * Note: the links are physical addresses
3738 * which are read by the adapter to determine the next
3739 * buffer entry to use.
3740 */
3741
3742 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3743 /* calculate and store physical address of this buffer entry */
3744 info->rx_buffer_list[i].phys_entry =
3745 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3746
3747 /* calculate and store physical address of */
3748 /* next entry in cirular list of entries */
3749
3750 info->rx_buffer_list[i].link = info->buffer_list_phys;
3751
3752 if ( i < info->rx_buffer_count - 1 )
3753 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3754 }
3755
3756 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3757 /* calculate and store physical address of this buffer entry */
3758 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3759 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3760
3761 /* calculate and store physical address of */
3762 /* next entry in cirular list of entries */
3763
3764 info->tx_buffer_list[i].link = info->buffer_list_phys +
3765 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3766
3767 if ( i < info->tx_buffer_count - 1 )
3768 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3769 }
3770
3771 return 0;
3772
3773 } /* end of mgsl_alloc_buffer_list_memory() */
3774
3775 /* Free DMA buffers allocated for use as the
3776 * receive and transmit buffer lists.
3777 * Warning:
3778 *
3779 * The data transfer buffers associated with the buffer list
3780 * MUST be freed before freeing the buffer list itself because
3781 * the buffer list contains the information necessary to free
3782 * the individual buffers!
3783 */
3784 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3785 {
3786 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3787 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3788
3789 info->buffer_list = NULL;
3790 info->rx_buffer_list = NULL;
3791 info->tx_buffer_list = NULL;
3792
3793 } /* end of mgsl_free_buffer_list_memory() */
3794
3795 /*
3796 * mgsl_alloc_frame_memory()
3797 *
3798 * Allocate the frame DMA buffers used by the specified buffer list.
3799 * Each DMA buffer will be one memory page in size. This is necessary
3800 * because memory can fragment enough that it may be impossible
3801 * contiguous pages.
3802 *
3803 * Arguments:
3804 *
3805 * info pointer to device instance data
3806 * BufferList pointer to list of buffer entries
3807 * Buffercount count of buffer entries in buffer list
3808 *
3809 * Return Value: 0 if success, otherwise -ENOMEM
3810 */
3811 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3812 {
3813 int i;
3814 u32 phys_addr;
3815
3816 /* Allocate page sized buffers for the receive buffer list */
3817
3818 for ( i = 0; i < Buffercount; i++ ) {
3819 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3820 /* PCI adapter uses shared memory buffers. */
3821 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3822 phys_addr = info->last_mem_alloc;
3823 info->last_mem_alloc += DMABUFFERSIZE;
3824 } else {
3825 /* ISA adapter uses system memory. */
3826 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3827 if (BufferList[i].virt_addr == NULL)
3828 return -ENOMEM;
3829 phys_addr = (u32)(BufferList[i].dma_addr);
3830 }
3831 BufferList[i].phys_addr = phys_addr;
3832 }
3833
3834 return 0;
3835
3836 } /* end of mgsl_alloc_frame_memory() */
3837
3838 /*
3839 * mgsl_free_frame_memory()
3840 *
3841 * Free the buffers associated with
3842 * each buffer entry of a buffer list.
3843 *
3844 * Arguments:
3845 *
3846 * info pointer to device instance data
3847 * BufferList pointer to list of buffer entries
3848 * Buffercount count of buffer entries in buffer list
3849 *
3850 * Return Value: None
3851 */
3852 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3853 {
3854 int i;
3855
3856 if ( BufferList ) {
3857 for ( i = 0 ; i < Buffercount ; i++ ) {
3858 if ( BufferList[i].virt_addr ) {
3859 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3860 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3861 BufferList[i].virt_addr = NULL;
3862 }
3863 }
3864 }
3865
3866 } /* end of mgsl_free_frame_memory() */
3867
3868 /* mgsl_free_dma_buffers()
3869 *
3870 * Free DMA buffers
3871 *
3872 * Arguments: info pointer to device instance data
3873 * Return Value: None
3874 */
3875 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3876 {
3877 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3878 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3879 mgsl_free_buffer_list_memory( info );
3880
3881 } /* end of mgsl_free_dma_buffers() */
3882
3883
3884 /*
3885 * mgsl_alloc_intermediate_rxbuffer_memory()
3886 *
3887 * Allocate a buffer large enough to hold max_frame_size. This buffer
3888 * is used to pass an assembled frame to the line discipline.
3889 *
3890 * Arguments:
3891 *
3892 * info pointer to device instance data
3893 *
3894 * Return Value: 0 if success, otherwise -ENOMEM
3895 */
3896 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3897 {
3898 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3899 if ( info->intermediate_rxbuffer == NULL )
3900 return -ENOMEM;
3901
3902 return 0;
3903
3904 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3905
3906 /*
3907 * mgsl_free_intermediate_rxbuffer_memory()
3908 *
3909 *
3910 * Arguments:
3911 *
3912 * info pointer to device instance data
3913 *
3914 * Return Value: None
3915 */
3916 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3917 {
3918 kfree(info->intermediate_rxbuffer);
3919 info->intermediate_rxbuffer = NULL;
3920
3921 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3922
3923 /*
3924 * mgsl_alloc_intermediate_txbuffer_memory()
3925 *
3926 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3927 * This buffer is used to load transmit frames into the adapter's dma transfer
3928 * buffers when there is sufficient space.
3929 *
3930 * Arguments:
3931 *
3932 * info pointer to device instance data
3933 *
3934 * Return Value: 0 if success, otherwise -ENOMEM
3935 */
3936 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3937 {
3938 int i;
3939
3940 if ( debug_level >= DEBUG_LEVEL_INFO )
3941 printk("%s %s(%d) allocating %d tx holding buffers\n",
3942 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3943
3944 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3945
3946 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3947 info->tx_holding_buffers[i].buffer =
3948 kmalloc(info->max_frame_size, GFP_KERNEL);
3949 if (info->tx_holding_buffers[i].buffer == NULL) {
3950 for (--i; i >= 0; i--) {
3951 kfree(info->tx_holding_buffers[i].buffer);
3952 info->tx_holding_buffers[i].buffer = NULL;
3953 }
3954 return -ENOMEM;
3955 }
3956 }
3957
3958 return 0;
3959
3960 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3961
3962 /*
3963 * mgsl_free_intermediate_txbuffer_memory()
3964 *
3965 *
3966 * Arguments:
3967 *
3968 * info pointer to device instance data
3969 *
3970 * Return Value: None
3971 */
3972 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3973 {
3974 int i;
3975
3976 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3977 kfree(info->tx_holding_buffers[i].buffer);
3978 info->tx_holding_buffers[i].buffer = NULL;
3979 }
3980
3981 info->get_tx_holding_index = 0;
3982 info->put_tx_holding_index = 0;
3983 info->tx_holding_count = 0;
3984
3985 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3986
3987
3988 /*
3989 * load_next_tx_holding_buffer()
3990 *
3991 * attempts to load the next buffered tx request into the
3992 * tx dma buffers
3993 *
3994 * Arguments:
3995 *
3996 * info pointer to device instance data
3997 *
3998 * Return Value: true if next buffered tx request loaded
3999 * into adapter's tx dma buffer,
4000 * false otherwise
4001 */
4002 static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4003 {
4004 bool ret = false;
4005
4006 if ( info->tx_holding_count ) {
4007 /* determine if we have enough tx dma buffers
4008 * to accommodate the next tx frame
4009 */
4010 struct tx_holding_buffer *ptx =
4011 &info->tx_holding_buffers[info->get_tx_holding_index];
4012 int num_free = num_free_tx_dma_buffers(info);
4013 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4014 if ( ptx->buffer_size % DMABUFFERSIZE )
4015 ++num_needed;
4016
4017 if (num_needed <= num_free) {
4018 info->xmit_cnt = ptx->buffer_size;
4019 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4020
4021 --info->tx_holding_count;
4022 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4023 info->get_tx_holding_index=0;
4024
4025 /* restart transmit timer */
4026 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4027
4028 ret = true;
4029 }
4030 }
4031
4032 return ret;
4033 }
4034
4035 /*
4036 * save_tx_buffer_request()
4037 *
4038 * attempt to store transmit frame request for later transmission
4039 *
4040 * Arguments:
4041 *
4042 * info pointer to device instance data
4043 * Buffer pointer to buffer containing frame to load
4044 * BufferSize size in bytes of frame in Buffer
4045 *
4046 * Return Value: 1 if able to store, 0 otherwise
4047 */
4048 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4049 {
4050 struct tx_holding_buffer *ptx;
4051
4052 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4053 return 0; /* all buffers in use */
4054 }
4055
4056 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4057 ptx->buffer_size = BufferSize;
4058 memcpy( ptx->buffer, Buffer, BufferSize);
4059
4060 ++info->tx_holding_count;
4061 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4062 info->put_tx_holding_index=0;
4063
4064 return 1;
4065 }
4066
4067 static int mgsl_claim_resources(struct mgsl_struct *info)
4068 {
4069 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4070 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4071 __FILE__,__LINE__,info->device_name, info->io_base);
4072 return -ENODEV;
4073 }
4074 info->io_addr_requested = true;
4075
4076 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4077 info->device_name, info ) < 0 ) {
4078 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4079 __FILE__,__LINE__,info->device_name, info->irq_level );
4080 goto errout;
4081 }
4082 info->irq_requested = true;
4083
4084 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4085 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4086 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4087 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4088 goto errout;
4089 }
4090 info->shared_mem_requested = true;
4091 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4092 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4093 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4094 goto errout;
4095 }
4096 info->lcr_mem_requested = true;
4097
4098 info->memory_base = ioremap_nocache(info->phys_memory_base,
4099 0x40000);
4100 if (!info->memory_base) {
4101 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4102 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4103 goto errout;
4104 }
4105
4106 if ( !mgsl_memory_test(info) ) {
4107 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4108 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4109 goto errout;
4110 }
4111
4112 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4113 PAGE_SIZE);
4114 if (!info->lcr_base) {
4115 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4116 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4117 goto errout;
4118 }
4119 info->lcr_base += info->lcr_offset;
4120
4121 } else {
4122 /* claim DMA channel */
4123
4124 if (request_dma(info->dma_level,info->device_name) < 0){
4125 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4126 __FILE__,__LINE__,info->device_name, info->dma_level );
4127 mgsl_release_resources( info );
4128 return -ENODEV;
4129 }
4130 info->dma_requested = true;
4131
4132 /* ISA adapter uses bus master DMA */
4133 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4134 enable_dma(info->dma_level);
4135 }
4136
4137 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4138 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4139 __FILE__,__LINE__,info->device_name, info->dma_level );
4140 goto errout;
4141 }
4142
4143 return 0;
4144 errout:
4145 mgsl_release_resources(info);
4146 return -ENODEV;
4147
4148 } /* end of mgsl_claim_resources() */
4149
4150 static void mgsl_release_resources(struct mgsl_struct *info)
4151 {
4152 if ( debug_level >= DEBUG_LEVEL_INFO )
4153 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4154 __FILE__,__LINE__,info->device_name );
4155
4156 if ( info->irq_requested ) {
4157 free_irq(info->irq_level, info);
4158 info->irq_requested = false;
4159 }
4160 if ( info->dma_requested ) {
4161 disable_dma(info->dma_level);
4162 free_dma(info->dma_level);
4163 info->dma_requested = false;
4164 }
4165 mgsl_free_dma_buffers(info);
4166 mgsl_free_intermediate_rxbuffer_memory(info);
4167 mgsl_free_intermediate_txbuffer_memory(info);
4168
4169 if ( info->io_addr_requested ) {
4170 release_region(info->io_base,info->io_addr_size);
4171 info->io_addr_requested = false;
4172 }
4173 if ( info->shared_mem_requested ) {
4174 release_mem_region(info->phys_memory_base,0x40000);
4175 info->shared_mem_requested = false;
4176 }
4177 if ( info->lcr_mem_requested ) {
4178 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4179 info->lcr_mem_requested = false;
4180 }
4181 if (info->memory_base){
4182 iounmap(info->memory_base);
4183 info->memory_base = NULL;
4184 }
4185 if (info->lcr_base){
4186 iounmap(info->lcr_base - info->lcr_offset);
4187 info->lcr_base = NULL;
4188 }
4189
4190 if ( debug_level >= DEBUG_LEVEL_INFO )
4191 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4192 __FILE__,__LINE__,info->device_name );
4193
4194 } /* end of mgsl_release_resources() */
4195
4196 /* mgsl_add_device()
4197 *
4198 * Add the specified device instance data structure to the
4199 * global linked list of devices and increment the device count.
4200 *
4201 * Arguments: info pointer to device instance data
4202 * Return Value: None
4203 */
4204 static void mgsl_add_device( struct mgsl_struct *info )
4205 {
4206 info->next_device = NULL;
4207 info->line = mgsl_device_count;
4208 sprintf(info->device_name,"ttySL%d",info->line);
4209
4210 if (info->line < MAX_TOTAL_DEVICES) {
4211 if (maxframe[info->line])
4212 info->max_frame_size = maxframe[info->line];
4213
4214 if (txdmabufs[info->line]) {
4215 info->num_tx_dma_buffers = txdmabufs[info->line];
4216 if (info->num_tx_dma_buffers < 1)
4217 info->num_tx_dma_buffers = 1;
4218 }
4219
4220 if (txholdbufs[info->line]) {
4221 info->num_tx_holding_buffers = txholdbufs[info->line];
4222 if (info->num_tx_holding_buffers < 1)
4223 info->num_tx_holding_buffers = 1;
4224 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4225 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4226 }
4227 }
4228
4229 mgsl_device_count++;
4230
4231 if ( !mgsl_device_list )
4232 mgsl_device_list = info;
4233 else {
4234 struct mgsl_struct *current_dev = mgsl_device_list;
4235 while( current_dev->next_device )
4236 current_dev = current_dev->next_device;
4237 current_dev->next_device = info;
4238 }
4239
4240 if ( info->max_frame_size < 4096 )
4241 info->max_frame_size = 4096;
4242 else if ( info->max_frame_size > 65535 )
4243 info->max_frame_size = 65535;
4244
4245 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4246 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4247 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4248 info->phys_memory_base, info->phys_lcr_base,
4249 info->max_frame_size );
4250 } else {
4251 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4252 info->device_name, info->io_base, info->irq_level, info->dma_level,
4253 info->max_frame_size );
4254 }
4255
4256 #if SYNCLINK_GENERIC_HDLC
4257 hdlcdev_init(info);
4258 #endif
4259
4260 } /* end of mgsl_add_device() */
4261
4262 static const struct tty_port_operations mgsl_port_ops = {
4263 .carrier_raised = carrier_raised,
4264 .dtr_rts = dtr_rts,
4265 };
4266
4267
4268 /* mgsl_allocate_device()
4269 *
4270 * Allocate and initialize a device instance structure
4271 *
4272 * Arguments: none
4273 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4274 */
4275 static struct mgsl_struct* mgsl_allocate_device(void)
4276 {
4277 struct mgsl_struct *info;
4278
4279 info = kzalloc(sizeof(struct mgsl_struct),
4280 GFP_KERNEL);
4281
4282 if (!info) {
4283 printk("Error can't allocate device instance data\n");
4284 } else {
4285 tty_port_init(&info->port);
4286 info->port.ops = &mgsl_port_ops;
4287 info->magic = MGSL_MAGIC;
4288 INIT_WORK(&info->task, mgsl_bh_handler);
4289 info->max_frame_size = 4096;
4290 info->port.close_delay = 5*HZ/10;
4291 info->port.closing_wait = 30*HZ;
4292 init_waitqueue_head(&info->status_event_wait_q);
4293 init_waitqueue_head(&info->event_wait_q);
4294 spin_lock_init(&info->irq_spinlock);
4295 spin_lock_init(&info->netlock);
4296 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4297 info->idle_mode = HDLC_TXIDLE_FLAGS;
4298 info->num_tx_dma_buffers = 1;
4299 info->num_tx_holding_buffers = 0;
4300 }
4301
4302 return info;
4303
4304 } /* end of mgsl_allocate_device()*/
4305
4306 static const struct tty_operations mgsl_ops = {
4307 .open = mgsl_open,
4308 .close = mgsl_close,
4309 .write = mgsl_write,
4310 .put_char = mgsl_put_char,
4311 .flush_chars = mgsl_flush_chars,
4312 .write_room = mgsl_write_room,
4313 .chars_in_buffer = mgsl_chars_in_buffer,
4314 .flush_buffer = mgsl_flush_buffer,
4315 .ioctl = mgsl_ioctl,
4316 .throttle = mgsl_throttle,
4317 .unthrottle = mgsl_unthrottle,
4318 .send_xchar = mgsl_send_xchar,
4319 .break_ctl = mgsl_break,
4320 .wait_until_sent = mgsl_wait_until_sent,
4321 .set_termios = mgsl_set_termios,
4322 .stop = mgsl_stop,
4323 .start = mgsl_start,
4324 .hangup = mgsl_hangup,
4325 .tiocmget = tiocmget,
4326 .tiocmset = tiocmset,
4327 .proc_fops = &mgsl_proc_fops,
4328 };
4329
4330 /*
4331 * perform tty device initialization
4332 */
4333 static int mgsl_init_tty(void)
4334 {
4335 int rc;
4336
4337 serial_driver = alloc_tty_driver(128);
4338 if (!serial_driver)
4339 return -ENOMEM;
4340
4341 serial_driver->owner = THIS_MODULE;
4342 serial_driver->driver_name = "synclink";
4343 serial_driver->name = "ttySL";
4344 serial_driver->major = ttymajor;
4345 serial_driver->minor_start = 64;
4346 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4347 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4348 serial_driver->init_termios = tty_std_termios;
4349 serial_driver->init_termios.c_cflag =
4350 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4351 serial_driver->init_termios.c_ispeed = 9600;
4352 serial_driver->init_termios.c_ospeed = 9600;
4353 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4354 tty_set_operations(serial_driver, &mgsl_ops);
4355 if ((rc = tty_register_driver(serial_driver)) < 0) {
4356 printk("%s(%d):Couldn't register serial driver\n",
4357 __FILE__,__LINE__);
4358 put_tty_driver(serial_driver);
4359 serial_driver = NULL;
4360 return rc;
4361 }
4362
4363 printk("%s %s, tty major#%d\n",
4364 driver_name, driver_version,
4365 serial_driver->major);
4366 return 0;
4367 }
4368
4369 /* enumerate user specified ISA adapters
4370 */
4371 static void mgsl_enum_isa_devices(void)
4372 {
4373 struct mgsl_struct *info;
4374 int i;
4375
4376 /* Check for user specified ISA devices */
4377
4378 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4379 if ( debug_level >= DEBUG_LEVEL_INFO )
4380 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4381 io[i], irq[i], dma[i] );
4382
4383 info = mgsl_allocate_device();
4384 if ( !info ) {
4385 /* error allocating device instance data */
4386 if ( debug_level >= DEBUG_LEVEL_ERROR )
4387 printk( "can't allocate device instance data.\n");
4388 continue;
4389 }
4390
4391 /* Copy user configuration info to device instance data */
4392 info->io_base = (unsigned int)io[i];
4393 info->irq_level = (unsigned int)irq[i];
4394 info->irq_level = irq_canonicalize(info->irq_level);
4395 info->dma_level = (unsigned int)dma[i];
4396 info->bus_type = MGSL_BUS_TYPE_ISA;
4397 info->io_addr_size = 16;
4398 info->irq_flags = 0;
4399
4400 mgsl_add_device( info );
4401 }
4402 }
4403
4404 static void synclink_cleanup(void)
4405 {
4406 int rc;
4407 struct mgsl_struct *info;
4408 struct mgsl_struct *tmp;
4409
4410 printk("Unloading %s: %s\n", driver_name, driver_version);
4411
4412 if (serial_driver) {
4413 if ((rc = tty_unregister_driver(serial_driver)))
4414 printk("%s(%d) failed to unregister tty driver err=%d\n",
4415 __FILE__,__LINE__,rc);
4416 put_tty_driver(serial_driver);
4417 }
4418
4419 info = mgsl_device_list;
4420 while(info) {
4421 #if SYNCLINK_GENERIC_HDLC
4422 hdlcdev_exit(info);
4423 #endif
4424 mgsl_release_resources(info);
4425 tmp = info;
4426 info = info->next_device;
4427 kfree(tmp);
4428 }
4429
4430 if (pci_registered)
4431 pci_unregister_driver(&synclink_pci_driver);
4432 }
4433
4434 static int __init synclink_init(void)
4435 {
4436 int rc;
4437
4438 if (break_on_load) {
4439 mgsl_get_text_ptr();
4440 BREAKPOINT();
4441 }
4442
4443 printk("%s %s\n", driver_name, driver_version);
4444
4445 mgsl_enum_isa_devices();
4446 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4447 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4448 else
4449 pci_registered = true;
4450
4451 if ((rc = mgsl_init_tty()) < 0)
4452 goto error;
4453
4454 return 0;
4455
4456 error:
4457 synclink_cleanup();
4458 return rc;
4459 }
4460
4461 static void __exit synclink_exit(void)
4462 {
4463 synclink_cleanup();
4464 }
4465
4466 module_init(synclink_init);
4467 module_exit(synclink_exit);
4468
4469 /*
4470 * usc_RTCmd()
4471 *
4472 * Issue a USC Receive/Transmit command to the
4473 * Channel Command/Address Register (CCAR).
4474 *
4475 * Notes:
4476 *
4477 * The command is encoded in the most significant 5 bits <15..11>
4478 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4479 * and Bits <6..0> must be written as zeros.
4480 *
4481 * Arguments:
4482 *
4483 * info pointer to device information structure
4484 * Cmd command mask (use symbolic macros)
4485 *
4486 * Return Value:
4487 *
4488 * None
4489 */
4490 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4491 {
4492 /* output command to CCAR in bits <15..11> */
4493 /* preserve bits <10..7>, bits <6..0> must be zero */
4494
4495 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4496
4497 /* Read to flush write to CCAR */
4498 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4499 inw( info->io_base + CCAR );
4500
4501 } /* end of usc_RTCmd() */
4502
4503 /*
4504 * usc_DmaCmd()
4505 *
4506 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4507 *
4508 * Arguments:
4509 *
4510 * info pointer to device information structure
4511 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4512 *
4513 * Return Value:
4514 *
4515 * None
4516 */
4517 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4518 {
4519 /* write command mask to DCAR */
4520 outw( Cmd + info->mbre_bit, info->io_base );
4521
4522 /* Read to flush write to DCAR */
4523 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4524 inw( info->io_base );
4525
4526 } /* end of usc_DmaCmd() */
4527
4528 /*
4529 * usc_OutDmaReg()
4530 *
4531 * Write a 16-bit value to a USC DMA register
4532 *
4533 * Arguments:
4534 *
4535 * info pointer to device info structure
4536 * RegAddr register address (number) for write
4537 * RegValue 16-bit value to write to register
4538 *
4539 * Return Value:
4540 *
4541 * None
4542 *
4543 */
4544 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4545 {
4546 /* Note: The DCAR is located at the adapter base address */
4547 /* Note: must preserve state of BIT8 in DCAR */
4548
4549 outw( RegAddr + info->mbre_bit, info->io_base );
4550 outw( RegValue, info->io_base );
4551
4552 /* Read to flush write to DCAR */
4553 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4554 inw( info->io_base );
4555
4556 } /* end of usc_OutDmaReg() */
4557
4558 /*
4559 * usc_InDmaReg()
4560 *
4561 * Read a 16-bit value from a DMA register
4562 *
4563 * Arguments:
4564 *
4565 * info pointer to device info structure
4566 * RegAddr register address (number) to read from
4567 *
4568 * Return Value:
4569 *
4570 * The 16-bit value read from register
4571 *
4572 */
4573 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4574 {
4575 /* Note: The DCAR is located at the adapter base address */
4576 /* Note: must preserve state of BIT8 in DCAR */
4577
4578 outw( RegAddr + info->mbre_bit, info->io_base );
4579 return inw( info->io_base );
4580
4581 } /* end of usc_InDmaReg() */
4582
4583 /*
4584 *
4585 * usc_OutReg()
4586 *
4587 * Write a 16-bit value to a USC serial channel register
4588 *
4589 * Arguments:
4590 *
4591 * info pointer to device info structure
4592 * RegAddr register address (number) to write to
4593 * RegValue 16-bit value to write to register
4594 *
4595 * Return Value:
4596 *
4597 * None
4598 *
4599 */
4600 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4601 {
4602 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4603 outw( RegValue, info->io_base + CCAR );
4604
4605 /* Read to flush write to CCAR */
4606 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4607 inw( info->io_base + CCAR );
4608
4609 } /* end of usc_OutReg() */
4610
4611 /*
4612 * usc_InReg()
4613 *
4614 * Reads a 16-bit value from a USC serial channel register
4615 *
4616 * Arguments:
4617 *
4618 * info pointer to device extension
4619 * RegAddr register address (number) to read from
4620 *
4621 * Return Value:
4622 *
4623 * 16-bit value read from register
4624 */
4625 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4626 {
4627 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4628 return inw( info->io_base + CCAR );
4629
4630 } /* end of usc_InReg() */
4631
4632 /* usc_set_sdlc_mode()
4633 *
4634 * Set up the adapter for SDLC DMA communications.
4635 *
4636 * Arguments: info pointer to device instance data
4637 * Return Value: NONE
4638 */
4639 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4640 {
4641 u16 RegValue;
4642 bool PreSL1660;
4643
4644 /*
4645 * determine if the IUSC on the adapter is pre-SL1660. If
4646 * not, take advantage of the UnderWait feature of more
4647 * modern chips. If an underrun occurs and this bit is set,
4648 * the transmitter will idle the programmed idle pattern
4649 * until the driver has time to service the underrun. Otherwise,
4650 * the dma controller may get the cycles previously requested
4651 * and begin transmitting queued tx data.
4652 */
4653 usc_OutReg(info,TMCR,0x1f);
4654 RegValue=usc_InReg(info,TMDR);
4655 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4656
4657 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4658 {
4659 /*
4660 ** Channel Mode Register (CMR)
4661 **
4662 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4663 ** <13> 0 0 = Transmit Disabled (initially)
4664 ** <12> 0 1 = Consecutive Idles share common 0
4665 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4666 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4667 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4668 **
4669 ** 1000 1110 0000 0110 = 0x8e06
4670 */
4671 RegValue = 0x8e06;
4672
4673 /*--------------------------------------------------
4674 * ignore user options for UnderRun Actions and
4675 * preambles
4676 *--------------------------------------------------*/
4677 }
4678 else
4679 {
4680 /* Channel mode Register (CMR)
4681 *
4682 * <15..14> 00 Tx Sub modes, Underrun Action
4683 * <13> 0 1 = Send Preamble before opening flag
4684 * <12> 0 1 = Consecutive Idles share common 0
4685 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4686 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4687 * <3..0> 0110 Receiver mode = HDLC/SDLC
4688 *
4689 * 0000 0110 0000 0110 = 0x0606
4690 */
4691 if (info->params.mode == MGSL_MODE_RAW) {
4692 RegValue = 0x0001; /* Set Receive mode = external sync */
4693
4694 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4695 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4696
4697 /*
4698 * TxSubMode:
4699 * CMR <15> 0 Don't send CRC on Tx Underrun
4700 * CMR <14> x undefined
4701 * CMR <13> 0 Send preamble before openning sync
4702 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4703 *
4704 * TxMode:
4705 * CMR <11-8) 0100 MonoSync
4706 *
4707 * 0x00 0100 xxxx xxxx 04xx
4708 */
4709 RegValue |= 0x0400;
4710 }
4711 else {
4712
4713 RegValue = 0x0606;
4714
4715 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4716 RegValue |= BIT14;
4717 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4718 RegValue |= BIT15;
4719 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4720 RegValue |= BIT15 + BIT14;
4721 }
4722
4723 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4724 RegValue |= BIT13;
4725 }
4726
4727 if ( info->params.mode == MGSL_MODE_HDLC &&
4728 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4729 RegValue |= BIT12;
4730
4731 if ( info->params.addr_filter != 0xff )
4732 {
4733 /* set up receive address filtering */
4734 usc_OutReg( info, RSR, info->params.addr_filter );
4735 RegValue |= BIT4;
4736 }
4737
4738 usc_OutReg( info, CMR, RegValue );
4739 info->cmr_value = RegValue;
4740
4741 /* Receiver mode Register (RMR)
4742 *
4743 * <15..13> 000 encoding
4744 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4745 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4746 * <9> 0 1 = Include Receive chars in CRC
4747 * <8> 1 1 = Use Abort/PE bit as abort indicator
4748 * <7..6> 00 Even parity
4749 * <5> 0 parity disabled
4750 * <4..2> 000 Receive Char Length = 8 bits
4751 * <1..0> 00 Disable Receiver
4752 *
4753 * 0000 0101 0000 0000 = 0x0500
4754 */
4755
4756 RegValue = 0x0500;
4757
4758 switch ( info->params.encoding ) {
4759 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4760 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4761 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4762 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4763 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4764 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4765 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4766 }
4767
4768 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4769 RegValue |= BIT9;
4770 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4771 RegValue |= ( BIT12 | BIT10 | BIT9 );
4772
4773 usc_OutReg( info, RMR, RegValue );
4774
4775 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4776 /* When an opening flag of an SDLC frame is recognized the */
4777 /* Receive Character count (RCC) is loaded with the value in */
4778 /* RCLR. The RCC is decremented for each received byte. The */
4779 /* value of RCC is stored after the closing flag of the frame */
4780 /* allowing the frame size to be computed. */
4781
4782 usc_OutReg( info, RCLR, RCLRVALUE );
4783
4784 usc_RCmd( info, RCmd_SelectRicrdma_level );
4785
4786 /* Receive Interrupt Control Register (RICR)
4787 *
4788 * <15..8> ? RxFIFO DMA Request Level
4789 * <7> 0 Exited Hunt IA (Interrupt Arm)
4790 * <6> 0 Idle Received IA
4791 * <5> 0 Break/Abort IA
4792 * <4> 0 Rx Bound IA
4793 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4794 * <2> 0 Abort/PE IA
4795 * <1> 1 Rx Overrun IA
4796 * <0> 0 Select TC0 value for readback
4797 *
4798 * 0000 0000 0000 1000 = 0x000a
4799 */
4800
4801 /* Carry over the Exit Hunt and Idle Received bits */
4802 /* in case they have been armed by usc_ArmEvents. */
4803
4804 RegValue = usc_InReg( info, RICR ) & 0xc0;
4805
4806 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4807 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4808 else
4809 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4810
4811 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4812
4813 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4814 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4815
4816 /* Transmit mode Register (TMR)
4817 *
4818 * <15..13> 000 encoding
4819 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4820 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4821 * <9> 0 1 = Tx CRC Enabled
4822 * <8> 0 1 = Append CRC to end of transmit frame
4823 * <7..6> 00 Transmit parity Even
4824 * <5> 0 Transmit parity Disabled
4825 * <4..2> 000 Tx Char Length = 8 bits
4826 * <1..0> 00 Disable Transmitter
4827 *
4828 * 0000 0100 0000 0000 = 0x0400
4829 */
4830
4831 RegValue = 0x0400;
4832
4833 switch ( info->params.encoding ) {
4834 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4835 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4836 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4837 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4838 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4839 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4840 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4841 }
4842
4843 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4844 RegValue |= BIT9 + BIT8;
4845 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4846 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4847
4848 usc_OutReg( info, TMR, RegValue );
4849
4850 usc_set_txidle( info );
4851
4852
4853 usc_TCmd( info, TCmd_SelectTicrdma_level );
4854
4855 /* Transmit Interrupt Control Register (TICR)
4856 *
4857 * <15..8> ? Transmit FIFO DMA Level
4858 * <7> 0 Present IA (Interrupt Arm)
4859 * <6> 0 Idle Sent IA
4860 * <5> 1 Abort Sent IA
4861 * <4> 1 EOF/EOM Sent IA
4862 * <3> 0 CRC Sent IA
4863 * <2> 1 1 = Wait for SW Trigger to Start Frame
4864 * <1> 1 Tx Underrun IA
4865 * <0> 0 TC0 constant on read back
4866 *
4867 * 0000 0000 0011 0110 = 0x0036
4868 */
4869
4870 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4871 usc_OutReg( info, TICR, 0x0736 );
4872 else
4873 usc_OutReg( info, TICR, 0x1436 );
4874
4875 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4876 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4877
4878 /*
4879 ** Transmit Command/Status Register (TCSR)
4880 **
4881 ** <15..12> 0000 TCmd
4882 ** <11> 0/1 UnderWait
4883 ** <10..08> 000 TxIdle
4884 ** <7> x PreSent
4885 ** <6> x IdleSent
4886 ** <5> x AbortSent
4887 ** <4> x EOF/EOM Sent
4888 ** <3> x CRC Sent
4889 ** <2> x All Sent
4890 ** <1> x TxUnder
4891 ** <0> x TxEmpty
4892 **
4893 ** 0000 0000 0000 0000 = 0x0000
4894 */
4895 info->tcsr_value = 0;
4896
4897 if ( !PreSL1660 )
4898 info->tcsr_value |= TCSR_UNDERWAIT;
4899
4900 usc_OutReg( info, TCSR, info->tcsr_value );
4901
4902 /* Clock mode Control Register (CMCR)
4903 *
4904 * <15..14> 00 counter 1 Source = Disabled
4905 * <13..12> 00 counter 0 Source = Disabled
4906 * <11..10> 11 BRG1 Input is TxC Pin
4907 * <9..8> 11 BRG0 Input is TxC Pin
4908 * <7..6> 01 DPLL Input is BRG1 Output
4909 * <5..3> XXX TxCLK comes from Port 0
4910 * <2..0> XXX RxCLK comes from Port 1
4911 *
4912 * 0000 1111 0111 0111 = 0x0f77
4913 */
4914
4915 RegValue = 0x0f40;
4916
4917 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4918 RegValue |= 0x0003; /* RxCLK from DPLL */
4919 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4920 RegValue |= 0x0004; /* RxCLK from BRG0 */
4921 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4922 RegValue |= 0x0006; /* RxCLK from TXC Input */
4923 else
4924 RegValue |= 0x0007; /* RxCLK from Port1 */
4925
4926 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4927 RegValue |= 0x0018; /* TxCLK from DPLL */
4928 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4929 RegValue |= 0x0020; /* TxCLK from BRG0 */
4930 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4931 RegValue |= 0x0038; /* RxCLK from TXC Input */
4932 else
4933 RegValue |= 0x0030; /* TxCLK from Port0 */
4934
4935 usc_OutReg( info, CMCR, RegValue );
4936
4937
4938 /* Hardware Configuration Register (HCR)
4939 *
4940 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4941 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4942 * <12> 0 CVOK:0=report code violation in biphase
4943 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4944 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4945 * <7..6> 00 reserved
4946 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4947 * <4> X BRG1 Enable
4948 * <3..2> 00 reserved
4949 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4950 * <0> 0 BRG0 Enable
4951 */
4952
4953 RegValue = 0x0000;
4954
4955 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4956 u32 XtalSpeed;
4957 u32 DpllDivisor;
4958 u16 Tc;
4959
4960 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4961 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4962
4963 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4964 XtalSpeed = 11059200;
4965 else
4966 XtalSpeed = 14745600;
4967
4968 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4969 DpllDivisor = 16;
4970 RegValue |= BIT10;
4971 }
4972 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4973 DpllDivisor = 8;
4974 RegValue |= BIT11;
4975 }
4976 else
4977 DpllDivisor = 32;
4978
4979 /* Tc = (Xtal/Speed) - 1 */
4980 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4981 /* then rounding up gives a more precise time constant. Instead */
4982 /* of rounding up and then subtracting 1 we just don't subtract */
4983 /* the one in this case. */
4984
4985 /*--------------------------------------------------
4986 * ejz: for DPLL mode, application should use the
4987 * same clock speed as the partner system, even
4988 * though clocking is derived from the input RxData.
4989 * In case the user uses a 0 for the clock speed,
4990 * default to 0xffffffff and don't try to divide by
4991 * zero
4992 *--------------------------------------------------*/
4993 if ( info->params.clock_speed )
4994 {
4995 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4996 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4997 / info->params.clock_speed) )
4998 Tc--;
4999 }
5000 else
5001 Tc = -1;
5002
5003
5004 /* Write 16-bit Time Constant for BRG1 */
5005 usc_OutReg( info, TC1R, Tc );
5006
5007 RegValue |= BIT4; /* enable BRG1 */
5008
5009 switch ( info->params.encoding ) {
5010 case HDLC_ENCODING_NRZ:
5011 case HDLC_ENCODING_NRZB:
5012 case HDLC_ENCODING_NRZI_MARK:
5013 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5014 case HDLC_ENCODING_BIPHASE_MARK:
5015 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5016 case HDLC_ENCODING_BIPHASE_LEVEL:
5017 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5018 }
5019 }
5020
5021 usc_OutReg( info, HCR, RegValue );
5022
5023
5024 /* Channel Control/status Register (CCSR)
5025 *
5026 * <15> X RCC FIFO Overflow status (RO)
5027 * <14> X RCC FIFO Not Empty status (RO)
5028 * <13> 0 1 = Clear RCC FIFO (WO)
5029 * <12> X DPLL Sync (RW)
5030 * <11> X DPLL 2 Missed Clocks status (RO)
5031 * <10> X DPLL 1 Missed Clock status (RO)
5032 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5033 * <7> X SDLC Loop On status (RO)
5034 * <6> X SDLC Loop Send status (RO)
5035 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5036 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5037 * <1..0> 00 reserved
5038 *
5039 * 0000 0000 0010 0000 = 0x0020
5040 */
5041
5042 usc_OutReg( info, CCSR, 0x1020 );
5043
5044
5045 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5046 usc_OutReg( info, SICR,
5047 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5048 }
5049
5050
5051 /* enable Master Interrupt Enable bit (MIE) */
5052 usc_EnableMasterIrqBit( info );
5053
5054 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5055 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5056
5057 /* arm RCC underflow interrupt */
5058 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5059 usc_EnableInterrupts(info, MISC);
5060
5061 info->mbre_bit = 0;
5062 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5063 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5064 info->mbre_bit = BIT8;
5065 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5066
5067 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5068 /* Enable DMAEN (Port 7, Bit 14) */
5069 /* This connects the DMA request signal to the ISA bus */
5070 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5071 }
5072
5073 /* DMA Control Register (DCR)
5074 *
5075 * <15..14> 10 Priority mode = Alternating Tx/Rx
5076 * 01 Rx has priority
5077 * 00 Tx has priority
5078 *
5079 * <13> 1 Enable Priority Preempt per DCR<15..14>
5080 * (WARNING DCR<11..10> must be 00 when this is 1)
5081 * 0 Choose activate channel per DCR<11..10>
5082 *
5083 * <12> 0 Little Endian for Array/List
5084 * <11..10> 00 Both Channels can use each bus grant
5085 * <9..6> 0000 reserved
5086 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5087 * <4> 0 1 = drive D/C and S/D pins
5088 * <3> 1 1 = Add one wait state to all DMA cycles.
5089 * <2> 0 1 = Strobe /UAS on every transfer.
5090 * <1..0> 11 Addr incrementing only affects LS24 bits
5091 *
5092 * 0110 0000 0000 1011 = 0x600b
5093 */
5094
5095 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5096 /* PCI adapter does not need DMA wait state */
5097 usc_OutDmaReg( info, DCR, 0xa00b );
5098 }
5099 else
5100 usc_OutDmaReg( info, DCR, 0x800b );
5101
5102
5103 /* Receive DMA mode Register (RDMR)
5104 *
5105 * <15..14> 11 DMA mode = Linked List Buffer mode
5106 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5107 * <12> 1 Clear count of List Entry after fetching
5108 * <11..10> 00 Address mode = Increment
5109 * <9> 1 Terminate Buffer on RxBound
5110 * <8> 0 Bus Width = 16bits
5111 * <7..0> ? status Bits (write as 0s)
5112 *
5113 * 1111 0010 0000 0000 = 0xf200
5114 */
5115
5116 usc_OutDmaReg( info, RDMR, 0xf200 );
5117
5118
5119 /* Transmit DMA mode Register (TDMR)
5120 *
5121 * <15..14> 11 DMA mode = Linked List Buffer mode
5122 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5123 * <12> 1 Clear count of List Entry after fetching
5124 * <11..10> 00 Address mode = Increment
5125 * <9> 1 Terminate Buffer on end of frame
5126 * <8> 0 Bus Width = 16bits
5127 * <7..0> ? status Bits (Read Only so write as 0)
5128 *
5129 * 1111 0010 0000 0000 = 0xf200
5130 */
5131
5132 usc_OutDmaReg( info, TDMR, 0xf200 );
5133
5134
5135 /* DMA Interrupt Control Register (DICR)
5136 *
5137 * <15> 1 DMA Interrupt Enable
5138 * <14> 0 1 = Disable IEO from USC
5139 * <13> 0 1 = Don't provide vector during IntAck
5140 * <12> 1 1 = Include status in Vector
5141 * <10..2> 0 reserved, Must be 0s
5142 * <1> 0 1 = Rx DMA Interrupt Enabled
5143 * <0> 0 1 = Tx DMA Interrupt Enabled
5144 *
5145 * 1001 0000 0000 0000 = 0x9000
5146 */
5147
5148 usc_OutDmaReg( info, DICR, 0x9000 );
5149
5150 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5151 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5152 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5153
5154 /* Channel Control Register (CCR)
5155 *
5156 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5157 * <13> 0 Trigger Tx on SW Command Disabled
5158 * <12> 0 Flag Preamble Disabled
5159 * <11..10> 00 Preamble Length
5160 * <9..8> 00 Preamble Pattern
5161 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5162 * <5> 0 Trigger Rx on SW Command Disabled
5163 * <4..0> 0 reserved
5164 *
5165 * 1000 0000 1000 0000 = 0x8080
5166 */
5167
5168 RegValue = 0x8080;
5169
5170 switch ( info->params.preamble_length ) {
5171 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5172 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5173 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5174 }
5175
5176 switch ( info->params.preamble ) {
5177 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5178 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5179 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5180 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5181 }
5182
5183 usc_OutReg( info, CCR, RegValue );
5184
5185
5186 /*
5187 * Burst/Dwell Control Register
5188 *
5189 * <15..8> 0x20 Maximum number of transfers per bus grant
5190 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5191 */
5192
5193 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5194 /* don't limit bus occupancy on PCI adapter */
5195 usc_OutDmaReg( info, BDCR, 0x0000 );
5196 }
5197 else
5198 usc_OutDmaReg( info, BDCR, 0x2000 );
5199
5200 usc_stop_transmitter(info);
5201 usc_stop_receiver(info);
5202
5203 } /* end of usc_set_sdlc_mode() */
5204
5205 /* usc_enable_loopback()
5206 *
5207 * Set the 16C32 for internal loopback mode.
5208 * The TxCLK and RxCLK signals are generated from the BRG0 and
5209 * the TxD is looped back to the RxD internally.
5210 *
5211 * Arguments: info pointer to device instance data
5212 * enable 1 = enable loopback, 0 = disable
5213 * Return Value: None
5214 */
5215 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5216 {
5217 if (enable) {
5218 /* blank external TXD output */
5219 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5220
5221 /* Clock mode Control Register (CMCR)
5222 *
5223 * <15..14> 00 counter 1 Disabled
5224 * <13..12> 00 counter 0 Disabled
5225 * <11..10> 11 BRG1 Input is TxC Pin
5226 * <9..8> 11 BRG0 Input is TxC Pin
5227 * <7..6> 01 DPLL Input is BRG1 Output
5228 * <5..3> 100 TxCLK comes from BRG0
5229 * <2..0> 100 RxCLK comes from BRG0
5230 *
5231 * 0000 1111 0110 0100 = 0x0f64
5232 */
5233
5234 usc_OutReg( info, CMCR, 0x0f64 );
5235
5236 /* Write 16-bit Time Constant for BRG0 */
5237 /* use clock speed if available, otherwise use 8 for diagnostics */
5238 if (info->params.clock_speed) {
5239 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5240 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5241 else
5242 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5243 } else
5244 usc_OutReg(info, TC0R, (u16)8);
5245
5246 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5247 mode = Continuous Set Bit 0 to enable BRG0. */
5248 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5249
5250 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5251 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5252
5253 /* set Internal Data loopback mode */
5254 info->loopback_bits = 0x300;
5255 outw( 0x0300, info->io_base + CCAR );
5256 } else {
5257 /* enable external TXD output */
5258 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5259
5260 /* clear Internal Data loopback mode */
5261 info->loopback_bits = 0;
5262 outw( 0,info->io_base + CCAR );
5263 }
5264
5265 } /* end of usc_enable_loopback() */
5266
5267 /* usc_enable_aux_clock()
5268 *
5269 * Enabled the AUX clock output at the specified frequency.
5270 *
5271 * Arguments:
5272 *
5273 * info pointer to device extension
5274 * data_rate data rate of clock in bits per second
5275 * A data rate of 0 disables the AUX clock.
5276 *
5277 * Return Value: None
5278 */
5279 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5280 {
5281 u32 XtalSpeed;
5282 u16 Tc;
5283
5284 if ( data_rate ) {
5285 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5286 XtalSpeed = 11059200;
5287 else
5288 XtalSpeed = 14745600;
5289
5290
5291 /* Tc = (Xtal/Speed) - 1 */
5292 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5293 /* then rounding up gives a more precise time constant. Instead */
5294 /* of rounding up and then subtracting 1 we just don't subtract */
5295 /* the one in this case. */
5296
5297
5298 Tc = (u16)(XtalSpeed/data_rate);
5299 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5300 Tc--;
5301
5302 /* Write 16-bit Time Constant for BRG0 */
5303 usc_OutReg( info, TC0R, Tc );
5304
5305 /*
5306 * Hardware Configuration Register (HCR)
5307 * Clear Bit 1, BRG0 mode = Continuous
5308 * Set Bit 0 to enable BRG0.
5309 */
5310
5311 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5312
5313 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5314 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5315 } else {
5316 /* data rate == 0 so turn off BRG0 */
5317 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5318 }
5319
5320 } /* end of usc_enable_aux_clock() */
5321
5322 /*
5323 *
5324 * usc_process_rxoverrun_sync()
5325 *
5326 * This function processes a receive overrun by resetting the
5327 * receive DMA buffers and issuing a Purge Rx FIFO command
5328 * to allow the receiver to continue receiving.
5329 *
5330 * Arguments:
5331 *
5332 * info pointer to device extension
5333 *
5334 * Return Value: None
5335 */
5336 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5337 {
5338 int start_index;
5339 int end_index;
5340 int frame_start_index;
5341 bool start_of_frame_found = false;
5342 bool end_of_frame_found = false;
5343 bool reprogram_dma = false;
5344
5345 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5346 u32 phys_addr;
5347
5348 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5349 usc_RCmd( info, RCmd_EnterHuntmode );
5350 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5351
5352 /* CurrentRxBuffer points to the 1st buffer of the next */
5353 /* possibly available receive frame. */
5354
5355 frame_start_index = start_index = end_index = info->current_rx_buffer;
5356
5357 /* Search for an unfinished string of buffers. This means */
5358 /* that a receive frame started (at least one buffer with */
5359 /* count set to zero) but there is no terminiting buffer */
5360 /* (status set to non-zero). */
5361
5362 while( !buffer_list[end_index].count )
5363 {
5364 /* Count field has been reset to zero by 16C32. */
5365 /* This buffer is currently in use. */
5366
5367 if ( !start_of_frame_found )
5368 {
5369 start_of_frame_found = true;
5370 frame_start_index = end_index;
5371 end_of_frame_found = false;
5372 }
5373
5374 if ( buffer_list[end_index].status )
5375 {
5376 /* Status field has been set by 16C32. */
5377 /* This is the last buffer of a received frame. */
5378
5379 /* We want to leave the buffers for this frame intact. */
5380 /* Move on to next possible frame. */
5381
5382 start_of_frame_found = false;
5383 end_of_frame_found = true;
5384 }
5385
5386 /* advance to next buffer entry in linked list */
5387 end_index++;
5388 if ( end_index == info->rx_buffer_count )
5389 end_index = 0;
5390
5391 if ( start_index == end_index )
5392 {
5393 /* The entire list has been searched with all Counts == 0 and */
5394 /* all Status == 0. The receive buffers are */
5395 /* completely screwed, reset all receive buffers! */
5396 mgsl_reset_rx_dma_buffers( info );
5397 frame_start_index = 0;
5398 start_of_frame_found = false;
5399 reprogram_dma = true;
5400 break;
5401 }
5402 }
5403
5404 if ( start_of_frame_found && !end_of_frame_found )
5405 {
5406 /* There is an unfinished string of receive DMA buffers */
5407 /* as a result of the receiver overrun. */
5408
5409 /* Reset the buffers for the unfinished frame */
5410 /* and reprogram the receive DMA controller to start */
5411 /* at the 1st buffer of unfinished frame. */
5412
5413 start_index = frame_start_index;
5414
5415 do
5416 {
5417 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5418
5419 /* Adjust index for wrap around. */
5420 if ( start_index == info->rx_buffer_count )
5421 start_index = 0;
5422
5423 } while( start_index != end_index );
5424
5425 reprogram_dma = true;
5426 }
5427
5428 if ( reprogram_dma )
5429 {
5430 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5431 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5432 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5433
5434 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5435
5436 /* This empties the receive FIFO and loads the RCC with RCLR */
5437 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5438
5439 /* program 16C32 with physical address of 1st DMA buffer entry */
5440 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5441 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5442 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5443
5444 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5445 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5446 usc_EnableInterrupts( info, RECEIVE_STATUS );
5447
5448 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5449 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5450
5451 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5452 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5453 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5454 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5455 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5456 else
5457 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5458 }
5459 else
5460 {
5461 /* This empties the receive FIFO and loads the RCC with RCLR */
5462 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5463 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5464 }
5465
5466 } /* end of usc_process_rxoverrun_sync() */
5467
5468 /* usc_stop_receiver()
5469 *
5470 * Disable USC receiver
5471 *
5472 * Arguments: info pointer to device instance data
5473 * Return Value: None
5474 */
5475 static void usc_stop_receiver( struct mgsl_struct *info )
5476 {
5477 if (debug_level >= DEBUG_LEVEL_ISR)
5478 printk("%s(%d):usc_stop_receiver(%s)\n",
5479 __FILE__,__LINE__, info->device_name );
5480
5481 /* Disable receive DMA channel. */
5482 /* This also disables receive DMA channel interrupts */
5483 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5484
5485 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5486 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5487 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5488
5489 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5490
5491 /* This empties the receive FIFO and loads the RCC with RCLR */
5492 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5493 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5494
5495 info->rx_enabled = false;
5496 info->rx_overflow = false;
5497 info->rx_rcc_underrun = false;
5498
5499 } /* end of stop_receiver() */
5500
5501 /* usc_start_receiver()
5502 *
5503 * Enable the USC receiver
5504 *
5505 * Arguments: info pointer to device instance data
5506 * Return Value: None
5507 */
5508 static void usc_start_receiver( struct mgsl_struct *info )
5509 {
5510 u32 phys_addr;
5511
5512 if (debug_level >= DEBUG_LEVEL_ISR)
5513 printk("%s(%d):usc_start_receiver(%s)\n",
5514 __FILE__,__LINE__, info->device_name );
5515
5516 mgsl_reset_rx_dma_buffers( info );
5517 usc_stop_receiver( info );
5518
5519 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5520 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5521
5522 if ( info->params.mode == MGSL_MODE_HDLC ||
5523 info->params.mode == MGSL_MODE_RAW ) {
5524 /* DMA mode Transfers */
5525 /* Program the DMA controller. */
5526 /* Enable the DMA controller end of buffer interrupt. */
5527
5528 /* program 16C32 with physical address of 1st DMA buffer entry */
5529 phys_addr = info->rx_buffer_list[0].phys_entry;
5530 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5531 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5532
5533 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5534 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5535 usc_EnableInterrupts( info, RECEIVE_STATUS );
5536
5537 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5538 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5539
5540 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5541 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5542 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5543 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5544 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5545 else
5546 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5547 } else {
5548 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5549 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5550 usc_EnableInterrupts(info, RECEIVE_DATA);
5551
5552 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5553 usc_RCmd( info, RCmd_EnterHuntmode );
5554
5555 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5556 }
5557
5558 usc_OutReg( info, CCSR, 0x1020 );
5559
5560 info->rx_enabled = true;
5561
5562 } /* end of usc_start_receiver() */
5563
5564 /* usc_start_transmitter()
5565 *
5566 * Enable the USC transmitter and send a transmit frame if
5567 * one is loaded in the DMA buffers.
5568 *
5569 * Arguments: info pointer to device instance data
5570 * Return Value: None
5571 */
5572 static void usc_start_transmitter( struct mgsl_struct *info )
5573 {
5574 u32 phys_addr;
5575 unsigned int FrameSize;
5576
5577 if (debug_level >= DEBUG_LEVEL_ISR)
5578 printk("%s(%d):usc_start_transmitter(%s)\n",
5579 __FILE__,__LINE__, info->device_name );
5580
5581 if ( info->xmit_cnt ) {
5582
5583 /* If auto RTS enabled and RTS is inactive, then assert */
5584 /* RTS and set a flag indicating that the driver should */
5585 /* negate RTS when the transmission completes. */
5586
5587 info->drop_rts_on_tx_done = false;
5588
5589 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5590 usc_get_serial_signals( info );
5591 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5592 info->serial_signals |= SerialSignal_RTS;
5593 usc_set_serial_signals( info );
5594 info->drop_rts_on_tx_done = true;
5595 }
5596 }
5597
5598
5599 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5600 if ( !info->tx_active ) {
5601 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5602 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5603 usc_EnableInterrupts(info, TRANSMIT_DATA);
5604 usc_load_txfifo(info);
5605 }
5606 } else {
5607 /* Disable transmit DMA controller while programming. */
5608 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5609
5610 /* Transmit DMA buffer is loaded, so program USC */
5611 /* to send the frame contained in the buffers. */
5612
5613 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5614
5615 /* if operating in Raw sync mode, reset the rcc component
5616 * of the tx dma buffer entry, otherwise, the serial controller
5617 * will send a closing sync char after this count.
5618 */
5619 if ( info->params.mode == MGSL_MODE_RAW )
5620 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5621
5622 /* Program the Transmit Character Length Register (TCLR) */
5623 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5624 usc_OutReg( info, TCLR, (u16)FrameSize );
5625
5626 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5627
5628 /* Program the address of the 1st DMA Buffer Entry in linked list */
5629 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5630 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5631 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5632
5633 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5634 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5635 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5636
5637 if ( info->params.mode == MGSL_MODE_RAW &&
5638 info->num_tx_dma_buffers > 1 ) {
5639 /* When running external sync mode, attempt to 'stream' transmit */
5640 /* by filling tx dma buffers as they become available. To do this */
5641 /* we need to enable Tx DMA EOB Status interrupts : */
5642 /* */
5643 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5644 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5645
5646 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5647 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5648 }
5649
5650 /* Initialize Transmit DMA Channel */
5651 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5652
5653 usc_TCmd( info, TCmd_SendFrame );
5654
5655 mod_timer(&info->tx_timer, jiffies +
5656 msecs_to_jiffies(5000));
5657 }
5658 info->tx_active = true;
5659 }
5660
5661 if ( !info->tx_enabled ) {
5662 info->tx_enabled = true;
5663 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5664 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5665 else
5666 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5667 }
5668
5669 } /* end of usc_start_transmitter() */
5670
5671 /* usc_stop_transmitter()
5672 *
5673 * Stops the transmitter and DMA
5674 *
5675 * Arguments: info pointer to device isntance data
5676 * Return Value: None
5677 */
5678 static void usc_stop_transmitter( struct mgsl_struct *info )
5679 {
5680 if (debug_level >= DEBUG_LEVEL_ISR)
5681 printk("%s(%d):usc_stop_transmitter(%s)\n",
5682 __FILE__,__LINE__, info->device_name );
5683
5684 del_timer(&info->tx_timer);
5685
5686 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5687 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5688 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5689
5690 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5691 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5692 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5693
5694 info->tx_enabled = false;
5695 info->tx_active = false;
5696
5697 } /* end of usc_stop_transmitter() */
5698
5699 /* usc_load_txfifo()
5700 *
5701 * Fill the transmit FIFO until the FIFO is full or
5702 * there is no more data to load.
5703 *
5704 * Arguments: info pointer to device extension (instance data)
5705 * Return Value: None
5706 */
5707 static void usc_load_txfifo( struct mgsl_struct *info )
5708 {
5709 int Fifocount;
5710 u8 TwoBytes[2];
5711
5712 if ( !info->xmit_cnt && !info->x_char )
5713 return;
5714
5715 /* Select transmit FIFO status readback in TICR */
5716 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5717
5718 /* load the Transmit FIFO until FIFOs full or all data sent */
5719
5720 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5721 /* there is more space in the transmit FIFO and */
5722 /* there is more data in transmit buffer */
5723
5724 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5725 /* write a 16-bit word from transmit buffer to 16C32 */
5726
5727 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5728 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5729 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5730 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5731
5732 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5733
5734 info->xmit_cnt -= 2;
5735 info->icount.tx += 2;
5736 } else {
5737 /* only 1 byte left to transmit or 1 FIFO slot left */
5738
5739 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5740 info->io_base + CCAR );
5741
5742 if (info->x_char) {
5743 /* transmit pending high priority char */
5744 outw( info->x_char,info->io_base + CCAR );
5745 info->x_char = 0;
5746 } else {
5747 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5748 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5749 info->xmit_cnt--;
5750 }
5751 info->icount.tx++;
5752 }
5753 }
5754
5755 } /* end of usc_load_txfifo() */
5756
5757 /* usc_reset()
5758 *
5759 * Reset the adapter to a known state and prepare it for further use.
5760 *
5761 * Arguments: info pointer to device instance data
5762 * Return Value: None
5763 */
5764 static void usc_reset( struct mgsl_struct *info )
5765 {
5766 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5767 int i;
5768 u32 readval;
5769
5770 /* Set BIT30 of Misc Control Register */
5771 /* (Local Control Register 0x50) to force reset of USC. */
5772
5773 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5774 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5775
5776 info->misc_ctrl_value |= BIT30;
5777 *MiscCtrl = info->misc_ctrl_value;
5778
5779 /*
5780 * Force at least 170ns delay before clearing
5781 * reset bit. Each read from LCR takes at least
5782 * 30ns so 10 times for 300ns to be safe.
5783 */
5784 for(i=0;i<10;i++)
5785 readval = *MiscCtrl;
5786
5787 info->misc_ctrl_value &= ~BIT30;
5788 *MiscCtrl = info->misc_ctrl_value;
5789
5790 *LCR0BRDR = BUS_DESCRIPTOR(
5791 1, // Write Strobe Hold (0-3)
5792 2, // Write Strobe Delay (0-3)
5793 2, // Read Strobe Delay (0-3)
5794 0, // NWDD (Write data-data) (0-3)
5795 4, // NWAD (Write Addr-data) (0-31)
5796 0, // NXDA (Read/Write Data-Addr) (0-3)
5797 0, // NRDD (Read Data-Data) (0-3)
5798 5 // NRAD (Read Addr-Data) (0-31)
5799 );
5800 } else {
5801 /* do HW reset */
5802 outb( 0,info->io_base + 8 );
5803 }
5804
5805 info->mbre_bit = 0;
5806 info->loopback_bits = 0;
5807 info->usc_idle_mode = 0;
5808
5809 /*
5810 * Program the Bus Configuration Register (BCR)
5811 *
5812 * <15> 0 Don't use separate address
5813 * <14..6> 0 reserved
5814 * <5..4> 00 IAckmode = Default, don't care
5815 * <3> 1 Bus Request Totem Pole output
5816 * <2> 1 Use 16 Bit data bus
5817 * <1> 0 IRQ Totem Pole output
5818 * <0> 0 Don't Shift Right Addr
5819 *
5820 * 0000 0000 0000 1100 = 0x000c
5821 *
5822 * By writing to io_base + SDPIN the Wait/Ack pin is
5823 * programmed to work as a Wait pin.
5824 */
5825
5826 outw( 0x000c,info->io_base + SDPIN );
5827
5828
5829 outw( 0,info->io_base );
5830 outw( 0,info->io_base + CCAR );
5831
5832 /* select little endian byte ordering */
5833 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5834
5835
5836 /* Port Control Register (PCR)
5837 *
5838 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5839 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5840 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5841 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5842 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5843 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5844 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5845 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5846 *
5847 * 1111 0000 1111 0101 = 0xf0f5
5848 */
5849
5850 usc_OutReg( info, PCR, 0xf0f5 );
5851
5852
5853 /*
5854 * Input/Output Control Register
5855 *
5856 * <15..14> 00 CTS is active low input
5857 * <13..12> 00 DCD is active low input
5858 * <11..10> 00 TxREQ pin is input (DSR)
5859 * <9..8> 00 RxREQ pin is input (RI)
5860 * <7..6> 00 TxD is output (Transmit Data)
5861 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5862 * <2..0> 100 RxC is Output (drive with BRG0)
5863 *
5864 * 0000 0000 0000 0100 = 0x0004
5865 */
5866
5867 usc_OutReg( info, IOCR, 0x0004 );
5868
5869 } /* end of usc_reset() */
5870
5871 /* usc_set_async_mode()
5872 *
5873 * Program adapter for asynchronous communications.
5874 *
5875 * Arguments: info pointer to device instance data
5876 * Return Value: None
5877 */
5878 static void usc_set_async_mode( struct mgsl_struct *info )
5879 {
5880 u16 RegValue;
5881
5882 /* disable interrupts while programming USC */
5883 usc_DisableMasterIrqBit( info );
5884
5885 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5886 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5887
5888 usc_loopback_frame( info );
5889
5890 /* Channel mode Register (CMR)
5891 *
5892 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5893 * <13..12> 00 00 = 16X Clock
5894 * <11..8> 0000 Transmitter mode = Asynchronous
5895 * <7..6> 00 reserved?
5896 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5897 * <3..0> 0000 Receiver mode = Asynchronous
5898 *
5899 * 0000 0000 0000 0000 = 0x0
5900 */
5901
5902 RegValue = 0;
5903 if ( info->params.stop_bits != 1 )
5904 RegValue |= BIT14;
5905 usc_OutReg( info, CMR, RegValue );
5906
5907
5908 /* Receiver mode Register (RMR)
5909 *
5910 * <15..13> 000 encoding = None
5911 * <12..08> 00000 reserved (Sync Only)
5912 * <7..6> 00 Even parity
5913 * <5> 0 parity disabled
5914 * <4..2> 000 Receive Char Length = 8 bits
5915 * <1..0> 00 Disable Receiver
5916 *
5917 * 0000 0000 0000 0000 = 0x0
5918 */
5919
5920 RegValue = 0;
5921
5922 if ( info->params.data_bits != 8 )
5923 RegValue |= BIT4+BIT3+BIT2;
5924
5925 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5926 RegValue |= BIT5;
5927 if ( info->params.parity != ASYNC_PARITY_ODD )
5928 RegValue |= BIT6;
5929 }
5930
5931 usc_OutReg( info, RMR, RegValue );
5932
5933
5934 /* Set IRQ trigger level */
5935
5936 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5937
5938
5939 /* Receive Interrupt Control Register (RICR)
5940 *
5941 * <15..8> ? RxFIFO IRQ Request Level
5942 *
5943 * Note: For async mode the receive FIFO level must be set
5944 * to 0 to avoid the situation where the FIFO contains fewer bytes
5945 * than the trigger level and no more data is expected.
5946 *
5947 * <7> 0 Exited Hunt IA (Interrupt Arm)
5948 * <6> 0 Idle Received IA
5949 * <5> 0 Break/Abort IA
5950 * <4> 0 Rx Bound IA
5951 * <3> 0 Queued status reflects oldest byte in FIFO
5952 * <2> 0 Abort/PE IA
5953 * <1> 0 Rx Overrun IA
5954 * <0> 0 Select TC0 value for readback
5955 *
5956 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5957 */
5958
5959 usc_OutReg( info, RICR, 0x0000 );
5960
5961 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5962 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5963
5964
5965 /* Transmit mode Register (TMR)
5966 *
5967 * <15..13> 000 encoding = None
5968 * <12..08> 00000 reserved (Sync Only)
5969 * <7..6> 00 Transmit parity Even
5970 * <5> 0 Transmit parity Disabled
5971 * <4..2> 000 Tx Char Length = 8 bits
5972 * <1..0> 00 Disable Transmitter
5973 *
5974 * 0000 0000 0000 0000 = 0x0
5975 */
5976
5977 RegValue = 0;
5978
5979 if ( info->params.data_bits != 8 )
5980 RegValue |= BIT4+BIT3+BIT2;
5981
5982 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5983 RegValue |= BIT5;
5984 if ( info->params.parity != ASYNC_PARITY_ODD )
5985 RegValue |= BIT6;
5986 }
5987
5988 usc_OutReg( info, TMR, RegValue );
5989
5990 usc_set_txidle( info );
5991
5992
5993 /* Set IRQ trigger level */
5994
5995 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5996
5997
5998 /* Transmit Interrupt Control Register (TICR)
5999 *
6000 * <15..8> ? Transmit FIFO IRQ Level
6001 * <7> 0 Present IA (Interrupt Arm)
6002 * <6> 1 Idle Sent IA
6003 * <5> 0 Abort Sent IA
6004 * <4> 0 EOF/EOM Sent IA
6005 * <3> 0 CRC Sent IA
6006 * <2> 0 1 = Wait for SW Trigger to Start Frame
6007 * <1> 0 Tx Underrun IA
6008 * <0> 0 TC0 constant on read back
6009 *
6010 * 0000 0000 0100 0000 = 0x0040
6011 */
6012
6013 usc_OutReg( info, TICR, 0x1f40 );
6014
6015 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6016 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6017
6018 usc_enable_async_clock( info, info->params.data_rate );
6019
6020
6021 /* Channel Control/status Register (CCSR)
6022 *
6023 * <15> X RCC FIFO Overflow status (RO)
6024 * <14> X RCC FIFO Not Empty status (RO)
6025 * <13> 0 1 = Clear RCC FIFO (WO)
6026 * <12> X DPLL in Sync status (RO)
6027 * <11> X DPLL 2 Missed Clocks status (RO)
6028 * <10> X DPLL 1 Missed Clock status (RO)
6029 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6030 * <7> X SDLC Loop On status (RO)
6031 * <6> X SDLC Loop Send status (RO)
6032 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6033 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6034 * <1..0> 00 reserved
6035 *
6036 * 0000 0000 0010 0000 = 0x0020
6037 */
6038
6039 usc_OutReg( info, CCSR, 0x0020 );
6040
6041 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6042 RECEIVE_DATA + RECEIVE_STATUS );
6043
6044 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6045 RECEIVE_DATA + RECEIVE_STATUS );
6046
6047 usc_EnableMasterIrqBit( info );
6048
6049 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6050 /* Enable INTEN (Port 6, Bit12) */
6051 /* This connects the IRQ request signal to the ISA bus */
6052 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6053 }
6054
6055 if (info->params.loopback) {
6056 info->loopback_bits = 0x300;
6057 outw(0x0300, info->io_base + CCAR);
6058 }
6059
6060 } /* end of usc_set_async_mode() */
6061
6062 /* usc_loopback_frame()
6063 *
6064 * Loop back a small (2 byte) dummy SDLC frame.
6065 * Interrupts and DMA are NOT used. The purpose of this is to
6066 * clear any 'stale' status info left over from running in async mode.
6067 *
6068 * The 16C32 shows the strange behaviour of marking the 1st
6069 * received SDLC frame with a CRC error even when there is no
6070 * CRC error. To get around this a small dummy from of 2 bytes
6071 * is looped back when switching from async to sync mode.
6072 *
6073 * Arguments: info pointer to device instance data
6074 * Return Value: None
6075 */
6076 static void usc_loopback_frame( struct mgsl_struct *info )
6077 {
6078 int i;
6079 unsigned long oldmode = info->params.mode;
6080
6081 info->params.mode = MGSL_MODE_HDLC;
6082
6083 usc_DisableMasterIrqBit( info );
6084
6085 usc_set_sdlc_mode( info );
6086 usc_enable_loopback( info, 1 );
6087
6088 /* Write 16-bit Time Constant for BRG0 */
6089 usc_OutReg( info, TC0R, 0 );
6090
6091 /* Channel Control Register (CCR)
6092 *
6093 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6094 * <13> 0 Trigger Tx on SW Command Disabled
6095 * <12> 0 Flag Preamble Disabled
6096 * <11..10> 00 Preamble Length = 8-Bits
6097 * <9..8> 01 Preamble Pattern = flags
6098 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6099 * <5> 0 Trigger Rx on SW Command Disabled
6100 * <4..0> 0 reserved
6101 *
6102 * 0000 0001 0000 0000 = 0x0100
6103 */
6104
6105 usc_OutReg( info, CCR, 0x0100 );
6106
6107 /* SETUP RECEIVER */
6108 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6109 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6110
6111 /* SETUP TRANSMITTER */
6112 /* Program the Transmit Character Length Register (TCLR) */
6113 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6114 usc_OutReg( info, TCLR, 2 );
6115 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6116
6117 /* unlatch Tx status bits, and start transmit channel. */
6118 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6119 outw(0,info->io_base + DATAREG);
6120
6121 /* ENABLE TRANSMITTER */
6122 usc_TCmd( info, TCmd_SendFrame );
6123 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6124
6125 /* WAIT FOR RECEIVE COMPLETE */
6126 for (i=0 ; i<1000 ; i++)
6127 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6128 break;
6129
6130 /* clear Internal Data loopback mode */
6131 usc_enable_loopback(info, 0);
6132
6133 usc_EnableMasterIrqBit(info);
6134
6135 info->params.mode = oldmode;
6136
6137 } /* end of usc_loopback_frame() */
6138
6139 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6140 *
6141 * Arguments: info pointer to adapter info structure
6142 * Return Value: None
6143 */
6144 static void usc_set_sync_mode( struct mgsl_struct *info )
6145 {
6146 usc_loopback_frame( info );
6147 usc_set_sdlc_mode( info );
6148
6149 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6150 /* Enable INTEN (Port 6, Bit12) */
6151 /* This connects the IRQ request signal to the ISA bus */
6152 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6153 }
6154
6155 usc_enable_aux_clock(info, info->params.clock_speed);
6156
6157 if (info->params.loopback)
6158 usc_enable_loopback(info,1);
6159
6160 } /* end of mgsl_set_sync_mode() */
6161
6162 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6163 *
6164 * Arguments: info pointer to device instance data
6165 * Return Value: None
6166 */
6167 static void usc_set_txidle( struct mgsl_struct *info )
6168 {
6169 u16 usc_idle_mode = IDLEMODE_FLAGS;
6170
6171 /* Map API idle mode to USC register bits */
6172
6173 switch( info->idle_mode ){
6174 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6175 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6176 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6177 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6178 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6179 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6180 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6181 }
6182
6183 info->usc_idle_mode = usc_idle_mode;
6184 //usc_OutReg(info, TCSR, usc_idle_mode);
6185 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6186 info->tcsr_value += usc_idle_mode;
6187 usc_OutReg(info, TCSR, info->tcsr_value);
6188
6189 /*
6190 * if SyncLink WAN adapter is running in external sync mode, the
6191 * transmitter has been set to Monosync in order to try to mimic
6192 * a true raw outbound bit stream. Monosync still sends an open/close
6193 * sync char at the start/end of a frame. Try to match those sync
6194 * patterns to the idle mode set here
6195 */
6196 if ( info->params.mode == MGSL_MODE_RAW ) {
6197 unsigned char syncpat = 0;
6198 switch( info->idle_mode ) {
6199 case HDLC_TXIDLE_FLAGS:
6200 syncpat = 0x7e;
6201 break;
6202 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6203 syncpat = 0x55;
6204 break;
6205 case HDLC_TXIDLE_ZEROS:
6206 case HDLC_TXIDLE_SPACE:
6207 syncpat = 0x00;
6208 break;
6209 case HDLC_TXIDLE_ONES:
6210 case HDLC_TXIDLE_MARK:
6211 syncpat = 0xff;
6212 break;
6213 case HDLC_TXIDLE_ALT_MARK_SPACE:
6214 syncpat = 0xaa;
6215 break;
6216 }
6217
6218 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6219 }
6220
6221 } /* end of usc_set_txidle() */
6222
6223 /* usc_get_serial_signals()
6224 *
6225 * Query the adapter for the state of the V24 status (input) signals.
6226 *
6227 * Arguments: info pointer to device instance data
6228 * Return Value: None
6229 */
6230 static void usc_get_serial_signals( struct mgsl_struct *info )
6231 {
6232 u16 status;
6233
6234 /* clear all serial signals except DTR and RTS */
6235 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6236
6237 /* Read the Misc Interrupt status Register (MISR) to get */
6238 /* the V24 status signals. */
6239
6240 status = usc_InReg( info, MISR );
6241
6242 /* set serial signal bits to reflect MISR */
6243
6244 if ( status & MISCSTATUS_CTS )
6245 info->serial_signals |= SerialSignal_CTS;
6246
6247 if ( status & MISCSTATUS_DCD )
6248 info->serial_signals |= SerialSignal_DCD;
6249
6250 if ( status & MISCSTATUS_RI )
6251 info->serial_signals |= SerialSignal_RI;
6252
6253 if ( status & MISCSTATUS_DSR )
6254 info->serial_signals |= SerialSignal_DSR;
6255
6256 } /* end of usc_get_serial_signals() */
6257
6258 /* usc_set_serial_signals()
6259 *
6260 * Set the state of DTR and RTS based on contents of
6261 * serial_signals member of device extension.
6262 *
6263 * Arguments: info pointer to device instance data
6264 * Return Value: None
6265 */
6266 static void usc_set_serial_signals( struct mgsl_struct *info )
6267 {
6268 u16 Control;
6269 unsigned char V24Out = info->serial_signals;
6270
6271 /* get the current value of the Port Control Register (PCR) */
6272
6273 Control = usc_InReg( info, PCR );
6274
6275 if ( V24Out & SerialSignal_RTS )
6276 Control &= ~(BIT6);
6277 else
6278 Control |= BIT6;
6279
6280 if ( V24Out & SerialSignal_DTR )
6281 Control &= ~(BIT4);
6282 else
6283 Control |= BIT4;
6284
6285 usc_OutReg( info, PCR, Control );
6286
6287 } /* end of usc_set_serial_signals() */
6288
6289 /* usc_enable_async_clock()
6290 *
6291 * Enable the async clock at the specified frequency.
6292 *
6293 * Arguments: info pointer to device instance data
6294 * data_rate data rate of clock in bps
6295 * 0 disables the AUX clock.
6296 * Return Value: None
6297 */
6298 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6299 {
6300 if ( data_rate ) {
6301 /*
6302 * Clock mode Control Register (CMCR)
6303 *
6304 * <15..14> 00 counter 1 Disabled
6305 * <13..12> 00 counter 0 Disabled
6306 * <11..10> 11 BRG1 Input is TxC Pin
6307 * <9..8> 11 BRG0 Input is TxC Pin
6308 * <7..6> 01 DPLL Input is BRG1 Output
6309 * <5..3> 100 TxCLK comes from BRG0
6310 * <2..0> 100 RxCLK comes from BRG0
6311 *
6312 * 0000 1111 0110 0100 = 0x0f64
6313 */
6314
6315 usc_OutReg( info, CMCR, 0x0f64 );
6316
6317
6318 /*
6319 * Write 16-bit Time Constant for BRG0
6320 * Time Constant = (ClkSpeed / data_rate) - 1
6321 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6322 */
6323
6324 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6325 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6326 else
6327 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6328
6329
6330 /*
6331 * Hardware Configuration Register (HCR)
6332 * Clear Bit 1, BRG0 mode = Continuous
6333 * Set Bit 0 to enable BRG0.
6334 */
6335
6336 usc_OutReg( info, HCR,
6337 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6338
6339
6340 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6341
6342 usc_OutReg( info, IOCR,
6343 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6344 } else {
6345 /* data rate == 0 so turn off BRG0 */
6346 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6347 }
6348
6349 } /* end of usc_enable_async_clock() */
6350
6351 /*
6352 * Buffer Structures:
6353 *
6354 * Normal memory access uses virtual addresses that can make discontiguous
6355 * physical memory pages appear to be contiguous in the virtual address
6356 * space (the processors memory mapping handles the conversions).
6357 *
6358 * DMA transfers require physically contiguous memory. This is because
6359 * the DMA system controller and DMA bus masters deal with memory using
6360 * only physical addresses.
6361 *
6362 * This causes a problem under Windows NT when large DMA buffers are
6363 * needed. Fragmentation of the nonpaged pool prevents allocations of
6364 * physically contiguous buffers larger than the PAGE_SIZE.
6365 *
6366 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6367 * allows DMA transfers to physically discontiguous buffers. Information
6368 * about each data transfer buffer is contained in a memory structure
6369 * called a 'buffer entry'. A list of buffer entries is maintained
6370 * to track and control the use of the data transfer buffers.
6371 *
6372 * To support this strategy we will allocate sufficient PAGE_SIZE
6373 * contiguous memory buffers to allow for the total required buffer
6374 * space.
6375 *
6376 * The 16C32 accesses the list of buffer entries using Bus Master
6377 * DMA. Control information is read from the buffer entries by the
6378 * 16C32 to control data transfers. status information is written to
6379 * the buffer entries by the 16C32 to indicate the status of completed
6380 * transfers.
6381 *
6382 * The CPU writes control information to the buffer entries to control
6383 * the 16C32 and reads status information from the buffer entries to
6384 * determine information about received and transmitted frames.
6385 *
6386 * Because the CPU and 16C32 (adapter) both need simultaneous access
6387 * to the buffer entries, the buffer entry memory is allocated with
6388 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6389 * entry list to PAGE_SIZE.
6390 *
6391 * The actual data buffers on the other hand will only be accessed
6392 * by the CPU or the adapter but not by both simultaneously. This allows
6393 * Scatter/Gather packet based DMA procedures for using physically
6394 * discontiguous pages.
6395 */
6396
6397 /*
6398 * mgsl_reset_tx_dma_buffers()
6399 *
6400 * Set the count for all transmit buffers to 0 to indicate the
6401 * buffer is available for use and set the current buffer to the
6402 * first buffer. This effectively makes all buffers free and
6403 * discards any data in buffers.
6404 *
6405 * Arguments: info pointer to device instance data
6406 * Return Value: None
6407 */
6408 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6409 {
6410 unsigned int i;
6411
6412 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6413 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6414 }
6415
6416 info->current_tx_buffer = 0;
6417 info->start_tx_dma_buffer = 0;
6418 info->tx_dma_buffers_used = 0;
6419
6420 info->get_tx_holding_index = 0;
6421 info->put_tx_holding_index = 0;
6422 info->tx_holding_count = 0;
6423
6424 } /* end of mgsl_reset_tx_dma_buffers() */
6425
6426 /*
6427 * num_free_tx_dma_buffers()
6428 *
6429 * returns the number of free tx dma buffers available
6430 *
6431 * Arguments: info pointer to device instance data
6432 * Return Value: number of free tx dma buffers
6433 */
6434 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6435 {
6436 return info->tx_buffer_count - info->tx_dma_buffers_used;
6437 }
6438
6439 /*
6440 * mgsl_reset_rx_dma_buffers()
6441 *
6442 * Set the count for all receive buffers to DMABUFFERSIZE
6443 * and set the current buffer to the first buffer. This effectively
6444 * makes all buffers free and discards any data in buffers.
6445 *
6446 * Arguments: info pointer to device instance data
6447 * Return Value: None
6448 */
6449 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6450 {
6451 unsigned int i;
6452
6453 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6454 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6455 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6456 // info->rx_buffer_list[i].status = 0;
6457 }
6458
6459 info->current_rx_buffer = 0;
6460
6461 } /* end of mgsl_reset_rx_dma_buffers() */
6462
6463 /*
6464 * mgsl_free_rx_frame_buffers()
6465 *
6466 * Free the receive buffers used by a received SDLC
6467 * frame such that the buffers can be reused.
6468 *
6469 * Arguments:
6470 *
6471 * info pointer to device instance data
6472 * StartIndex index of 1st receive buffer of frame
6473 * EndIndex index of last receive buffer of frame
6474 *
6475 * Return Value: None
6476 */
6477 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6478 {
6479 bool Done = false;
6480 DMABUFFERENTRY *pBufEntry;
6481 unsigned int Index;
6482
6483 /* Starting with 1st buffer entry of the frame clear the status */
6484 /* field and set the count field to DMA Buffer Size. */
6485
6486 Index = StartIndex;
6487
6488 while( !Done ) {
6489 pBufEntry = &(info->rx_buffer_list[Index]);
6490
6491 if ( Index == EndIndex ) {
6492 /* This is the last buffer of the frame! */
6493 Done = true;
6494 }
6495
6496 /* reset current buffer for reuse */
6497 // pBufEntry->status = 0;
6498 // pBufEntry->count = DMABUFFERSIZE;
6499 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6500
6501 /* advance to next buffer entry in linked list */
6502 Index++;
6503 if ( Index == info->rx_buffer_count )
6504 Index = 0;
6505 }
6506
6507 /* set current buffer to next buffer after last buffer of frame */
6508 info->current_rx_buffer = Index;
6509
6510 } /* end of free_rx_frame_buffers() */
6511
6512 /* mgsl_get_rx_frame()
6513 *
6514 * This function attempts to return a received SDLC frame from the
6515 * receive DMA buffers. Only frames received without errors are returned.
6516 *
6517 * Arguments: info pointer to device extension
6518 * Return Value: true if frame returned, otherwise false
6519 */
6520 static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6521 {
6522 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6523 unsigned short status;
6524 DMABUFFERENTRY *pBufEntry;
6525 unsigned int framesize = 0;
6526 bool ReturnCode = false;
6527 unsigned long flags;
6528 struct tty_struct *tty = info->port.tty;
6529 bool return_frame = false;
6530
6531 /*
6532 * current_rx_buffer points to the 1st buffer of the next available
6533 * receive frame. To find the last buffer of the frame look for
6534 * a non-zero status field in the buffer entries. (The status
6535 * field is set by the 16C32 after completing a receive frame.
6536 */
6537
6538 StartIndex = EndIndex = info->current_rx_buffer;
6539
6540 while( !info->rx_buffer_list[EndIndex].status ) {
6541 /*
6542 * If the count field of the buffer entry is non-zero then
6543 * this buffer has not been used. (The 16C32 clears the count
6544 * field when it starts using the buffer.) If an unused buffer
6545 * is encountered then there are no frames available.
6546 */
6547
6548 if ( info->rx_buffer_list[EndIndex].count )
6549 goto Cleanup;
6550
6551 /* advance to next buffer entry in linked list */
6552 EndIndex++;
6553 if ( EndIndex == info->rx_buffer_count )
6554 EndIndex = 0;
6555
6556 /* if entire list searched then no frame available */
6557 if ( EndIndex == StartIndex ) {
6558 /* If this occurs then something bad happened,
6559 * all buffers have been 'used' but none mark
6560 * the end of a frame. Reset buffers and receiver.
6561 */
6562
6563 if ( info->rx_enabled ){
6564 spin_lock_irqsave(&info->irq_spinlock,flags);
6565 usc_start_receiver(info);
6566 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6567 }
6568 goto Cleanup;
6569 }
6570 }
6571
6572
6573 /* check status of receive frame */
6574
6575 status = info->rx_buffer_list[EndIndex].status;
6576
6577 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6578 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6579 if ( status & RXSTATUS_SHORT_FRAME )
6580 info->icount.rxshort++;
6581 else if ( status & RXSTATUS_ABORT )
6582 info->icount.rxabort++;
6583 else if ( status & RXSTATUS_OVERRUN )
6584 info->icount.rxover++;
6585 else {
6586 info->icount.rxcrc++;
6587 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6588 return_frame = true;
6589 }
6590 framesize = 0;
6591 #if SYNCLINK_GENERIC_HDLC
6592 {
6593 info->netdev->stats.rx_errors++;
6594 info->netdev->stats.rx_frame_errors++;
6595 }
6596 #endif
6597 } else
6598 return_frame = true;
6599
6600 if ( return_frame ) {
6601 /* receive frame has no errors, get frame size.
6602 * The frame size is the starting value of the RCC (which was
6603 * set to 0xffff) minus the ending value of the RCC (decremented
6604 * once for each receive character) minus 2 for the 16-bit CRC.
6605 */
6606
6607 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6608
6609 /* adjust frame size for CRC if any */
6610 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6611 framesize -= 2;
6612 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6613 framesize -= 4;
6614 }
6615
6616 if ( debug_level >= DEBUG_LEVEL_BH )
6617 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6618 __FILE__,__LINE__,info->device_name,status,framesize);
6619
6620 if ( debug_level >= DEBUG_LEVEL_DATA )
6621 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6622 min_t(int, framesize, DMABUFFERSIZE),0);
6623
6624 if (framesize) {
6625 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6626 ((framesize+1) > info->max_frame_size) ) ||
6627 (framesize > info->max_frame_size) )
6628 info->icount.rxlong++;
6629 else {
6630 /* copy dma buffer(s) to contiguous intermediate buffer */
6631 int copy_count = framesize;
6632 int index = StartIndex;
6633 unsigned char *ptmp = info->intermediate_rxbuffer;
6634
6635 if ( !(status & RXSTATUS_CRC_ERROR))
6636 info->icount.rxok++;
6637
6638 while(copy_count) {
6639 int partial_count;
6640 if ( copy_count > DMABUFFERSIZE )
6641 partial_count = DMABUFFERSIZE;
6642 else
6643 partial_count = copy_count;
6644
6645 pBufEntry = &(info->rx_buffer_list[index]);
6646 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6647 ptmp += partial_count;
6648 copy_count -= partial_count;
6649
6650 if ( ++index == info->rx_buffer_count )
6651 index = 0;
6652 }
6653
6654 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6655 ++framesize;
6656 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6657 RX_CRC_ERROR :
6658 RX_OK);
6659
6660 if ( debug_level >= DEBUG_LEVEL_DATA )
6661 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6662 __FILE__,__LINE__,info->device_name,
6663 *ptmp);
6664 }
6665
6666 #if SYNCLINK_GENERIC_HDLC
6667 if (info->netcount)
6668 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6669 else
6670 #endif
6671 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6672 }
6673 }
6674 /* Free the buffers used by this frame. */
6675 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6676
6677 ReturnCode = true;
6678
6679 Cleanup:
6680
6681 if ( info->rx_enabled && info->rx_overflow ) {
6682 /* The receiver needs to restarted because of
6683 * a receive overflow (buffer or FIFO). If the
6684 * receive buffers are now empty, then restart receiver.
6685 */
6686
6687 if ( !info->rx_buffer_list[EndIndex].status &&
6688 info->rx_buffer_list[EndIndex].count ) {
6689 spin_lock_irqsave(&info->irq_spinlock,flags);
6690 usc_start_receiver(info);
6691 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6692 }
6693 }
6694
6695 return ReturnCode;
6696
6697 } /* end of mgsl_get_rx_frame() */
6698
6699 /* mgsl_get_raw_rx_frame()
6700 *
6701 * This function attempts to return a received frame from the
6702 * receive DMA buffers when running in external loop mode. In this mode,
6703 * we will return at most one DMABUFFERSIZE frame to the application.
6704 * The USC receiver is triggering off of DCD going active to start a new
6705 * frame, and DCD going inactive to terminate the frame (similar to
6706 * processing a closing flag character).
6707 *
6708 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6709 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6710 * status field and the RCC field will indicate the length of the
6711 * entire received frame. We take this RCC field and get the modulus
6712 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6713 * last Rx DMA buffer and return that last portion of the frame.
6714 *
6715 * Arguments: info pointer to device extension
6716 * Return Value: true if frame returned, otherwise false
6717 */
6718 static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6719 {
6720 unsigned int CurrentIndex, NextIndex;
6721 unsigned short status;
6722 DMABUFFERENTRY *pBufEntry;
6723 unsigned int framesize = 0;
6724 bool ReturnCode = false;
6725 unsigned long flags;
6726 struct tty_struct *tty = info->port.tty;
6727
6728 /*
6729 * current_rx_buffer points to the 1st buffer of the next available
6730 * receive frame. The status field is set by the 16C32 after
6731 * completing a receive frame. If the status field of this buffer
6732 * is zero, either the USC is still filling this buffer or this
6733 * is one of a series of buffers making up a received frame.
6734 *
6735 * If the count field of this buffer is zero, the USC is either
6736 * using this buffer or has used this buffer. Look at the count
6737 * field of the next buffer. If that next buffer's count is
6738 * non-zero, the USC is still actively using the current buffer.
6739 * Otherwise, if the next buffer's count field is zero, the
6740 * current buffer is complete and the USC is using the next
6741 * buffer.
6742 */
6743 CurrentIndex = NextIndex = info->current_rx_buffer;
6744 ++NextIndex;
6745 if ( NextIndex == info->rx_buffer_count )
6746 NextIndex = 0;
6747
6748 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6749 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6750 info->rx_buffer_list[NextIndex].count == 0)) {
6751 /*
6752 * Either the status field of this dma buffer is non-zero
6753 * (indicating the last buffer of a receive frame) or the next
6754 * buffer is marked as in use -- implying this buffer is complete
6755 * and an intermediate buffer for this received frame.
6756 */
6757
6758 status = info->rx_buffer_list[CurrentIndex].status;
6759
6760 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6761 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6762 if ( status & RXSTATUS_SHORT_FRAME )
6763 info->icount.rxshort++;
6764 else if ( status & RXSTATUS_ABORT )
6765 info->icount.rxabort++;
6766 else if ( status & RXSTATUS_OVERRUN )
6767 info->icount.rxover++;
6768 else
6769 info->icount.rxcrc++;
6770 framesize = 0;
6771 } else {
6772 /*
6773 * A receive frame is available, get frame size and status.
6774 *
6775 * The frame size is the starting value of the RCC (which was
6776 * set to 0xffff) minus the ending value of the RCC (decremented
6777 * once for each receive character) minus 2 or 4 for the 16-bit
6778 * or 32-bit CRC.
6779 *
6780 * If the status field is zero, this is an intermediate buffer.
6781 * It's size is 4K.
6782 *
6783 * If the DMA Buffer Entry's Status field is non-zero, the
6784 * receive operation completed normally (ie: DCD dropped). The
6785 * RCC field is valid and holds the received frame size.
6786 * It is possible that the RCC field will be zero on a DMA buffer
6787 * entry with a non-zero status. This can occur if the total
6788 * frame size (number of bytes between the time DCD goes active
6789 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6790 * case the 16C32 has underrun on the RCC count and appears to
6791 * stop updating this counter to let us know the actual received
6792 * frame size. If this happens (non-zero status and zero RCC),
6793 * simply return the entire RxDMA Buffer
6794 */
6795 if ( status ) {
6796 /*
6797 * In the event that the final RxDMA Buffer is
6798 * terminated with a non-zero status and the RCC
6799 * field is zero, we interpret this as the RCC
6800 * having underflowed (received frame > 65535 bytes).
6801 *
6802 * Signal the event to the user by passing back
6803 * a status of RxStatus_CrcError returning the full
6804 * buffer and let the app figure out what data is
6805 * actually valid
6806 */
6807 if ( info->rx_buffer_list[CurrentIndex].rcc )
6808 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6809 else
6810 framesize = DMABUFFERSIZE;
6811 }
6812 else
6813 framesize = DMABUFFERSIZE;
6814 }
6815
6816 if ( framesize > DMABUFFERSIZE ) {
6817 /*
6818 * if running in raw sync mode, ISR handler for
6819 * End Of Buffer events terminates all buffers at 4K.
6820 * If this frame size is said to be >4K, get the
6821 * actual number of bytes of the frame in this buffer.
6822 */
6823 framesize = framesize % DMABUFFERSIZE;
6824 }
6825
6826
6827 if ( debug_level >= DEBUG_LEVEL_BH )
6828 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6829 __FILE__,__LINE__,info->device_name,status,framesize);
6830
6831 if ( debug_level >= DEBUG_LEVEL_DATA )
6832 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6833 min_t(int, framesize, DMABUFFERSIZE),0);
6834
6835 if (framesize) {
6836 /* copy dma buffer(s) to contiguous intermediate buffer */
6837 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6838
6839 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6840 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6841 info->icount.rxok++;
6842
6843 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6844 }
6845
6846 /* Free the buffers used by this frame. */
6847 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6848
6849 ReturnCode = true;
6850 }
6851
6852
6853 if ( info->rx_enabled && info->rx_overflow ) {
6854 /* The receiver needs to restarted because of
6855 * a receive overflow (buffer or FIFO). If the
6856 * receive buffers are now empty, then restart receiver.
6857 */
6858
6859 if ( !info->rx_buffer_list[CurrentIndex].status &&
6860 info->rx_buffer_list[CurrentIndex].count ) {
6861 spin_lock_irqsave(&info->irq_spinlock,flags);
6862 usc_start_receiver(info);
6863 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6864 }
6865 }
6866
6867 return ReturnCode;
6868
6869 } /* end of mgsl_get_raw_rx_frame() */
6870
6871 /* mgsl_load_tx_dma_buffer()
6872 *
6873 * Load the transmit DMA buffer with the specified data.
6874 *
6875 * Arguments:
6876 *
6877 * info pointer to device extension
6878 * Buffer pointer to buffer containing frame to load
6879 * BufferSize size in bytes of frame in Buffer
6880 *
6881 * Return Value: None
6882 */
6883 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6884 const char *Buffer, unsigned int BufferSize)
6885 {
6886 unsigned short Copycount;
6887 unsigned int i = 0;
6888 DMABUFFERENTRY *pBufEntry;
6889
6890 if ( debug_level >= DEBUG_LEVEL_DATA )
6891 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6892
6893 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6894 /* set CMR:13 to start transmit when
6895 * next GoAhead (abort) is received
6896 */
6897 info->cmr_value |= BIT13;
6898 }
6899
6900 /* begin loading the frame in the next available tx dma
6901 * buffer, remember it's starting location for setting
6902 * up tx dma operation
6903 */
6904 i = info->current_tx_buffer;
6905 info->start_tx_dma_buffer = i;
6906
6907 /* Setup the status and RCC (Frame Size) fields of the 1st */
6908 /* buffer entry in the transmit DMA buffer list. */
6909
6910 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6911 info->tx_buffer_list[i].rcc = BufferSize;
6912 info->tx_buffer_list[i].count = BufferSize;
6913
6914 /* Copy frame data from 1st source buffer to the DMA buffers. */
6915 /* The frame data may span multiple DMA buffers. */
6916
6917 while( BufferSize ){
6918 /* Get a pointer to next DMA buffer entry. */
6919 pBufEntry = &info->tx_buffer_list[i++];
6920
6921 if ( i == info->tx_buffer_count )
6922 i=0;
6923
6924 /* Calculate the number of bytes that can be copied from */
6925 /* the source buffer to this DMA buffer. */
6926 if ( BufferSize > DMABUFFERSIZE )
6927 Copycount = DMABUFFERSIZE;
6928 else
6929 Copycount = BufferSize;
6930
6931 /* Actually copy data from source buffer to DMA buffer. */
6932 /* Also set the data count for this individual DMA buffer. */
6933 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6934 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6935 else
6936 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6937
6938 pBufEntry->count = Copycount;
6939
6940 /* Advance source pointer and reduce remaining data count. */
6941 Buffer += Copycount;
6942 BufferSize -= Copycount;
6943
6944 ++info->tx_dma_buffers_used;
6945 }
6946
6947 /* remember next available tx dma buffer */
6948 info->current_tx_buffer = i;
6949
6950 } /* end of mgsl_load_tx_dma_buffer() */
6951
6952 /*
6953 * mgsl_register_test()
6954 *
6955 * Performs a register test of the 16C32.
6956 *
6957 * Arguments: info pointer to device instance data
6958 * Return Value: true if test passed, otherwise false
6959 */
6960 static bool mgsl_register_test( struct mgsl_struct *info )
6961 {
6962 static unsigned short BitPatterns[] =
6963 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6964 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6965 unsigned int i;
6966 bool rc = true;
6967 unsigned long flags;
6968
6969 spin_lock_irqsave(&info->irq_spinlock,flags);
6970 usc_reset(info);
6971
6972 /* Verify the reset state of some registers. */
6973
6974 if ( (usc_InReg( info, SICR ) != 0) ||
6975 (usc_InReg( info, IVR ) != 0) ||
6976 (usc_InDmaReg( info, DIVR ) != 0) ){
6977 rc = false;
6978 }
6979
6980 if ( rc ){
6981 /* Write bit patterns to various registers but do it out of */
6982 /* sync, then read back and verify values. */
6983
6984 for ( i = 0 ; i < Patterncount ; i++ ) {
6985 usc_OutReg( info, TC0R, BitPatterns[i] );
6986 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6987 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6988 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6989 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6990 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6991
6992 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6993 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6994 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6995 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6996 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6997 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6998 rc = false;
6999 break;
7000 }
7001 }
7002 }
7003
7004 usc_reset(info);
7005 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7006
7007 return rc;
7008
7009 } /* end of mgsl_register_test() */
7010
7011 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7012 *
7013 * Arguments: info pointer to device instance data
7014 * Return Value: true if test passed, otherwise false
7015 */
7016 static bool mgsl_irq_test( struct mgsl_struct *info )
7017 {
7018 unsigned long EndTime;
7019 unsigned long flags;
7020
7021 spin_lock_irqsave(&info->irq_spinlock,flags);
7022 usc_reset(info);
7023
7024 /*
7025 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7026 * The ISR sets irq_occurred to true.
7027 */
7028
7029 info->irq_occurred = false;
7030
7031 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7032 /* Enable INTEN (Port 6, Bit12) */
7033 /* This connects the IRQ request signal to the ISA bus */
7034 /* on the ISA adapter. This has no effect for the PCI adapter */
7035 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7036
7037 usc_EnableMasterIrqBit(info);
7038 usc_EnableInterrupts(info, IO_PIN);
7039 usc_ClearIrqPendingBits(info, IO_PIN);
7040
7041 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7042 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7043
7044 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7045
7046 EndTime=100;
7047 while( EndTime-- && !info->irq_occurred ) {
7048 msleep_interruptible(10);
7049 }
7050
7051 spin_lock_irqsave(&info->irq_spinlock,flags);
7052 usc_reset(info);
7053 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7054
7055 return info->irq_occurred;
7056
7057 } /* end of mgsl_irq_test() */
7058
7059 /* mgsl_dma_test()
7060 *
7061 * Perform a DMA test of the 16C32. A small frame is
7062 * transmitted via DMA from a transmit buffer to a receive buffer
7063 * using single buffer DMA mode.
7064 *
7065 * Arguments: info pointer to device instance data
7066 * Return Value: true if test passed, otherwise false
7067 */
7068 static bool mgsl_dma_test( struct mgsl_struct *info )
7069 {
7070 unsigned short FifoLevel;
7071 unsigned long phys_addr;
7072 unsigned int FrameSize;
7073 unsigned int i;
7074 char *TmpPtr;
7075 bool rc = true;
7076 unsigned short status=0;
7077 unsigned long EndTime;
7078 unsigned long flags;
7079 MGSL_PARAMS tmp_params;
7080
7081 /* save current port options */
7082 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7083 /* load default port options */
7084 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7085
7086 #define TESTFRAMESIZE 40
7087
7088 spin_lock_irqsave(&info->irq_spinlock,flags);
7089
7090 /* setup 16C32 for SDLC DMA transfer mode */
7091
7092 usc_reset(info);
7093 usc_set_sdlc_mode(info);
7094 usc_enable_loopback(info,1);
7095
7096 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7097 * field of the buffer entry after fetching buffer address. This
7098 * way we can detect a DMA failure for a DMA read (which should be
7099 * non-destructive to system memory) before we try and write to
7100 * memory (where a failure could corrupt system memory).
7101 */
7102
7103 /* Receive DMA mode Register (RDMR)
7104 *
7105 * <15..14> 11 DMA mode = Linked List Buffer mode
7106 * <13> 1 RSBinA/L = store Rx status Block in List entry
7107 * <12> 0 1 = Clear count of List Entry after fetching
7108 * <11..10> 00 Address mode = Increment
7109 * <9> 1 Terminate Buffer on RxBound
7110 * <8> 0 Bus Width = 16bits
7111 * <7..0> ? status Bits (write as 0s)
7112 *
7113 * 1110 0010 0000 0000 = 0xe200
7114 */
7115
7116 usc_OutDmaReg( info, RDMR, 0xe200 );
7117
7118 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7119
7120
7121 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7122
7123 FrameSize = TESTFRAMESIZE;
7124
7125 /* setup 1st transmit buffer entry: */
7126 /* with frame size and transmit control word */
7127
7128 info->tx_buffer_list[0].count = FrameSize;
7129 info->tx_buffer_list[0].rcc = FrameSize;
7130 info->tx_buffer_list[0].status = 0x4000;
7131
7132 /* build a transmit frame in 1st transmit DMA buffer */
7133
7134 TmpPtr = info->tx_buffer_list[0].virt_addr;
7135 for (i = 0; i < FrameSize; i++ )
7136 *TmpPtr++ = i;
7137
7138 /* setup 1st receive buffer entry: */
7139 /* clear status, set max receive buffer size */
7140
7141 info->rx_buffer_list[0].status = 0;
7142 info->rx_buffer_list[0].count = FrameSize + 4;
7143
7144 /* zero out the 1st receive buffer */
7145
7146 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7147
7148 /* Set count field of next buffer entries to prevent */
7149 /* 16C32 from using buffers after the 1st one. */
7150
7151 info->tx_buffer_list[1].count = 0;
7152 info->rx_buffer_list[1].count = 0;
7153
7154
7155 /***************************/
7156 /* Program 16C32 receiver. */
7157 /***************************/
7158
7159 spin_lock_irqsave(&info->irq_spinlock,flags);
7160
7161 /* setup DMA transfers */
7162 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7163
7164 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7165 phys_addr = info->rx_buffer_list[0].phys_entry;
7166 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7167 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7168
7169 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7170 usc_InDmaReg( info, RDMR );
7171 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7172
7173 /* Enable Receiver (RMR <1..0> = 10) */
7174 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7175
7176 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7177
7178
7179 /*************************************************************/
7180 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7181 /*************************************************************/
7182
7183 /* Wait 100ms for interrupt. */
7184 EndTime = jiffies + msecs_to_jiffies(100);
7185
7186 for(;;) {
7187 if (time_after(jiffies, EndTime)) {
7188 rc = false;
7189 break;
7190 }
7191
7192 spin_lock_irqsave(&info->irq_spinlock,flags);
7193 status = usc_InDmaReg( info, RDMR );
7194 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7195
7196 if ( !(status & BIT4) && (status & BIT5) ) {
7197 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7198 /* BUSY (BIT 5) is active (channel still active). */
7199 /* This means the buffer entry read has completed. */
7200 break;
7201 }
7202 }
7203
7204
7205 /******************************/
7206 /* Program 16C32 transmitter. */
7207 /******************************/
7208
7209 spin_lock_irqsave(&info->irq_spinlock,flags);
7210
7211 /* Program the Transmit Character Length Register (TCLR) */
7212 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7213
7214 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7215 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7216
7217 /* Program the address of the 1st DMA Buffer Entry in linked list */
7218
7219 phys_addr = info->tx_buffer_list[0].phys_entry;
7220 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7221 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7222
7223 /* unlatch Tx status bits, and start transmit channel. */
7224
7225 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7226 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7227
7228 /* wait for DMA controller to fill transmit FIFO */
7229
7230 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7231
7232 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7233
7234
7235 /**********************************/
7236 /* WAIT FOR TRANSMIT FIFO TO FILL */
7237 /**********************************/
7238
7239 /* Wait 100ms */
7240 EndTime = jiffies + msecs_to_jiffies(100);
7241
7242 for(;;) {
7243 if (time_after(jiffies, EndTime)) {
7244 rc = false;
7245 break;
7246 }
7247
7248 spin_lock_irqsave(&info->irq_spinlock,flags);
7249 FifoLevel = usc_InReg(info, TICR) >> 8;
7250 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7251
7252 if ( FifoLevel < 16 )
7253 break;
7254 else
7255 if ( FrameSize < 32 ) {
7256 /* This frame is smaller than the entire transmit FIFO */
7257 /* so wait for the entire frame to be loaded. */
7258 if ( FifoLevel <= (32 - FrameSize) )
7259 break;
7260 }
7261 }
7262
7263
7264 if ( rc )
7265 {
7266 /* Enable 16C32 transmitter. */
7267
7268 spin_lock_irqsave(&info->irq_spinlock,flags);
7269
7270 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7271 usc_TCmd( info, TCmd_SendFrame );
7272 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7273
7274 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7275
7276
7277 /******************************/
7278 /* WAIT FOR TRANSMIT COMPLETE */
7279 /******************************/
7280
7281 /* Wait 100ms */
7282 EndTime = jiffies + msecs_to_jiffies(100);
7283
7284 /* While timer not expired wait for transmit complete */
7285
7286 spin_lock_irqsave(&info->irq_spinlock,flags);
7287 status = usc_InReg( info, TCSR );
7288 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7289
7290 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7291 if (time_after(jiffies, EndTime)) {
7292 rc = false;
7293 break;
7294 }
7295
7296 spin_lock_irqsave(&info->irq_spinlock,flags);
7297 status = usc_InReg( info, TCSR );
7298 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7299 }
7300 }
7301
7302
7303 if ( rc ){
7304 /* CHECK FOR TRANSMIT ERRORS */
7305 if ( status & (BIT5 + BIT1) )
7306 rc = false;
7307 }
7308
7309 if ( rc ) {
7310 /* WAIT FOR RECEIVE COMPLETE */
7311
7312 /* Wait 100ms */
7313 EndTime = jiffies + msecs_to_jiffies(100);
7314
7315 /* Wait for 16C32 to write receive status to buffer entry. */
7316 status=info->rx_buffer_list[0].status;
7317 while ( status == 0 ) {
7318 if (time_after(jiffies, EndTime)) {
7319 rc = false;
7320 break;
7321 }
7322 status=info->rx_buffer_list[0].status;
7323 }
7324 }
7325
7326
7327 if ( rc ) {
7328 /* CHECK FOR RECEIVE ERRORS */
7329 status = info->rx_buffer_list[0].status;
7330
7331 if ( status & (BIT8 + BIT3 + BIT1) ) {
7332 /* receive error has occurred */
7333 rc = false;
7334 } else {
7335 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7336 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7337 rc = false;
7338 }
7339 }
7340 }
7341
7342 spin_lock_irqsave(&info->irq_spinlock,flags);
7343 usc_reset( info );
7344 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7345
7346 /* restore current port options */
7347 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7348
7349 return rc;
7350
7351 } /* end of mgsl_dma_test() */
7352
7353 /* mgsl_adapter_test()
7354 *
7355 * Perform the register, IRQ, and DMA tests for the 16C32.
7356 *
7357 * Arguments: info pointer to device instance data
7358 * Return Value: 0 if success, otherwise -ENODEV
7359 */
7360 static int mgsl_adapter_test( struct mgsl_struct *info )
7361 {
7362 if ( debug_level >= DEBUG_LEVEL_INFO )
7363 printk( "%s(%d):Testing device %s\n",
7364 __FILE__,__LINE__,info->device_name );
7365
7366 if ( !mgsl_register_test( info ) ) {
7367 info->init_error = DiagStatus_AddressFailure;
7368 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7369 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7370 return -ENODEV;
7371 }
7372
7373 if ( !mgsl_irq_test( info ) ) {
7374 info->init_error = DiagStatus_IrqFailure;
7375 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7376 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7377 return -ENODEV;
7378 }
7379
7380 if ( !mgsl_dma_test( info ) ) {
7381 info->init_error = DiagStatus_DmaFailure;
7382 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7383 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7384 return -ENODEV;
7385 }
7386
7387 if ( debug_level >= DEBUG_LEVEL_INFO )
7388 printk( "%s(%d):device %s passed diagnostics\n",
7389 __FILE__,__LINE__,info->device_name );
7390
7391 return 0;
7392
7393 } /* end of mgsl_adapter_test() */
7394
7395 /* mgsl_memory_test()
7396 *
7397 * Test the shared memory on a PCI adapter.
7398 *
7399 * Arguments: info pointer to device instance data
7400 * Return Value: true if test passed, otherwise false
7401 */
7402 static bool mgsl_memory_test( struct mgsl_struct *info )
7403 {
7404 static unsigned long BitPatterns[] =
7405 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7406 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7407 unsigned long i;
7408 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7409 unsigned long * TestAddr;
7410
7411 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7412 return true;
7413
7414 TestAddr = (unsigned long *)info->memory_base;
7415
7416 /* Test data lines with test pattern at one location. */
7417
7418 for ( i = 0 ; i < Patterncount ; i++ ) {
7419 *TestAddr = BitPatterns[i];
7420 if ( *TestAddr != BitPatterns[i] )
7421 return false;
7422 }
7423
7424 /* Test address lines with incrementing pattern over */
7425 /* entire address range. */
7426
7427 for ( i = 0 ; i < TestLimit ; i++ ) {
7428 *TestAddr = i * 4;
7429 TestAddr++;
7430 }
7431
7432 TestAddr = (unsigned long *)info->memory_base;
7433
7434 for ( i = 0 ; i < TestLimit ; i++ ) {
7435 if ( *TestAddr != i * 4 )
7436 return false;
7437 TestAddr++;
7438 }
7439
7440 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7441
7442 return true;
7443
7444 } /* End Of mgsl_memory_test() */
7445
7446
7447 /* mgsl_load_pci_memory()
7448 *
7449 * Load a large block of data into the PCI shared memory.
7450 * Use this instead of memcpy() or memmove() to move data
7451 * into the PCI shared memory.
7452 *
7453 * Notes:
7454 *
7455 * This function prevents the PCI9050 interface chip from hogging
7456 * the adapter local bus, which can starve the 16C32 by preventing
7457 * 16C32 bus master cycles.
7458 *
7459 * The PCI9050 documentation says that the 9050 will always release
7460 * control of the local bus after completing the current read
7461 * or write operation.
7462 *
7463 * It appears that as long as the PCI9050 write FIFO is full, the
7464 * PCI9050 treats all of the writes as a single burst transaction
7465 * and will not release the bus. This causes DMA latency problems
7466 * at high speeds when copying large data blocks to the shared
7467 * memory.
7468 *
7469 * This function in effect, breaks the a large shared memory write
7470 * into multiple transations by interleaving a shared memory read
7471 * which will flush the write FIFO and 'complete' the write
7472 * transation. This allows any pending DMA request to gain control
7473 * of the local bus in a timely fasion.
7474 *
7475 * Arguments:
7476 *
7477 * TargetPtr pointer to target address in PCI shared memory
7478 * SourcePtr pointer to source buffer for data
7479 * count count in bytes of data to copy
7480 *
7481 * Return Value: None
7482 */
7483 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7484 unsigned short count )
7485 {
7486 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7487 #define PCI_LOAD_INTERVAL 64
7488
7489 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7490 unsigned short Index;
7491 unsigned long Dummy;
7492
7493 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7494 {
7495 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7496 Dummy = *((volatile unsigned long *)TargetPtr);
7497 TargetPtr += PCI_LOAD_INTERVAL;
7498 SourcePtr += PCI_LOAD_INTERVAL;
7499 }
7500
7501 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7502
7503 } /* End Of mgsl_load_pci_memory() */
7504
7505 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7506 {
7507 int i;
7508 int linecount;
7509 if (xmit)
7510 printk("%s tx data:\n",info->device_name);
7511 else
7512 printk("%s rx data:\n",info->device_name);
7513
7514 while(count) {
7515 if (count > 16)
7516 linecount = 16;
7517 else
7518 linecount = count;
7519
7520 for(i=0;i<linecount;i++)
7521 printk("%02X ",(unsigned char)data[i]);
7522 for(;i<17;i++)
7523 printk(" ");
7524 for(i=0;i<linecount;i++) {
7525 if (data[i]>=040 && data[i]<=0176)
7526 printk("%c",data[i]);
7527 else
7528 printk(".");
7529 }
7530 printk("\n");
7531
7532 data += linecount;
7533 count -= linecount;
7534 }
7535 } /* end of mgsl_trace_block() */
7536
7537 /* mgsl_tx_timeout()
7538 *
7539 * called when HDLC frame times out
7540 * update stats and do tx completion processing
7541 *
7542 * Arguments: context pointer to device instance data
7543 * Return Value: None
7544 */
7545 static void mgsl_tx_timeout(unsigned long context)
7546 {
7547 struct mgsl_struct *info = (struct mgsl_struct*)context;
7548 unsigned long flags;
7549
7550 if ( debug_level >= DEBUG_LEVEL_INFO )
7551 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7552 __FILE__,__LINE__,info->device_name);
7553 if(info->tx_active &&
7554 (info->params.mode == MGSL_MODE_HDLC ||
7555 info->params.mode == MGSL_MODE_RAW) ) {
7556 info->icount.txtimeout++;
7557 }
7558 spin_lock_irqsave(&info->irq_spinlock,flags);
7559 info->tx_active = false;
7560 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7561
7562 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7563 usc_loopmode_cancel_transmit( info );
7564
7565 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7566
7567 #if SYNCLINK_GENERIC_HDLC
7568 if (info->netcount)
7569 hdlcdev_tx_done(info);
7570 else
7571 #endif
7572 mgsl_bh_transmit(info);
7573
7574 } /* end of mgsl_tx_timeout() */
7575
7576 /* signal that there are no more frames to send, so that
7577 * line is 'released' by echoing RxD to TxD when current
7578 * transmission is complete (or immediately if no tx in progress).
7579 */
7580 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7581 {
7582 unsigned long flags;
7583
7584 spin_lock_irqsave(&info->irq_spinlock,flags);
7585 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7586 if (info->tx_active)
7587 info->loopmode_send_done_requested = true;
7588 else
7589 usc_loopmode_send_done(info);
7590 }
7591 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7592
7593 return 0;
7594 }
7595
7596 /* release the line by echoing RxD to TxD
7597 * upon completion of a transmit frame
7598 */
7599 static void usc_loopmode_send_done( struct mgsl_struct * info )
7600 {
7601 info->loopmode_send_done_requested = false;
7602 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7603 info->cmr_value &= ~BIT13;
7604 usc_OutReg(info, CMR, info->cmr_value);
7605 }
7606
7607 /* abort a transmit in progress while in HDLC LoopMode
7608 */
7609 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7610 {
7611 /* reset tx dma channel and purge TxFifo */
7612 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7613 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7614 usc_loopmode_send_done( info );
7615 }
7616
7617 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7618 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7619 * we must clear CMR:13 to begin repeating TxData to RxData
7620 */
7621 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7622 {
7623 info->loopmode_insert_requested = true;
7624
7625 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7626 * begin repeating TxData on RxData (complete insertion)
7627 */
7628 usc_OutReg( info, RICR,
7629 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7630
7631 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7632 info->cmr_value |= BIT13;
7633 usc_OutReg(info, CMR, info->cmr_value);
7634 }
7635
7636 /* return 1 if station is inserted into the loop, otherwise 0
7637 */
7638 static int usc_loopmode_active( struct mgsl_struct * info)
7639 {
7640 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7641 }
7642
7643 #if SYNCLINK_GENERIC_HDLC
7644
7645 /**
7646 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7647 * set encoding and frame check sequence (FCS) options
7648 *
7649 * dev pointer to network device structure
7650 * encoding serial encoding setting
7651 * parity FCS setting
7652 *
7653 * returns 0 if success, otherwise error code
7654 */
7655 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7656 unsigned short parity)
7657 {
7658 struct mgsl_struct *info = dev_to_port(dev);
7659 unsigned char new_encoding;
7660 unsigned short new_crctype;
7661
7662 /* return error if TTY interface open */
7663 if (info->port.count)
7664 return -EBUSY;
7665
7666 switch (encoding)
7667 {
7668 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7669 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7670 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7671 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7672 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7673 default: return -EINVAL;
7674 }
7675
7676 switch (parity)
7677 {
7678 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7679 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7680 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7681 default: return -EINVAL;
7682 }
7683
7684 info->params.encoding = new_encoding;
7685 info->params.crc_type = new_crctype;
7686
7687 /* if network interface up, reprogram hardware */
7688 if (info->netcount)
7689 mgsl_program_hw(info);
7690
7691 return 0;
7692 }
7693
7694 /**
7695 * called by generic HDLC layer to send frame
7696 *
7697 * skb socket buffer containing HDLC frame
7698 * dev pointer to network device structure
7699 *
7700 * returns 0 if success, otherwise error code
7701 */
7702 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7703 {
7704 struct mgsl_struct *info = dev_to_port(dev);
7705 unsigned long flags;
7706
7707 if (debug_level >= DEBUG_LEVEL_INFO)
7708 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7709
7710 /* stop sending until this frame completes */
7711 netif_stop_queue(dev);
7712
7713 /* copy data to device buffers */
7714 info->xmit_cnt = skb->len;
7715 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7716
7717 /* update network statistics */
7718 dev->stats.tx_packets++;
7719 dev->stats.tx_bytes += skb->len;
7720
7721 /* done with socket buffer, so free it */
7722 dev_kfree_skb(skb);
7723
7724 /* save start time for transmit timeout detection */
7725 dev->trans_start = jiffies;
7726
7727 /* start hardware transmitter if necessary */
7728 spin_lock_irqsave(&info->irq_spinlock,flags);
7729 if (!info->tx_active)
7730 usc_start_transmitter(info);
7731 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7732
7733 return 0;
7734 }
7735
7736 /**
7737 * called by network layer when interface enabled
7738 * claim resources and initialize hardware
7739 *
7740 * dev pointer to network device structure
7741 *
7742 * returns 0 if success, otherwise error code
7743 */
7744 static int hdlcdev_open(struct net_device *dev)
7745 {
7746 struct mgsl_struct *info = dev_to_port(dev);
7747 int rc;
7748 unsigned long flags;
7749
7750 if (debug_level >= DEBUG_LEVEL_INFO)
7751 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7752
7753 /* generic HDLC layer open processing */
7754 if ((rc = hdlc_open(dev)))
7755 return rc;
7756
7757 /* arbitrate between network and tty opens */
7758 spin_lock_irqsave(&info->netlock, flags);
7759 if (info->port.count != 0 || info->netcount != 0) {
7760 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7761 spin_unlock_irqrestore(&info->netlock, flags);
7762 return -EBUSY;
7763 }
7764 info->netcount=1;
7765 spin_unlock_irqrestore(&info->netlock, flags);
7766
7767 /* claim resources and init adapter */
7768 if ((rc = startup(info)) != 0) {
7769 spin_lock_irqsave(&info->netlock, flags);
7770 info->netcount=0;
7771 spin_unlock_irqrestore(&info->netlock, flags);
7772 return rc;
7773 }
7774
7775 /* assert DTR and RTS, apply hardware settings */
7776 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7777 mgsl_program_hw(info);
7778
7779 /* enable network layer transmit */
7780 dev->trans_start = jiffies;
7781 netif_start_queue(dev);
7782
7783 /* inform generic HDLC layer of current DCD status */
7784 spin_lock_irqsave(&info->irq_spinlock, flags);
7785 usc_get_serial_signals(info);
7786 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7787 if (info->serial_signals & SerialSignal_DCD)
7788 netif_carrier_on(dev);
7789 else
7790 netif_carrier_off(dev);
7791 return 0;
7792 }
7793
7794 /**
7795 * called by network layer when interface is disabled
7796 * shutdown hardware and release resources
7797 *
7798 * dev pointer to network device structure
7799 *
7800 * returns 0 if success, otherwise error code
7801 */
7802 static int hdlcdev_close(struct net_device *dev)
7803 {
7804 struct mgsl_struct *info = dev_to_port(dev);
7805 unsigned long flags;
7806
7807 if (debug_level >= DEBUG_LEVEL_INFO)
7808 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7809
7810 netif_stop_queue(dev);
7811
7812 /* shutdown adapter and release resources */
7813 shutdown(info);
7814
7815 hdlc_close(dev);
7816
7817 spin_lock_irqsave(&info->netlock, flags);
7818 info->netcount=0;
7819 spin_unlock_irqrestore(&info->netlock, flags);
7820
7821 return 0;
7822 }
7823
7824 /**
7825 * called by network layer to process IOCTL call to network device
7826 *
7827 * dev pointer to network device structure
7828 * ifr pointer to network interface request structure
7829 * cmd IOCTL command code
7830 *
7831 * returns 0 if success, otherwise error code
7832 */
7833 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7834 {
7835 const size_t size = sizeof(sync_serial_settings);
7836 sync_serial_settings new_line;
7837 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7838 struct mgsl_struct *info = dev_to_port(dev);
7839 unsigned int flags;
7840
7841 if (debug_level >= DEBUG_LEVEL_INFO)
7842 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7843
7844 /* return error if TTY interface open */
7845 if (info->port.count)
7846 return -EBUSY;
7847
7848 if (cmd != SIOCWANDEV)
7849 return hdlc_ioctl(dev, ifr, cmd);
7850
7851 switch(ifr->ifr_settings.type) {
7852 case IF_GET_IFACE: /* return current sync_serial_settings */
7853
7854 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7855 if (ifr->ifr_settings.size < size) {
7856 ifr->ifr_settings.size = size; /* data size wanted */
7857 return -ENOBUFS;
7858 }
7859
7860 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7861 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7862 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7863 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7864
7865 switch (flags){
7866 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7867 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7868 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7870 default: new_line.clock_type = CLOCK_DEFAULT;
7871 }
7872
7873 new_line.clock_rate = info->params.clock_speed;
7874 new_line.loopback = info->params.loopback ? 1:0;
7875
7876 if (copy_to_user(line, &new_line, size))
7877 return -EFAULT;
7878 return 0;
7879
7880 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7881
7882 if(!capable(CAP_NET_ADMIN))
7883 return -EPERM;
7884 if (copy_from_user(&new_line, line, size))
7885 return -EFAULT;
7886
7887 switch (new_line.clock_type)
7888 {
7889 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7890 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7891 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7892 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7893 case CLOCK_DEFAULT: flags = info->params.flags &
7894 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7895 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7896 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7897 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7898 default: return -EINVAL;
7899 }
7900
7901 if (new_line.loopback != 0 && new_line.loopback != 1)
7902 return -EINVAL;
7903
7904 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7905 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7906 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7907 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7908 info->params.flags |= flags;
7909
7910 info->params.loopback = new_line.loopback;
7911
7912 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7913 info->params.clock_speed = new_line.clock_rate;
7914 else
7915 info->params.clock_speed = 0;
7916
7917 /* if network interface up, reprogram hardware */
7918 if (info->netcount)
7919 mgsl_program_hw(info);
7920 return 0;
7921
7922 default:
7923 return hdlc_ioctl(dev, ifr, cmd);
7924 }
7925 }
7926
7927 /**
7928 * called by network layer when transmit timeout is detected
7929 *
7930 * dev pointer to network device structure
7931 */
7932 static void hdlcdev_tx_timeout(struct net_device *dev)
7933 {
7934 struct mgsl_struct *info = dev_to_port(dev);
7935 unsigned long flags;
7936
7937 if (debug_level >= DEBUG_LEVEL_INFO)
7938 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7939
7940 dev->stats.tx_errors++;
7941 dev->stats.tx_aborted_errors++;
7942
7943 spin_lock_irqsave(&info->irq_spinlock,flags);
7944 usc_stop_transmitter(info);
7945 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7946
7947 netif_wake_queue(dev);
7948 }
7949
7950 /**
7951 * called by device driver when transmit completes
7952 * reenable network layer transmit if stopped
7953 *
7954 * info pointer to device instance information
7955 */
7956 static void hdlcdev_tx_done(struct mgsl_struct *info)
7957 {
7958 if (netif_queue_stopped(info->netdev))
7959 netif_wake_queue(info->netdev);
7960 }
7961
7962 /**
7963 * called by device driver when frame received
7964 * pass frame to network layer
7965 *
7966 * info pointer to device instance information
7967 * buf pointer to buffer contianing frame data
7968 * size count of data bytes in buf
7969 */
7970 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7971 {
7972 struct sk_buff *skb = dev_alloc_skb(size);
7973 struct net_device *dev = info->netdev;
7974
7975 if (debug_level >= DEBUG_LEVEL_INFO)
7976 printk("hdlcdev_rx(%s)\n", dev->name);
7977
7978 if (skb == NULL) {
7979 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7980 dev->name);
7981 dev->stats.rx_dropped++;
7982 return;
7983 }
7984
7985 memcpy(skb_put(skb, size), buf, size);
7986
7987 skb->protocol = hdlc_type_trans(skb, dev);
7988
7989 dev->stats.rx_packets++;
7990 dev->stats.rx_bytes += size;
7991
7992 netif_rx(skb);
7993 }
7994
7995 static const struct net_device_ops hdlcdev_ops = {
7996 .ndo_open = hdlcdev_open,
7997 .ndo_stop = hdlcdev_close,
7998 .ndo_change_mtu = hdlc_change_mtu,
7999 .ndo_start_xmit = hdlc_start_xmit,
8000 .ndo_do_ioctl = hdlcdev_ioctl,
8001 .ndo_tx_timeout = hdlcdev_tx_timeout,
8002 };
8003
8004 /**
8005 * called by device driver when adding device instance
8006 * do generic HDLC initialization
8007 *
8008 * info pointer to device instance information
8009 *
8010 * returns 0 if success, otherwise error code
8011 */
8012 static int hdlcdev_init(struct mgsl_struct *info)
8013 {
8014 int rc;
8015 struct net_device *dev;
8016 hdlc_device *hdlc;
8017
8018 /* allocate and initialize network and HDLC layer objects */
8019
8020 if (!(dev = alloc_hdlcdev(info))) {
8021 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8022 return -ENOMEM;
8023 }
8024
8025 /* for network layer reporting purposes only */
8026 dev->base_addr = info->io_base;
8027 dev->irq = info->irq_level;
8028 dev->dma = info->dma_level;
8029
8030 /* network layer callbacks and settings */
8031 dev->netdev_ops = &hdlcdev_ops;
8032 dev->watchdog_timeo = 10 * HZ;
8033 dev->tx_queue_len = 50;
8034
8035 /* generic HDLC layer callbacks and settings */
8036 hdlc = dev_to_hdlc(dev);
8037 hdlc->attach = hdlcdev_attach;
8038 hdlc->xmit = hdlcdev_xmit;
8039
8040 /* register objects with HDLC layer */
8041 if ((rc = register_hdlc_device(dev))) {
8042 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8043 free_netdev(dev);
8044 return rc;
8045 }
8046
8047 info->netdev = dev;
8048 return 0;
8049 }
8050
8051 /**
8052 * called by device driver when removing device instance
8053 * do generic HDLC cleanup
8054 *
8055 * info pointer to device instance information
8056 */
8057 static void hdlcdev_exit(struct mgsl_struct *info)
8058 {
8059 unregister_hdlc_device(info->netdev);
8060 free_netdev(info->netdev);
8061 info->netdev = NULL;
8062 }
8063
8064 #endif /* CONFIG_HDLC */
8065
8066
8067 static int __devinit synclink_init_one (struct pci_dev *dev,
8068 const struct pci_device_id *ent)
8069 {
8070 struct mgsl_struct *info;
8071
8072 if (pci_enable_device(dev)) {
8073 printk("error enabling pci device %p\n", dev);
8074 return -EIO;
8075 }
8076
8077 if (!(info = mgsl_allocate_device())) {
8078 printk("can't allocate device instance data.\n");
8079 return -EIO;
8080 }
8081
8082 /* Copy user configuration info to device instance data */
8083
8084 info->io_base = pci_resource_start(dev, 2);
8085 info->irq_level = dev->irq;
8086 info->phys_memory_base = pci_resource_start(dev, 3);
8087
8088 /* Because veremap only works on page boundaries we must map
8089 * a larger area than is actually implemented for the LCR
8090 * memory range. We map a full page starting at the page boundary.
8091 */
8092 info->phys_lcr_base = pci_resource_start(dev, 0);
8093 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8094 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8095
8096 info->bus_type = MGSL_BUS_TYPE_PCI;
8097 info->io_addr_size = 8;
8098 info->irq_flags = IRQF_SHARED;
8099
8100 if (dev->device == 0x0210) {
8101 /* Version 1 PCI9030 based universal PCI adapter */
8102 info->misc_ctrl_value = 0x007c4080;
8103 info->hw_version = 1;
8104 } else {
8105 /* Version 0 PCI9050 based 5V PCI adapter
8106 * A PCI9050 bug prevents reading LCR registers if
8107 * LCR base address bit 7 is set. Maintain shadow
8108 * value so we can write to LCR misc control reg.
8109 */
8110 info->misc_ctrl_value = 0x087e4546;
8111 info->hw_version = 0;
8112 }
8113
8114 mgsl_add_device(info);
8115
8116 return 0;
8117 }
8118
8119 static void __devexit synclink_remove_one (struct pci_dev *dev)
8120 {
8121 }
8122
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree