2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2007, 2008 Cavium Networks
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/time.h>
13 #include <linux/delay.h>
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-npei-defs.h>
17 #include <asm/octeon/cvmx-pciercx-defs.h>
18 #include <asm/octeon/cvmx-pescx-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/cvmx-helper-errata.h>
22 #include "pci-common.h"
24 union cvmx_pcie_address
{
27 uint64_t upper
:2; /* Normally 2 for XKPHYS */
28 uint64_t reserved_49_61
:13; /* Must be zero */
29 uint64_t io
:1; /* 1 for IO space access */
30 uint64_t did
:5; /* PCIe DID = 3 */
31 uint64_t subdid
:3; /* PCIe SubDID = 1 */
32 uint64_t reserved_36_39
:4; /* Must be zero */
33 uint64_t es
:2; /* Endian swap = 1 */
34 uint64_t port
:2; /* PCIe port 0,1 */
35 uint64_t reserved_29_31
:3; /* Must be zero */
37 * Selects the type of the configuration request (0 = type 0,
41 /* Target bus number sent in the ID in the request. */
44 * Target device number sent in the ID in the
45 * request. Note that Dev must be zero for type 0
46 * configuration requests.
49 /* Target function number sent in the ID in the request. */
52 * Selects a register in the configuration space of
58 uint64_t upper
:2; /* Normally 2 for XKPHYS */
59 uint64_t reserved_49_61
:13; /* Must be zero */
60 uint64_t io
:1; /* 1 for IO space access */
61 uint64_t did
:5; /* PCIe DID = 3 */
62 uint64_t subdid
:3; /* PCIe SubDID = 2 */
63 uint64_t reserved_36_39
:4; /* Must be zero */
64 uint64_t es
:2; /* Endian swap = 1 */
65 uint64_t port
:2; /* PCIe port 0,1 */
66 uint64_t address
:32; /* PCIe IO address */
69 uint64_t upper
:2; /* Normally 2 for XKPHYS */
70 uint64_t reserved_49_61
:13; /* Must be zero */
71 uint64_t io
:1; /* 1 for IO space access */
72 uint64_t did
:5; /* PCIe DID = 3 */
73 uint64_t subdid
:3; /* PCIe SubDID = 3-6 */
74 uint64_t reserved_36_39
:4; /* Must be zero */
75 uint64_t address
:36; /* PCIe Mem address */
80 * Return the Core virtual base address for PCIe IO access. IOs are
81 * read/written as an offset from this address.
83 * @pcie_port: PCIe port the IO is for
85 * Returns 64bit Octeon IO base address for read/write
87 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port
)
89 union cvmx_pcie_address pcie_addr
;
91 pcie_addr
.io
.upper
= 0;
94 pcie_addr
.io
.subdid
= 2;
96 pcie_addr
.io
.port
= pcie_port
;
101 * Size of the IO address region returned at address
102 * cvmx_pcie_get_io_base_address()
104 * @pcie_port: PCIe port the IO is for
106 * Returns Size of the IO window
108 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port
)
114 * Return the Core virtual base address for PCIe MEM access. Memory is
115 * read/written as an offset from this address.
117 * @pcie_port: PCIe port the IO is for
119 * Returns 64bit Octeon IO base address for read/write
121 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port
)
123 union cvmx_pcie_address pcie_addr
;
125 pcie_addr
.mem
.upper
= 0;
126 pcie_addr
.mem
.io
= 1;
127 pcie_addr
.mem
.did
= 3;
128 pcie_addr
.mem
.subdid
= 3 + pcie_port
;
129 return pcie_addr
.u64
;
133 * Size of the Mem address region returned at address
134 * cvmx_pcie_get_mem_base_address()
136 * @pcie_port: PCIe port the IO is for
138 * Returns Size of the Mem window
140 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port
)
146 * Read a PCIe config space register indirectly. This is used for
147 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
149 * @pcie_port: PCIe port to read from
150 * @cfg_offset: Address to read
154 static uint32_t cvmx_pcie_cfgx_read(int pcie_port
, uint32_t cfg_offset
)
156 union cvmx_pescx_cfg_rd pescx_cfg_rd
;
157 pescx_cfg_rd
.u64
= 0;
158 pescx_cfg_rd
.s
.addr
= cfg_offset
;
159 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port
), pescx_cfg_rd
.u64
);
160 pescx_cfg_rd
.u64
= cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port
));
161 return pescx_cfg_rd
.s
.data
;
165 * Write a PCIe config space register indirectly. This is used for
166 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168 * @pcie_port: PCIe port to write to
169 * @cfg_offset: Address to write
170 * @val: Value to write
172 static void cvmx_pcie_cfgx_write(int pcie_port
, uint32_t cfg_offset
,
175 union cvmx_pescx_cfg_wr pescx_cfg_wr
;
176 pescx_cfg_wr
.u64
= 0;
177 pescx_cfg_wr
.s
.addr
= cfg_offset
;
178 pescx_cfg_wr
.s
.data
= val
;
179 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port
), pescx_cfg_wr
.u64
);
183 * Build a PCIe config space request address for a device
185 * @pcie_port: PCIe port to access
188 * @fn: Device sub function
189 * @reg: Register to access
191 * Returns 64bit Octeon IO address
193 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port
, int bus
,
194 int dev
, int fn
, int reg
)
196 union cvmx_pcie_address pcie_addr
;
197 union cvmx_pciercx_cfg006 pciercx_cfg006
;
200 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG006(pcie_port
));
201 if ((bus
<= pciercx_cfg006
.s
.pbnum
) && (dev
!= 0))
205 pcie_addr
.config
.upper
= 2;
206 pcie_addr
.config
.io
= 1;
207 pcie_addr
.config
.did
= 3;
208 pcie_addr
.config
.subdid
= 1;
209 pcie_addr
.config
.es
= 1;
210 pcie_addr
.config
.port
= pcie_port
;
211 pcie_addr
.config
.ty
= (bus
> pciercx_cfg006
.s
.pbnum
);
212 pcie_addr
.config
.bus
= bus
;
213 pcie_addr
.config
.dev
= dev
;
214 pcie_addr
.config
.func
= fn
;
215 pcie_addr
.config
.reg
= reg
;
216 return pcie_addr
.u64
;
220 * Read 8bits from a Device's config space
222 * @pcie_port: PCIe port the device is on
225 * @fn: Device sub function
226 * @reg: Register to access
228 * Returns Result of the read
230 static uint8_t cvmx_pcie_config_read8(int pcie_port
, int bus
, int dev
,
234 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
236 return cvmx_read64_uint8(address
);
242 * Read 16bits from a Device's config space
244 * @pcie_port: PCIe port the device is on
247 * @fn: Device sub function
248 * @reg: Register to access
250 * Returns Result of the read
252 static uint16_t cvmx_pcie_config_read16(int pcie_port
, int bus
, int dev
,
256 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
258 return le16_to_cpu(cvmx_read64_uint16(address
));
264 * Read 32bits from a Device's config space
266 * @pcie_port: PCIe port the device is on
269 * @fn: Device sub function
270 * @reg: Register to access
272 * Returns Result of the read
274 static uint32_t cvmx_pcie_config_read32(int pcie_port
, int bus
, int dev
,
278 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
280 return le32_to_cpu(cvmx_read64_uint32(address
));
286 * Write 8bits to a Device's config space
288 * @pcie_port: PCIe port the device is on
291 * @fn: Device sub function
292 * @reg: Register to access
293 * @val: Value to write
295 static void cvmx_pcie_config_write8(int pcie_port
, int bus
, int dev
, int fn
,
296 int reg
, uint8_t val
)
299 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
301 cvmx_write64_uint8(address
, val
);
305 * Write 16bits to a Device's config space
307 * @pcie_port: PCIe port the device is on
310 * @fn: Device sub function
311 * @reg: Register to access
312 * @val: Value to write
314 static void cvmx_pcie_config_write16(int pcie_port
, int bus
, int dev
, int fn
,
315 int reg
, uint16_t val
)
318 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
320 cvmx_write64_uint16(address
, cpu_to_le16(val
));
324 * Write 32bits to a Device's config space
326 * @pcie_port: PCIe port the device is on
329 * @fn: Device sub function
330 * @reg: Register to access
331 * @val: Value to write
333 static void cvmx_pcie_config_write32(int pcie_port
, int bus
, int dev
, int fn
,
334 int reg
, uint32_t val
)
337 __cvmx_pcie_build_config_addr(pcie_port
, bus
, dev
, fn
, reg
);
339 cvmx_write64_uint32(address
, cpu_to_le32(val
));
343 * Initialize the RC config space CSRs
345 * @pcie_port: PCIe port to initialize
347 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port
)
349 union cvmx_pciercx_cfg030 pciercx_cfg030
;
350 union cvmx_npei_ctl_status2 npei_ctl_status2
;
351 union cvmx_pciercx_cfg070 pciercx_cfg070
;
352 union cvmx_pciercx_cfg001 pciercx_cfg001
;
353 union cvmx_pciercx_cfg032 pciercx_cfg032
;
354 union cvmx_pciercx_cfg006 pciercx_cfg006
;
355 union cvmx_pciercx_cfg008 pciercx_cfg008
;
356 union cvmx_pciercx_cfg009 pciercx_cfg009
;
357 union cvmx_pciercx_cfg010 pciercx_cfg010
;
358 union cvmx_pciercx_cfg011 pciercx_cfg011
;
359 union cvmx_pciercx_cfg035 pciercx_cfg035
;
360 union cvmx_pciercx_cfg075 pciercx_cfg075
;
361 union cvmx_pciercx_cfg034 pciercx_cfg034
;
363 /* Max Payload Size (PCIE*_CFG030[MPS]) */
364 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
365 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
366 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
368 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG030(pcie_port
));
370 * Max payload size = 128 bytes for best Octeon DMA
373 pciercx_cfg030
.s
.mps
= 0;
375 * Max read request size = 128 bytes for best Octeon DMA
378 pciercx_cfg030
.s
.mrrs
= 0;
379 /* Enable relaxed ordering. */
380 pciercx_cfg030
.s
.ro_en
= 1;
381 /* Enable no snoop. */
382 pciercx_cfg030
.s
.ns_en
= 1;
383 /* Correctable error reporting enable. */
384 pciercx_cfg030
.s
.ce_en
= 1;
385 /* Non-fatal error reporting enable. */
386 pciercx_cfg030
.s
.nfe_en
= 1;
387 /* Fatal error reporting enable. */
388 pciercx_cfg030
.s
.fe_en
= 1;
389 /* Unsupported request reporting enable. */
390 pciercx_cfg030
.s
.ur_en
= 1;
391 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG030(pcie_port
),
395 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
398 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
399 * exceed PCIE*_CFG030[MRRS].
401 npei_ctl_status2
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2
);
402 /* Max payload size = 128 bytes for best Octeon DMA performance */
403 npei_ctl_status2
.s
.mps
= 0;
404 /* Max read request size = 128 bytes for best Octeon DMA performance */
405 npei_ctl_status2
.s
.mrrs
= 0;
406 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2
, npei_ctl_status2
.u64
);
408 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
410 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG070(pcie_port
));
411 pciercx_cfg070
.s
.ge
= 1; /* ECRC generation enable. */
412 pciercx_cfg070
.s
.ce
= 1; /* ECRC check enable. */
413 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG070(pcie_port
),
417 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
420 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
421 * Message Enable (PCIE*_CFG001[SEE])
424 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG001(pcie_port
));
425 pciercx_cfg001
.s
.msae
= 1; /* Memory space enable. */
426 pciercx_cfg001
.s
.me
= 1; /* Bus master enable. */
427 pciercx_cfg001
.s
.i_dis
= 1; /* INTx assertion disable. */
428 pciercx_cfg001
.s
.see
= 1; /* SERR# enable */
429 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG001(pcie_port
),
432 /* Advanced Error Recovery Message Enables */
433 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
434 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG066(pcie_port
), 0);
435 /* Use CVMX_PCIERCX_CFG067 hardware default */
436 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG069(pcie_port
), 0);
438 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
440 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG032(pcie_port
));
441 pciercx_cfg032
.s
.aslpc
= 0; /* Active state Link PM control. */
442 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG032(pcie_port
),
445 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
448 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
449 * cvmx_pcie_rc_initialize_link()
451 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
453 * We set the primary bus number to 1 so IDT bridges are
454 * happy. They don't like zero.
456 pciercx_cfg006
.u32
= 0;
457 pciercx_cfg006
.s
.pbnum
= 1;
458 pciercx_cfg006
.s
.sbnum
= 1;
459 pciercx_cfg006
.s
.subbnum
= 1;
460 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG006(pcie_port
),
464 * Memory-mapped I/O BAR (PCIERCn_CFG008)
465 * Most applications should disable the memory-mapped I/O BAR by
466 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
468 pciercx_cfg008
.u32
= 0;
469 pciercx_cfg008
.s
.mb_addr
= 0x100;
470 pciercx_cfg008
.s
.ml_addr
= 0;
471 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG008(pcie_port
),
475 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
476 * Most applications should disable the prefetchable BAR by setting
477 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
478 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
481 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG009(pcie_port
));
483 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG010(pcie_port
));
485 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG011(pcie_port
));
486 pciercx_cfg009
.s
.lmem_base
= 0x100;
487 pciercx_cfg009
.s
.lmem_limit
= 0;
488 pciercx_cfg010
.s
.umem_base
= 0x100;
489 pciercx_cfg011
.s
.umem_limit
= 0;
490 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG009(pcie_port
),
492 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG010(pcie_port
),
494 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG011(pcie_port
),
498 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
499 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
502 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG035(pcie_port
));
503 /* System error on correctable error enable. */
504 pciercx_cfg035
.s
.secee
= 1;
505 /* System error on fatal error enable. */
506 pciercx_cfg035
.s
.sefee
= 1;
507 /* System error on non-fatal error enable. */
508 pciercx_cfg035
.s
.senfee
= 1;
509 /* PME interrupt enable. */
510 pciercx_cfg035
.s
.pmeie
= 1;
511 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG035(pcie_port
),
515 * Advanced Error Recovery Interrupt Enables
516 * (PCIERCn_CFG075[CERE,NFERE,FERE])
519 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG075(pcie_port
));
520 /* Correctable error reporting enable. */
521 pciercx_cfg075
.s
.cere
= 1;
522 /* Non-fatal error reporting enable. */
523 pciercx_cfg075
.s
.nfere
= 1;
524 /* Fatal error reporting enable. */
525 pciercx_cfg075
.s
.fere
= 1;
526 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG075(pcie_port
),
529 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
530 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
533 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG034(pcie_port
));
534 /* Hot-plug interrupt enable. */
535 pciercx_cfg034
.s
.hpint_en
= 1;
536 /* Data Link Layer state changed enable */
537 pciercx_cfg034
.s
.dlls_en
= 1;
538 /* Command completed interrupt enable. */
539 pciercx_cfg034
.s
.ccint_en
= 1;
540 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG034(pcie_port
),
545 * Initialize a host mode PCIe link. This function takes a PCIe
546 * port from reset to a link up state. Software can then begin
547 * configuring the rest of the link.
549 * @pcie_port: PCIe port to initialize
551 * Returns Zero on success
553 static int __cvmx_pcie_rc_initialize_link(int pcie_port
)
555 uint64_t start_cycle
;
556 union cvmx_pescx_ctl_status pescx_ctl_status
;
557 union cvmx_pciercx_cfg452 pciercx_cfg452
;
558 union cvmx_pciercx_cfg032 pciercx_cfg032
;
559 union cvmx_pciercx_cfg448 pciercx_cfg448
;
561 /* Set the lane width */
563 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG452(pcie_port
));
564 pescx_ctl_status
.u64
= cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port
));
565 if (pescx_ctl_status
.s
.qlm_cfg
== 0) {
566 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
567 pciercx_cfg452
.s
.lme
= 0xf;
569 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
570 pciercx_cfg452
.s
.lme
= 0x7;
572 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG452(pcie_port
),
576 * CN52XX pass 1.x has an errata where length mismatches on UR
577 * responses can cause bus errors on 64bit memory
578 * reads. Turning off length error checking fixes this.
580 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
581 union cvmx_pciercx_cfg455 pciercx_cfg455
;
583 cvmx_pcie_cfgx_read(pcie_port
,
584 CVMX_PCIERCX_CFG455(pcie_port
));
585 pciercx_cfg455
.s
.m_cpl_len_err
= 1;
586 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG455(pcie_port
),
590 /* Lane swap needs to be manually enabled for CN52XX */
591 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) && (pcie_port
== 1)) {
592 pescx_ctl_status
.s
.lane_swp
= 1;
593 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port
),
594 pescx_ctl_status
.u64
);
597 /* Bring up the link */
598 pescx_ctl_status
.u64
= cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port
));
599 pescx_ctl_status
.s
.lnk_enb
= 1;
600 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port
), pescx_ctl_status
.u64
);
603 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
606 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0
))
607 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
609 /* Wait for the link to come up */
610 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port
);
611 start_cycle
= cvmx_get_cycle();
613 if (cvmx_get_cycle() - start_cycle
>
614 2 * cvmx_sysinfo_get()->cpu_clock_hz
) {
615 cvmx_dprintf("PCIe: Port %d link timeout\n",
621 cvmx_pcie_cfgx_read(pcie_port
,
622 CVMX_PCIERCX_CFG032(pcie_port
));
623 } while (pciercx_cfg032
.s
.dlla
== 0);
625 /* Display the link status */
626 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port
,
627 pciercx_cfg032
.s
.nlw
);
630 * Update the Replay Time Limit. Empirically, some PCIe
631 * devices take a little longer to respond than expected under
632 * load. As a workaround for this we configure the Replay Time
633 * Limit to the value expected for a 512 byte MPS instead of
634 * our actual 256 byte MPS. The numbers below are directly
635 * from the PCIe spec table 3-4.
638 cvmx_pcie_cfgx_read(pcie_port
, CVMX_PCIERCX_CFG448(pcie_port
));
639 switch (pciercx_cfg032
.s
.nlw
) {
641 pciercx_cfg448
.s
.rtl
= 1677;
643 case 2: /* 2 lanes */
644 pciercx_cfg448
.s
.rtl
= 867;
646 case 4: /* 4 lanes */
647 pciercx_cfg448
.s
.rtl
= 462;
649 case 8: /* 8 lanes */
650 pciercx_cfg448
.s
.rtl
= 258;
653 cvmx_pcie_cfgx_write(pcie_port
, CVMX_PCIERCX_CFG448(pcie_port
),
660 * Initialize a PCIe port for use in host(RC) mode. It doesn't
663 * @pcie_port: PCIe port to initialize
665 * Returns Zero on success
667 static int cvmx_pcie_rc_initialize(int pcie_port
)
670 union cvmx_ciu_soft_prst ciu_soft_prst
;
671 union cvmx_pescx_bist_status pescx_bist_status
;
672 union cvmx_pescx_bist_status2 pescx_bist_status2
;
673 union cvmx_npei_ctl_status npei_ctl_status
;
674 union cvmx_npei_mem_access_ctl npei_mem_access_ctl
;
675 union cvmx_npei_mem_access_subidx mem_access_subid
;
676 union cvmx_npei_dbg_data npei_dbg_data
;
677 union cvmx_pescx_ctl_status2 pescx_ctl_status2
;
680 * Make sure we aren't trying to setup a target mode interface
683 npei_ctl_status
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS
);
684 if ((pcie_port
== 0) && !npei_ctl_status
.s
.host_mode
) {
685 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
686 "on port0, but port0 is not in host mode\n");
691 * Make sure a CN52XX isn't trying to bring up port 1 when it
694 if (OCTEON_IS_MODEL(OCTEON_CN52XX
)) {
695 npei_dbg_data
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA
);
696 if ((pcie_port
== 1) && npei_dbg_data
.cn52xx
.qlm0_link_width
) {
697 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
698 "called on port1, but port1 is "
705 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
706 * PCIe0, then PCIe1. '1' == round robin.
708 npei_ctl_status
.s
.arb
= 1;
709 /* Allow up to 0x20 config retries */
710 npei_ctl_status
.s
.cfg_rtry
= 0x20;
712 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
715 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
716 npei_ctl_status
.s
.p0_ntags
= 0x20;
717 npei_ctl_status
.s
.p1_ntags
= 0x20;
719 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS
, npei_ctl_status
.u64
);
721 /* Bring the PCIe out of reset */
722 if (cvmx_sysinfo_get()->board_type
== CVMX_BOARD_TYPE_EBH5200
) {
724 * The EBH5200 board swapped the PCIe reset lines on
725 * the board. As a workaround for this bug, we bring
726 * both PCIe ports out of reset at the same time
727 * instead of on separate calls. So for port 0, we
728 * bring both out of reset and do nothing on port 1.
730 if (pcie_port
== 0) {
731 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
733 * After a chip reset the PCIe will also be in
734 * reset. If it isn't, most likely someone is
735 * trying to init it again without a proper
738 if (ciu_soft_prst
.s
.soft_prst
== 0) {
739 /* Reset the ports */
740 ciu_soft_prst
.s
.soft_prst
= 1;
741 cvmx_write_csr(CVMX_CIU_SOFT_PRST
,
744 cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
745 ciu_soft_prst
.s
.soft_prst
= 1;
746 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
,
748 /* Wait until pcie resets the ports. */
751 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
752 ciu_soft_prst
.s
.soft_prst
= 0;
753 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
, ciu_soft_prst
.u64
);
754 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
755 ciu_soft_prst
.s
.soft_prst
= 0;
756 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, ciu_soft_prst
.u64
);
760 * The normal case: The PCIe ports are completely
761 * separate and can be brought out of reset
765 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
767 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
769 * After a chip reset the PCIe will also be in
770 * reset. If it isn't, most likely someone is trying
771 * to init it again without a proper PCIe reset.
773 if (ciu_soft_prst
.s
.soft_prst
== 0) {
775 ciu_soft_prst
.s
.soft_prst
= 1;
777 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
,
780 cvmx_write_csr(CVMX_CIU_SOFT_PRST
,
782 /* Wait until pcie resets the ports. */
786 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST1
);
787 ciu_soft_prst
.s
.soft_prst
= 0;
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST1
, ciu_soft_prst
.u64
);
790 ciu_soft_prst
.u64
= cvmx_read_csr(CVMX_CIU_SOFT_PRST
);
791 ciu_soft_prst
.s
.soft_prst
= 0;
792 cvmx_write_csr(CVMX_CIU_SOFT_PRST
, ciu_soft_prst
.u64
);
797 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
798 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
799 * fixed number of cycles.
803 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
804 CN52XX, so we only probe it on newer chips */
805 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X
)
806 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
807 /* Clear PCLK_RUN so we can check if the clock is running */
808 pescx_ctl_status2
.u64
=
809 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
));
810 pescx_ctl_status2
.s
.pclk_run
= 1;
811 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
),
812 pescx_ctl_status2
.u64
);
814 * Now that we cleared PCLK_RUN, wait for it to be set
815 * again telling us the clock is running.
817 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port
),
818 union cvmx_pescx_ctl_status2
,
819 pclk_run
, ==, 1, 10000)) {
820 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
827 * Check and make sure PCIe came out of reset. If it doesn't
828 * the board probably hasn't wired the clocks up and the
829 * interface should be skipped.
831 pescx_ctl_status2
.u64
=
832 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port
));
833 if (pescx_ctl_status2
.s
.pcierst
) {
834 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
840 * Check BIST2 status. If any bits are set skip this interface. This
841 * is an attempt to catch PCIE-813 on pass 1 parts.
843 pescx_bist_status2
.u64
=
844 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port
));
845 if (pescx_bist_status2
.u64
) {
846 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
847 "port isn't hooked up, skipping.\n",
852 /* Check BIST status */
853 pescx_bist_status
.u64
=
854 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port
));
855 if (pescx_bist_status
.u64
)
856 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
857 pcie_port
, CAST64(pescx_bist_status
.u64
));
859 /* Initialize the config space CSRs */
860 __cvmx_pcie_rc_initialize_config_space(pcie_port
);
862 /* Bring the link up */
863 if (__cvmx_pcie_rc_initialize_link(pcie_port
)) {
865 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
869 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
870 npei_mem_access_ctl
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL
);
871 /* Allow 16 words to combine */
872 npei_mem_access_ctl
.s
.max_word
= 0;
873 /* Wait up to 127 cycles for more data */
874 npei_mem_access_ctl
.s
.timer
= 127;
875 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL
, npei_mem_access_ctl
.u64
);
877 /* Setup Mem access SubDIDs */
878 mem_access_subid
.u64
= 0;
879 /* Port the request is sent to. */
880 mem_access_subid
.s
.port
= pcie_port
;
881 /* Due to an errata on pass 1 chips, no merging is allowed. */
882 mem_access_subid
.s
.nmerge
= 1;
883 /* Endian-swap for Reads. */
884 mem_access_subid
.s
.esr
= 1;
885 /* Endian-swap for Writes. */
886 mem_access_subid
.s
.esw
= 1;
887 /* No Snoop for Reads. */
888 mem_access_subid
.s
.nsr
= 1;
889 /* No Snoop for Writes. */
890 mem_access_subid
.s
.nsw
= 1;
891 /* Disable Relaxed Ordering for Reads. */
892 mem_access_subid
.s
.ror
= 0;
893 /* Disable Relaxed Ordering for Writes. */
894 mem_access_subid
.s
.row
= 0;
895 /* PCIe Adddress Bits <63:34>. */
896 mem_access_subid
.s
.ba
= 0;
899 * Setup mem access 12-15 for port 0, 16-19 for port 1,
900 * supplying 36 bits of address space.
902 for (i
= 12 + pcie_port
* 4; i
< 16 + pcie_port
* 4; i
++) {
903 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i
),
904 mem_access_subid
.u64
);
905 /* Set each SUBID to extend the addressable range */
906 mem_access_subid
.s
.ba
+= 1;
910 * Disable the peer to peer forwarding register. This must be
911 * setup by the OS after it enumerates the bus and assigns
912 * addresses to the PCIe busses.
914 for (i
= 0; i
< 4; i
++) {
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i
, pcie_port
), -1);
916 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i
, pcie_port
), -1);
919 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
920 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port
), 0);
923 * Disable Octeon's BAR1. It isn't needed in RC mode since
924 * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
925 * the 2nd 256MB of memory.
927 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port
), -1);
930 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
931 * precedence where they overlap. It also overlaps with the
932 * device addresses, so make sure the peer to peer forwarding
935 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port
), 0);
938 * Setup BAR2 attributes
940 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
941 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
942 * - WAIT_COM=0 will likely work for all applications.
944 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
947 union cvmx_npei_ctl_port1 npei_ctl_port
;
948 npei_ctl_port
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1
);
949 npei_ctl_port
.s
.bar2_enb
= 1;
950 npei_ctl_port
.s
.bar2_esx
= 1;
951 npei_ctl_port
.s
.bar2_cax
= 0;
952 npei_ctl_port
.s
.ptlp_ro
= 1;
953 npei_ctl_port
.s
.ctlp_ro
= 1;
954 npei_ctl_port
.s
.wait_com
= 0;
955 npei_ctl_port
.s
.waitl_com
= 0;
956 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1
, npei_ctl_port
.u64
);
958 union cvmx_npei_ctl_port0 npei_ctl_port
;
959 npei_ctl_port
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0
);
960 npei_ctl_port
.s
.bar2_enb
= 1;
961 npei_ctl_port
.s
.bar2_esx
= 1;
962 npei_ctl_port
.s
.bar2_cax
= 0;
963 npei_ctl_port
.s
.ptlp_ro
= 1;
964 npei_ctl_port
.s
.ctlp_ro
= 1;
965 npei_ctl_port
.s
.wait_com
= 0;
966 npei_ctl_port
.s
.waitl_com
= 0;
967 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0
, npei_ctl_port
.u64
);
973 /* Above was cvmx-pcie.c, below original pcie.c */
977 * Map a PCI device to the appropriate interrupt line
979 * @param dev The Linux PCI device structure for the device to map
980 * @param slot The slot number for this device on __BUS 0__. Linux
981 * enumerates through all the bridges and figures out the
982 * slot on Bus 0 where this device eventually hooks to.
983 * @param pin The PCI interrupt pin read from the device, then swizzled
984 * as it goes through each bridge.
985 * @return Interrupt number for the device
987 int __init
octeon_pcie_pcibios_map_irq(const struct pci_dev
*dev
,
991 * The EBH5600 board with the PCI to PCIe bridge mistakenly
992 * wires the first slot for both device id 2 and interrupt
993 * A. According to the PCI spec, device id 2 should be C. The
994 * following kludge attempts to fix this.
996 if (strstr(octeon_board_type_string(), "EBH5600") &&
997 dev
->bus
&& dev
->bus
->parent
) {
999 * Iterate all the way up the device chain and find
1002 while (dev
->bus
&& dev
->bus
->parent
)
1003 dev
= to_pci_dev(dev
->bus
->bridge
);
1004 /* If the root bus is number 0 and the PEX 8114 is the
1005 * root, assume we are behind the miswired bus. We
1006 * need to correct the swizzle level by two. Yuck.
1008 if ((dev
->bus
->number
== 0) &&
1009 (dev
->vendor
== 0x10b5) && (dev
->device
== 0x8114)) {
1011 * The pin field is one based, not zero. We
1012 * need to swizzle it by minus two.
1014 pin
= ((pin
- 3) & 3) + 1;
1018 * The -1 is because pin starts with one, not zero. It might
1019 * be that this equation needs to include the slot number, but
1020 * I don't have hardware to check that against.
1022 return pin
- 1 + OCTEON_IRQ_PCI_INT0
;
1026 * Read a value from configuration space
1035 static inline int octeon_pcie_read_config(int pcie_port
, struct pci_bus
*bus
,
1036 unsigned int devfn
, int reg
, int size
,
1039 union octeon_cvmemctl cvmmemctl
;
1040 union octeon_cvmemctl cvmmemctl_save
;
1041 int bus_number
= bus
->number
;
1044 * We need to force the bus number to be zero on the root
1045 * bus. Linux numbers the 2nd root bus to start after all
1048 if (bus
->parent
== NULL
)
1052 * PCIe only has a single device connected to Octeon. It is
1053 * always device ID 0. Don't bother doing reads for other
1054 * device IDs on the first segment.
1056 if ((bus_number
== 0) && (devfn
>> 3 != 0))
1057 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1060 * The following is a workaround for the CN57XX, CN56XX,
1061 * CN55XX, and CN54XX errata with PCIe config reads from non
1062 * existent devices. These chips will hang the PCIe link if a
1063 * config read is performed that causes a UR response.
1065 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1
) ||
1066 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1
)) {
1068 * For our EBH5600 board, port 0 has a bridge with two
1069 * PCI-X slots. We need a new special checks to make
1070 * sure we only probe valid stuff. The PCIe->PCI-X
1071 * bridge only respondes to device ID 0, function
1074 if ((bus_number
== 0) && (devfn
>= 2))
1075 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1077 * The PCI-X slots are device ID 2,3. Choose one of
1078 * the below "if" blocks based on what is plugged into
1082 /* Use this option if you aren't using either slot */
1083 if (bus_number
== 1)
1084 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1087 * Use this option if you are using the first slot but
1090 if ((bus_number
== 1) && (devfn
>> 3 != 2))
1091 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1094 * Use this option if you are using the second slot
1095 * but not the first.
1097 if ((bus_number
== 1) && (devfn
>> 3 != 3))
1098 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1100 /* Use this opion if you are using both slots */
1101 if ((bus_number
== 1) &&
1102 !((devfn
== (2 << 3)) || (devfn
== (3 << 3))))
1103 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1107 * Shorten the DID timeout so bus errors for PCIe
1108 * config reads from non existent devices happen
1109 * faster. This allows us to continue booting even if
1110 * the above "if" checks are wrong. Once one of these
1111 * errors happens, the PCIe port is dead.
1113 cvmmemctl_save
.u64
= __read_64bit_c0_register($
11, 7);
1114 cvmmemctl
.u64
= cvmmemctl_save
.u64
;
1115 cvmmemctl
.s
.didtto
= 2;
1116 __write_64bit_c0_register($
11, 7, cvmmemctl
.u64
);
1121 *val
= cvmx_pcie_config_read32(pcie_port
, bus_number
,
1122 devfn
>> 3, devfn
& 0x7, reg
);
1125 *val
= cvmx_pcie_config_read16(pcie_port
, bus_number
,
1126 devfn
>> 3, devfn
& 0x7, reg
);
1129 *val
= cvmx_pcie_config_read8(pcie_port
, bus_number
, devfn
>> 3,
1133 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1136 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1
) ||
1137 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1
))
1138 __write_64bit_c0_register($
11, 7, cvmmemctl_save
.u64
);
1139 return PCIBIOS_SUCCESSFUL
;
1142 static int octeon_pcie0_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1143 int reg
, int size
, u32
*val
)
1145 return octeon_pcie_read_config(0, bus
, devfn
, reg
, size
, val
);
1148 static int octeon_pcie1_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1149 int reg
, int size
, u32
*val
)
1151 return octeon_pcie_read_config(1, bus
, devfn
, reg
, size
, val
);
1157 * Write a value to PCI configuration space
1166 static inline int octeon_pcie_write_config(int pcie_port
, struct pci_bus
*bus
,
1167 unsigned int devfn
, int reg
,
1170 int bus_number
= bus
->number
;
1172 * We need to force the bus number to be zero on the root
1173 * bus. Linux numbers the 2nd root bus to start after all
1176 if (bus
->parent
== NULL
)
1181 cvmx_pcie_config_write32(pcie_port
, bus_number
, devfn
>> 3,
1182 devfn
& 0x7, reg
, val
);
1183 return PCIBIOS_SUCCESSFUL
;
1185 cvmx_pcie_config_write16(pcie_port
, bus_number
, devfn
>> 3,
1186 devfn
& 0x7, reg
, val
);
1187 return PCIBIOS_SUCCESSFUL
;
1189 cvmx_pcie_config_write8(pcie_port
, bus_number
, devfn
>> 3,
1190 devfn
& 0x7, reg
, val
);
1191 return PCIBIOS_SUCCESSFUL
;
1193 #if PCI_CONFIG_SPACE_DELAY
1194 udelay(PCI_CONFIG_SPACE_DELAY
);
1196 return PCIBIOS_FUNC_NOT_SUPPORTED
;
1199 static int octeon_pcie0_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1200 int reg
, int size
, u32 val
)
1202 return octeon_pcie_write_config(0, bus
, devfn
, reg
, size
, val
);
1205 static int octeon_pcie1_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1206 int reg
, int size
, u32 val
)
1208 return octeon_pcie_write_config(1, bus
, devfn
, reg
, size
, val
);
1211 static struct pci_ops octeon_pcie0_ops
= {
1212 octeon_pcie0_read_config
,
1213 octeon_pcie0_write_config
,
1216 static struct resource octeon_pcie0_mem_resource
= {
1217 .name
= "Octeon PCIe0 MEM",
1218 .flags
= IORESOURCE_MEM
,
1221 static struct resource octeon_pcie0_io_resource
= {
1222 .name
= "Octeon PCIe0 IO",
1223 .flags
= IORESOURCE_IO
,
1226 static struct pci_controller octeon_pcie0_controller
= {
1227 .pci_ops
= &octeon_pcie0_ops
,
1228 .mem_resource
= &octeon_pcie0_mem_resource
,
1229 .io_resource
= &octeon_pcie0_io_resource
,
1232 static struct pci_ops octeon_pcie1_ops
= {
1233 octeon_pcie1_read_config
,
1234 octeon_pcie1_write_config
,
1237 static struct resource octeon_pcie1_mem_resource
= {
1238 .name
= "Octeon PCIe1 MEM",
1239 .flags
= IORESOURCE_MEM
,
1242 static struct resource octeon_pcie1_io_resource
= {
1243 .name
= "Octeon PCIe1 IO",
1244 .flags
= IORESOURCE_IO
,
1247 static struct pci_controller octeon_pcie1_controller
= {
1248 .pci_ops
= &octeon_pcie1_ops
,
1249 .mem_resource
= &octeon_pcie1_mem_resource
,
1250 .io_resource
= &octeon_pcie1_io_resource
,
1255 * Initialize the Octeon PCIe controllers
1259 static int __init
octeon_pcie_setup(void)
1261 union cvmx_npei_ctl_status npei_ctl_status
;
1264 /* These chips don't have PCIe */
1265 if (!octeon_has_feature(OCTEON_FEATURE_PCIE
))
1268 /* Point pcibios_map_irq() to the PCIe version of it */
1269 octeon_pcibios_map_irq
= octeon_pcie_pcibios_map_irq
;
1271 /* Use the PCIe based DMA mappings */
1272 octeon_dma_bar_type
= OCTEON_DMA_BAR_TYPE_PCIE
;
1275 * PCIe I/O range. It is based on port 0 but includes up until
1278 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1279 ioport_resource
.start
= 0;
1280 ioport_resource
.end
=
1281 cvmx_pcie_get_io_base_address(1) -
1282 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1284 npei_ctl_status
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS
);
1285 if (npei_ctl_status
.s
.host_mode
) {
1286 pr_notice("PCIe: Initializing port 0\n");
1287 result
= cvmx_pcie_rc_initialize(0);
1289 /* Memory offsets are physical addresses */
1290 octeon_pcie0_controller
.mem_offset
=
1291 cvmx_pcie_get_mem_base_address(0);
1292 /* IO offsets are Mips virtual addresses */
1293 octeon_pcie0_controller
.io_map_base
=
1294 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1296 octeon_pcie0_controller
.io_offset
= 0;
1298 * To keep things similar to PCI, we start
1299 * device addresses at the same place as PCI
1300 * uisng big bar support. This normally
1301 * translates to 4GB-256MB, which is the same
1304 octeon_pcie0_controller
.mem_resource
->start
=
1305 cvmx_pcie_get_mem_base_address(0) +
1306 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE
<< 20);
1307 octeon_pcie0_controller
.mem_resource
->end
=
1308 cvmx_pcie_get_mem_base_address(0) +
1309 cvmx_pcie_get_mem_size(0) - 1;
1311 * Ports must be above 16KB for the ISA bus
1312 * filtering in the PCI-X to PCI bridge.
1314 octeon_pcie0_controller
.io_resource
->start
= 4 << 10;
1315 octeon_pcie0_controller
.io_resource
->end
=
1316 cvmx_pcie_get_io_size(0) - 1;
1317 register_pci_controller(&octeon_pcie0_controller
);
1320 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1323 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1324 if (OCTEON_IS_MODEL(OCTEON_CN52XX
)) {
1325 union cvmx_npei_dbg_data npei_dbg_data
;
1326 npei_dbg_data
.u64
= cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA
);
1327 if (npei_dbg_data
.cn52xx
.qlm0_link_width
)
1331 pr_notice("PCIe: Initializing port 1\n");
1332 result
= cvmx_pcie_rc_initialize(1);
1334 /* Memory offsets are physical addresses */
1335 octeon_pcie1_controller
.mem_offset
=
1336 cvmx_pcie_get_mem_base_address(1);
1337 /* IO offsets are Mips virtual addresses */
1338 octeon_pcie1_controller
.io_map_base
=
1339 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1340 octeon_pcie1_controller
.io_offset
=
1341 cvmx_pcie_get_io_base_address(1) -
1342 cvmx_pcie_get_io_base_address(0);
1344 * To keep things similar to PCI, we start device
1345 * addresses at the same place as PCI uisng big bar
1346 * support. This normally translates to 4GB-256MB,
1347 * which is the same as most x86 PCs.
1349 octeon_pcie1_controller
.mem_resource
->start
=
1350 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1351 (OCTEON_PCI_BAR1_HOLE_SIZE
<< 20);
1352 octeon_pcie1_controller
.mem_resource
->end
=
1353 cvmx_pcie_get_mem_base_address(1) +
1354 cvmx_pcie_get_mem_size(1) - 1;
1356 * Ports must be above 16KB for the ISA bus filtering
1357 * in the PCI-X to PCI bridge.
1359 octeon_pcie1_controller
.io_resource
->start
=
1360 cvmx_pcie_get_io_base_address(1) -
1361 cvmx_pcie_get_io_base_address(0);
1362 octeon_pcie1_controller
.io_resource
->end
=
1363 octeon_pcie1_controller
.io_resource
->start
+
1364 cvmx_pcie_get_io_size(1) - 1;
1365 register_pci_controller(&octeon_pcie1_controller
);
1370 arch_initcall(octeon_pcie_setup
);