drivers/ide/ns87415.c

   1 /*
   2  * Copyright (C) 1997-1998      Mark Lord <mlord@pobox.com>
   3  * Copyright (C) 1998           Eddie C. Dost <ecd@skynet.be>
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2004           Grant Grundler <grundler at parisc-linux.org>
   6  *
   7  * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/ide.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/io.h>
  20
  21 #define DRV_NAME "ns87415"
  22
  23 #ifdef CONFIG_SUPERIO
  24 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  25  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  26  * which use the integrated NS87514 cell for CD-ROM support.
  27  * i.e we have to support for CD-ROM installs.
  28  * See drivers/parisc/superio.c for more gory details.
  29  */
  30 #include <asm/superio.h>
  31
  32 #define SUPERIO_IDE_MAX_RETRIES 25
  33
  34 /* Because of a defect in Super I/O, all reads of the PCI DMA status
  35  * registers, IDE status register and the IDE select register need to be
  36  * retried
  37  */
  38 static u8 superio_ide_inb (unsigned long port)
  39 {
  40         u8 tmp;
  41         int retries = SUPERIO_IDE_MAX_RETRIES;
  42
  43         /* printk(" [ reading port 0x%x with retry ] ", port); */
  44
  45         do {
  46                 tmp = inb(port);
  47                 if (tmp == 0)
  48                         udelay(50);
  49         } while (tmp == 0 && retries-- > 0);
  50
  51         return tmp;
  52 }
  53
  54 static u8 superio_read_status(ide_hwif_t *hwif)
  55 {
  56         return superio_ide_inb(hwif->io_ports.status_addr);
  57 }
  58
  59 static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
  60 {
  61         return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
  62 }
  63
  64 static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
  65 {
  66         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
  67         struct ide_taskfile *tf = &cmd->tf;
  68
  69         /* be sure we're looking at the low order bits */
  70         outb(ATA_DEVCTL_OBS, io_ports->ctl_addr);
  71
  72         if (cmd->tf_flags & IDE_TFLAG_IN_ERROR)
  73                 tf->error  = inb(io_ports->feature_addr);
  74         if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
  75                 tf->nsect  = inb(io_ports->nsect_addr);
  76         if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
  77                 tf->lbal   = inb(io_ports->lbal_addr);
  78         if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
  79                 tf->lbam   = inb(io_ports->lbam_addr);
  80         if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
  81                 tf->lbah   = inb(io_ports->lbah_addr);
  82         if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
  83                 tf->device = superio_ide_inb(io_ports->device_addr);
  84
  85         if (cmd->tf_flags & IDE_TFLAG_LBA48) {
  86                 outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr);
  87
  88                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR)
  89                         tf->hob_error = inb(io_ports->feature_addr);
  90                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
  91                         tf->hob_nsect = inb(io_ports->nsect_addr);
  92                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
  93                         tf->hob_lbal  = inb(io_ports->lbal_addr);
  94                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
  95                         tf->hob_lbam  = inb(io_ports->lbam_addr);
  96                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
  97                         tf->hob_lbah  = inb(io_ports->lbah_addr);
  98         }
  99 }
 100
 101 static void ns87415_dev_select(ide_drive_t *drive);
 102
 103 static const struct ide_tp_ops superio_tp_ops = {
 104         .exec_command           = ide_exec_command,
 105         .read_status            = superio_read_status,
 106         .read_altstatus         = ide_read_altstatus,
 107         .write_devctl           = ide_write_devctl,
 108
 109         .dev_select             = ns87415_dev_select,
 110         .tf_load                = ide_tf_load,
 111         .tf_read                = superio_tf_read,
 112
 113         .input_data             = ide_input_data,
 114         .output_data            = ide_output_data,
 115 };
 116
 117 static void __devinit superio_init_iops(struct hwif_s *hwif)
 118 {
 119         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 120         u32 dma_stat;
 121         u8 port = hwif->channel, tmp;
 122
 123         dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
 124
 125         /* Clear error/interrupt, enable dma */
 126         tmp = superio_ide_inb(dma_stat);
 127         outb(tmp | 0x66, dma_stat);
 128 }
 129 #else
 130 #define superio_dma_sff_read_status ide_dma_sff_read_status
 131 #endif
 132
 133 static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
 134
 135 /*
 136  * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
 137  * the IRQ associated with the port,
 138  * and selects either PIO or DMA handshaking for the next I/O operation.
 139  */
 140 static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 141 {
 142         ide_hwif_t *hwif = drive->hwif;
 143         struct pci_dev *dev = to_pci_dev(hwif->dev);
 144         unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
 145         unsigned long flags;
 146
 147         local_irq_save(flags);
 148         new = *old;
 149
 150         /* Adjust IRQ enable bit */
 151         bit = 1 << (8 + hwif->channel);
 152
 153         if (drive->dev_flags & IDE_DFLAG_PRESENT)
 154                 new &= ~bit;
 155         else
 156                 new |= bit;
 157
 158         /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
 159         bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
 160         other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
 161         new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
 162
 163         if (new != *old) {
 164                 unsigned char stat;
 165
 166                 /*
 167                  * Don't change DMA engine settings while Write Buffers
 168                  * are busy.
 169                  */
 170                 (void) pci_read_config_byte(dev, 0x43, &stat);
 171                 while (stat & 0x03) {
 172                         udelay(1);
 173                         (void) pci_read_config_byte(dev, 0x43, &stat);
 174                 }
 175
 176                 *old = new;
 177                 (void) pci_write_config_dword(dev, 0x40, new);
 178
 179                 /*
 180                  * And let things settle...
 181                  */
 182                 udelay(10);
 183         }
 184
 185         local_irq_restore(flags);
 186 }
 187
 188 static void ns87415_dev_select(ide_drive_t *drive)
 189 {
 190         ns87415_prepare_drive(drive,
 191                               !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
 192
 193         outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
 194 }
 195
 196 static void ns87415_dma_start(ide_drive_t *drive)
 197 {
 198         ns87415_prepare_drive(drive, 1);
 199         ide_dma_start(drive);
 200 }
 201
 202 static int ns87415_dma_end(ide_drive_t *drive)
 203 {
 204         ide_hwif_t *hwif = drive->hwif;
 205         u8 dma_stat = 0, dma_cmd = 0;
 206
 207         dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
 208         /* get DMA command mode */
 209         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 210         /* stop DMA */
 211         outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 212         /* from ERRATA: clear the INTR & ERROR bits */
 213         dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 214         outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
 215
 216         ns87415_prepare_drive(drive, 0);
 217
 218         /* verify good DMA status */
 219         return (dma_stat & 7) != 4;
 220 }
 221
 222 static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
 223 {
 224         struct pci_dev *dev = to_pci_dev(hwif->dev);
 225         unsigned int ctrl, using_inta;
 226         u8 progif;
 227 #ifdef __sparc_v9__
 228         int timeout;
 229         u8 stat;
 230 #endif
 231
 232         /*
 233          * We cannot probe for IRQ: both ports share common IRQ on INTA.
 234          * Also, leave IRQ masked during drive probing, to prevent infinite
 235          * interrupts from a potentially floating INTA..
 236          *
 237          * IRQs get unmasked in dev_select() when drive is first used.
 238          */
 239         (void) pci_read_config_dword(dev, 0x40, &ctrl);
 240         (void) pci_read_config_byte(dev, 0x09, &progif);
 241         /* is irq in "native" mode? */
 242         using_inta = progif & (1 << (hwif->channel << 1));
 243         if (!using_inta)
 244                 using_inta = ctrl & (1 << (4 + hwif->channel));
 245         if (hwif->mate) {
 246                 hwif->select_data = hwif->mate->select_data;
 247         } else {
 248                 hwif->select_data = (unsigned long)
 249                                         &ns87415_control[ns87415_count++];
 250                 ctrl |= (1 << 8) | (1 << 9);    /* mask both IRQs */
 251                 if (using_inta)
 252                         ctrl &= ~(1 << 6);      /* unmask INTA */
 253                 *((unsigned int *)hwif->select_data) = ctrl;
 254                 (void) pci_write_config_dword(dev, 0x40, ctrl);
 255
 256                 /*
 257                  * Set prefetch size to 512 bytes for both ports,
 258                  * but don't turn on/off prefetching here.
 259                  */
 260                 pci_write_config_byte(dev, 0x55, 0xee);
 261
 262 #ifdef __sparc_v9__
 263                 /*
 264                  * XXX: Reset the device, if we don't it will not respond to
 265                  *      SELECT_DRIVE() properly during first ide_probe_port().
 266                  */
 267                 timeout = 10000;
 268                 outb(12, hwif->io_ports.ctl_addr);
 269                 udelay(10);
 270                 outb(8, hwif->io_ports.ctl_addr);
 271                 do {
 272                         udelay(50);
 273                         stat = hwif->tp_ops->read_status(hwif);
 274                         if (stat == 0xff)
 275                                 break;
 276                 } while ((stat & ATA_BUSY) && --timeout);
 277 #endif
 278         }
 279
 280         if (!using_inta)
 281                 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
 282
 283         if (!hwif->dma_base)
 284                 return;
 285
 286         outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
 287 }
 288
 289 static const struct ide_tp_ops ns87415_tp_ops = {
 290         .exec_command           = ide_exec_command,
 291         .read_status            = ide_read_status,
 292         .read_altstatus         = ide_read_altstatus,
 293         .write_devctl           = ide_write_devctl,
 294
 295         .dev_select             = ns87415_dev_select,
 296         .tf_load                = ide_tf_load,
 297         .tf_read                = ide_tf_read,
 298
 299         .input_data             = ide_input_data,
 300         .output_data            = ide_output_data,
 301 };
 302
 303 static const struct ide_dma_ops ns87415_dma_ops = {
 304         .dma_host_set           = ide_dma_host_set,
 305         .dma_setup              = ide_dma_setup,
 306         .dma_start              = ns87415_dma_start,
 307         .dma_end                = ns87415_dma_end,
 308         .dma_test_irq           = ide_dma_test_irq,
 309         .dma_lost_irq           = ide_dma_lost_irq,
 310         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 311         .dma_sff_read_status    = superio_dma_sff_read_status,
 312 };
 313
 314 static const struct ide_port_info ns87415_chipset __devinitdata = {
 315         .name           = DRV_NAME,
 316         .init_hwif      = init_hwif_ns87415,
 317         .tp_ops         = &ns87415_tp_ops,
 318         .dma_ops        = &ns87415_dma_ops,
 319         .host_flags     = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
 320                           IDE_HFLAG_NO_ATAPI_DMA,
 321 };
 322
 323 static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 324 {
 325         struct ide_port_info d = ns87415_chipset;
 326
 327 #ifdef CONFIG_SUPERIO
 328         if (PCI_SLOT(dev->devfn) == 0xE) {
 329                 /* Built-in - assume it's under superio. */
 330                 d.init_iops = superio_init_iops;
 331                 d.tp_ops = &superio_tp_ops;
 332         }
 333 #endif
 334         return ide_pci_init_one(dev, &d, NULL);
 335 }
 336
 337 static const struct pci_device_id ns87415_pci_tbl[] = {
 338         { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
 339         { 0, },
 340 };
 341 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
 342
 343 static struct pci_driver ns87415_pci_driver = {
 344         .name           = "NS87415_IDE",
 345         .id_table       = ns87415_pci_tbl,
 346         .probe          = ns87415_init_one,
 347         .remove         = ide_pci_remove,
 348         .suspend        = ide_pci_suspend,
 349         .resume         = ide_pci_resume,
 350 };
 351
 352 static int __init ns87415_ide_init(void)
 353 {
 354         return ide_pci_register_driver(&ns87415_pci_driver);
 355 }
 356
 357 static void __exit ns87415_ide_exit(void)
 358 {
 359         pci_unregister_driver(&ns87415_pci_driver);
 360 }
 361
 362 module_init(ns87415_ide_init);
 363 module_exit(ns87415_ide_exit);
 364
 365 MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
 366 MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
 367 MODULE_LICENSE("GPL");