2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/list.h>
24 #include <linux/interrupt.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
28 /* Address offset of Registers */
29 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
31 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
32 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
33 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
34 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
35 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
36 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
37 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
39 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
40 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
41 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
42 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
43 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
44 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
45 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
46 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
47 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
48 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
49 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
51 /* Endpoint control register */
53 #define UDC_EPCTL_MRXFLUSH (1 << 12)
54 #define UDC_EPCTL_RRDY (1 << 9)
55 #define UDC_EPCTL_CNAK (1 << 8)
56 #define UDC_EPCTL_SNAK (1 << 7)
57 #define UDC_EPCTL_NAK (1 << 6)
58 #define UDC_EPCTL_P (1 << 3)
59 #define UDC_EPCTL_F (1 << 1)
60 #define UDC_EPCTL_S (1 << 0)
61 #define UDC_EPCTL_ET_SHIFT 4
63 #define UDC_EPCTL_ET_MASK 0x00000030
64 /* Value for ET field */
65 #define UDC_EPCTL_ET_CONTROL 0
66 #define UDC_EPCTL_ET_ISO 1
67 #define UDC_EPCTL_ET_BULK 2
68 #define UDC_EPCTL_ET_INTERRUPT 3
70 /* Endpoint status register */
72 #define UDC_EPSTS_XFERDONE (1 << 27)
73 #define UDC_EPSTS_RSS (1 << 26)
74 #define UDC_EPSTS_RCS (1 << 25)
75 #define UDC_EPSTS_TXEMPTY (1 << 24)
76 #define UDC_EPSTS_TDC (1 << 10)
77 #define UDC_EPSTS_HE (1 << 9)
78 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
79 #define UDC_EPSTS_BNA (1 << 7)
80 #define UDC_EPSTS_IN (1 << 6)
81 #define UDC_EPSTS_OUT_SHIFT 4
83 #define UDC_EPSTS_OUT_MASK 0x00000030
84 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
85 /* Value for OUT field */
86 #define UDC_EPSTS_OUT_SETUP 2
87 #define UDC_EPSTS_OUT_DATA 1
89 /* Device configuration register */
91 #define UDC_DEVCFG_CSR_PRG (1 << 17)
92 #define UDC_DEVCFG_SP (1 << 3)
94 #define UDC_DEVCFG_SPD_HS 0x0
95 #define UDC_DEVCFG_SPD_FS 0x1
96 #define UDC_DEVCFG_SPD_LS 0x2
98 /* Device control register */
100 #define UDC_DEVCTL_THLEN_SHIFT 24
101 #define UDC_DEVCTL_BRLEN_SHIFT 16
102 #define UDC_DEVCTL_CSR_DONE (1 << 13)
103 #define UDC_DEVCTL_SD (1 << 10)
104 #define UDC_DEVCTL_MODE (1 << 9)
105 #define UDC_DEVCTL_BREN (1 << 8)
106 #define UDC_DEVCTL_THE (1 << 7)
107 #define UDC_DEVCTL_DU (1 << 4)
108 #define UDC_DEVCTL_TDE (1 << 3)
109 #define UDC_DEVCTL_RDE (1 << 2)
110 #define UDC_DEVCTL_RES (1 << 0)
112 /* Device status register */
114 #define UDC_DEVSTS_TS_SHIFT 18
115 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
116 #define UDC_DEVSTS_ALT_SHIFT 8
117 #define UDC_DEVSTS_INTF_SHIFT 4
118 #define UDC_DEVSTS_CFG_SHIFT 0
120 #define UDC_DEVSTS_TS_MASK 0xfffc0000
121 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
122 #define UDC_DEVSTS_ALT_MASK 0x00000f00
123 #define UDC_DEVSTS_INTF_MASK 0x000000f0
124 #define UDC_DEVSTS_CFG_MASK 0x0000000f
125 /* value for maximum speed for SPEED field */
126 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
127 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
128 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
129 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
131 /* Device irq register */
133 #define UDC_DEVINT_RWKP (1 << 7)
134 #define UDC_DEVINT_ENUM (1 << 6)
135 #define UDC_DEVINT_SOF (1 << 5)
136 #define UDC_DEVINT_US (1 << 4)
137 #define UDC_DEVINT_UR (1 << 3)
138 #define UDC_DEVINT_ES (1 << 2)
139 #define UDC_DEVINT_SI (1 << 1)
140 #define UDC_DEVINT_SC (1 << 0)
142 #define UDC_DEVINT_MSK 0x7f
144 /* Endpoint irq register */
146 #define UDC_EPINT_IN_SHIFT 0
147 #define UDC_EPINT_OUT_SHIFT 16
148 #define UDC_EPINT_IN_EP0 (1 << 0)
149 #define UDC_EPINT_OUT_EP0 (1 << 16)
151 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
153 /* UDC_CSR_BUSY Status register */
155 #define UDC_CSR_BUSY (1 << 0)
157 /* SOFT RESET register */
159 #define UDC_PSRST (1 << 1)
160 #define UDC_SRST (1 << 0)
162 /* USB_DEVICE endpoint register */
164 #define UDC_CSR_NE_NUM_SHIFT 0
165 #define UDC_CSR_NE_DIR_SHIFT 4
166 #define UDC_CSR_NE_TYPE_SHIFT 5
167 #define UDC_CSR_NE_CFG_SHIFT 7
168 #define UDC_CSR_NE_INTF_SHIFT 11
169 #define UDC_CSR_NE_ALT_SHIFT 15
170 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
172 #define UDC_CSR_NE_NUM_MASK 0x0000000f
173 #define UDC_CSR_NE_DIR_MASK 0x00000010
174 #define UDC_CSR_NE_TYPE_MASK 0x00000060
175 #define UDC_CSR_NE_CFG_MASK 0x00000780
176 #define UDC_CSR_NE_INTF_MASK 0x00007800
177 #define UDC_CSR_NE_ALT_MASK 0x00078000
178 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
180 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
181 #define PCH_UDC_EPINT(in, num)\
182 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
184 /* Index of endpoint */
185 #define UDC_EP0IN_IDX 0
186 #define UDC_EP0OUT_IDX 1
187 #define UDC_EPIN_IDX(ep) (ep * 2)
188 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
189 #define PCH_UDC_EP0 0
190 #define PCH_UDC_EP1 1
191 #define PCH_UDC_EP2 2
192 #define PCH_UDC_EP3 3
194 /* Number of endpoint */
195 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
196 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
198 #define PCH_UDC_BRLEN 0x0F /* Burst length */
199 #define PCH_UDC_THLEN 0x1F /* Threshold length */
200 /* Value of EP Buffer Size */
201 #define UDC_EP0IN_BUFF_SIZE 16
202 #define UDC_EPIN_BUFF_SIZE 256
203 #define UDC_EP0OUT_BUFF_SIZE 16
204 #define UDC_EPOUT_BUFF_SIZE 256
205 /* Value of EP maximum packet size */
206 #define UDC_EP0IN_MAX_PKT_SIZE 64
207 #define UDC_EP0OUT_MAX_PKT_SIZE 64
208 #define UDC_BULK_MAX_PKT_SIZE 512
211 #define DMA_DIR_RX 1 /* DMA for data receive */
212 #define DMA_DIR_TX 2 /* DMA for data transmit */
213 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
214 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
217 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
219 * @status: Status quadlet
220 * @reserved: Reserved
221 * @dataptr: Buffer descriptor
222 * @next: Next descriptor
224 struct pch_udc_data_dma_desc
{
232 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
235 * @reserved: Reserved
236 * @data12: First setup word
237 * @data34: Second setup word
239 struct pch_udc_stp_dma_desc
{
242 struct usb_ctrlrequest request
;
243 } __attribute((packed
));
245 /* DMA status definitions */
247 #define PCH_UDC_BUFF_STS 0xC0000000
248 #define PCH_UDC_BS_HST_RDY 0x00000000
249 #define PCH_UDC_BS_DMA_BSY 0x40000000
250 #define PCH_UDC_BS_DMA_DONE 0x80000000
251 #define PCH_UDC_BS_HST_BSY 0xC0000000
253 #define PCH_UDC_RXTX_STS 0x30000000
254 #define PCH_UDC_RTS_SUCC 0x00000000
255 #define PCH_UDC_RTS_DESERR 0x10000000
256 #define PCH_UDC_RTS_BUFERR 0x30000000
257 /* Last Descriptor Indication */
258 #define PCH_UDC_DMA_LAST 0x08000000
259 /* Number of Rx/Tx Bytes Mask */
260 #define PCH_UDC_RXTX_BYTES 0x0000ffff
263 * struct pch_udc_cfg_data - Structure to hold current configuration
264 * and interface information
265 * @cur_cfg: current configuration in use
266 * @cur_intf: current interface in use
267 * @cur_alt: current alt interface in use
269 struct pch_udc_cfg_data
{
276 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
277 * @ep: embedded ep request
278 * @td_stp_phys: for setup request
279 * @td_data_phys: for data request
280 * @td_stp: for setup request
281 * @td_data: for data request
282 * @dev: reference to device struct
283 * @offset_addr: offset address of ep register
285 * @queue: queue for requests
286 * @num: endpoint number
287 * @in: endpoint is IN
288 * @halted: endpoint halted?
289 * @epsts: Endpoint status
293 dma_addr_t td_stp_phys
;
294 dma_addr_t td_data_phys
;
295 struct pch_udc_stp_dma_desc
*td_stp
;
296 struct pch_udc_data_dma_desc
*td_data
;
297 struct pch_udc_dev
*dev
;
298 unsigned long offset_addr
;
299 const struct usb_endpoint_descriptor
*desc
;
300 struct list_head queue
;
308 * struct pch_udc_dev - Structure holding complete information
309 * of the PCH USB device
310 * @gadget: gadget driver data
311 * @driver: reference to gadget driver bound
312 * @pdev: reference to the PCI device
313 * @ep: array of endpoints
314 * @lock: protects all state
315 * @active: enabled the PCI device
316 * @stall: stall requested
317 * @prot_stall: protcol stall requested
318 * @irq_registered: irq registered with system
319 * @mem_region: device memory mapped
320 * @registered: driver regsitered with system
321 * @suspended: driver in suspended state
322 * @connected: gadget driver associated
323 * @set_cfg_not_acked: pending acknowledgement 4 setup
324 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
325 * @data_requests: DMA pool for data requests
326 * @stp_requests: DMA pool for setup requests
327 * @dma_addr: DMA pool for received
328 * @ep0out_buf: Buffer for DMA
329 * @setup_data: Received setup data
330 * @phys_addr: of device memory
331 * @base_addr: for mapped device memory
332 * @irq: IRQ line for the device
333 * @cfg_data: current cfg, intf, and alt in use
336 struct usb_gadget gadget
;
337 struct usb_gadget_driver
*driver
;
338 struct pci_dev
*pdev
;
339 struct pch_udc_ep ep
[PCH_UDC_EP_NUM
];
340 spinlock_t lock
; /* protects all state */
351 struct pci_pool
*data_requests
;
352 struct pci_pool
*stp_requests
;
355 struct usb_ctrlrequest setup_data
;
356 unsigned long phys_addr
;
357 void __iomem
*base_addr
;
359 struct pch_udc_cfg_data cfg_data
;
362 #define PCH_UDC_PCI_BAR 1
363 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
365 static const char ep0_string
[] = "ep0in";
366 static DEFINE_SPINLOCK(udc_stall_spinlock
); /* stall spin lock */
367 struct pch_udc_dev
*pch_udc
; /* pointer to device object */
370 module_param_named(speed_fs
, speed_fs
, bool, S_IRUGO
);
371 MODULE_PARM_DESC(speed_fs
, "true for Full speed operation");
374 * struct pch_udc_request - Structure holding a PCH USB device request packet
375 * @req: embedded ep request
376 * @td_data_phys: phys. address
377 * @td_data: first dma desc. of chain
378 * @td_data_last: last dma desc. of chain
379 * @queue: associated queue
380 * @dma_going: DMA in progress for request
381 * @dma_mapped: DMA memory mapped for request
382 * @dma_done: DMA completed for request
383 * @chain_len: chain length
385 struct pch_udc_request
{
386 struct usb_request req
;
387 dma_addr_t td_data_phys
;
388 struct pch_udc_data_dma_desc
*td_data
;
389 struct pch_udc_data_dma_desc
*td_data_last
;
390 struct list_head queue
;
391 unsigned dma_going
:1,
397 static inline u32
pch_udc_readl(struct pch_udc_dev
*dev
, unsigned long reg
)
399 return ioread32(dev
->base_addr
+ reg
);
402 static inline void pch_udc_writel(struct pch_udc_dev
*dev
,
403 unsigned long val
, unsigned long reg
)
405 iowrite32(val
, dev
->base_addr
+ reg
);
408 static inline void pch_udc_bit_set(struct pch_udc_dev
*dev
,
410 unsigned long bitmask
)
412 pch_udc_writel(dev
, pch_udc_readl(dev
, reg
) | bitmask
, reg
);
415 static inline void pch_udc_bit_clr(struct pch_udc_dev
*dev
,
417 unsigned long bitmask
)
419 pch_udc_writel(dev
, pch_udc_readl(dev
, reg
) & ~(bitmask
), reg
);
422 static inline u32
pch_udc_ep_readl(struct pch_udc_ep
*ep
, unsigned long reg
)
424 return ioread32(ep
->dev
->base_addr
+ ep
->offset_addr
+ reg
);
427 static inline void pch_udc_ep_writel(struct pch_udc_ep
*ep
,
428 unsigned long val
, unsigned long reg
)
430 iowrite32(val
, ep
->dev
->base_addr
+ ep
->offset_addr
+ reg
);
433 static inline void pch_udc_ep_bit_set(struct pch_udc_ep
*ep
,
435 unsigned long bitmask
)
437 pch_udc_ep_writel(ep
, pch_udc_ep_readl(ep
, reg
) | bitmask
, reg
);
440 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep
*ep
,
442 unsigned long bitmask
)
444 pch_udc_ep_writel(ep
, pch_udc_ep_readl(ep
, reg
) & ~(bitmask
), reg
);
448 * pch_udc_csr_busy() - Wait till idle.
449 * @dev: Reference to pch_udc_dev structure
451 static void pch_udc_csr_busy(struct pch_udc_dev
*dev
)
453 unsigned int count
= 200;
456 while ((pch_udc_readl(dev
, UDC_CSR_BUSY_ADDR
) & UDC_CSR_BUSY
)
460 dev_err(&dev
->pdev
->dev
, "%s: wait error\n", __func__
);
464 * pch_udc_write_csr() - Write the command and status registers.
465 * @dev: Reference to pch_udc_dev structure
466 * @val: value to be written to CSR register
467 * @addr: address of CSR register
469 static void pch_udc_write_csr(struct pch_udc_dev
*dev
, unsigned long val
,
472 unsigned long reg
= PCH_UDC_CSR(ep
);
474 pch_udc_csr_busy(dev
); /* Wait till idle */
475 pch_udc_writel(dev
, val
, reg
);
476 pch_udc_csr_busy(dev
); /* Wait till idle */
480 * pch_udc_read_csr() - Read the command and status registers.
481 * @dev: Reference to pch_udc_dev structure
482 * @addr: address of CSR register
484 * Return codes: content of CSR register
486 static u32
pch_udc_read_csr(struct pch_udc_dev
*dev
, unsigned int ep
)
488 unsigned long reg
= PCH_UDC_CSR(ep
);
490 pch_udc_csr_busy(dev
); /* Wait till idle */
491 pch_udc_readl(dev
, reg
); /* Dummy read */
492 pch_udc_csr_busy(dev
); /* Wait till idle */
493 return pch_udc_readl(dev
, reg
);
497 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
498 * @dev: Reference to pch_udc_dev structure
500 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev
*dev
)
502 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RES
);
504 pch_udc_bit_clr(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RES
);
508 * pch_udc_get_frame() - Get the current frame from device status register
509 * @dev: Reference to pch_udc_dev structure
510 * Retern current frame
512 static inline int pch_udc_get_frame(struct pch_udc_dev
*dev
)
514 u32 frame
= pch_udc_readl(dev
, UDC_DEVSTS_ADDR
);
515 return (frame
& UDC_DEVSTS_TS_MASK
) >> UDC_DEVSTS_TS_SHIFT
;
519 * pch_udc_clear_selfpowered() - Clear the self power control
520 * @dev: Reference to pch_udc_regs structure
522 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev
*dev
)
524 pch_udc_bit_clr(dev
, UDC_DEVCFG_ADDR
, UDC_DEVCFG_SP
);
528 * pch_udc_set_selfpowered() - Set the self power control
529 * @dev: Reference to pch_udc_regs structure
531 static inline void pch_udc_set_selfpowered(struct pch_udc_dev
*dev
)
533 pch_udc_bit_set(dev
, UDC_DEVCFG_ADDR
, UDC_DEVCFG_SP
);
537 * pch_udc_set_disconnect() - Set the disconnect status.
538 * @dev: Reference to pch_udc_regs structure
540 static inline void pch_udc_set_disconnect(struct pch_udc_dev
*dev
)
542 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_SD
);
546 * pch_udc_clear_disconnect() - Clear the disconnect status.
547 * @dev: Reference to pch_udc_regs structure
549 static void pch_udc_clear_disconnect(struct pch_udc_dev
*dev
)
551 /* Clear the disconnect */
552 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RES
);
553 pch_udc_bit_clr(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_SD
);
555 /* Resume USB signalling */
556 pch_udc_bit_clr(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RES
);
560 * pch_udc_vbus_session() - set or clearr the disconnect status.
561 * @dev: Reference to pch_udc_regs structure
562 * @is_active: Parameter specifying the action
563 * 0: indicating VBUS power is ending
564 * !0: indicating VBUS power is starting
566 static inline void pch_udc_vbus_session(struct pch_udc_dev
*dev
,
570 pch_udc_clear_disconnect(dev
);
572 pch_udc_set_disconnect(dev
);
576 * pch_udc_ep_set_stall() - Set the stall of endpoint
577 * @ep: Reference to structure of type pch_udc_ep_regs
579 static void pch_udc_ep_set_stall(struct pch_udc_ep
*ep
)
582 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_F
);
583 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_S
);
585 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_S
);
590 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
591 * @ep: Reference to structure of type pch_udc_ep_regs
593 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep
*ep
)
595 /* Clear the stall */
596 pch_udc_ep_bit_clr(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_S
);
597 /* Clear NAK by writing CNAK */
598 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_CNAK
);
602 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
603 * @ep: Reference to structure of type pch_udc_ep_regs
604 * @type: Type of endpoint
606 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep
*ep
,
609 pch_udc_ep_writel(ep
, ((type
<< UDC_EPCTL_ET_SHIFT
) &
610 UDC_EPCTL_ET_MASK
), UDC_EPCTL_ADDR
);
614 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
615 * @ep: Reference to structure of type pch_udc_ep_regs
616 * @buf_size: The buffer size
618 static void pch_udc_ep_set_bufsz(struct pch_udc_ep
*ep
,
619 u32 buf_size
, u32 ep_in
)
623 data
= pch_udc_ep_readl(ep
, UDC_BUFIN_FRAMENUM_ADDR
);
624 data
= (data
& 0xffff0000) | (buf_size
& 0xffff);
625 pch_udc_ep_writel(ep
, data
, UDC_BUFIN_FRAMENUM_ADDR
);
627 data
= pch_udc_ep_readl(ep
, UDC_BUFOUT_MAXPKT_ADDR
);
628 data
= (buf_size
<< 16) | (data
& 0xffff);
629 pch_udc_ep_writel(ep
, data
, UDC_BUFOUT_MAXPKT_ADDR
);
634 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
635 * @ep: Reference to structure of type pch_udc_ep_regs
636 * @pkt_size: The packet size
638 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep
*ep
, u32 pkt_size
)
640 u32 data
= pch_udc_ep_readl(ep
, UDC_BUFOUT_MAXPKT_ADDR
);
641 data
= (data
& 0xffff0000) | (pkt_size
& 0xffff);
642 pch_udc_ep_writel(ep
, data
, UDC_BUFOUT_MAXPKT_ADDR
);
646 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
647 * @ep: Reference to structure of type pch_udc_ep_regs
648 * @addr: Address of the register
650 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep
*ep
, u32 addr
)
652 pch_udc_ep_writel(ep
, addr
, UDC_SUBPTR_ADDR
);
656 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
657 * @ep: Reference to structure of type pch_udc_ep_regs
658 * @addr: Address of the register
660 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep
*ep
, u32 addr
)
662 pch_udc_ep_writel(ep
, addr
, UDC_DESPTR_ADDR
);
666 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
667 * @ep: Reference to structure of type pch_udc_ep_regs
669 static inline void pch_udc_ep_set_pd(struct pch_udc_ep
*ep
)
671 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_P
);
675 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
676 * @ep: Reference to structure of type pch_udc_ep_regs
678 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep
*ep
)
680 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_RRDY
);
684 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
685 * @ep: Reference to structure of type pch_udc_ep_regs
687 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep
*ep
)
689 pch_udc_ep_bit_clr(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_RRDY
);
693 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
694 * register depending on the direction specified
695 * @dev: Reference to structure of type pch_udc_regs
696 * @dir: whether Tx or Rx
697 * DMA_DIR_RX: Receive
698 * DMA_DIR_TX: Transmit
700 static inline void pch_udc_set_dma(struct pch_udc_dev
*dev
, int dir
)
702 if (dir
== DMA_DIR_RX
)
703 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RDE
);
704 else if (dir
== DMA_DIR_TX
)
705 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_TDE
);
709 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
710 * register depending on the direction specified
711 * @dev: Reference to structure of type pch_udc_regs
712 * @dir: Whether Tx or Rx
713 * DMA_DIR_RX: Receive
714 * DMA_DIR_TX: Transmit
716 static inline void pch_udc_clear_dma(struct pch_udc_dev
*dev
, int dir
)
718 if (dir
== DMA_DIR_RX
)
719 pch_udc_bit_clr(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_RDE
);
720 else if (dir
== DMA_DIR_TX
)
721 pch_udc_bit_clr(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_TDE
);
725 * pch_udc_set_csr_done() - Set the device control register
726 * CSR done field (bit 13)
727 * @dev: reference to structure of type pch_udc_regs
729 static inline void pch_udc_set_csr_done(struct pch_udc_dev
*dev
)
731 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
, UDC_DEVCTL_CSR_DONE
);
735 * pch_udc_disable_interrupts() - Disables the specified interrupts
736 * @dev: Reference to structure of type pch_udc_regs
737 * @mask: Mask to disable interrupts
739 static inline void pch_udc_disable_interrupts(struct pch_udc_dev
*dev
,
742 pch_udc_bit_set(dev
, UDC_DEVIRQMSK_ADDR
, mask
);
746 * pch_udc_enable_interrupts() - Enable the specified interrupts
747 * @dev: Reference to structure of type pch_udc_regs
748 * @mask: Mask to enable interrupts
750 static inline void pch_udc_enable_interrupts(struct pch_udc_dev
*dev
,
753 pch_udc_bit_clr(dev
, UDC_DEVIRQMSK_ADDR
, mask
);
757 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
758 * @dev: Reference to structure of type pch_udc_regs
759 * @mask: Mask to disable interrupts
761 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev
*dev
,
764 pch_udc_bit_set(dev
, UDC_EPIRQMSK_ADDR
, mask
);
768 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
769 * @dev: Reference to structure of type pch_udc_regs
770 * @mask: Mask to enable interrupts
772 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev
*dev
,
775 pch_udc_bit_clr(dev
, UDC_EPIRQMSK_ADDR
, mask
);
779 * pch_udc_read_device_interrupts() - Read the device interrupts
780 * @dev: Reference to structure of type pch_udc_regs
781 * Retern The device interrupts
783 static inline u32
pch_udc_read_device_interrupts(struct pch_udc_dev
*dev
)
785 return pch_udc_readl(dev
, UDC_DEVIRQSTS_ADDR
);
789 * pch_udc_write_device_interrupts() - Write device interrupts
790 * @dev: Reference to structure of type pch_udc_regs
791 * @val: The value to be written to interrupt register
793 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev
*dev
,
796 pch_udc_writel(dev
, val
, UDC_DEVIRQSTS_ADDR
);
800 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
801 * @dev: Reference to structure of type pch_udc_regs
802 * Retern The endpoint interrupt
804 static inline u32
pch_udc_read_ep_interrupts(struct pch_udc_dev
*dev
)
806 return pch_udc_readl(dev
, UDC_EPIRQSTS_ADDR
);
810 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
811 * @dev: Reference to structure of type pch_udc_regs
812 * @val: The value to be written to interrupt register
814 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev
*dev
,
817 pch_udc_writel(dev
, val
, UDC_EPIRQSTS_ADDR
);
821 * pch_udc_read_device_status() - Read the device status
822 * @dev: Reference to structure of type pch_udc_regs
823 * Retern The device status
825 static inline u32
pch_udc_read_device_status(struct pch_udc_dev
*dev
)
827 return pch_udc_readl(dev
, UDC_DEVSTS_ADDR
);
831 * pch_udc_read_ep_control() - Read the endpoint control
832 * @ep: Reference to structure of type pch_udc_ep_regs
833 * Retern The endpoint control register value
835 static inline u32
pch_udc_read_ep_control(struct pch_udc_ep
*ep
)
837 return pch_udc_ep_readl(ep
, UDC_EPCTL_ADDR
);
841 * pch_udc_clear_ep_control() - Clear the endpoint control register
842 * @ep: Reference to structure of type pch_udc_ep_regs
843 * Retern The endpoint control register value
845 static inline void pch_udc_clear_ep_control(struct pch_udc_ep
*ep
)
847 return pch_udc_ep_writel(ep
, 0, UDC_EPCTL_ADDR
);
851 * pch_udc_read_ep_status() - Read the endpoint status
852 * @ep: Reference to structure of type pch_udc_ep_regs
853 * Retern The endpoint status
855 static inline u32
pch_udc_read_ep_status(struct pch_udc_ep
*ep
)
857 return pch_udc_ep_readl(ep
, UDC_EPSTS_ADDR
);
861 * pch_udc_clear_ep_status() - Clear the endpoint status
862 * @ep: Reference to structure of type pch_udc_ep_regs
863 * @stat: Endpoint status
865 static inline void pch_udc_clear_ep_status(struct pch_udc_ep
*ep
,
868 return pch_udc_ep_writel(ep
, stat
, UDC_EPSTS_ADDR
);
872 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
873 * of the endpoint control register
874 * @ep: Reference to structure of type pch_udc_ep_regs
876 static inline void pch_udc_ep_set_nak(struct pch_udc_ep
*ep
)
878 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_SNAK
);
882 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
883 * of the endpoint control register
884 * @ep: reference to structure of type pch_udc_ep_regs
886 static void pch_udc_ep_clear_nak(struct pch_udc_ep
*ep
)
888 unsigned int loopcnt
= 0;
889 struct pch_udc_dev
*dev
= ep
->dev
;
891 if (!(pch_udc_ep_readl(ep
, UDC_EPCTL_ADDR
) & UDC_EPCTL_NAK
))
895 while (!(pch_udc_read_ep_status(ep
) & UDC_EPSTS_MRXFIFO_EMP
) &&
899 dev_err(&dev
->pdev
->dev
, "%s: RxFIFO not Empty\n",
903 while ((pch_udc_read_ep_control(ep
) & UDC_EPCTL_NAK
) && --loopcnt
) {
904 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_CNAK
);
908 dev_err(&dev
->pdev
->dev
, "%s: Clear NAK not set for ep%d%s\n",
909 __func__
, ep
->num
, (ep
->in
? "in" : "out"));
913 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
914 * @ep: reference to structure of type pch_udc_ep_regs
915 * @dir: direction of endpoint
919 static void pch_udc_ep_fifo_flush(struct pch_udc_ep
*ep
, int dir
)
921 unsigned int loopcnt
= 0;
922 struct pch_udc_dev
*dev
= ep
->dev
;
924 if (dir
) { /* IN ep */
925 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_F
);
929 if (pch_udc_read_ep_status(ep
) & UDC_EPSTS_MRXFIFO_EMP
)
931 pch_udc_ep_bit_set(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_MRXFLUSH
);
932 /* Wait for RxFIFO Empty */
934 while (!(pch_udc_read_ep_status(ep
) & UDC_EPSTS_MRXFIFO_EMP
) &&
938 dev_err(&dev
->pdev
->dev
, "RxFIFO not Empty\n");
939 pch_udc_ep_bit_clr(ep
, UDC_EPCTL_ADDR
, UDC_EPCTL_MRXFLUSH
);
943 * pch_udc_ep_enable() - This api enables endpoint
944 * @regs: Reference to structure pch_udc_ep_regs
945 * @desc: endpoint descriptor
947 static void pch_udc_ep_enable(struct pch_udc_ep
*ep
,
948 struct pch_udc_cfg_data
*cfg
,
949 const struct usb_endpoint_descriptor
*desc
)
954 pch_udc_ep_set_trfr_type(ep
, desc
->bmAttributes
);
956 buff_size
= UDC_EPIN_BUFF_SIZE
;
958 buff_size
= UDC_EPOUT_BUFF_SIZE
;
959 pch_udc_ep_set_bufsz(ep
, buff_size
, ep
->in
);
960 pch_udc_ep_set_maxpkt(ep
, le16_to_cpu(desc
->wMaxPacketSize
));
961 pch_udc_ep_set_nak(ep
);
962 pch_udc_ep_fifo_flush(ep
, ep
->in
);
963 /* Configure the endpoint */
964 val
= ep
->num
<< UDC_CSR_NE_NUM_SHIFT
| ep
->in
<< UDC_CSR_NE_DIR_SHIFT
|
965 ((desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) <<
966 UDC_CSR_NE_TYPE_SHIFT
) |
967 (cfg
->cur_cfg
<< UDC_CSR_NE_CFG_SHIFT
) |
968 (cfg
->cur_intf
<< UDC_CSR_NE_INTF_SHIFT
) |
969 (cfg
->cur_alt
<< UDC_CSR_NE_ALT_SHIFT
) |
970 le16_to_cpu(desc
->wMaxPacketSize
) << UDC_CSR_NE_MAX_PKT_SHIFT
;
973 pch_udc_write_csr(ep
->dev
, val
, UDC_EPIN_IDX(ep
->num
));
975 pch_udc_write_csr(ep
->dev
, val
, UDC_EPOUT_IDX(ep
->num
));
979 * pch_udc_ep_disable() - This api disables endpoint
980 * @regs: Reference to structure pch_udc_ep_regs
982 static void pch_udc_ep_disable(struct pch_udc_ep
*ep
)
986 pch_udc_ep_writel(ep
, UDC_EPCTL_F
, UDC_EPCTL_ADDR
);
988 pch_udc_ep_writel(ep
, UDC_EPCTL_SNAK
, UDC_EPCTL_ADDR
);
989 pch_udc_ep_bit_set(ep
, UDC_EPSTS_ADDR
, UDC_EPSTS_IN
);
992 pch_udc_ep_writel(ep
, UDC_EPCTL_SNAK
, UDC_EPCTL_ADDR
);
994 /* reset desc pointer */
995 pch_udc_ep_writel(ep
, 0, UDC_DESPTR_ADDR
);
999 * pch_udc_wait_ep_stall() - Wait EP stall.
1000 * @dev: Reference to pch_udc_dev structure
1002 static void pch_udc_wait_ep_stall(struct pch_udc_ep
*ep
)
1004 unsigned int count
= 10000;
1006 /* Wait till idle */
1007 while ((pch_udc_read_ep_control(ep
) & UDC_EPCTL_S
) && --count
)
1010 dev_err(&ep
->dev
->pdev
->dev
, "%s: wait error\n", __func__
);
1014 * pch_udc_init() - This API initializes usb device controller
1015 * @dev: Rreference to pch_udc_regs structure
1017 static void pch_udc_init(struct pch_udc_dev
*dev
)
1020 pr_err("%s: Invalid address\n", __func__
);
1023 /* Soft Reset and Reset PHY */
1024 pch_udc_writel(dev
, UDC_SRST
, UDC_SRST_ADDR
);
1025 pch_udc_writel(dev
, UDC_SRST
| UDC_PSRST
, UDC_SRST_ADDR
);
1027 pch_udc_writel(dev
, UDC_SRST
, UDC_SRST_ADDR
);
1028 pch_udc_writel(dev
, 0x00, UDC_SRST_ADDR
);
1030 /* mask and clear all device interrupts */
1031 pch_udc_bit_set(dev
, UDC_DEVIRQMSK_ADDR
, UDC_DEVINT_MSK
);
1032 pch_udc_bit_set(dev
, UDC_DEVIRQSTS_ADDR
, UDC_DEVINT_MSK
);
1034 /* mask and clear all ep interrupts */
1035 pch_udc_bit_set(dev
, UDC_EPIRQMSK_ADDR
, UDC_EPINT_MSK_DISABLE_ALL
);
1036 pch_udc_bit_set(dev
, UDC_EPIRQSTS_ADDR
, UDC_EPINT_MSK_DISABLE_ALL
);
1038 /* enable dynamic CSR programmingi, self powered and device speed */
1040 pch_udc_bit_set(dev
, UDC_DEVCFG_ADDR
, UDC_DEVCFG_CSR_PRG
|
1041 UDC_DEVCFG_SP
| UDC_DEVCFG_SPD_FS
);
1042 else /* defaul high speed */
1043 pch_udc_bit_set(dev
, UDC_DEVCFG_ADDR
, UDC_DEVCFG_CSR_PRG
|
1044 UDC_DEVCFG_SP
| UDC_DEVCFG_SPD_HS
);
1045 pch_udc_bit_set(dev
, UDC_DEVCTL_ADDR
,
1046 (PCH_UDC_THLEN
<< UDC_DEVCTL_THLEN_SHIFT
) |
1047 (PCH_UDC_BRLEN
<< UDC_DEVCTL_BRLEN_SHIFT
) |
1048 UDC_DEVCTL_MODE
| UDC_DEVCTL_BREN
|
1053 * pch_udc_exit() - This API exit usb device controller
1054 * @dev: Reference to pch_udc_regs structure
1056 static void pch_udc_exit(struct pch_udc_dev
*dev
)
1058 /* mask all device interrupts */
1059 pch_udc_bit_set(dev
, UDC_DEVIRQMSK_ADDR
, UDC_DEVINT_MSK
);
1060 /* mask all ep interrupts */
1061 pch_udc_bit_set(dev
, UDC_EPIRQMSK_ADDR
, UDC_EPINT_MSK_DISABLE_ALL
);
1062 /* put device in disconnected state */
1063 pch_udc_set_disconnect(dev
);
1067 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1068 * @gadget: Reference to the gadget driver
1072 * -EINVAL: If the gadget passed is NULL
1074 static int pch_udc_pcd_get_frame(struct usb_gadget
*gadget
)
1076 struct pch_udc_dev
*dev
;
1080 dev
= container_of(gadget
, struct pch_udc_dev
, gadget
);
1081 return pch_udc_get_frame(dev
);
1085 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1086 * @gadget: Reference to the gadget driver
1090 * -EINVAL: If the gadget passed is NULL
1092 static int pch_udc_pcd_wakeup(struct usb_gadget
*gadget
)
1094 struct pch_udc_dev
*dev
;
1095 unsigned long flags
;
1099 dev
= container_of(gadget
, struct pch_udc_dev
, gadget
);
1100 spin_lock_irqsave(&dev
->lock
, flags
);
1101 pch_udc_rmt_wakeup(dev
);
1102 spin_unlock_irqrestore(&dev
->lock
, flags
);
1107 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1108 * is self powered or not
1109 * @gadget: Reference to the gadget driver
1110 * @value: Specifies self powered or not
1114 * -EINVAL: If the gadget passed is NULL
1116 static int pch_udc_pcd_selfpowered(struct usb_gadget
*gadget
, int value
)
1118 struct pch_udc_dev
*dev
;
1122 dev
= container_of(gadget
, struct pch_udc_dev
, gadget
);
1124 pch_udc_set_selfpowered(dev
);
1126 pch_udc_clear_selfpowered(dev
);
1131 * pch_udc_pcd_pullup() - This API is invoked to make the device
1132 * visible/invisible to the host
1133 * @gadget: Reference to the gadget driver
1134 * @is_on: Specifies whether the pull up is made active or inactive
1138 * -EINVAL: If the gadget passed is NULL
1140 static int pch_udc_pcd_pullup(struct usb_gadget
*gadget
, int is_on
)
1142 struct pch_udc_dev
*dev
;
1146 dev
= container_of(gadget
, struct pch_udc_dev
, gadget
);
1147 pch_udc_vbus_session(dev
, is_on
);
1152 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1153 * transceiver (or GPIO) that
1154 * detects a VBUS power session starting/ending
1155 * @gadget: Reference to the gadget driver
1156 * @is_active: specifies whether the session is starting or ending
1160 * -EINVAL: If the gadget passed is NULL
1162 static int pch_udc_pcd_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1164 struct pch_udc_dev
*dev
;
1168 dev
= container_of(gadget
, struct pch_udc_dev
, gadget
);
1169 pch_udc_vbus_session(dev
, is_active
);
1174 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1175 * SET_CONFIGURATION calls to
1176 * specify how much power the device can consume
1177 * @gadget: Reference to the gadget driver
1178 * @mA: specifies the current limit in 2mA unit
1181 * -EINVAL: If the gadget passed is NULL
1184 static int pch_udc_pcd_vbus_draw(struct usb_gadget
*gadget
, unsigned int mA
)
1189 static const struct usb_gadget_ops pch_udc_ops
= {
1190 .get_frame
= pch_udc_pcd_get_frame
,
1191 .wakeup
= pch_udc_pcd_wakeup
,
1192 .set_selfpowered
= pch_udc_pcd_selfpowered
,
1193 .pullup
= pch_udc_pcd_pullup
,
1194 .vbus_session
= pch_udc_pcd_vbus_session
,
1195 .vbus_draw
= pch_udc_pcd_vbus_draw
,
1199 * complete_req() - This API is invoked from the driver when processing
1200 * of a request is complete
1201 * @ep: Reference to the endpoint structure
1202 * @req: Reference to the request structure
1203 * @status: Indicates the success/failure of completion
1205 static void complete_req(struct pch_udc_ep
*ep
, struct pch_udc_request
*req
,
1208 struct pch_udc_dev
*dev
;
1209 unsigned halted
= ep
->halted
;
1211 list_del_init(&req
->queue
);
1213 /* set new status if pending */
1214 if (req
->req
.status
== -EINPROGRESS
)
1215 req
->req
.status
= status
;
1217 status
= req
->req
.status
;
1220 if (req
->dma_mapped
) {
1222 dma_unmap_single(&dev
->pdev
->dev
, req
->req
.dma
,
1223 req
->req
.length
, DMA_TO_DEVICE
);
1225 dma_unmap_single(&dev
->pdev
->dev
, req
->req
.dma
,
1226 req
->req
.length
, DMA_FROM_DEVICE
);
1227 req
->dma_mapped
= 0;
1228 req
->req
.dma
= DMA_ADDR_INVALID
;
1231 spin_unlock(&dev
->lock
);
1233 pch_udc_ep_clear_rrdy(ep
);
1234 req
->req
.complete(&ep
->ep
, &req
->req
);
1235 spin_lock(&dev
->lock
);
1236 ep
->halted
= halted
;
1240 * empty_req_queue() - This API empties the request queue of an endpoint
1241 * @ep: Reference to the endpoint structure
1243 static void empty_req_queue(struct pch_udc_ep
*ep
)
1245 struct pch_udc_request
*req
;
1248 while (!list_empty(&ep
->queue
)) {
1249 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
1250 complete_req(ep
, req
, -ESHUTDOWN
); /* Remove from list */
1255 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1257 * @dev Reference to the driver structure
1258 * @req Reference to the request to be freed
1263 static void pch_udc_free_dma_chain(struct pch_udc_dev
*dev
,
1264 struct pch_udc_request
*req
)
1266 struct pch_udc_data_dma_desc
*td
= req
->td_data
;
1267 unsigned i
= req
->chain_len
;
1269 for (; i
> 1; --i
) {
1270 dma_addr_t addr
= (dma_addr_t
)td
->next
;
1271 /* do not free first desc., will be done by free for request */
1272 td
= phys_to_virt(addr
);
1273 pci_pool_free(dev
->data_requests
, td
, addr
);
1278 * pch_udc_create_dma_chain() - This function creates or reinitializes
1280 * @ep: Reference to the endpoint structure
1281 * @req: Reference to the request
1282 * @buf_len: The buffer length
1283 * @gfp_flags: Flags to be used while mapping the data buffer
1287 * -ENOMEM: pci_pool_alloc invocation fails
1289 static int pch_udc_create_dma_chain(struct pch_udc_ep
*ep
,
1290 struct pch_udc_request
*req
,
1291 unsigned long buf_len
,
1294 struct pch_udc_data_dma_desc
*td
= req
->td_data
, *last
;
1295 unsigned long bytes
= req
->req
.length
, i
= 0;
1296 dma_addr_t dma_addr
;
1299 if (req
->chain_len
> 1)
1300 pch_udc_free_dma_chain(ep
->dev
, req
);
1302 for (; ; bytes
-= buf_len
, ++len
) {
1304 td
->status
= PCH_UDC_BS_HST_BSY
| min(buf_len
, bytes
);
1306 td
->status
= PCH_UDC_BS_HST_BSY
;
1308 if (bytes
<= buf_len
)
1312 td
= pci_pool_alloc(ep
->dev
->data_requests
, gfp_flags
,
1318 td
->dataptr
= req
->req
.dma
+ i
;
1319 last
->next
= dma_addr
;
1322 req
->td_data_last
= td
;
1323 td
->status
|= PCH_UDC_DMA_LAST
;
1324 td
->next
= req
->td_data_phys
;
1325 req
->chain_len
= len
;
1330 req
->chain_len
= len
;
1331 pch_udc_free_dma_chain(ep
->dev
, req
);
1338 * prepare_dma() - This function creates and initializes the DMA chain
1340 * @ep: Reference to the endpoint structure
1341 * @req: Reference to the request
1342 * @gfp: Flag to be used while mapping the data buffer
1346 * Other 0: linux error number on failure
1348 static int prepare_dma(struct pch_udc_ep
*ep
, struct pch_udc_request
*req
,
1353 req
->td_data
->dataptr
= req
->req
.dma
;
1354 req
->td_data
->status
|= PCH_UDC_DMA_LAST
;
1355 /* Allocate and create a DMA chain */
1356 retval
= pch_udc_create_dma_chain(ep
, req
, ep
->ep
.maxpacket
, gfp
);
1358 pr_err("%s: could not create DMA chain: %d\n",
1364 if (req
->req
.length
<= ep
->ep
.maxpacket
)
1365 req
->td_data
->status
= PCH_UDC_DMA_LAST
| PCH_UDC_BS_HST_BSY
|
1367 /* if bytes < max packet then tx bytes must
1368 * be written in packet per buffer mode
1370 if ((req
->req
.length
< ep
->ep
.maxpacket
) || !ep
->num
)
1371 req
->td_data
->status
= (req
->td_data
->status
&
1372 ~PCH_UDC_RXTX_BYTES
) | req
->req
.length
;
1373 req
->td_data
->status
= (req
->td_data
->status
&
1374 ~PCH_UDC_BUFF_STS
) | PCH_UDC_BS_HST_BSY
;
1379 * process_zlp() - This function process zero length packets
1380 * from the gadget driver
1381 * @ep: Reference to the endpoint structure
1382 * @req: Reference to the request
1384 static void process_zlp(struct pch_udc_ep
*ep
, struct pch_udc_request
*req
)
1386 struct pch_udc_dev
*dev
= ep
->dev
;
1388 /* IN zlp's are handled by hardware */
1389 complete_req(ep
, req
, 0);
1391 /* if set_config or set_intf is waiting for ack by zlp
1394 if (dev
->set_cfg_not_acked
) {
1395 pch_udc_set_csr_done(dev
);
1396 dev
->set_cfg_not_acked
= 0;
1398 /* setup command is ACK'ed now by zlp */
1399 if (!dev
->stall
&& dev
->waiting_zlp_ack
) {
1400 pch_udc_ep_clear_nak(&(dev
->ep
[UDC_EP0IN_IDX
]));
1401 dev
->waiting_zlp_ack
= 0;
1406 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1407 * @ep: Reference to the endpoint structure
1408 * @req: Reference to the request structure
1410 static void pch_udc_start_rxrequest(struct pch_udc_ep
*ep
,
1411 struct pch_udc_request
*req
)
1413 struct pch_udc_data_dma_desc
*td_data
;
1415 pch_udc_clear_dma(ep
->dev
, DMA_DIR_RX
);
1416 td_data
= req
->td_data
;
1417 /* Set the status bits for all descriptors */
1419 td_data
->status
= (td_data
->status
& ~PCH_UDC_BUFF_STS
) |
1421 if ((td_data
->status
& PCH_UDC_DMA_LAST
) == PCH_UDC_DMA_LAST
)
1423 td_data
= phys_to_virt(td_data
->next
);
1425 /* Write the descriptor pointer */
1426 pch_udc_ep_set_ddptr(ep
, req
->td_data_phys
);
1428 pch_udc_enable_ep_interrupts(ep
->dev
, UDC_EPINT_OUT_EP0
<< ep
->num
);
1429 pch_udc_set_dma(ep
->dev
, DMA_DIR_RX
);
1430 pch_udc_ep_clear_nak(ep
);
1431 pch_udc_ep_set_rrdy(ep
);
1435 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1436 * from gadget driver
1437 * @usbep: Reference to the USB endpoint structure
1438 * @desc: Reference to the USB endpoint descriptor structure
1445 static int pch_udc_pcd_ep_enable(struct usb_ep
*usbep
,
1446 const struct usb_endpoint_descriptor
*desc
)
1448 struct pch_udc_ep
*ep
;
1449 struct pch_udc_dev
*dev
;
1450 unsigned long iflags
;
1452 if (!usbep
|| (usbep
->name
== ep0_string
) || !desc
||
1453 (desc
->bDescriptorType
!= USB_DT_ENDPOINT
) || !desc
->wMaxPacketSize
)
1456 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1458 if (!dev
->driver
|| (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
))
1460 spin_lock_irqsave(&dev
->lock
, iflags
);
1463 pch_udc_ep_enable(ep
, &ep
->dev
->cfg_data
, desc
);
1464 ep
->ep
.maxpacket
= le16_to_cpu(desc
->wMaxPacketSize
);
1465 pch_udc_enable_ep_interrupts(ep
->dev
, PCH_UDC_EPINT(ep
->in
, ep
->num
));
1466 spin_unlock_irqrestore(&dev
->lock
, iflags
);
1471 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1472 * from gadget driver
1473 * @usbep Reference to the USB endpoint structure
1479 static int pch_udc_pcd_ep_disable(struct usb_ep
*usbep
)
1481 struct pch_udc_ep
*ep
;
1482 struct pch_udc_dev
*dev
;
1483 unsigned long iflags
;
1488 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1490 if ((usbep
->name
== ep0_string
) || !ep
->desc
)
1493 spin_lock_irqsave(&ep
->dev
->lock
, iflags
);
1494 empty_req_queue(ep
);
1496 pch_udc_ep_disable(ep
);
1497 pch_udc_disable_ep_interrupts(ep
->dev
, PCH_UDC_EPINT(ep
->in
, ep
->num
));
1499 INIT_LIST_HEAD(&ep
->queue
);
1500 spin_unlock_irqrestore(&ep
->dev
->lock
, iflags
);
1505 * pch_udc_alloc_request() - This function allocates request structure.
1506 * It is called by gadget driver
1507 * @usbep: Reference to the USB endpoint structure
1508 * @gfp: Flag to be used while allocating memory
1512 * Allocated address: Success
1514 static struct usb_request
*pch_udc_alloc_request(struct usb_ep
*usbep
,
1517 struct pch_udc_request
*req
;
1518 struct pch_udc_ep
*ep
;
1519 struct pch_udc_data_dma_desc
*dma_desc
;
1520 struct pch_udc_dev
*dev
;
1524 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1526 req
= kzalloc(sizeof *req
, gfp
);
1529 req
->req
.dma
= DMA_ADDR_INVALID
;
1530 INIT_LIST_HEAD(&req
->queue
);
1531 if (!ep
->dev
->dma_addr
)
1533 /* ep0 in requests are allocated from data pool here */
1534 dma_desc
= pci_pool_alloc(ep
->dev
->data_requests
, gfp
,
1535 &req
->td_data_phys
);
1536 if (NULL
== dma_desc
) {
1540 /* prevent from using desc. - set HOST BUSY */
1541 dma_desc
->status
|= PCH_UDC_BS_HST_BSY
;
1542 dma_desc
->dataptr
= __constant_cpu_to_le32(DMA_ADDR_INVALID
);
1543 req
->td_data
= dma_desc
;
1544 req
->td_data_last
= dma_desc
;
1550 * pch_udc_free_request() - This function frees request structure.
1551 * It is called by gadget driver
1552 * @usbep: Reference to the USB endpoint structure
1553 * @usbreq: Reference to the USB request
1555 static void pch_udc_free_request(struct usb_ep
*usbep
,
1556 struct usb_request
*usbreq
)
1558 struct pch_udc_ep
*ep
;
1559 struct pch_udc_request
*req
;
1560 struct pch_udc_dev
*dev
;
1562 if (!usbep
|| !usbreq
)
1564 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1565 req
= container_of(usbreq
, struct pch_udc_request
, req
);
1567 if (!list_empty(&req
->queue
))
1568 dev_err(&dev
->pdev
->dev
, "%s: %s req=0x%p queue not empty\n",
1569 __func__
, usbep
->name
, req
);
1570 if (req
->td_data
!= NULL
) {
1571 if (req
->chain_len
> 1)
1572 pch_udc_free_dma_chain(ep
->dev
, req
);
1573 pci_pool_free(ep
->dev
->data_requests
, req
->td_data
,
1580 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1582 * @usbep: Reference to the USB endpoint structure
1583 * @usbreq: Reference to the USB request
1584 * @gfp: Flag to be used while mapping the data buffer
1588 * linux error number: Failure
1590 static int pch_udc_pcd_queue(struct usb_ep
*usbep
, struct usb_request
*usbreq
,
1594 struct pch_udc_ep
*ep
;
1595 struct pch_udc_dev
*dev
;
1596 struct pch_udc_request
*req
;
1597 unsigned long iflags
;
1599 if (!usbep
|| !usbreq
|| !usbreq
->complete
|| !usbreq
->buf
)
1601 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1603 if (!ep
->desc
&& ep
->num
)
1605 req
= container_of(usbreq
, struct pch_udc_request
, req
);
1606 if (!list_empty(&req
->queue
))
1608 if (!dev
->driver
|| (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
))
1610 spin_lock_irqsave(&ep
->dev
->lock
, iflags
);
1611 /* map the buffer for dma */
1612 if (usbreq
->length
&&
1613 ((usbreq
->dma
== DMA_ADDR_INVALID
) || !usbreq
->dma
)) {
1615 usbreq
->dma
= dma_map_single(&dev
->pdev
->dev
,
1620 usbreq
->dma
= dma_map_single(&dev
->pdev
->dev
,
1624 req
->dma_mapped
= 1;
1626 if (usbreq
->length
> 0) {
1627 retval
= prepare_dma(ep
, req
, GFP_ATOMIC
);
1632 usbreq
->status
= -EINPROGRESS
;
1634 if (list_empty(&ep
->queue
) && !ep
->halted
) {
1635 /* no pending transfer, so start this req */
1636 if (!usbreq
->length
) {
1637 process_zlp(ep
, req
);
1642 pch_udc_start_rxrequest(ep
, req
);
1645 * For IN trfr the descriptors will be programmed and
1646 * P bit will be set when
1647 * we get an IN token
1649 pch_udc_wait_ep_stall(ep
);
1650 pch_udc_ep_clear_nak(ep
);
1651 pch_udc_enable_ep_interrupts(ep
->dev
, (1 << ep
->num
));
1654 /* Now add this request to the ep's pending requests */
1656 list_add_tail(&req
->queue
, &ep
->queue
);
1659 spin_unlock_irqrestore(&dev
->lock
, iflags
);
1664 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1665 * It is called by gadget driver
1666 * @usbep: Reference to the USB endpoint structure
1667 * @usbreq: Reference to the USB request
1671 * linux error number: Failure
1673 static int pch_udc_pcd_dequeue(struct usb_ep
*usbep
,
1674 struct usb_request
*usbreq
)
1676 struct pch_udc_ep
*ep
;
1677 struct pch_udc_request
*req
;
1678 struct pch_udc_dev
*dev
;
1679 unsigned long flags
;
1682 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1684 if (!usbep
|| !usbreq
|| (!ep
->desc
&& ep
->num
))
1686 req
= container_of(usbreq
, struct pch_udc_request
, req
);
1687 spin_lock_irqsave(&ep
->dev
->lock
, flags
);
1688 /* make sure it's still queued on this endpoint */
1689 list_for_each_entry(req
, &ep
->queue
, queue
) {
1690 if (&req
->req
== usbreq
) {
1691 pch_udc_ep_set_nak(ep
);
1692 if (!list_empty(&req
->queue
))
1693 complete_req(ep
, req
, -ECONNRESET
);
1698 spin_unlock_irqrestore(&ep
->dev
->lock
, flags
);
1703 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1705 * @usbep: Reference to the USB endpoint structure
1706 * @halt: Specifies whether to set or clear the feature
1710 * linux error number: Failure
1712 static int pch_udc_pcd_set_halt(struct usb_ep
*usbep
, int halt
)
1714 struct pch_udc_ep
*ep
;
1715 struct pch_udc_dev
*dev
;
1716 unsigned long iflags
;
1721 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1723 if (!ep
->desc
&& !ep
->num
)
1725 if (!ep
->dev
->driver
|| (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
))
1727 spin_lock_irqsave(&udc_stall_spinlock
, iflags
);
1728 if (list_empty(&ep
->queue
)) {
1730 if (ep
->num
== PCH_UDC_EP0
)
1732 pch_udc_ep_set_stall(ep
);
1733 pch_udc_enable_ep_interrupts(ep
->dev
,
1734 PCH_UDC_EPINT(ep
->in
,
1737 pch_udc_ep_clear_stall(ep
);
1743 spin_unlock_irqrestore(&udc_stall_spinlock
, iflags
);
1748 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1750 * @usbep: Reference to the USB endpoint structure
1751 * @halt: Specifies whether to set or clear the feature
1755 * linux error number: Failure
1757 static int pch_udc_pcd_set_wedge(struct usb_ep
*usbep
)
1759 struct pch_udc_ep
*ep
;
1760 struct pch_udc_dev
*dev
;
1761 unsigned long iflags
;
1766 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1768 if (!ep
->desc
&& !ep
->num
)
1770 if (!ep
->dev
->driver
|| (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
))
1772 spin_lock_irqsave(&udc_stall_spinlock
, iflags
);
1773 if (!list_empty(&ep
->queue
)) {
1776 if (ep
->num
== PCH_UDC_EP0
)
1778 pch_udc_ep_set_stall(ep
);
1779 pch_udc_enable_ep_interrupts(ep
->dev
,
1780 PCH_UDC_EPINT(ep
->in
, ep
->num
));
1781 ep
->dev
->prot_stall
= 1;
1784 spin_unlock_irqrestore(&udc_stall_spinlock
, iflags
);
1789 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1790 * @usbep: Reference to the USB endpoint structure
1792 static void pch_udc_pcd_fifo_flush(struct usb_ep
*usbep
)
1794 struct pch_udc_ep
*ep
;
1799 ep
= container_of(usbep
, struct pch_udc_ep
, ep
);
1800 if (ep
->desc
|| !ep
->num
)
1801 pch_udc_ep_fifo_flush(ep
, ep
->in
);
1804 static const struct usb_ep_ops pch_udc_ep_ops
= {
1805 .enable
= pch_udc_pcd_ep_enable
,
1806 .disable
= pch_udc_pcd_ep_disable
,
1807 .alloc_request
= pch_udc_alloc_request
,
1808 .free_request
= pch_udc_free_request
,
1809 .queue
= pch_udc_pcd_queue
,
1810 .dequeue
= pch_udc_pcd_dequeue
,
1811 .set_halt
= pch_udc_pcd_set_halt
,
1812 .set_wedge
= pch_udc_pcd_set_wedge
,
1813 .fifo_status
= NULL
,
1814 .fifo_flush
= pch_udc_pcd_fifo_flush
,
1818 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
1819 * @td_stp: Reference to the SETP buffer structure
1821 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc
*td_stp
)
1823 static u32 pky_marker
;
1827 td_stp
->reserved
= ++pky_marker
;
1828 memset(&td_stp
->request
, 0xFF, sizeof td_stp
->request
);
1829 td_stp
->status
= PCH_UDC_BS_HST_RDY
;
1833 * pch_udc_start_next_txrequest() - This function starts
1834 * the next transmission requirement
1835 * @ep: Reference to the endpoint structure
1837 static void pch_udc_start_next_txrequest(struct pch_udc_ep
*ep
)
1839 struct pch_udc_request
*req
;
1840 struct pch_udc_data_dma_desc
*td_data
;
1842 if (pch_udc_read_ep_control(ep
) & UDC_EPCTL_P
)
1845 if (list_empty(&ep
->queue
))
1849 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
1854 pch_udc_wait_ep_stall(ep
);
1856 pch_udc_ep_set_ddptr(ep
, 0);
1857 td_data
= req
->td_data
;
1859 td_data
->status
= (td_data
->status
& ~PCH_UDC_BUFF_STS
) |
1861 if ((td_data
->status
& PCH_UDC_DMA_LAST
) == PCH_UDC_DMA_LAST
)
1863 td_data
= phys_to_virt(td_data
->next
);
1865 pch_udc_ep_set_ddptr(ep
, req
->td_data_phys
);
1866 pch_udc_set_dma(ep
->dev
, DMA_DIR_TX
);
1867 pch_udc_ep_set_pd(ep
);
1868 pch_udc_enable_ep_interrupts(ep
->dev
, PCH_UDC_EPINT(ep
->in
, ep
->num
));
1869 pch_udc_ep_clear_nak(ep
);
1873 * pch_udc_complete_transfer() - This function completes a transfer
1874 * @ep: Reference to the endpoint structure
1876 static void pch_udc_complete_transfer(struct pch_udc_ep
*ep
)
1878 struct pch_udc_request
*req
;
1879 struct pch_udc_dev
*dev
= ep
->dev
;
1881 if (list_empty(&ep
->queue
))
1883 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
1884 if ((req
->td_data_last
->status
& PCH_UDC_BUFF_STS
) !=
1885 PCH_UDC_BS_DMA_DONE
)
1887 if ((req
->td_data_last
->status
& PCH_UDC_RXTX_STS
) !=
1889 dev_err(&dev
->pdev
->dev
, "Invalid RXTX status (0x%08x) "
1890 "epstatus=0x%08x\n",
1891 (req
->td_data_last
->status
& PCH_UDC_RXTX_STS
),
1896 req
->req
.actual
= req
->req
.length
;
1897 req
->td_data_last
->status
= PCH_UDC_BS_HST_BSY
| PCH_UDC_DMA_LAST
;
1898 req
->td_data
->status
= PCH_UDC_BS_HST_BSY
| PCH_UDC_DMA_LAST
;
1899 complete_req(ep
, req
, 0);
1901 if (!list_empty(&ep
->queue
)) {
1902 pch_udc_wait_ep_stall(ep
);
1903 pch_udc_ep_clear_nak(ep
);
1904 pch_udc_enable_ep_interrupts(ep
->dev
,
1905 PCH_UDC_EPINT(ep
->in
, ep
->num
));
1907 pch_udc_disable_ep_interrupts(ep
->dev
,
1908 PCH_UDC_EPINT(ep
->in
, ep
->num
));
1913 * pch_udc_complete_receiver() - This function completes a receiver
1914 * @ep: Reference to the endpoint structure
1916 static void pch_udc_complete_receiver(struct pch_udc_ep
*ep
)
1918 struct pch_udc_request
*req
;
1919 struct pch_udc_dev
*dev
= ep
->dev
;
1922 if (list_empty(&ep
->queue
))
1926 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
1927 if ((req
->td_data_last
->status
& PCH_UDC_BUFF_STS
) !=
1928 PCH_UDC_BS_DMA_DONE
)
1930 pch_udc_clear_dma(ep
->dev
, DMA_DIR_RX
);
1931 pch_udc_ep_set_ddptr(ep
, 0);
1932 if ((req
->td_data_last
->status
& PCH_UDC_RXTX_STS
) !=
1934 dev_err(&dev
->pdev
->dev
, "Invalid RXTX status (0x%08x) "
1935 "epstatus=0x%08x\n",
1936 (req
->td_data_last
->status
& PCH_UDC_RXTX_STS
),
1940 count
= req
->td_data_last
->status
& PCH_UDC_RXTX_BYTES
;
1942 /* on 64k packets the RXBYTES field is zero */
1943 if (!count
&& (req
->req
.length
== UDC_DMA_MAXPACKET
))
1944 count
= UDC_DMA_MAXPACKET
;
1945 req
->td_data
->status
|= PCH_UDC_DMA_LAST
;
1946 req
->td_data_last
->status
|= PCH_UDC_BS_HST_BSY
;
1949 req
->req
.actual
= count
;
1950 complete_req(ep
, req
, 0);
1951 /* If there is a new/failed requests try that now */
1952 if (!list_empty(&ep
->queue
)) {
1953 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
1954 pch_udc_start_rxrequest(ep
, req
);
1959 * pch_udc_svc_data_in() - This function process endpoint interrupts
1961 * @dev: Reference to the device structure
1962 * @ep_num: Endpoint that generated the interrupt
1964 static void pch_udc_svc_data_in(struct pch_udc_dev
*dev
, int ep_num
)
1967 struct pch_udc_ep
*ep
;
1969 ep
= &dev
->ep
[UDC_EPIN_IDX(ep_num
)];
1973 if (!(epsts
& (UDC_EPSTS_IN
| UDC_EPSTS_BNA
| UDC_EPSTS_HE
|
1974 UDC_EPSTS_TDC
| UDC_EPSTS_RCS
| UDC_EPSTS_TXEMPTY
|
1975 UDC_EPSTS_RSS
| UDC_EPSTS_XFERDONE
)))
1977 if ((epsts
& UDC_EPSTS_BNA
))
1979 if (epsts
& UDC_EPSTS_HE
)
1981 if (epsts
& UDC_EPSTS_RSS
) {
1982 pch_udc_ep_set_stall(ep
);
1983 pch_udc_enable_ep_interrupts(ep
->dev
,
1984 PCH_UDC_EPINT(ep
->in
, ep
->num
));
1986 if (epsts
& UDC_EPSTS_RCS
) {
1987 if (!dev
->prot_stall
) {
1988 pch_udc_ep_clear_stall(ep
);
1990 pch_udc_ep_set_stall(ep
);
1991 pch_udc_enable_ep_interrupts(ep
->dev
,
1992 PCH_UDC_EPINT(ep
->in
, ep
->num
));
1995 if (epsts
& UDC_EPSTS_TDC
)
1996 pch_udc_complete_transfer(ep
);
1997 /* On IN interrupt, provide data if we have any */
1998 if ((epsts
& UDC_EPSTS_IN
) && !(epsts
& UDC_EPSTS_RSS
) &&
1999 !(epsts
& UDC_EPSTS_TDC
) && !(epsts
& UDC_EPSTS_TXEMPTY
))
2000 pch_udc_start_next_txrequest(ep
);
2004 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2005 * @dev: Reference to the device structure
2006 * @ep_num: Endpoint that generated the interrupt
2008 static void pch_udc_svc_data_out(struct pch_udc_dev
*dev
, int ep_num
)
2011 struct pch_udc_ep
*ep
;
2012 struct pch_udc_request
*req
= NULL
;
2014 ep
= &dev
->ep
[UDC_EPOUT_IDX(ep_num
)];
2018 if ((epsts
& UDC_EPSTS_BNA
) && (!list_empty(&ep
->queue
))) {
2020 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
,
2022 if ((req
->td_data_last
->status
& PCH_UDC_BUFF_STS
) !=
2023 PCH_UDC_BS_DMA_DONE
) {
2024 if (!req
->dma_going
)
2025 pch_udc_start_rxrequest(ep
, req
);
2029 if (epsts
& UDC_EPSTS_HE
)
2031 if (epsts
& UDC_EPSTS_RSS
) {
2032 pch_udc_ep_set_stall(ep
);
2033 pch_udc_enable_ep_interrupts(ep
->dev
,
2034 PCH_UDC_EPINT(ep
->in
, ep
->num
));
2036 if (epsts
& UDC_EPSTS_RCS
) {
2037 if (!dev
->prot_stall
) {
2038 pch_udc_ep_clear_stall(ep
);
2040 pch_udc_ep_set_stall(ep
);
2041 pch_udc_enable_ep_interrupts(ep
->dev
,
2042 PCH_UDC_EPINT(ep
->in
, ep
->num
));
2045 if (((epsts
& UDC_EPSTS_OUT_MASK
) >> UDC_EPSTS_OUT_SHIFT
) ==
2046 UDC_EPSTS_OUT_DATA
) {
2047 if (ep
->dev
->prot_stall
== 1) {
2048 pch_udc_ep_set_stall(ep
);
2049 pch_udc_enable_ep_interrupts(ep
->dev
,
2050 PCH_UDC_EPINT(ep
->in
, ep
->num
));
2052 pch_udc_complete_receiver(ep
);
2055 if (list_empty(&ep
->queue
))
2056 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2060 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2061 * @dev: Reference to the device structure
2063 static void pch_udc_svc_control_in(struct pch_udc_dev
*dev
)
2066 struct pch_udc_ep
*ep
;
2067 struct pch_udc_ep
*ep_out
;
2069 ep
= &dev
->ep
[UDC_EP0IN_IDX
];
2070 ep_out
= &dev
->ep
[UDC_EP0OUT_IDX
];
2074 if (!(epsts
& (UDC_EPSTS_IN
| UDC_EPSTS_BNA
| UDC_EPSTS_HE
|
2075 UDC_EPSTS_TDC
| UDC_EPSTS_RCS
| UDC_EPSTS_TXEMPTY
|
2076 UDC_EPSTS_XFERDONE
)))
2078 if ((epsts
& UDC_EPSTS_BNA
))
2080 if (epsts
& UDC_EPSTS_HE
)
2082 if ((epsts
& UDC_EPSTS_TDC
) && (!dev
->stall
)) {
2083 pch_udc_complete_transfer(ep
);
2084 pch_udc_clear_dma(dev
, DMA_DIR_RX
);
2085 ep_out
->td_data
->status
= (ep_out
->td_data
->status
&
2086 ~PCH_UDC_BUFF_STS
) |
2088 pch_udc_ep_clear_nak(ep_out
);
2089 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2090 pch_udc_ep_set_rrdy(ep_out
);
2092 /* On IN interrupt, provide data if we have any */
2093 if ((epsts
& UDC_EPSTS_IN
) && !(epsts
& UDC_EPSTS_TDC
) &&
2094 !(epsts
& UDC_EPSTS_TXEMPTY
))
2095 pch_udc_start_next_txrequest(ep
);
2099 * pch_udc_svc_control_out() - Routine that handle Control
2100 * OUT endpoint interrupts
2101 * @dev: Reference to the device structure
2103 static void pch_udc_svc_control_out(struct pch_udc_dev
*dev
)
2106 int setup_supported
;
2107 struct pch_udc_ep
*ep
;
2109 ep
= &dev
->ep
[UDC_EP0OUT_IDX
];
2114 if (((stat
& UDC_EPSTS_OUT_MASK
) >> UDC_EPSTS_OUT_SHIFT
) ==
2115 UDC_EPSTS_OUT_SETUP
) {
2117 dev
->ep
[UDC_EP0IN_IDX
].halted
= 0;
2118 dev
->ep
[UDC_EP0OUT_IDX
].halted
= 0;
2119 dev
->setup_data
= ep
->td_stp
->request
;
2120 pch_udc_init_setup_buff(ep
->td_stp
);
2121 pch_udc_clear_dma(dev
, DMA_DIR_RX
);
2122 pch_udc_ep_fifo_flush(&(dev
->ep
[UDC_EP0IN_IDX
]),
2123 dev
->ep
[UDC_EP0IN_IDX
].in
);
2124 if ((dev
->setup_data
.bRequestType
& USB_DIR_IN
))
2125 dev
->gadget
.ep0
= &dev
->ep
[UDC_EP0IN_IDX
].ep
;
2127 dev
->gadget
.ep0
= &ep
->ep
;
2128 spin_unlock(&dev
->lock
);
2129 /* If Mass storage Reset */
2130 if ((dev
->setup_data
.bRequestType
== 0x21) &&
2131 (dev
->setup_data
.bRequest
== 0xFF))
2132 dev
->prot_stall
= 0;
2133 /* call gadget with setup data received */
2134 setup_supported
= dev
->driver
->setup(&dev
->gadget
,
2136 spin_lock(&dev
->lock
);
2138 if (dev
->setup_data
.bRequestType
& USB_DIR_IN
) {
2139 ep
->td_data
->status
= (ep
->td_data
->status
&
2140 ~PCH_UDC_BUFF_STS
) |
2142 pch_udc_ep_set_ddptr(ep
, ep
->td_data_phys
);
2144 /* ep0 in returns data on IN phase */
2145 if (setup_supported
>= 0 && setup_supported
<
2146 UDC_EP0IN_MAX_PKT_SIZE
) {
2147 pch_udc_ep_clear_nak(&(dev
->ep
[UDC_EP0IN_IDX
]));
2148 /* Gadget would have queued a request when
2149 * we called the setup */
2150 if (!(dev
->setup_data
.bRequestType
& USB_DIR_IN
)) {
2151 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2152 pch_udc_ep_clear_nak(ep
);
2154 } else if (setup_supported
< 0) {
2155 /* if unsupported request, then stall */
2156 pch_udc_ep_set_stall(&(dev
->ep
[UDC_EP0IN_IDX
]));
2157 pch_udc_enable_ep_interrupts(ep
->dev
,
2158 PCH_UDC_EPINT(ep
->in
, ep
->num
));
2160 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2162 dev
->waiting_zlp_ack
= 1;
2164 } else if ((((stat
& UDC_EPSTS_OUT_MASK
) >> UDC_EPSTS_OUT_SHIFT
) ==
2165 UDC_EPSTS_OUT_DATA
) && !dev
->stall
) {
2166 pch_udc_clear_dma(dev
, DMA_DIR_RX
);
2167 pch_udc_ep_set_ddptr(ep
, 0);
2168 if (!list_empty(&ep
->queue
)) {
2170 pch_udc_svc_data_out(dev
, PCH_UDC_EP0
);
2172 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2174 pch_udc_ep_set_rrdy(ep
);
2179 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2180 * and clears NAK status
2181 * @dev: Reference to the device structure
2182 * @ep_num: End point number
2184 static void pch_udc_postsvc_epinters(struct pch_udc_dev
*dev
, int ep_num
)
2186 struct pch_udc_ep
*ep
;
2187 struct pch_udc_request
*req
;
2189 ep
= &dev
->ep
[UDC_EPIN_IDX(ep_num
)];
2190 if (!list_empty(&ep
->queue
)) {
2191 req
= list_entry(ep
->queue
.next
, struct pch_udc_request
, queue
);
2192 pch_udc_enable_ep_interrupts(ep
->dev
,
2193 PCH_UDC_EPINT(ep
->in
, ep
->num
));
2194 pch_udc_ep_clear_nak(ep
);
2199 * pch_udc_read_all_epstatus() - This function read all endpoint status
2200 * @dev: Reference to the device structure
2201 * @ep_intr: Status of endpoint interrupt
2203 static void pch_udc_read_all_epstatus(struct pch_udc_dev
*dev
, u32 ep_intr
)
2206 struct pch_udc_ep
*ep
;
2208 for (i
= 0; i
< PCH_UDC_USED_EP_NUM
; i
++) {
2210 if (ep_intr
& (0x1 << i
)) {
2211 ep
= &dev
->ep
[UDC_EPIN_IDX(i
)];
2212 ep
->epsts
= pch_udc_read_ep_status(ep
);
2213 pch_udc_clear_ep_status(ep
, ep
->epsts
);
2216 if (ep_intr
& (0x10000 << i
)) {
2217 ep
= &dev
->ep
[UDC_EPOUT_IDX(i
)];
2218 ep
->epsts
= pch_udc_read_ep_status(ep
);
2219 pch_udc_clear_ep_status(ep
, ep
->epsts
);
2225 * pch_udc_activate_control_ep() - This function enables the control endpoints
2226 * for traffic after a reset
2227 * @dev: Reference to the device structure
2229 static void pch_udc_activate_control_ep(struct pch_udc_dev
*dev
)
2231 struct pch_udc_ep
*ep
;
2234 /* Setup the IN endpoint */
2235 ep
= &dev
->ep
[UDC_EP0IN_IDX
];
2236 pch_udc_clear_ep_control(ep
);
2237 pch_udc_ep_fifo_flush(ep
, ep
->in
);
2238 pch_udc_ep_set_bufsz(ep
, UDC_EP0IN_BUFF_SIZE
, ep
->in
);
2239 pch_udc_ep_set_maxpkt(ep
, UDC_EP0IN_MAX_PKT_SIZE
);
2240 /* Initialize the IN EP Descriptor */
2243 ep
->td_data_phys
= 0;
2244 ep
->td_stp_phys
= 0;
2246 /* Setup the OUT endpoint */
2247 ep
= &dev
->ep
[UDC_EP0OUT_IDX
];
2248 pch_udc_clear_ep_control(ep
);
2249 pch_udc_ep_fifo_flush(ep
, ep
->in
);
2250 pch_udc_ep_set_bufsz(ep
, UDC_EP0OUT_BUFF_SIZE
, ep
->in
);
2251 pch_udc_ep_set_maxpkt(ep
, UDC_EP0OUT_MAX_PKT_SIZE
);
2252 val
= UDC_EP0OUT_MAX_PKT_SIZE
<< UDC_CSR_NE_MAX_PKT_SHIFT
;
2253 pch_udc_write_csr(ep
->dev
, val
, UDC_EP0OUT_IDX
);
2255 /* Initialize the SETUP buffer */
2256 pch_udc_init_setup_buff(ep
->td_stp
);
2257 /* Write the pointer address of dma descriptor */
2258 pch_udc_ep_set_subptr(ep
, ep
->td_stp_phys
);
2259 /* Write the pointer address of Setup descriptor */
2260 pch_udc_ep_set_ddptr(ep
, ep
->td_data_phys
);
2262 /* Initialize the dma descriptor */
2263 ep
->td_data
->status
= PCH_UDC_DMA_LAST
;
2264 ep
->td_data
->dataptr
= dev
->dma_addr
;
2265 ep
->td_data
->next
= ep
->td_data_phys
;
2267 pch_udc_ep_clear_nak(ep
);
2272 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2273 * @dev: Reference to driver structure
2275 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev
*dev
)
2277 struct pch_udc_ep
*ep
;
2280 pch_udc_clear_dma(dev
, DMA_DIR_TX
);
2281 pch_udc_clear_dma(dev
, DMA_DIR_RX
);
2282 /* Mask all endpoint interrupts */
2283 pch_udc_disable_ep_interrupts(dev
, UDC_EPINT_MSK_DISABLE_ALL
);
2284 /* clear all endpoint interrupts */
2285 pch_udc_write_ep_interrupts(dev
, UDC_EPINT_MSK_DISABLE_ALL
);
2287 for (i
= 0; i
< PCH_UDC_EP_NUM
; i
++) {
2289 pch_udc_clear_ep_status(ep
, UDC_EPSTS_ALL_CLR_MASK
);
2290 pch_udc_clear_ep_control(ep
);
2291 pch_udc_ep_set_ddptr(ep
, 0);
2292 pch_udc_write_csr(ep
->dev
, 0x00, i
);
2295 dev
->prot_stall
= 0;
2296 dev
->waiting_zlp_ack
= 0;
2297 dev
->set_cfg_not_acked
= 0;
2299 /* disable ep to empty req queue. Skip the control EP's */
2300 for (i
= 0; i
< (PCH_UDC_USED_EP_NUM
*2); i
++) {
2302 pch_udc_ep_set_nak(ep
);
2303 pch_udc_ep_fifo_flush(ep
, ep
->in
);
2304 /* Complete request queue */
2305 empty_req_queue(ep
);
2307 if (dev
->driver
&& dev
->driver
->disconnect
)
2308 dev
->driver
->disconnect(&dev
->gadget
);
2312 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2314 * @dev: Reference to driver structure
2316 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev
*dev
)
2318 u32 dev_stat
, dev_speed
;
2319 u32 speed
= USB_SPEED_FULL
;
2321 dev_stat
= pch_udc_read_device_status(dev
);
2322 dev_speed
= (dev_stat
& UDC_DEVSTS_ENUM_SPEED_MASK
) >>
2323 UDC_DEVSTS_ENUM_SPEED_SHIFT
;
2324 switch (dev_speed
) {
2325 case UDC_DEVSTS_ENUM_SPEED_HIGH
:
2326 speed
= USB_SPEED_HIGH
;
2328 case UDC_DEVSTS_ENUM_SPEED_FULL
:
2329 speed
= USB_SPEED_FULL
;
2331 case UDC_DEVSTS_ENUM_SPEED_LOW
:
2332 speed
= USB_SPEED_LOW
;
2337 dev
->gadget
.speed
= speed
;
2338 pch_udc_activate_control_ep(dev
);
2339 pch_udc_enable_ep_interrupts(dev
, UDC_EPINT_IN_EP0
| UDC_EPINT_OUT_EP0
);
2340 pch_udc_set_dma(dev
, DMA_DIR_TX
);
2341 pch_udc_set_dma(dev
, DMA_DIR_RX
);
2342 pch_udc_ep_set_rrdy(&(dev
->ep
[UDC_EP0OUT_IDX
]));
2346 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2348 * @dev: Reference to driver structure
2350 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev
*dev
)
2352 u32 reg
, dev_stat
= 0;
2355 dev_stat
= pch_udc_read_device_status(dev
);
2356 dev
->cfg_data
.cur_intf
= (dev_stat
& UDC_DEVSTS_INTF_MASK
) >>
2357 UDC_DEVSTS_INTF_SHIFT
;
2358 dev
->cfg_data
.cur_alt
= (dev_stat
& UDC_DEVSTS_ALT_MASK
) >>
2359 UDC_DEVSTS_ALT_SHIFT
;
2360 dev
->set_cfg_not_acked
= 1;
2361 /* Construct the usb request for gadget driver and inform it */
2362 memset(&dev
->setup_data
, 0 , sizeof dev
->setup_data
);
2363 dev
->setup_data
.bRequest
= USB_REQ_SET_INTERFACE
;
2364 dev
->setup_data
.bRequestType
= USB_RECIP_INTERFACE
;
2365 dev
->setup_data
.wValue
= cpu_to_le16(dev
->cfg_data
.cur_alt
);
2366 dev
->setup_data
.wIndex
= cpu_to_le16(dev
->cfg_data
.cur_intf
);
2367 /* programm the Endpoint Cfg registers */
2368 /* Only one end point cfg register */
2369 reg
= pch_udc_read_csr(dev
, UDC_EP0OUT_IDX
);
2370 reg
= (reg
& ~UDC_CSR_NE_INTF_MASK
) |
2371 (dev
->cfg_data
.cur_intf
<< UDC_CSR_NE_INTF_SHIFT
);
2372 reg
= (reg
& ~UDC_CSR_NE_ALT_MASK
) |
2373 (dev
->cfg_data
.cur_alt
<< UDC_CSR_NE_ALT_SHIFT
);
2374 pch_udc_write_csr(dev
, reg
, UDC_EP0OUT_IDX
);
2375 for (i
= 0; i
< PCH_UDC_USED_EP_NUM
* 2; i
++) {
2376 /* clear stall bits */
2377 pch_udc_ep_clear_stall(&(dev
->ep
[i
]));
2378 dev
->ep
[i
].halted
= 0;
2381 spin_unlock(&dev
->lock
);
2382 ret
= dev
->driver
->setup(&dev
->gadget
, &dev
->setup_data
);
2383 spin_lock(&dev
->lock
);
2387 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2389 * @dev: Reference to driver structure
2391 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev
*dev
)
2394 u32 reg
, dev_stat
= 0;
2396 dev_stat
= pch_udc_read_device_status(dev
);
2397 dev
->set_cfg_not_acked
= 1;
2398 dev
->cfg_data
.cur_cfg
= (dev_stat
& UDC_DEVSTS_CFG_MASK
) >>
2399 UDC_DEVSTS_CFG_SHIFT
;
2400 /* make usb request for gadget driver */
2401 memset(&dev
->setup_data
, 0 , sizeof dev
->setup_data
);
2402 dev
->setup_data
.bRequest
= USB_REQ_SET_CONFIGURATION
;
2403 dev
->setup_data
.wValue
= cpu_to_le16(dev
->cfg_data
.cur_cfg
);
2404 /* program the NE registers */
2405 /* Only one end point cfg register */
2406 reg
= pch_udc_read_csr(dev
, UDC_EP0OUT_IDX
);
2407 reg
= (reg
& ~UDC_CSR_NE_CFG_MASK
) |
2408 (dev
->cfg_data
.cur_cfg
<< UDC_CSR_NE_CFG_SHIFT
);
2409 pch_udc_write_csr(dev
, reg
, UDC_EP0OUT_IDX
);
2410 for (i
= 0; i
< PCH_UDC_USED_EP_NUM
* 2; i
++) {
2411 /* clear stall bits */
2412 pch_udc_ep_clear_stall(&(dev
->ep
[i
]));
2413 dev
->ep
[i
].halted
= 0;
2417 /* call gadget zero with setup data received */
2418 spin_unlock(&dev
->lock
);
2419 ret
= dev
->driver
->setup(&dev
->gadget
, &dev
->setup_data
);
2420 spin_lock(&dev
->lock
);
2424 * pch_udc_dev_isr() - This function services device interrupts
2425 * by invoking appropriate routines.
2426 * @dev: Reference to the device structure
2427 * @dev_intr: The Device interrupt status.
2429 static void pch_udc_dev_isr(struct pch_udc_dev
*dev
, u32 dev_intr
)
2431 /* USB Reset Interrupt */
2432 if (dev_intr
& UDC_DEVINT_UR
)
2433 pch_udc_svc_ur_interrupt(dev
);
2434 /* Enumeration Done Interrupt */
2435 if (dev_intr
& UDC_DEVINT_ENUM
)
2436 pch_udc_svc_enum_interrupt(dev
);
2437 /* Set Interface Interrupt */
2438 if (dev_intr
& UDC_DEVINT_SI
)
2439 pch_udc_svc_intf_interrupt(dev
);
2440 /* Set Config Interrupt */
2441 if (dev_intr
& UDC_DEVINT_SC
)
2442 pch_udc_svc_cfg_interrupt(dev
);
2443 /* USB Suspend interrupt */
2444 if (dev_intr
& UDC_DEVINT_US
)
2445 dev_dbg(&dev
->pdev
->dev
, "USB_SUSPEND\n");
2446 /* Clear the SOF interrupt, if enabled */
2447 if (dev_intr
& UDC_DEVINT_SOF
)
2448 dev_dbg(&dev
->pdev
->dev
, "SOF\n");
2449 /* ES interrupt, IDLE > 3ms on the USB */
2450 if (dev_intr
& UDC_DEVINT_ES
)
2451 dev_dbg(&dev
->pdev
->dev
, "ES\n");
2452 /* RWKP interrupt */
2453 if (dev_intr
& UDC_DEVINT_RWKP
)
2454 dev_dbg(&dev
->pdev
->dev
, "RWKP\n");
2458 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2459 * @irq: Interrupt request number
2460 * @dev: Reference to the device structure
2462 static irqreturn_t
pch_udc_isr(int irq
, void *pdev
)
2464 struct pch_udc_dev
*dev
= (struct pch_udc_dev
*) pdev
;
2465 u32 dev_intr
, ep_intr
;
2468 dev_intr
= pch_udc_read_device_interrupts(dev
);
2469 ep_intr
= pch_udc_read_ep_interrupts(dev
);
2472 /* Clear device interrupts */
2473 pch_udc_write_device_interrupts(dev
, dev_intr
);
2475 /* Clear ep interrupts */
2476 pch_udc_write_ep_interrupts(dev
, ep_intr
);
2477 if (!dev_intr
&& !ep_intr
)
2479 spin_lock(&dev
->lock
);
2481 pch_udc_dev_isr(dev
, dev_intr
);
2483 pch_udc_read_all_epstatus(dev
, ep_intr
);
2484 /* Process Control In interrupts, if present */
2485 if (ep_intr
& UDC_EPINT_IN_EP0
) {
2486 pch_udc_svc_control_in(dev
);
2487 pch_udc_postsvc_epinters(dev
, 0);
2489 /* Process Control Out interrupts, if present */
2490 if (ep_intr
& UDC_EPINT_OUT_EP0
)
2491 pch_udc_svc_control_out(dev
);
2492 /* Process data in end point interrupts */
2493 for (i
= 1; i
< PCH_UDC_USED_EP_NUM
; i
++) {
2494 if (ep_intr
& (1 << i
)) {
2495 pch_udc_svc_data_in(dev
, i
);
2496 pch_udc_postsvc_epinters(dev
, i
);
2499 /* Process data out end point interrupts */
2500 for (i
= UDC_EPINT_OUT_SHIFT
+ 1; i
< (UDC_EPINT_OUT_SHIFT
+
2501 PCH_UDC_USED_EP_NUM
); i
++)
2502 if (ep_intr
& (1 << i
))
2503 pch_udc_svc_data_out(dev
, i
-
2504 UDC_EPINT_OUT_SHIFT
);
2506 spin_unlock(&dev
->lock
);
2511 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2512 * @dev: Reference to the device structure
2514 static void pch_udc_setup_ep0(struct pch_udc_dev
*dev
)
2516 /* enable ep0 interrupts */
2517 pch_udc_enable_ep_interrupts(dev
, UDC_EPINT_IN_EP0
|
2519 /* enable device interrupts */
2520 pch_udc_enable_interrupts(dev
, UDC_DEVINT_UR
| UDC_DEVINT_US
|
2521 UDC_DEVINT_ES
| UDC_DEVINT_ENUM
|
2522 UDC_DEVINT_SI
| UDC_DEVINT_SC
);
2526 * gadget_release() - Free the gadget driver private data
2527 * @pdev reference to struct pci_dev
2529 static void gadget_release(struct device
*pdev
)
2531 struct pch_udc_dev
*dev
= dev_get_drvdata(pdev
);
2537 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2538 * @dev: Reference to the driver structure
2540 static void pch_udc_pcd_reinit(struct pch_udc_dev
*dev
)
2542 const char *const ep_string
[] = {
2543 ep0_string
, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2544 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2545 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2546 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2547 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2548 "ep15in", "ep15out",
2552 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2553 INIT_LIST_HEAD(&dev
->gadget
.ep_list
);
2555 /* Initialize the endpoints structures */
2556 memset(dev
->ep
, 0, sizeof dev
->ep
);
2557 for (i
= 0; i
< PCH_UDC_EP_NUM
; i
++) {
2558 struct pch_udc_ep
*ep
= &dev
->ep
[i
];
2563 ep
->ep
.name
= ep_string
[i
];
2564 ep
->ep
.ops
= &pch_udc_ep_ops
;
2566 ep
->offset_addr
= ep
->num
* UDC_EP_REG_SHIFT
;
2568 ep
->offset_addr
= (UDC_EPINT_OUT_SHIFT
+ ep
->num
) *
2570 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2571 ep
->ep
.maxpacket
= UDC_BULK_MAX_PKT_SIZE
;
2572 list_add_tail(&ep
->ep
.ep_list
, &dev
->gadget
.ep_list
);
2573 INIT_LIST_HEAD(&ep
->queue
);
2575 dev
->ep
[UDC_EP0IN_IDX
].ep
.maxpacket
= UDC_EP0IN_MAX_PKT_SIZE
;
2576 dev
->ep
[UDC_EP0OUT_IDX
].ep
.maxpacket
= UDC_EP0OUT_MAX_PKT_SIZE
;
2578 /* remove ep0 in and out from the list. They have own pointer */
2579 list_del_init(&dev
->ep
[UDC_EP0IN_IDX
].ep
.ep_list
);
2580 list_del_init(&dev
->ep
[UDC_EP0OUT_IDX
].ep
.ep_list
);
2582 dev
->gadget
.ep0
= &dev
->ep
[UDC_EP0IN_IDX
].ep
;
2583 INIT_LIST_HEAD(&dev
->gadget
.ep0
->ep_list
);
2587 * pch_udc_pcd_init() - This API initializes the driver structure
2588 * @dev: Reference to the driver structure
2593 static int pch_udc_pcd_init(struct pch_udc_dev
*dev
)
2596 pch_udc_pcd_reinit(dev
);
2601 * init_dma_pools() - create dma pools during initialization
2602 * @pdev: reference to struct pci_dev
2604 static int init_dma_pools(struct pch_udc_dev
*dev
)
2606 struct pch_udc_stp_dma_desc
*td_stp
;
2607 struct pch_udc_data_dma_desc
*td_data
;
2610 dev
->data_requests
= pci_pool_create("data_requests", dev
->pdev
,
2611 sizeof(struct pch_udc_data_dma_desc
), 0, 0);
2612 if (!dev
->data_requests
) {
2613 dev_err(&dev
->pdev
->dev
, "%s: can't get request data pool\n",
2618 /* dma desc for setup data */
2619 dev
->stp_requests
= pci_pool_create("setup requests", dev
->pdev
,
2620 sizeof(struct pch_udc_stp_dma_desc
), 0, 0);
2621 if (!dev
->stp_requests
) {
2622 dev_err(&dev
->pdev
->dev
, "%s: can't get setup request pool\n",
2627 td_stp
= pci_pool_alloc(dev
->stp_requests
, GFP_KERNEL
,
2628 &dev
->ep
[UDC_EP0OUT_IDX
].td_stp_phys
);
2630 dev_err(&dev
->pdev
->dev
,
2631 "%s: can't allocate setup dma descriptor\n", __func__
);
2634 dev
->ep
[UDC_EP0OUT_IDX
].td_stp
= td_stp
;
2636 /* data: 0 packets !? */
2637 td_data
= pci_pool_alloc(dev
->data_requests
, GFP_KERNEL
,
2638 &dev
->ep
[UDC_EP0OUT_IDX
].td_data_phys
);
2640 dev_err(&dev
->pdev
->dev
,
2641 "%s: can't allocate data dma descriptor\n", __func__
);
2644 dev
->ep
[UDC_EP0OUT_IDX
].td_data
= td_data
;
2645 dev
->ep
[UDC_EP0IN_IDX
].td_stp
= NULL
;
2646 dev
->ep
[UDC_EP0IN_IDX
].td_stp_phys
= 0;
2647 dev
->ep
[UDC_EP0IN_IDX
].td_data
= NULL
;
2648 dev
->ep
[UDC_EP0IN_IDX
].td_data_phys
= 0;
2650 dev
->ep0out_buf
= kzalloc(UDC_EP0OUT_BUFF_SIZE
* 4, GFP_KERNEL
);
2651 if (!dev
->ep0out_buf
)
2653 dev
->dma_addr
= dma_map_single(&dev
->pdev
->dev
, dev
->ep0out_buf
,
2654 UDC_EP0OUT_BUFF_SIZE
* 4,
2659 int usb_gadget_probe_driver(struct usb_gadget_driver
*driver
,
2660 int (*bind
)(struct usb_gadget
*))
2662 struct pch_udc_dev
*dev
= pch_udc
;
2665 if (!driver
|| (driver
->speed
== USB_SPEED_UNKNOWN
) || !bind
||
2666 !driver
->setup
|| !driver
->unbind
|| !driver
->disconnect
) {
2667 dev_err(&dev
->pdev
->dev
,
2668 "%s: invalid driver parameter\n", __func__
);
2676 dev_err(&dev
->pdev
->dev
, "%s: already bound\n", __func__
);
2679 driver
->driver
.bus
= NULL
;
2680 dev
->driver
= driver
;
2681 dev
->gadget
.dev
.driver
= &driver
->driver
;
2683 /* Invoke the bind routine of the gadget driver */
2684 retval
= bind(&dev
->gadget
);
2687 dev_err(&dev
->pdev
->dev
, "%s: binding to %s returning %d\n",
2688 __func__
, driver
->driver
.name
, retval
);
2690 dev
->gadget
.dev
.driver
= NULL
;
2693 /* get ready for ep0 traffic */
2694 pch_udc_setup_ep0(dev
);
2697 pch_udc_clear_disconnect(dev
);
2702 EXPORT_SYMBOL(usb_gadget_probe_driver
);
2704 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
2706 struct pch_udc_dev
*dev
= pch_udc
;
2711 if (!driver
|| (driver
!= dev
->driver
)) {
2712 dev_err(&dev
->pdev
->dev
,
2713 "%s: invalid driver parameter\n", __func__
);
2717 pch_udc_disable_interrupts(dev
, UDC_DEVINT_MSK
);
2719 /* Assues that there are no pending requets with this driver */
2720 driver
->unbind(&dev
->gadget
);
2721 dev
->gadget
.dev
.driver
= NULL
;
2726 pch_udc_set_disconnect(dev
);
2729 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
2731 static void pch_udc_shutdown(struct pci_dev
*pdev
)
2733 struct pch_udc_dev
*dev
= pci_get_drvdata(pdev
);
2735 pch_udc_disable_interrupts(dev
, UDC_DEVINT_MSK
);
2736 pch_udc_disable_ep_interrupts(dev
, UDC_EPINT_MSK_DISABLE_ALL
);
2738 /* disable the pullup so the host will think we're gone */
2739 pch_udc_set_disconnect(dev
);
2742 static void pch_udc_remove(struct pci_dev
*pdev
)
2744 struct pch_udc_dev
*dev
= pci_get_drvdata(pdev
);
2746 /* gadget driver must not be registered */
2749 "%s: gadget driver still bound!!!\n", __func__
);
2750 /* dma pool cleanup */
2751 if (dev
->data_requests
)
2752 pci_pool_destroy(dev
->data_requests
);
2754 if (dev
->stp_requests
) {
2755 /* cleanup DMA desc's for ep0in */
2756 if (dev
->ep
[UDC_EP0OUT_IDX
].td_stp
) {
2757 pci_pool_free(dev
->stp_requests
,
2758 dev
->ep
[UDC_EP0OUT_IDX
].td_stp
,
2759 dev
->ep
[UDC_EP0OUT_IDX
].td_stp_phys
);
2761 if (dev
->ep
[UDC_EP0OUT_IDX
].td_data
) {
2762 pci_pool_free(dev
->stp_requests
,
2763 dev
->ep
[UDC_EP0OUT_IDX
].td_data
,
2764 dev
->ep
[UDC_EP0OUT_IDX
].td_data_phys
);
2766 pci_pool_destroy(dev
->stp_requests
);
2770 dma_unmap_single(&dev
->pdev
->dev
, dev
->dma_addr
,
2771 UDC_EP0OUT_BUFF_SIZE
* 4, DMA_FROM_DEVICE
);
2772 kfree(dev
->ep0out_buf
);
2776 if (dev
->irq_registered
)
2777 free_irq(pdev
->irq
, dev
);
2779 iounmap(dev
->base_addr
);
2780 if (dev
->mem_region
)
2781 release_mem_region(dev
->phys_addr
,
2782 pci_resource_len(pdev
, PCH_UDC_PCI_BAR
));
2784 pci_disable_device(pdev
);
2785 if (dev
->registered
)
2786 device_unregister(&dev
->gadget
.dev
);
2788 pci_set_drvdata(pdev
, NULL
);
2792 static int pch_udc_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2794 struct pch_udc_dev
*dev
= pci_get_drvdata(pdev
);
2796 pch_udc_disable_interrupts(dev
, UDC_DEVINT_MSK
);
2797 pch_udc_disable_ep_interrupts(dev
, UDC_EPINT_MSK_DISABLE_ALL
);
2799 pci_disable_device(pdev
);
2800 pci_enable_wake(pdev
, PCI_D3hot
, 0);
2802 if (pci_save_state(pdev
)) {
2804 "%s: could not save PCI config state\n", __func__
);
2807 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2811 static int pch_udc_resume(struct pci_dev
*pdev
)
2815 pci_set_power_state(pdev
, PCI_D0
);
2816 pci_restore_state(pdev
);
2817 ret
= pci_enable_device(pdev
);
2819 dev_err(&pdev
->dev
, "%s: pci_enable_device failed\n", __func__
);
2822 pci_enable_wake(pdev
, PCI_D3hot
, 0);
2826 #define pch_udc_suspend NULL
2827 #define pch_udc_resume NULL
2828 #endif /* CONFIG_PM */
2830 static int pch_udc_probe(struct pci_dev
*pdev
,
2831 const struct pci_device_id
*id
)
2833 unsigned long resource
;
2836 struct pch_udc_dev
*dev
;
2840 pr_err("%s: already probed\n", __func__
);
2844 dev
= kzalloc(sizeof *dev
, GFP_KERNEL
);
2846 pr_err("%s: no memory for device structure\n", __func__
);
2850 if (pci_enable_device(pdev
) < 0) {
2852 pr_err("%s: pci_enable_device failed\n", __func__
);
2856 pci_set_drvdata(pdev
, dev
);
2858 /* PCI resource allocation */
2859 resource
= pci_resource_start(pdev
, 1);
2860 len
= pci_resource_len(pdev
, 1);
2862 if (!request_mem_region(resource
, len
, KBUILD_MODNAME
)) {
2863 dev_err(&pdev
->dev
, "%s: pci device used already\n", __func__
);
2867 dev
->phys_addr
= resource
;
2868 dev
->mem_region
= 1;
2870 dev
->base_addr
= ioremap_nocache(resource
, len
);
2871 if (!dev
->base_addr
) {
2872 pr_err("%s: device memory cannot be mapped\n", __func__
);
2877 dev_err(&pdev
->dev
, "%s: irq not set\n", __func__
);
2882 /* initialize the hardware */
2883 if (pch_udc_pcd_init(dev
))
2885 if (request_irq(pdev
->irq
, pch_udc_isr
, IRQF_SHARED
, KBUILD_MODNAME
,
2887 dev_err(&pdev
->dev
, "%s: request_irq(%d) fail\n", __func__
,
2892 dev
->irq
= pdev
->irq
;
2893 dev
->irq_registered
= 1;
2895 pci_set_master(pdev
);
2896 pci_try_set_mwi(pdev
);
2898 /* device struct setup */
2899 spin_lock_init(&dev
->lock
);
2901 dev
->gadget
.ops
= &pch_udc_ops
;
2903 retval
= init_dma_pools(dev
);
2907 dev_set_name(&dev
->gadget
.dev
, "gadget");
2908 dev
->gadget
.dev
.parent
= &pdev
->dev
;
2909 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
2910 dev
->gadget
.dev
.release
= gadget_release
;
2911 dev
->gadget
.name
= KBUILD_MODNAME
;
2912 dev
->gadget
.is_dualspeed
= 1;
2914 retval
= device_register(&dev
->gadget
.dev
);
2917 dev
->registered
= 1;
2919 /* Put the device in disconnected state till a driver is bound */
2920 pch_udc_set_disconnect(dev
);
2924 pch_udc_remove(pdev
);
2928 static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id
) = {
2930 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EG20T_UDC
),
2931 .class = (PCI_CLASS_SERIAL_USB
<< 8) | 0xfe,
2932 .class_mask
= 0xffffffff,
2937 MODULE_DEVICE_TABLE(pci
, pch_udc_pcidev_id
);
2940 static struct pci_driver pch_udc_driver
= {
2941 .name
= KBUILD_MODNAME
,
2942 .id_table
= pch_udc_pcidev_id
,
2943 .probe
= pch_udc_probe
,
2944 .remove
= pch_udc_remove
,
2945 .suspend
= pch_udc_suspend
,
2946 .resume
= pch_udc_resume
,
2947 .shutdown
= pch_udc_shutdown
,
2950 static int __init
pch_udc_pci_init(void)
2952 return pci_register_driver(&pch_udc_driver
);
2954 module_init(pch_udc_pci_init
);
2956 static void __exit
pch_udc_pci_exit(void)
2958 pci_unregister_driver(&pch_udc_driver
);
2960 module_exit(pch_udc_pci_exit
);
2962 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
2963 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2964 MODULE_LICENSE("GPL");