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drivers/net: Remove IRQF_SAMPLE_RANDOM flag from network drivers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blobb7e03a6ebf250bef05557291b303b38f1ecf0980
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
40 #include <linux/ip.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
46
47 #include <net/checksum.h>
48 #include <net/ip.h>
49
50 #include <asm/system.h>
51 #include <linux/io.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
54
55 #ifdef CONFIG_SPARC
56 #include <asm/idprom.h>
57 #include <asm/prom.h>
58 #endif
59
60 #define BAR_0 0
61 #define BAR_2 2
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define TG3_MAJ_NUM 3
67 #define TG3_MIN_NUM 117
68 #define DRV_MODULE_VERSION \
69 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
70 #define DRV_MODULE_RELDATE "January 25, 2011"
71
72 #define TG3_DEF_MAC_MODE 0
73 #define TG3_DEF_RX_MODE 0
74 #define TG3_DEF_TX_MODE 0
75 #define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85 /* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88 #define TG3_TX_TIMEOUT (5 * HZ)
89
90 /* hardware minimum and maximum for a single frame's data payload */
91 #define TG3_MIN_MTU 60
92 #define TG3_MAX_MTU(tp) \
93 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
94
95 /* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
99 #define TG3_RX_STD_RING_SIZE(tp) \
100 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
102 RX_STD_MAX_SIZE_5717 : 512)
103 #define TG3_DEF_RX_RING_PENDING 200
104 #define TG3_RX_JMB_RING_SIZE(tp) \
105 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107 1024 : 256)
108 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
109 #define TG3_RSS_INDIR_TBL_SIZE 128
110
111 /* Do not place this n-ring entries value into the tp struct itself,
112 * we really want to expose these constants to GCC so that modulo et
113 * al. operations are done with shifts and masks instead of with
114 * hw multiply/modulo instructions. Another solution would be to
115 * replace things like '% foo' with '& (foo - 1)'.
116 */
117
118 #define TG3_TX_RING_SIZE 512
119 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120
121 #define TG3_RX_STD_RING_BYTES(tp) \
122 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
123 #define TG3_RX_JMB_RING_BYTES(tp) \
124 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
125 #define TG3_RX_RCB_RING_BYTES(tp) \
126 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
127 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 TG3_TX_RING_SIZE)
129 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130
131 #define TG3_DMA_BYTE_ENAB 64
132
133 #define TG3_RX_STD_DMA_SZ 1536
134 #define TG3_RX_JMB_DMA_SZ 9046
135
136 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137
138 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
139 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140
141 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
142 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
143
144 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
145 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
146
147 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
148 * that are at least dword aligned when used in PCIX mode. The driver
149 * works around this bug by double copying the packet. This workaround
150 * is built into the normal double copy length check for efficiency.
151 *
152 * However, the double copy is only necessary on those architectures
153 * where unaligned memory accesses are inefficient. For those architectures
154 * where unaligned memory accesses incur little penalty, we can reintegrate
155 * the 5701 in the normal rx path. Doing so saves a device structure
156 * dereference by hardcoding the double copy threshold in place.
157 */
158 #define TG3_RX_COPY_THRESHOLD 256
159 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
160 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
161 #else
162 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
163 #endif
164
165 /* minimum number of free TX descriptors required to wake up TX process */
166 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
167
168 #define TG3_RAW_IP_ALIGN 2
169
170 /* number of ETHTOOL_GSTATS u64's */
171 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
172
173 #define TG3_NUM_TEST 6
174
175 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
176
177 #define FIRMWARE_TG3 "tigon/tg3.bin"
178 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
179 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
180
181 static char version[] __devinitdata =
182 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
183
184 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
185 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_MODULE_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_TG3);
189 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
191
192 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
193 module_param(tg3_debug, int, 0);
194 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
195
196 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
269 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
270 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
271 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
272 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
273 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
274 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
275 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
276 {}
277 };
278
279 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
280
281 static const struct {
282 const char string[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[TG3_NUM_STATS] = {
284 { "rx_octets" },
285 { "rx_fragments" },
286 { "rx_ucast_packets" },
287 { "rx_mcast_packets" },
288 { "rx_bcast_packets" },
289 { "rx_fcs_errors" },
290 { "rx_align_errors" },
291 { "rx_xon_pause_rcvd" },
292 { "rx_xoff_pause_rcvd" },
293 { "rx_mac_ctrl_rcvd" },
294 { "rx_xoff_entered" },
295 { "rx_frame_too_long_errors" },
296 { "rx_jabbers" },
297 { "rx_undersize_packets" },
298 { "rx_in_length_errors" },
299 { "rx_out_length_errors" },
300 { "rx_64_or_less_octet_packets" },
301 { "rx_65_to_127_octet_packets" },
302 { "rx_128_to_255_octet_packets" },
303 { "rx_256_to_511_octet_packets" },
304 { "rx_512_to_1023_octet_packets" },
305 { "rx_1024_to_1522_octet_packets" },
306 { "rx_1523_to_2047_octet_packets" },
307 { "rx_2048_to_4095_octet_packets" },
308 { "rx_4096_to_8191_octet_packets" },
309 { "rx_8192_to_9022_octet_packets" },
310
311 { "tx_octets" },
312 { "tx_collisions" },
313
314 { "tx_xon_sent" },
315 { "tx_xoff_sent" },
316 { "tx_flow_control" },
317 { "tx_mac_errors" },
318 { "tx_single_collisions" },
319 { "tx_mult_collisions" },
320 { "tx_deferred" },
321 { "tx_excessive_collisions" },
322 { "tx_late_collisions" },
323 { "tx_collide_2times" },
324 { "tx_collide_3times" },
325 { "tx_collide_4times" },
326 { "tx_collide_5times" },
327 { "tx_collide_6times" },
328 { "tx_collide_7times" },
329 { "tx_collide_8times" },
330 { "tx_collide_9times" },
331 { "tx_collide_10times" },
332 { "tx_collide_11times" },
333 { "tx_collide_12times" },
334 { "tx_collide_13times" },
335 { "tx_collide_14times" },
336 { "tx_collide_15times" },
337 { "tx_ucast_packets" },
338 { "tx_mcast_packets" },
339 { "tx_bcast_packets" },
340 { "tx_carrier_sense_errors" },
341 { "tx_discards" },
342 { "tx_errors" },
343
344 { "dma_writeq_full" },
345 { "dma_write_prioq_full" },
346 { "rxbds_empty" },
347 { "rx_discards" },
348 { "rx_errors" },
349 { "rx_threshold_hit" },
350
351 { "dma_readq_full" },
352 { "dma_read_prioq_full" },
353 { "tx_comp_queue_full" },
354
355 { "ring_set_send_prod_index" },
356 { "ring_status_update" },
357 { "nic_irqs" },
358 { "nic_avoided_irqs" },
359 { "nic_tx_threshold_hit" }
360 };
361
362 static const struct {
363 const char string[ETH_GSTRING_LEN];
364 } ethtool_test_keys[TG3_NUM_TEST] = {
365 { "nvram test (online) " },
366 { "link test (online) " },
367 { "register test (offline)" },
368 { "memory test (offline)" },
369 { "loopback test (offline)" },
370 { "interrupt test (offline)" },
371 };
372
373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
374 {
375 writel(val, tp->regs + off);
376 }
377
378 static u32 tg3_read32(struct tg3 *tp, u32 off)
379 {
380 return readl(tp->regs + off);
381 }
382
383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
384 {
385 writel(val, tp->aperegs + off);
386 }
387
388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
389 {
390 return readl(tp->aperegs + off);
391 }
392
393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
394 {
395 unsigned long flags;
396
397 spin_lock_irqsave(&tp->indirect_lock, flags);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
400 spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 }
402
403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
404 {
405 writel(val, tp->regs + off);
406 readl(tp->regs + off);
407 }
408
409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
410 {
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419 }
420
421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423 unsigned long flags;
424
425 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
426 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
427 TG3_64BIT_REG_LOW, val);
428 return;
429 }
430 if (off == TG3_RX_STD_PROD_IDX_REG) {
431 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
432 TG3_64BIT_REG_LOW, val);
433 return;
434 }
435
436 spin_lock_irqsave(&tp->indirect_lock, flags);
437 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
438 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
439 spin_unlock_irqrestore(&tp->indirect_lock, flags);
440
441 /* In indirect mode when disabling interrupts, we also need
442 * to clear the interrupt bit in the GRC local ctrl register.
443 */
444 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
445 (val == 0x1)) {
446 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
447 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
448 }
449 }
450
451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
452 {
453 unsigned long flags;
454 u32 val;
455
456 spin_lock_irqsave(&tp->indirect_lock, flags);
457 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
458 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
459 spin_unlock_irqrestore(&tp->indirect_lock, flags);
460 return val;
461 }
462
463 /* usec_wait specifies the wait time in usec when writing to certain registers
464 * where it is unsafe to read back the register without some delay.
465 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
466 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
467 */
468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
469 {
470 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
471 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
472 /* Non-posted methods */
473 tp->write32(tp, off, val);
474 else {
475 /* Posted method */
476 tg3_write32(tp, off, val);
477 if (usec_wait)
478 udelay(usec_wait);
479 tp->read32(tp, off);
480 }
481 /* Wait again after the read for the posted method to guarantee that
482 * the wait time is met.
483 */
484 if (usec_wait)
485 udelay(usec_wait);
486 }
487
488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
489 {
490 tp->write32_mbox(tp, off, val);
491 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
492 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
493 tp->read32_mbox(tp, off);
494 }
495
496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
497 {
498 void __iomem *mbox = tp->regs + off;
499 writel(val, mbox);
500 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
501 writel(val, mbox);
502 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
503 readl(mbox);
504 }
505
506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
507 {
508 return readl(tp->regs + off + GRCMBOX_BASE);
509 }
510
511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
512 {
513 writel(val, tp->regs + off + GRCMBOX_BASE);
514 }
515
516 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
517 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
518 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
519 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
520 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
521
522 #define tw32(reg, val) tp->write32(tp, reg, val)
523 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
524 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
525 #define tr32(reg) tp->read32(tp, reg)
526
527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
528 {
529 unsigned long flags;
530
531 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
532 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
533 return;
534
535 spin_lock_irqsave(&tp->indirect_lock, flags);
536 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
538 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
539
540 /* Always leave this as zero. */
541 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
542 } else {
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
544 tw32_f(TG3PCI_MEM_WIN_DATA, val);
545
546 /* Always leave this as zero. */
547 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 }
549 spin_unlock_irqrestore(&tp->indirect_lock, flags);
550 }
551
552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
553 {
554 unsigned long flags;
555
556 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
557 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
558 *val = 0;
559 return;
560 }
561
562 spin_lock_irqsave(&tp->indirect_lock, flags);
563 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
564 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
565 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566
567 /* Always leave this as zero. */
568 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569 } else {
570 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
571 *val = tr32(TG3PCI_MEM_WIN_DATA);
572
573 /* Always leave this as zero. */
574 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575 }
576 spin_unlock_irqrestore(&tp->indirect_lock, flags);
577 }
578
579 static void tg3_ape_lock_init(struct tg3 *tp)
580 {
581 int i;
582 u32 regbase;
583
584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
585 regbase = TG3_APE_LOCK_GRANT;
586 else
587 regbase = TG3_APE_PER_LOCK_GRANT;
588
589 /* Make sure the driver hasn't any stale locks. */
590 for (i = 0; i < 8; i++)
591 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
592 }
593
594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
595 {
596 int i, off;
597 int ret = 0;
598 u32 status, req, gnt;
599
600 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
601 return 0;
602
603 switch (locknum) {
604 case TG3_APE_LOCK_GRC:
605 case TG3_APE_LOCK_MEM:
606 break;
607 default:
608 return -EINVAL;
609 }
610
611 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
612 req = TG3_APE_LOCK_REQ;
613 gnt = TG3_APE_LOCK_GRANT;
614 } else {
615 req = TG3_APE_PER_LOCK_REQ;
616 gnt = TG3_APE_PER_LOCK_GRANT;
617 }
618
619 off = 4 * locknum;
620
621 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
622
623 /* Wait for up to 1 millisecond to acquire lock. */
624 for (i = 0; i < 100; i++) {
625 status = tg3_ape_read32(tp, gnt + off);
626 if (status == APE_LOCK_GRANT_DRIVER)
627 break;
628 udelay(10);
629 }
630
631 if (status != APE_LOCK_GRANT_DRIVER) {
632 /* Revoke the lock request. */
633 tg3_ape_write32(tp, gnt + off,
634 APE_LOCK_GRANT_DRIVER);
635
636 ret = -EBUSY;
637 }
638
639 return ret;
640 }
641
642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
643 {
644 u32 gnt;
645
646 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
647 return;
648
649 switch (locknum) {
650 case TG3_APE_LOCK_GRC:
651 case TG3_APE_LOCK_MEM:
652 break;
653 default:
654 return;
655 }
656
657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
658 gnt = TG3_APE_LOCK_GRANT;
659 else
660 gnt = TG3_APE_PER_LOCK_GRANT;
661
662 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
663 }
664
665 static void tg3_disable_ints(struct tg3 *tp)
666 {
667 int i;
668
669 tw32(TG3PCI_MISC_HOST_CTRL,
670 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
671 for (i = 0; i < tp->irq_max; i++)
672 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
673 }
674
675 static void tg3_enable_ints(struct tg3 *tp)
676 {
677 int i;
678
679 tp->irq_sync = 0;
680 wmb();
681
682 tw32(TG3PCI_MISC_HOST_CTRL,
683 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
684
685 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
686 for (i = 0; i < tp->irq_cnt; i++) {
687 struct tg3_napi *tnapi = &tp->napi[i];
688
689 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
690 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
691 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
692
693 tp->coal_now |= tnapi->coal_now;
694 }
695
696 /* Force an initial interrupt */
697 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
698 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
699 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
700 else
701 tw32(HOSTCC_MODE, tp->coal_now);
702
703 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
704 }
705
706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
707 {
708 struct tg3 *tp = tnapi->tp;
709 struct tg3_hw_status *sblk = tnapi->hw_status;
710 unsigned int work_exists = 0;
711
712 /* check for phy events */
713 if (!(tp->tg3_flags &
714 (TG3_FLAG_USE_LINKCHG_REG |
715 TG3_FLAG_POLL_SERDES))) {
716 if (sblk->status & SD_STATUS_LINK_CHG)
717 work_exists = 1;
718 }
719 /* check for RX/TX work to do */
720 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
721 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
722 work_exists = 1;
723
724 return work_exists;
725 }
726
727 /* tg3_int_reenable
728 * similar to tg3_enable_ints, but it accurately determines whether there
729 * is new work pending and can return without flushing the PIO write
730 * which reenables interrupts
731 */
732 static void tg3_int_reenable(struct tg3_napi *tnapi)
733 {
734 struct tg3 *tp = tnapi->tp;
735
736 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
737 mmiowb();
738
739 /* When doing tagged status, this work check is unnecessary.
740 * The last_tag we write above tells the chip which piece of
741 * work we've completed.
742 */
743 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
744 tg3_has_work(tnapi))
745 tw32(HOSTCC_MODE, tp->coalesce_mode |
746 HOSTCC_MODE_ENABLE | tnapi->coal_now);
747 }
748
749 static void tg3_switch_clocks(struct tg3 *tp)
750 {
751 u32 clock_ctrl;
752 u32 orig_clock_ctrl;
753
754 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
755 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
756 return;
757
758 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
759
760 orig_clock_ctrl = clock_ctrl;
761 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
762 CLOCK_CTRL_CLKRUN_OENABLE |
763 0x1f);
764 tp->pci_clock_ctrl = clock_ctrl;
765
766 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
767 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
768 tw32_wait_f(TG3PCI_CLOCK_CTRL,
769 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
770 }
771 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
772 tw32_wait_f(TG3PCI_CLOCK_CTRL,
773 clock_ctrl |
774 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
775 40);
776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777 clock_ctrl | (CLOCK_CTRL_ALTCLK),
778 40);
779 }
780 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
781 }
782
783 #define PHY_BUSY_LOOPS 5000
784
785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 {
787 u32 frame_val;
788 unsigned int loops;
789 int ret;
790
791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 *val = 0x0;
798
799 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
800 MI_COM_PHY_ADDR_MASK);
801 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
802 MI_COM_REG_ADDR_MASK);
803 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
804
805 tw32_f(MAC_MI_COM, frame_val);
806
807 loops = PHY_BUSY_LOOPS;
808 while (loops != 0) {
809 udelay(10);
810 frame_val = tr32(MAC_MI_COM);
811
812 if ((frame_val & MI_COM_BUSY) == 0) {
813 udelay(5);
814 frame_val = tr32(MAC_MI_COM);
815 break;
816 }
817 loops -= 1;
818 }
819
820 ret = -EBUSY;
821 if (loops != 0) {
822 *val = frame_val & MI_COM_DATA_MASK;
823 ret = 0;
824 }
825
826 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
827 tw32_f(MAC_MI_MODE, tp->mi_mode);
828 udelay(80);
829 }
830
831 return ret;
832 }
833
834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 {
836 u32 frame_val;
837 unsigned int loops;
838 int ret;
839
840 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
841 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
842 return 0;
843
844 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
845 tw32_f(MAC_MI_MODE,
846 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
847 udelay(80);
848 }
849
850 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
851 MI_COM_PHY_ADDR_MASK);
852 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
853 MI_COM_REG_ADDR_MASK);
854 frame_val |= (val & MI_COM_DATA_MASK);
855 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
856
857 tw32_f(MAC_MI_COM, frame_val);
858
859 loops = PHY_BUSY_LOOPS;
860 while (loops != 0) {
861 udelay(10);
862 frame_val = tr32(MAC_MI_COM);
863 if ((frame_val & MI_COM_BUSY) == 0) {
864 udelay(5);
865 frame_val = tr32(MAC_MI_COM);
866 break;
867 }
868 loops -= 1;
869 }
870
871 ret = -EBUSY;
872 if (loops != 0)
873 ret = 0;
874
875 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
876 tw32_f(MAC_MI_MODE, tp->mi_mode);
877 udelay(80);
878 }
879
880 return ret;
881 }
882
883 static int tg3_bmcr_reset(struct tg3 *tp)
884 {
885 u32 phy_control;
886 int limit, err;
887
888 /* OK, reset it, and poll the BMCR_RESET bit until it
889 * clears or we time out.
890 */
891 phy_control = BMCR_RESET;
892 err = tg3_writephy(tp, MII_BMCR, phy_control);
893 if (err != 0)
894 return -EBUSY;
895
896 limit = 5000;
897 while (limit--) {
898 err = tg3_readphy(tp, MII_BMCR, &phy_control);
899 if (err != 0)
900 return -EBUSY;
901
902 if ((phy_control & BMCR_RESET) == 0) {
903 udelay(40);
904 break;
905 }
906 udelay(10);
907 }
908 if (limit < 0)
909 return -EBUSY;
910
911 return 0;
912 }
913
914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
915 {
916 struct tg3 *tp = bp->priv;
917 u32 val;
918
919 spin_lock_bh(&tp->lock);
920
921 if (tg3_readphy(tp, reg, &val))
922 val = -EIO;
923
924 spin_unlock_bh(&tp->lock);
925
926 return val;
927 }
928
929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
930 {
931 struct tg3 *tp = bp->priv;
932 u32 ret = 0;
933
934 spin_lock_bh(&tp->lock);
935
936 if (tg3_writephy(tp, reg, val))
937 ret = -EIO;
938
939 spin_unlock_bh(&tp->lock);
940
941 return ret;
942 }
943
944 static int tg3_mdio_reset(struct mii_bus *bp)
945 {
946 return 0;
947 }
948
949 static void tg3_mdio_config_5785(struct tg3 *tp)
950 {
951 u32 val;
952 struct phy_device *phydev;
953
954 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
955 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
956 case PHY_ID_BCM50610:
957 case PHY_ID_BCM50610M:
958 val = MAC_PHYCFG2_50610_LED_MODES;
959 break;
960 case PHY_ID_BCMAC131:
961 val = MAC_PHYCFG2_AC131_LED_MODES;
962 break;
963 case PHY_ID_RTL8211C:
964 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
965 break;
966 case PHY_ID_RTL8201E:
967 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968 break;
969 default:
970 return;
971 }
972
973 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
974 tw32(MAC_PHYCFG2, val);
975
976 val = tr32(MAC_PHYCFG1);
977 val &= ~(MAC_PHYCFG1_RGMII_INT |
978 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
979 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
980 tw32(MAC_PHYCFG1, val);
981
982 return;
983 }
984
985 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
986 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
987 MAC_PHYCFG2_FMODE_MASK_MASK |
988 MAC_PHYCFG2_GMODE_MASK_MASK |
989 MAC_PHYCFG2_ACT_MASK_MASK |
990 MAC_PHYCFG2_QUAL_MASK_MASK |
991 MAC_PHYCFG2_INBAND_ENABLE;
992
993 tw32(MAC_PHYCFG2, val);
994
995 val = tr32(MAC_PHYCFG1);
996 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
997 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
998 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
999 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003 }
1004 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006 tw32(MAC_PHYCFG1, val);
1007
1008 val = tr32(MAC_EXT_RGMII_MODE);
1009 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010 MAC_RGMII_MODE_RX_QUALITY |
1011 MAC_RGMII_MODE_RX_ACTIVITY |
1012 MAC_RGMII_MODE_RX_ENG_DET |
1013 MAC_RGMII_MODE_TX_ENABLE |
1014 MAC_RGMII_MODE_TX_LOWPWR |
1015 MAC_RGMII_MODE_TX_RESET);
1016 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018 val |= MAC_RGMII_MODE_RX_INT_B |
1019 MAC_RGMII_MODE_RX_QUALITY |
1020 MAC_RGMII_MODE_RX_ACTIVITY |
1021 MAC_RGMII_MODE_RX_ENG_DET;
1022 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023 val |= MAC_RGMII_MODE_TX_ENABLE |
1024 MAC_RGMII_MODE_TX_LOWPWR |
1025 MAC_RGMII_MODE_TX_RESET;
1026 }
1027 tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033 tw32_f(MAC_MI_MODE, tp->mi_mode);
1034 udelay(80);
1035
1036 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043 int i;
1044 u32 reg;
1045 struct phy_device *phydev;
1046
1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1048 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1049 u32 is_serdes;
1050
1051 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1052
1053 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1054 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1055 else
1056 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1057 TG3_CPMU_PHY_STRAP_IS_SERDES;
1058 if (is_serdes)
1059 tp->phy_addr += 7;
1060 } else
1061 tp->phy_addr = TG3_PHY_MII_ADDR;
1062
1063 tg3_mdio_start(tp);
1064
1065 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1066 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067 return 0;
1068
1069 tp->mdio_bus = mdiobus_alloc();
1070 if (tp->mdio_bus == NULL)
1071 return -ENOMEM;
1072
1073 tp->mdio_bus->name = "tg3 mdio bus";
1074 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1075 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1076 tp->mdio_bus->priv = tp;
1077 tp->mdio_bus->parent = &tp->pdev->dev;
1078 tp->mdio_bus->read = &tg3_mdio_read;
1079 tp->mdio_bus->write = &tg3_mdio_write;
1080 tp->mdio_bus->reset = &tg3_mdio_reset;
1081 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1082 tp->mdio_bus->irq = &tp->mdio_irq[0];
1083
1084 for (i = 0; i < PHY_MAX_ADDR; i++)
1085 tp->mdio_bus->irq[i] = PHY_POLL;
1086
1087 /* The bus registration will look for all the PHYs on the mdio bus.
1088 * Unfortunately, it does not ensure the PHY is powered up before
1089 * accessing the PHY ID registers. A chip reset is the
1090 * quickest way to bring the device back to an operational state..
1091 */
1092 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1093 tg3_bmcr_reset(tp);
1094
1095 i = mdiobus_register(tp->mdio_bus);
1096 if (i) {
1097 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1098 mdiobus_free(tp->mdio_bus);
1099 return i;
1100 }
1101
1102 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103
1104 if (!phydev || !phydev->drv) {
1105 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1106 mdiobus_unregister(tp->mdio_bus);
1107 mdiobus_free(tp->mdio_bus);
1108 return -ENODEV;
1109 }
1110
1111 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1112 case PHY_ID_BCM57780:
1113 phydev->interface = PHY_INTERFACE_MODE_GMII;
1114 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1115 break;
1116 case PHY_ID_BCM50610:
1117 case PHY_ID_BCM50610M:
1118 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1119 PHY_BRCM_RX_REFCLK_UNUSED |
1120 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1121 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1123 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1124 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1125 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1126 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1127 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1128 /* fallthru */
1129 case PHY_ID_RTL8211C:
1130 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1131 break;
1132 case PHY_ID_RTL8201E:
1133 case PHY_ID_BCMAC131:
1134 phydev->interface = PHY_INTERFACE_MODE_MII;
1135 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1136 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1137 break;
1138 }
1139
1140 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1141
1142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1143 tg3_mdio_config_5785(tp);
1144
1145 return 0;
1146 }
1147
1148 static void tg3_mdio_fini(struct tg3 *tp)
1149 {
1150 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1151 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1152 mdiobus_unregister(tp->mdio_bus);
1153 mdiobus_free(tp->mdio_bus);
1154 }
1155 }
1156
1157 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1158 {
1159 int err;
1160
1161 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1162 if (err)
1163 goto done;
1164
1165 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1166 if (err)
1167 goto done;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1170 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1171 if (err)
1172 goto done;
1173
1174 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1175
1176 done:
1177 return err;
1178 }
1179
1180 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1181 {
1182 int err;
1183
1184 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1185 if (err)
1186 goto done;
1187
1188 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1189 if (err)
1190 goto done;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1193 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1194 if (err)
1195 goto done;
1196
1197 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1198
1199 done:
1200 return err;
1201 }
1202
1203 /* tp->lock is held. */
1204 static inline void tg3_generate_fw_event(struct tg3 *tp)
1205 {
1206 u32 val;
1207
1208 val = tr32(GRC_RX_CPU_EVENT);
1209 val |= GRC_RX_CPU_DRIVER_EVENT;
1210 tw32_f(GRC_RX_CPU_EVENT, val);
1211
1212 tp->last_event_jiffies = jiffies;
1213 }
1214
1215 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216
1217 /* tp->lock is held. */
1218 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 {
1220 int i;
1221 unsigned int delay_cnt;
1222 long time_remain;
1223
1224 /* If enough time has passed, no wait is necessary. */
1225 time_remain = (long)(tp->last_event_jiffies + 1 +
1226 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1227 (long)jiffies;
1228 if (time_remain < 0)
1229 return;
1230
1231 /* Check if we can shorten the wait time. */
1232 delay_cnt = jiffies_to_usecs(time_remain);
1233 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1234 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1235 delay_cnt = (delay_cnt >> 3) + 1;
1236
1237 for (i = 0; i < delay_cnt; i++) {
1238 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1239 break;
1240 udelay(8);
1241 }
1242 }
1243
1244 /* tp->lock is held. */
1245 static void tg3_ump_link_report(struct tg3 *tp)
1246 {
1247 u32 reg;
1248 u32 val;
1249
1250 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1251 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1252 return;
1253
1254 tg3_wait_for_event_ack(tp);
1255
1256 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1257
1258 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259
1260 val = 0;
1261 if (!tg3_readphy(tp, MII_BMCR, &reg))
1262 val = reg << 16;
1263 if (!tg3_readphy(tp, MII_BMSR, &reg))
1264 val |= (reg & 0xffff);
1265 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266
1267 val = 0;
1268 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1269 val = reg << 16;
1270 if (!tg3_readphy(tp, MII_LPA, &reg))
1271 val |= (reg & 0xffff);
1272 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273
1274 val = 0;
1275 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1276 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1277 val = reg << 16;
1278 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1279 val |= (reg & 0xffff);
1280 }
1281 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1282
1283 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1284 val = reg << 16;
1285 else
1286 val = 0;
1287 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1288
1289 tg3_generate_fw_event(tp);
1290 }
1291
1292 static void tg3_link_report(struct tg3 *tp)
1293 {
1294 if (!netif_carrier_ok(tp->dev)) {
1295 netif_info(tp, link, tp->dev, "Link is down\n");
1296 tg3_ump_link_report(tp);
1297 } else if (netif_msg_link(tp)) {
1298 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1299 (tp->link_config.active_speed == SPEED_1000 ?
1300 1000 :
1301 (tp->link_config.active_speed == SPEED_100 ?
1302 100 : 10)),
1303 (tp->link_config.active_duplex == DUPLEX_FULL ?
1304 "full" : "half"));
1305
1306 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1307 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1308 "on" : "off",
1309 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1310 "on" : "off");
1311 tg3_ump_link_report(tp);
1312 }
1313 }
1314
1315 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1316 {
1317 u16 miireg;
1318
1319 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1320 miireg = ADVERTISE_PAUSE_CAP;
1321 else if (flow_ctrl & FLOW_CTRL_TX)
1322 miireg = ADVERTISE_PAUSE_ASYM;
1323 else if (flow_ctrl & FLOW_CTRL_RX)
1324 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1325 else
1326 miireg = 0;
1327
1328 return miireg;
1329 }
1330
1331 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1332 {
1333 u16 miireg;
1334
1335 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1336 miireg = ADVERTISE_1000XPAUSE;
1337 else if (flow_ctrl & FLOW_CTRL_TX)
1338 miireg = ADVERTISE_1000XPSE_ASYM;
1339 else if (flow_ctrl & FLOW_CTRL_RX)
1340 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1341 else
1342 miireg = 0;
1343
1344 return miireg;
1345 }
1346
1347 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1348 {
1349 u8 cap = 0;
1350
1351 if (lcladv & ADVERTISE_1000XPAUSE) {
1352 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1353 if (rmtadv & LPA_1000XPAUSE)
1354 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356 cap = FLOW_CTRL_RX;
1357 } else {
1358 if (rmtadv & LPA_1000XPAUSE)
1359 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1360 }
1361 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1363 cap = FLOW_CTRL_TX;
1364 }
1365
1366 return cap;
1367 }
1368
1369 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1370 {
1371 u8 autoneg;
1372 u8 flowctrl = 0;
1373 u32 old_rx_mode = tp->rx_mode;
1374 u32 old_tx_mode = tp->tx_mode;
1375
1376 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1377 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1378 else
1379 autoneg = tp->link_config.autoneg;
1380
1381 if (autoneg == AUTONEG_ENABLE &&
1382 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1383 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1384 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1385 else
1386 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1387 } else
1388 flowctrl = tp->link_config.flowctrl;
1389
1390 tp->link_config.active_flowctrl = flowctrl;
1391
1392 if (flowctrl & FLOW_CTRL_RX)
1393 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1394 else
1395 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1396
1397 if (old_rx_mode != tp->rx_mode)
1398 tw32_f(MAC_RX_MODE, tp->rx_mode);
1399
1400 if (flowctrl & FLOW_CTRL_TX)
1401 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1402 else
1403 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1404
1405 if (old_tx_mode != tp->tx_mode)
1406 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 }
1408
1409 static void tg3_adjust_link(struct net_device *dev)
1410 {
1411 u8 oldflowctrl, linkmesg = 0;
1412 u32 mac_mode, lcl_adv, rmt_adv;
1413 struct tg3 *tp = netdev_priv(dev);
1414 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1415
1416 spin_lock_bh(&tp->lock);
1417
1418 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1419 MAC_MODE_HALF_DUPLEX);
1420
1421 oldflowctrl = tp->link_config.active_flowctrl;
1422
1423 if (phydev->link) {
1424 lcl_adv = 0;
1425 rmt_adv = 0;
1426
1427 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1428 mac_mode |= MAC_MODE_PORT_MODE_MII;
1429 else if (phydev->speed == SPEED_1000 ||
1430 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1431 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1432 else
1433 mac_mode |= MAC_MODE_PORT_MODE_MII;
1434
1435 if (phydev->duplex == DUPLEX_HALF)
1436 mac_mode |= MAC_MODE_HALF_DUPLEX;
1437 else {
1438 lcl_adv = tg3_advert_flowctrl_1000T(
1439 tp->link_config.flowctrl);
1440
1441 if (phydev->pause)
1442 rmt_adv = LPA_PAUSE_CAP;
1443 if (phydev->asym_pause)
1444 rmt_adv |= LPA_PAUSE_ASYM;
1445 }
1446
1447 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1448 } else
1449 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1450
1451 if (mac_mode != tp->mac_mode) {
1452 tp->mac_mode = mac_mode;
1453 tw32_f(MAC_MODE, tp->mac_mode);
1454 udelay(40);
1455 }
1456
1457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1458 if (phydev->speed == SPEED_10)
1459 tw32(MAC_MI_STAT,
1460 MAC_MI_STAT_10MBPS_MODE |
1461 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462 else
1463 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464 }
1465
1466 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1467 tw32(MAC_TX_LENGTHS,
1468 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469 (6 << TX_LENGTHS_IPG_SHIFT) |
1470 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471 else
1472 tw32(MAC_TX_LENGTHS,
1473 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1474 (6 << TX_LENGTHS_IPG_SHIFT) |
1475 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1476
1477 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1478 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1479 phydev->speed != tp->link_config.active_speed ||
1480 phydev->duplex != tp->link_config.active_duplex ||
1481 oldflowctrl != tp->link_config.active_flowctrl)
1482 linkmesg = 1;
1483
1484 tp->link_config.active_speed = phydev->speed;
1485 tp->link_config.active_duplex = phydev->duplex;
1486
1487 spin_unlock_bh(&tp->lock);
1488
1489 if (linkmesg)
1490 tg3_link_report(tp);
1491 }
1492
1493 static int tg3_phy_init(struct tg3 *tp)
1494 {
1495 struct phy_device *phydev;
1496
1497 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498 return 0;
1499
1500 /* Bring the PHY back to a known state. */
1501 tg3_bmcr_reset(tp);
1502
1503 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504
1505 /* Attach the MAC to the PHY. */
1506 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1507 phydev->dev_flags, phydev->interface);
1508 if (IS_ERR(phydev)) {
1509 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1510 return PTR_ERR(phydev);
1511 }
1512
1513 /* Mask with MAC supported features. */
1514 switch (phydev->interface) {
1515 case PHY_INTERFACE_MODE_GMII:
1516 case PHY_INTERFACE_MODE_RGMII:
1517 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1518 phydev->supported &= (PHY_GBIT_FEATURES |
1519 SUPPORTED_Pause |
1520 SUPPORTED_Asym_Pause);
1521 break;
1522 }
1523 /* fallthru */
1524 case PHY_INTERFACE_MODE_MII:
1525 phydev->supported &= (PHY_BASIC_FEATURES |
1526 SUPPORTED_Pause |
1527 SUPPORTED_Asym_Pause);
1528 break;
1529 default:
1530 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1531 return -EINVAL;
1532 }
1533
1534 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1535
1536 phydev->advertising = phydev->supported;
1537
1538 return 0;
1539 }
1540
1541 static void tg3_phy_start(struct tg3 *tp)
1542 {
1543 struct phy_device *phydev;
1544
1545 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546 return;
1547
1548 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1549
1550 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1551 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1552 phydev->speed = tp->link_config.orig_speed;
1553 phydev->duplex = tp->link_config.orig_duplex;
1554 phydev->autoneg = tp->link_config.orig_autoneg;
1555 phydev->advertising = tp->link_config.orig_advertising;
1556 }
1557
1558 phy_start(phydev);
1559
1560 phy_start_aneg(phydev);
1561 }
1562
1563 static void tg3_phy_stop(struct tg3 *tp)
1564 {
1565 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566 return;
1567
1568 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 }
1570
1571 static void tg3_phy_fini(struct tg3 *tp)
1572 {
1573 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1574 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1575 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1576 }
1577 }
1578
1579 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1580 {
1581 int err;
1582
1583 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1584 if (!err)
1585 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1586
1587 return err;
1588 }
1589
1590 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1591 {
1592 int err;
1593
1594 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1595 if (!err)
1596 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1597
1598 return err;
1599 }
1600
1601 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603 u32 phytest;
1604
1605 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606 u32 phy;
1607
1608 tg3_writephy(tp, MII_TG3_FET_TEST,
1609 phytest | MII_TG3_FET_SHADOW_EN);
1610 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1611 if (enable)
1612 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613 else
1614 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1615 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1616 }
1617 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1618 }
1619 }
1620
1621 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1622 {
1623 u32 reg;
1624
1625 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1626 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1628 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1629 return;
1630
1631 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1632 tg3_phy_fet_toggle_apd(tp, enable);
1633 return;
1634 }
1635
1636 reg = MII_TG3_MISC_SHDW_WREN |
1637 MII_TG3_MISC_SHDW_SCR5_SEL |
1638 MII_TG3_MISC_SHDW_SCR5_LPED |
1639 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1640 MII_TG3_MISC_SHDW_SCR5_SDTL |
1641 MII_TG3_MISC_SHDW_SCR5_C125OE;
1642 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1643 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1644
1645 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1646
1647
1648 reg = MII_TG3_MISC_SHDW_WREN |
1649 MII_TG3_MISC_SHDW_APD_SEL |
1650 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1651 if (enable)
1652 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1653
1654 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655 }
1656
1657 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1658 {
1659 u32 phy;
1660
1661 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1662 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1663 return;
1664
1665 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666 u32 ephy;
1667
1668 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1669 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1670
1671 tg3_writephy(tp, MII_TG3_FET_TEST,
1672 ephy | MII_TG3_FET_SHADOW_EN);
1673 if (!tg3_readphy(tp, reg, &phy)) {
1674 if (enable)
1675 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676 else
1677 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1678 tg3_writephy(tp, reg, phy);
1679 }
1680 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1681 }
1682 } else {
1683 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1684 MII_TG3_AUXCTL_SHDWSEL_MISC;
1685 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1686 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1687 if (enable)
1688 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689 else
1690 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1691 phy |= MII_TG3_AUXCTL_MISC_WREN;
1692 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1693 }
1694 }
1695 }
1696
1697 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1698 {
1699 u32 val;
1700
1701 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1702 return;
1703
1704 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1705 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1706 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1707 (val | (1 << 15) | (1 << 4)));
1708 }
1709
1710 static void tg3_phy_apply_otp(struct tg3 *tp)
1711 {
1712 u32 otp, phy;
1713
1714 if (!tp->phy_otp)
1715 return;
1716
1717 otp = tp->phy_otp;
1718
1719 /* Enable SM_DSP clock and tx 6dB coding. */
1720 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1721 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1722 MII_TG3_AUXCTL_ACTL_TX_6DB;
1723 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1724
1725 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1726 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1727 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1728
1729 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1730 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1731 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1732
1733 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1734 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1735 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1736
1737 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1738 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1739
1740 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1741 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1742
1743 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1744 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1745 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1746
1747 /* Turn off SM_DSP clock. */
1748 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1749 MII_TG3_AUXCTL_ACTL_TX_6DB;
1750 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1751 }
1752
1753 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1754 {
1755 u32 val;
1756
1757 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1758 return;
1759
1760 tp->setlpicnt = 0;
1761
1762 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1763 current_link_up == 1 &&
1764 tp->link_config.active_duplex == DUPLEX_FULL &&
1765 (tp->link_config.active_speed == SPEED_100 ||
1766 tp->link_config.active_speed == SPEED_1000)) {
1767 u32 eeectl;
1768
1769 if (tp->link_config.active_speed == SPEED_1000)
1770 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1771 else
1772 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1773
1774 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1775
1776 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1777 TG3_CL45_D7_EEERES_STAT, &val);
1778
1779 switch (val) {
1780 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1781 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1782 case ASIC_REV_5717:
1783 case ASIC_REV_5719:
1784 case ASIC_REV_57765:
1785 /* Enable SM_DSP clock and tx 6dB coding. */
1786 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1787 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1788 MII_TG3_AUXCTL_ACTL_TX_6DB;
1789 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1790
1791 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1792
1793 /* Turn off SM_DSP clock. */
1794 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1795 MII_TG3_AUXCTL_ACTL_TX_6DB;
1796 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1797 }
1798 /* Fallthrough */
1799 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1800 tp->setlpicnt = 2;
1801 }
1802 }
1803
1804 if (!tp->setlpicnt) {
1805 val = tr32(TG3_CPMU_EEE_MODE);
1806 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1807 }
1808 }
1809
1810 static int tg3_wait_macro_done(struct tg3 *tp)
1811 {
1812 int limit = 100;
1813
1814 while (limit--) {
1815 u32 tmp32;
1816
1817 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1818 if ((tmp32 & 0x1000) == 0)
1819 break;
1820 }
1821 }
1822 if (limit < 0)
1823 return -EBUSY;
1824
1825 return 0;
1826 }
1827
1828 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1829 {
1830 static const u32 test_pat[4][6] = {
1831 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1832 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1833 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1834 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1835 };
1836 int chan;
1837
1838 for (chan = 0; chan < 4; chan++) {
1839 int i;
1840
1841 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1842 (chan * 0x2000) | 0x0200);
1843 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1844
1845 for (i = 0; i < 6; i++)
1846 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1847 test_pat[chan][i]);
1848
1849 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1850 if (tg3_wait_macro_done(tp)) {
1851 *resetp = 1;
1852 return -EBUSY;
1853 }
1854
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1856 (chan * 0x2000) | 0x0200);
1857 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1858 if (tg3_wait_macro_done(tp)) {
1859 *resetp = 1;
1860 return -EBUSY;
1861 }
1862
1863 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1864 if (tg3_wait_macro_done(tp)) {
1865 *resetp = 1;
1866 return -EBUSY;
1867 }
1868
1869 for (i = 0; i < 6; i += 2) {
1870 u32 low, high;
1871
1872 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1873 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1874 tg3_wait_macro_done(tp)) {
1875 *resetp = 1;
1876 return -EBUSY;
1877 }
1878 low &= 0x7fff;
1879 high &= 0x000f;
1880 if (low != test_pat[chan][i] ||
1881 high != test_pat[chan][i+1]) {
1882 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1884 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1885
1886 return -EBUSY;
1887 }
1888 }
1889 }
1890
1891 return 0;
1892 }
1893
1894 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1895 {
1896 int chan;
1897
1898 for (chan = 0; chan < 4; chan++) {
1899 int i;
1900
1901 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1902 (chan * 0x2000) | 0x0200);
1903 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1904 for (i = 0; i < 6; i++)
1905 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1906 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1907 if (tg3_wait_macro_done(tp))
1908 return -EBUSY;
1909 }
1910
1911 return 0;
1912 }
1913
1914 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1915 {
1916 u32 reg32, phy9_orig;
1917 int retries, do_phy_reset, err;
1918
1919 retries = 10;
1920 do_phy_reset = 1;
1921 do {
1922 if (do_phy_reset) {
1923 err = tg3_bmcr_reset(tp);
1924 if (err)
1925 return err;
1926 do_phy_reset = 0;
1927 }
1928
1929 /* Disable transmitter and interrupt. */
1930 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1931 continue;
1932
1933 reg32 |= 0x3000;
1934 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1935
1936 /* Set full-duplex, 1000 mbps. */
1937 tg3_writephy(tp, MII_BMCR,
1938 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1939
1940 /* Set to master mode. */
1941 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1942 continue;
1943
1944 tg3_writephy(tp, MII_TG3_CTRL,
1945 (MII_TG3_CTRL_AS_MASTER |
1946 MII_TG3_CTRL_ENABLE_AS_MASTER));
1947
1948 /* Enable SM_DSP_CLOCK and 6dB. */
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950
1951 /* Block the PHY control access. */
1952 tg3_phydsp_write(tp, 0x8005, 0x0800);
1953
1954 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1955 if (!err)
1956 break;
1957 } while (--retries);
1958
1959 err = tg3_phy_reset_chanpat(tp);
1960 if (err)
1961 return err;
1962
1963 tg3_phydsp_write(tp, 0x8005, 0x0000);
1964
1965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1966 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1967
1968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1970 /* Set Extended packet length bit for jumbo frames */
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1972 } else {
1973 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1974 }
1975
1976 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1977
1978 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1979 reg32 &= ~0x3000;
1980 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1981 } else if (!err)
1982 err = -EBUSY;
1983
1984 return err;
1985 }
1986
1987 /* This will reset the tigon3 PHY if there is no valid
1988 * link unless the FORCE argument is non-zero.
1989 */
1990 static int tg3_phy_reset(struct tg3 *tp)
1991 {
1992 u32 val, cpmuctrl;
1993 int err;
1994
1995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1996 val = tr32(GRC_MISC_CFG);
1997 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1998 udelay(40);
1999 }
2000 err = tg3_readphy(tp, MII_BMSR, &val);
2001 err |= tg3_readphy(tp, MII_BMSR, &val);
2002 if (err != 0)
2003 return -EBUSY;
2004
2005 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2006 netif_carrier_off(tp->dev);
2007 tg3_link_report(tp);
2008 }
2009
2010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2013 err = tg3_phy_reset_5703_4_5(tp);
2014 if (err)
2015 return err;
2016 goto out;
2017 }
2018
2019 cpmuctrl = 0;
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2021 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2022 cpmuctrl = tr32(TG3_CPMU_CTRL);
2023 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2024 tw32(TG3_CPMU_CTRL,
2025 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2026 }
2027
2028 err = tg3_bmcr_reset(tp);
2029 if (err)
2030 return err;
2031
2032 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2033 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2034 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2035
2036 tw32(TG3_CPMU_CTRL, cpmuctrl);
2037 }
2038
2039 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2040 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2041 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2042 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2043 CPMU_LSPD_1000MB_MACCLK_12_5) {
2044 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2045 udelay(40);
2046 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2047 }
2048 }
2049
2050 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2052 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2053 return 0;
2054
2055 tg3_phy_apply_otp(tp);
2056
2057 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2058 tg3_phy_toggle_apd(tp, true);
2059 else
2060 tg3_phy_toggle_apd(tp, false);
2061
2062 out:
2063 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2065 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2066 tg3_phydsp_write(tp, 0x000a, 0x0323);
2067 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2068 }
2069 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2070 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2071 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2072 }
2073 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2074 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2075 tg3_phydsp_write(tp, 0x000a, 0x310b);
2076 tg3_phydsp_write(tp, 0x201f, 0x9506);
2077 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2078 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2079 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2080 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2081 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2082 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2083 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2084 tg3_writephy(tp, MII_TG3_TEST1,
2085 MII_TG3_TEST1_TRIM_EN | 0x4);
2086 } else
2087 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2088 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2089 }
2090 /* Set Extended packet length bit (bit 14) on all chips that */
2091 /* support jumbo frames */
2092 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2093 /* Cannot do read-modify-write on 5401 */
2094 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2095 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2096 /* Set bit 14 with read-modify-write to preserve other bits */
2097 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2098 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2099 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2100 }
2101
2102 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2103 * jumbo frames transmission.
2104 */
2105 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2106 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2108 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2109 }
2110
2111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2112 /* adjust output voltage */
2113 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2114 }
2115
2116 tg3_phy_toggle_automdix(tp, 1);
2117 tg3_phy_set_wirespeed(tp);
2118 return 0;
2119 }
2120
2121 static void tg3_frob_aux_power(struct tg3 *tp)
2122 {
2123 bool need_vaux = false;
2124
2125 /* The GPIOs do something completely different on 57765. */
2126 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2128 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2129 return;
2130
2131 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2133 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) &&
2134 tp->pdev_peer != tp->pdev) {
2135 struct net_device *dev_peer;
2136
2137 dev_peer = pci_get_drvdata(tp->pdev_peer);
2138
2139 /* remove_one() may have been run on the peer. */
2140 if (dev_peer) {
2141 struct tg3 *tp_peer = netdev_priv(dev_peer);
2142
2143 if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2144 return;
2145
2146 if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2147 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2148 need_vaux = true;
2149 }
2150 }
2151
2152 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2153 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2154 need_vaux = true;
2155
2156 if (need_vaux) {
2157 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2158 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2159 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2160 (GRC_LCLCTRL_GPIO_OE0 |
2161 GRC_LCLCTRL_GPIO_OE1 |
2162 GRC_LCLCTRL_GPIO_OE2 |
2163 GRC_LCLCTRL_GPIO_OUTPUT0 |
2164 GRC_LCLCTRL_GPIO_OUTPUT1),
2165 100);
2166 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2167 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2168 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2169 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2170 GRC_LCLCTRL_GPIO_OE1 |
2171 GRC_LCLCTRL_GPIO_OE2 |
2172 GRC_LCLCTRL_GPIO_OUTPUT0 |
2173 GRC_LCLCTRL_GPIO_OUTPUT1 |
2174 tp->grc_local_ctrl;
2175 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2176
2177 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2178 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2179
2180 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2181 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2182 } else {
2183 u32 no_gpio2;
2184 u32 grc_local_ctrl = 0;
2185
2186 /* Workaround to prevent overdrawing Amps. */
2187 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2188 ASIC_REV_5714) {
2189 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2190 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2191 grc_local_ctrl, 100);
2192 }
2193
2194 /* On 5753 and variants, GPIO2 cannot be used. */
2195 no_gpio2 = tp->nic_sram_data_cfg &
2196 NIC_SRAM_DATA_CFG_NO_GPIO2;
2197
2198 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2199 GRC_LCLCTRL_GPIO_OE1 |
2200 GRC_LCLCTRL_GPIO_OE2 |
2201 GRC_LCLCTRL_GPIO_OUTPUT1 |
2202 GRC_LCLCTRL_GPIO_OUTPUT2;
2203 if (no_gpio2) {
2204 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2205 GRC_LCLCTRL_GPIO_OUTPUT2);
2206 }
2207 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2208 grc_local_ctrl, 100);
2209
2210 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2211
2212 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2213 grc_local_ctrl, 100);
2214
2215 if (!no_gpio2) {
2216 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2217 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218 grc_local_ctrl, 100);
2219 }
2220 }
2221 } else {
2222 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2223 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2224 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2225 (GRC_LCLCTRL_GPIO_OE1 |
2226 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2227
2228 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2229 GRC_LCLCTRL_GPIO_OE1, 100);
2230
2231 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2232 (GRC_LCLCTRL_GPIO_OE1 |
2233 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2234 }
2235 }
2236 }
2237
2238 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2239 {
2240 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2241 return 1;
2242 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2243 if (speed != SPEED_10)
2244 return 1;
2245 } else if (speed == SPEED_10)
2246 return 1;
2247
2248 return 0;
2249 }
2250
2251 static int tg3_setup_phy(struct tg3 *, int);
2252
2253 #define RESET_KIND_SHUTDOWN 0
2254 #define RESET_KIND_INIT 1
2255 #define RESET_KIND_SUSPEND 2
2256
2257 static void tg3_write_sig_post_reset(struct tg3 *, int);
2258 static int tg3_halt_cpu(struct tg3 *, u32);
2259
2260 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2261 {
2262 u32 val;
2263
2264 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2266 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2267 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2268
2269 sg_dig_ctrl |=
2270 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2271 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2272 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2273 }
2274 return;
2275 }
2276
2277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2278 tg3_bmcr_reset(tp);
2279 val = tr32(GRC_MISC_CFG);
2280 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2281 udelay(40);
2282 return;
2283 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2284 u32 phytest;
2285 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2286 u32 phy;
2287
2288 tg3_writephy(tp, MII_ADVERTISE, 0);
2289 tg3_writephy(tp, MII_BMCR,
2290 BMCR_ANENABLE | BMCR_ANRESTART);
2291
2292 tg3_writephy(tp, MII_TG3_FET_TEST,
2293 phytest | MII_TG3_FET_SHADOW_EN);
2294 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2295 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2296 tg3_writephy(tp,
2297 MII_TG3_FET_SHDW_AUXMODE4,
2298 phy);
2299 }
2300 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2301 }
2302 return;
2303 } else if (do_low_power) {
2304 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2305 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2306
2307 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2308 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2309 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2310 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2311 MII_TG3_AUXCTL_PCTL_VREG_11V);
2312 }
2313
2314 /* The PHY should not be powered down on some chips because
2315 * of bugs.
2316 */
2317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2319 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2320 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2321 return;
2322
2323 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2324 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2325 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2326 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2327 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2328 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2329 }
2330
2331 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2332 }
2333
2334 /* tp->lock is held. */
2335 static int tg3_nvram_lock(struct tg3 *tp)
2336 {
2337 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2338 int i;
2339
2340 if (tp->nvram_lock_cnt == 0) {
2341 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2342 for (i = 0; i < 8000; i++) {
2343 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2344 break;
2345 udelay(20);
2346 }
2347 if (i == 8000) {
2348 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2349 return -ENODEV;
2350 }
2351 }
2352 tp->nvram_lock_cnt++;
2353 }
2354 return 0;
2355 }
2356
2357 /* tp->lock is held. */
2358 static void tg3_nvram_unlock(struct tg3 *tp)
2359 {
2360 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2361 if (tp->nvram_lock_cnt > 0)
2362 tp->nvram_lock_cnt--;
2363 if (tp->nvram_lock_cnt == 0)
2364 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2365 }
2366 }
2367
2368 /* tp->lock is held. */
2369 static void tg3_enable_nvram_access(struct tg3 *tp)
2370 {
2371 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2372 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2373 u32 nvaccess = tr32(NVRAM_ACCESS);
2374
2375 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2376 }
2377 }
2378
2379 /* tp->lock is held. */
2380 static void tg3_disable_nvram_access(struct tg3 *tp)
2381 {
2382 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2383 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2384 u32 nvaccess = tr32(NVRAM_ACCESS);
2385
2386 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2387 }
2388 }
2389
2390 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2391 u32 offset, u32 *val)
2392 {
2393 u32 tmp;
2394 int i;
2395
2396 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2397 return -EINVAL;
2398
2399 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2400 EEPROM_ADDR_DEVID_MASK |
2401 EEPROM_ADDR_READ);
2402 tw32(GRC_EEPROM_ADDR,
2403 tmp |
2404 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2405 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2406 EEPROM_ADDR_ADDR_MASK) |
2407 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2408
2409 for (i = 0; i < 1000; i++) {
2410 tmp = tr32(GRC_EEPROM_ADDR);
2411
2412 if (tmp & EEPROM_ADDR_COMPLETE)
2413 break;
2414 msleep(1);
2415 }
2416 if (!(tmp & EEPROM_ADDR_COMPLETE))
2417 return -EBUSY;
2418
2419 tmp = tr32(GRC_EEPROM_DATA);
2420
2421 /*
2422 * The data will always be opposite the native endian
2423 * format. Perform a blind byteswap to compensate.
2424 */
2425 *val = swab32(tmp);
2426
2427 return 0;
2428 }
2429
2430 #define NVRAM_CMD_TIMEOUT 10000
2431
2432 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2433 {
2434 int i;
2435
2436 tw32(NVRAM_CMD, nvram_cmd);
2437 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2438 udelay(10);
2439 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2440 udelay(10);
2441 break;
2442 }
2443 }
2444
2445 if (i == NVRAM_CMD_TIMEOUT)
2446 return -EBUSY;
2447
2448 return 0;
2449 }
2450
2451 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2452 {
2453 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2454 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2455 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2456 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2457 (tp->nvram_jedecnum == JEDEC_ATMEL))
2458
2459 addr = ((addr / tp->nvram_pagesize) <<
2460 ATMEL_AT45DB0X1B_PAGE_POS) +
2461 (addr % tp->nvram_pagesize);
2462
2463 return addr;
2464 }
2465
2466 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2467 {
2468 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2469 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2470 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2471 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2472 (tp->nvram_jedecnum == JEDEC_ATMEL))
2473
2474 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2475 tp->nvram_pagesize) +
2476 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2477
2478 return addr;
2479 }
2480
2481 /* NOTE: Data read in from NVRAM is byteswapped according to
2482 * the byteswapping settings for all other register accesses.
2483 * tg3 devices are BE devices, so on a BE machine, the data
2484 * returned will be exactly as it is seen in NVRAM. On a LE
2485 * machine, the 32-bit value will be byteswapped.
2486 */
2487 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2488 {
2489 int ret;
2490
2491 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2492 return tg3_nvram_read_using_eeprom(tp, offset, val);
2493
2494 offset = tg3_nvram_phys_addr(tp, offset);
2495
2496 if (offset > NVRAM_ADDR_MSK)
2497 return -EINVAL;
2498
2499 ret = tg3_nvram_lock(tp);
2500 if (ret)
2501 return ret;
2502
2503 tg3_enable_nvram_access(tp);
2504
2505 tw32(NVRAM_ADDR, offset);
2506 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2507 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2508
2509 if (ret == 0)
2510 *val = tr32(NVRAM_RDDATA);
2511
2512 tg3_disable_nvram_access(tp);
2513
2514 tg3_nvram_unlock(tp);
2515
2516 return ret;
2517 }
2518
2519 /* Ensures NVRAM data is in bytestream format. */
2520 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2521 {
2522 u32 v;
2523 int res = tg3_nvram_read(tp, offset, &v);
2524 if (!res)
2525 *val = cpu_to_be32(v);
2526 return res;
2527 }
2528
2529 /* tp->lock is held. */
2530 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2531 {
2532 u32 addr_high, addr_low;
2533 int i;
2534
2535 addr_high = ((tp->dev->dev_addr[0] << 8) |
2536 tp->dev->dev_addr[1]);
2537 addr_low = ((tp->dev->dev_addr[2] << 24) |
2538 (tp->dev->dev_addr[3] << 16) |
2539 (tp->dev->dev_addr[4] << 8) |
2540 (tp->dev->dev_addr[5] << 0));
2541 for (i = 0; i < 4; i++) {
2542 if (i == 1 && skip_mac_1)
2543 continue;
2544 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2545 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2546 }
2547
2548 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2550 for (i = 0; i < 12; i++) {
2551 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2552 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2553 }
2554 }
2555
2556 addr_high = (tp->dev->dev_addr[0] +
2557 tp->dev->dev_addr[1] +
2558 tp->dev->dev_addr[2] +
2559 tp->dev->dev_addr[3] +
2560 tp->dev->dev_addr[4] +
2561 tp->dev->dev_addr[5]) &
2562 TX_BACKOFF_SEED_MASK;
2563 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2564 }
2565
2566 static void tg3_enable_register_access(struct tg3 *tp)
2567 {
2568 /*
2569 * Make sure register accesses (indirect or otherwise) will function
2570 * correctly.
2571 */
2572 pci_write_config_dword(tp->pdev,
2573 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2574 }
2575
2576 static int tg3_power_up(struct tg3 *tp)
2577 {
2578 tg3_enable_register_access(tp);
2579
2580 pci_set_power_state(tp->pdev, PCI_D0);
2581
2582 /* Switch out of Vaux if it is a NIC */
2583 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2584 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2585
2586 return 0;
2587 }
2588
2589 static int tg3_power_down_prepare(struct tg3 *tp)
2590 {
2591 u32 misc_host_ctrl;
2592 bool device_should_wake, do_low_power;
2593
2594 tg3_enable_register_access(tp);
2595
2596 /* Restore the CLKREQ setting. */
2597 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2598 u16 lnkctl;
2599
2600 pci_read_config_word(tp->pdev,
2601 tp->pcie_cap + PCI_EXP_LNKCTL,
2602 &lnkctl);
2603 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2604 pci_write_config_word(tp->pdev,
2605 tp->pcie_cap + PCI_EXP_LNKCTL,
2606 lnkctl);
2607 }
2608
2609 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2610 tw32(TG3PCI_MISC_HOST_CTRL,
2611 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2612
2613 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2614 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2615
2616 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2617 do_low_power = false;
2618 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2619 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2620 struct phy_device *phydev;
2621 u32 phyid, advertising;
2622
2623 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2624
2625 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2626
2627 tp->link_config.orig_speed = phydev->speed;
2628 tp->link_config.orig_duplex = phydev->duplex;
2629 tp->link_config.orig_autoneg = phydev->autoneg;
2630 tp->link_config.orig_advertising = phydev->advertising;
2631
2632 advertising = ADVERTISED_TP |
2633 ADVERTISED_Pause |
2634 ADVERTISED_Autoneg |
2635 ADVERTISED_10baseT_Half;
2636
2637 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2638 device_should_wake) {
2639 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2640 advertising |=
2641 ADVERTISED_100baseT_Half |
2642 ADVERTISED_100baseT_Full |
2643 ADVERTISED_10baseT_Full;
2644 else
2645 advertising |= ADVERTISED_10baseT_Full;
2646 }
2647
2648 phydev->advertising = advertising;
2649
2650 phy_start_aneg(phydev);
2651
2652 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2653 if (phyid != PHY_ID_BCMAC131) {
2654 phyid &= PHY_BCM_OUI_MASK;
2655 if (phyid == PHY_BCM_OUI_1 ||
2656 phyid == PHY_BCM_OUI_2 ||
2657 phyid == PHY_BCM_OUI_3)
2658 do_low_power = true;
2659 }
2660 }
2661 } else {
2662 do_low_power = true;
2663
2664 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2665 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2666 tp->link_config.orig_speed = tp->link_config.speed;
2667 tp->link_config.orig_duplex = tp->link_config.duplex;
2668 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2669 }
2670
2671 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2672 tp->link_config.speed = SPEED_10;
2673 tp->link_config.duplex = DUPLEX_HALF;
2674 tp->link_config.autoneg = AUTONEG_ENABLE;
2675 tg3_setup_phy(tp, 0);
2676 }
2677 }
2678
2679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2680 u32 val;
2681
2682 val = tr32(GRC_VCPU_EXT_CTRL);
2683 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2684 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2685 int i;
2686 u32 val;
2687
2688 for (i = 0; i < 200; i++) {
2689 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2690 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2691 break;
2692 msleep(1);
2693 }
2694 }
2695 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2696 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2697 WOL_DRV_STATE_SHUTDOWN |
2698 WOL_DRV_WOL |
2699 WOL_SET_MAGIC_PKT);
2700
2701 if (device_should_wake) {
2702 u32 mac_mode;
2703
2704 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2705 if (do_low_power) {
2706 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2707 udelay(40);
2708 }
2709
2710 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2711 mac_mode = MAC_MODE_PORT_MODE_GMII;
2712 else
2713 mac_mode = MAC_MODE_PORT_MODE_MII;
2714
2715 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2716 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2717 ASIC_REV_5700) {
2718 u32 speed = (tp->tg3_flags &
2719 TG3_FLAG_WOL_SPEED_100MB) ?
2720 SPEED_100 : SPEED_10;
2721 if (tg3_5700_link_polarity(tp, speed))
2722 mac_mode |= MAC_MODE_LINK_POLARITY;
2723 else
2724 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2725 }
2726 } else {
2727 mac_mode = MAC_MODE_PORT_MODE_TBI;
2728 }
2729
2730 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2731 tw32(MAC_LED_CTRL, tp->led_ctrl);
2732
2733 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2734 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2735 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2736 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2737 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2738 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2739
2740 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2741 mac_mode |= MAC_MODE_APE_TX_EN |
2742 MAC_MODE_APE_RX_EN |
2743 MAC_MODE_TDE_ENABLE;
2744
2745 tw32_f(MAC_MODE, mac_mode);
2746 udelay(100);
2747
2748 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2749 udelay(10);
2750 }
2751
2752 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2755 u32 base_val;
2756
2757 base_val = tp->pci_clock_ctrl;
2758 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2759 CLOCK_CTRL_TXCLK_DISABLE);
2760
2761 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2762 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2763 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2764 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2765 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2766 /* do nothing */
2767 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2768 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2769 u32 newbits1, newbits2;
2770
2771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2773 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2774 CLOCK_CTRL_TXCLK_DISABLE |
2775 CLOCK_CTRL_ALTCLK);
2776 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2777 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2778 newbits1 = CLOCK_CTRL_625_CORE;
2779 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2780 } else {
2781 newbits1 = CLOCK_CTRL_ALTCLK;
2782 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2783 }
2784
2785 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2786 40);
2787
2788 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2789 40);
2790
2791 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2792 u32 newbits3;
2793
2794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2796 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2797 CLOCK_CTRL_TXCLK_DISABLE |
2798 CLOCK_CTRL_44MHZ_CORE);
2799 } else {
2800 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2801 }
2802
2803 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2804 tp->pci_clock_ctrl | newbits3, 40);
2805 }
2806 }
2807
2808 if (!(device_should_wake) &&
2809 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2810 tg3_power_down_phy(tp, do_low_power);
2811
2812 tg3_frob_aux_power(tp);
2813
2814 /* Workaround for unstable PLL clock */
2815 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2816 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2817 u32 val = tr32(0x7d00);
2818
2819 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2820 tw32(0x7d00, val);
2821 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2822 int err;
2823
2824 err = tg3_nvram_lock(tp);
2825 tg3_halt_cpu(tp, RX_CPU_BASE);
2826 if (!err)
2827 tg3_nvram_unlock(tp);
2828 }
2829 }
2830
2831 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2832
2833 return 0;
2834 }
2835
2836 static void tg3_power_down(struct tg3 *tp)
2837 {
2838 tg3_power_down_prepare(tp);
2839
2840 pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2841 pci_set_power_state(tp->pdev, PCI_D3hot);
2842 }
2843
2844 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2845 {
2846 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2847 case MII_TG3_AUX_STAT_10HALF:
2848 *speed = SPEED_10;
2849 *duplex = DUPLEX_HALF;
2850 break;
2851
2852 case MII_TG3_AUX_STAT_10FULL:
2853 *speed = SPEED_10;
2854 *duplex = DUPLEX_FULL;
2855 break;
2856
2857 case MII_TG3_AUX_STAT_100HALF:
2858 *speed = SPEED_100;
2859 *duplex = DUPLEX_HALF;
2860 break;
2861
2862 case MII_TG3_AUX_STAT_100FULL:
2863 *speed = SPEED_100;
2864 *duplex = DUPLEX_FULL;
2865 break;
2866
2867 case MII_TG3_AUX_STAT_1000HALF:
2868 *speed = SPEED_1000;
2869 *duplex = DUPLEX_HALF;
2870 break;
2871
2872 case MII_TG3_AUX_STAT_1000FULL:
2873 *speed = SPEED_1000;
2874 *duplex = DUPLEX_FULL;
2875 break;
2876
2877 default:
2878 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2879 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2880 SPEED_10;
2881 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2882 DUPLEX_HALF;
2883 break;
2884 }
2885 *speed = SPEED_INVALID;
2886 *duplex = DUPLEX_INVALID;
2887 break;
2888 }
2889 }
2890
2891 static void tg3_phy_copper_begin(struct tg3 *tp)
2892 {
2893 u32 new_adv;
2894 int i;
2895
2896 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2897 /* Entering low power mode. Disable gigabit and
2898 * 100baseT advertisements.
2899 */
2900 tg3_writephy(tp, MII_TG3_CTRL, 0);
2901
2902 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2903 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2904 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2905 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2906
2907 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2908 } else if (tp->link_config.speed == SPEED_INVALID) {
2909 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2910 tp->link_config.advertising &=
2911 ~(ADVERTISED_1000baseT_Half |
2912 ADVERTISED_1000baseT_Full);
2913
2914 new_adv = ADVERTISE_CSMA;
2915 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2916 new_adv |= ADVERTISE_10HALF;
2917 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2918 new_adv |= ADVERTISE_10FULL;
2919 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2920 new_adv |= ADVERTISE_100HALF;
2921 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2922 new_adv |= ADVERTISE_100FULL;
2923
2924 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925
2926 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2927
2928 if (tp->link_config.advertising &
2929 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2930 new_adv = 0;
2931 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2932 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2933 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2934 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2935 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2936 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2937 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2938 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2939 MII_TG3_CTRL_ENABLE_AS_MASTER);
2940 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2941 } else {
2942 tg3_writephy(tp, MII_TG3_CTRL, 0);
2943 }
2944 } else {
2945 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2946 new_adv |= ADVERTISE_CSMA;
2947
2948 /* Asking for a specific link mode. */
2949 if (tp->link_config.speed == SPEED_1000) {
2950 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2951
2952 if (tp->link_config.duplex == DUPLEX_FULL)
2953 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2954 else
2955 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2956 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2957 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2958 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2959 MII_TG3_CTRL_ENABLE_AS_MASTER);
2960 } else {
2961 if (tp->link_config.speed == SPEED_100) {
2962 if (tp->link_config.duplex == DUPLEX_FULL)
2963 new_adv |= ADVERTISE_100FULL;
2964 else
2965 new_adv |= ADVERTISE_100HALF;
2966 } else {
2967 if (tp->link_config.duplex == DUPLEX_FULL)
2968 new_adv |= ADVERTISE_10FULL;
2969 else
2970 new_adv |= ADVERTISE_10HALF;
2971 }
2972 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2973
2974 new_adv = 0;
2975 }
2976
2977 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2978 }
2979
2980 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2981 u32 val;
2982
2983 tw32(TG3_CPMU_EEE_MODE,
2984 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2985
2986 /* Enable SM_DSP clock and tx 6dB coding. */
2987 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2988 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2989 MII_TG3_AUXCTL_ACTL_TX_6DB;
2990 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2991
2992 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2993 case ASIC_REV_5717:
2994 case ASIC_REV_57765:
2995 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2996 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2997 MII_TG3_DSP_CH34TP2_HIBW01);
2998 /* Fall through */
2999 case ASIC_REV_5719:
3000 val = MII_TG3_DSP_TAP26_ALNOKO |
3001 MII_TG3_DSP_TAP26_RMRXSTO |
3002 MII_TG3_DSP_TAP26_OPCSINPT;
3003 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3004 }
3005
3006 val = 0;
3007 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3008 /* Advertise 100-BaseTX EEE ability */
3009 if (tp->link_config.advertising &
3010 ADVERTISED_100baseT_Full)
3011 val |= MDIO_AN_EEE_ADV_100TX;
3012 /* Advertise 1000-BaseT EEE ability */
3013 if (tp->link_config.advertising &
3014 ADVERTISED_1000baseT_Full)
3015 val |= MDIO_AN_EEE_ADV_1000T;
3016 }
3017 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3018
3019 /* Turn off SM_DSP clock. */
3020 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3021 MII_TG3_AUXCTL_ACTL_TX_6DB;
3022 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3023 }
3024
3025 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3026 tp->link_config.speed != SPEED_INVALID) {
3027 u32 bmcr, orig_bmcr;
3028
3029 tp->link_config.active_speed = tp->link_config.speed;
3030 tp->link_config.active_duplex = tp->link_config.duplex;
3031
3032 bmcr = 0;
3033 switch (tp->link_config.speed) {
3034 default:
3035 case SPEED_10:
3036 break;
3037
3038 case SPEED_100:
3039 bmcr |= BMCR_SPEED100;
3040 break;
3041
3042 case SPEED_1000:
3043 bmcr |= TG3_BMCR_SPEED1000;
3044 break;
3045 }
3046
3047 if (tp->link_config.duplex == DUPLEX_FULL)
3048 bmcr |= BMCR_FULLDPLX;
3049
3050 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3051 (bmcr != orig_bmcr)) {
3052 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3053 for (i = 0; i < 1500; i++) {
3054 u32 tmp;
3055
3056 udelay(10);
3057 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3058 tg3_readphy(tp, MII_BMSR, &tmp))
3059 continue;
3060 if (!(tmp & BMSR_LSTATUS)) {
3061 udelay(40);
3062 break;
3063 }
3064 }
3065 tg3_writephy(tp, MII_BMCR, bmcr);
3066 udelay(40);
3067 }
3068 } else {
3069 tg3_writephy(tp, MII_BMCR,
3070 BMCR_ANENABLE | BMCR_ANRESTART);
3071 }
3072 }
3073
3074 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3075 {
3076 int err;
3077
3078 /* Turn off tap power management. */
3079 /* Set Extended packet length bit */
3080 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3081
3082 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3083 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3084 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3085 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3086 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3087
3088 udelay(40);
3089
3090 return err;
3091 }
3092
3093 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3094 {
3095 u32 adv_reg, all_mask = 0;
3096
3097 if (mask & ADVERTISED_10baseT_Half)
3098 all_mask |= ADVERTISE_10HALF;
3099 if (mask & ADVERTISED_10baseT_Full)
3100 all_mask |= ADVERTISE_10FULL;
3101 if (mask & ADVERTISED_100baseT_Half)
3102 all_mask |= ADVERTISE_100HALF;
3103 if (mask & ADVERTISED_100baseT_Full)
3104 all_mask |= ADVERTISE_100FULL;
3105
3106 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3107 return 0;
3108
3109 if ((adv_reg & all_mask) != all_mask)
3110 return 0;
3111 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3112 u32 tg3_ctrl;
3113
3114 all_mask = 0;
3115 if (mask & ADVERTISED_1000baseT_Half)
3116 all_mask |= ADVERTISE_1000HALF;
3117 if (mask & ADVERTISED_1000baseT_Full)
3118 all_mask |= ADVERTISE_1000FULL;
3119
3120 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3121 return 0;
3122
3123 if ((tg3_ctrl & all_mask) != all_mask)
3124 return 0;
3125 }
3126 return 1;
3127 }
3128
3129 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3130 {
3131 u32 curadv, reqadv;
3132
3133 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3134 return 1;
3135
3136 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3137 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3138
3139 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3140 if (curadv != reqadv)
3141 return 0;
3142
3143 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3144 tg3_readphy(tp, MII_LPA, rmtadv);
3145 } else {
3146 /* Reprogram the advertisement register, even if it
3147 * does not affect the current link. If the link
3148 * gets renegotiated in the future, we can save an
3149 * additional renegotiation cycle by advertising
3150 * it correctly in the first place.
3151 */
3152 if (curadv != reqadv) {
3153 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3154 ADVERTISE_PAUSE_ASYM);
3155 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3156 }
3157 }
3158
3159 return 1;
3160 }
3161
3162 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3163 {
3164 int current_link_up;
3165 u32 bmsr, val;
3166 u32 lcl_adv, rmt_adv;
3167 u16 current_speed;
3168 u8 current_duplex;
3169 int i, err;
3170
3171 tw32(MAC_EVENT, 0);
3172
3173 tw32_f(MAC_STATUS,
3174 (MAC_STATUS_SYNC_CHANGED |
3175 MAC_STATUS_CFG_CHANGED |
3176 MAC_STATUS_MI_COMPLETION |
3177 MAC_STATUS_LNKSTATE_CHANGED));
3178 udelay(40);
3179
3180 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3181 tw32_f(MAC_MI_MODE,
3182 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3183 udelay(80);
3184 }
3185
3186 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3187
3188 /* Some third-party PHYs need to be reset on link going
3189 * down.
3190 */
3191 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3194 netif_carrier_ok(tp->dev)) {
3195 tg3_readphy(tp, MII_BMSR, &bmsr);
3196 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3197 !(bmsr & BMSR_LSTATUS))
3198 force_reset = 1;
3199 }
3200 if (force_reset)
3201 tg3_phy_reset(tp);
3202
3203 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3204 tg3_readphy(tp, MII_BMSR, &bmsr);
3205 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3206 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3207 bmsr = 0;
3208
3209 if (!(bmsr & BMSR_LSTATUS)) {
3210 err = tg3_init_5401phy_dsp(tp);
3211 if (err)
3212 return err;
3213
3214 tg3_readphy(tp, MII_BMSR, &bmsr);
3215 for (i = 0; i < 1000; i++) {
3216 udelay(10);
3217 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3218 (bmsr & BMSR_LSTATUS)) {
3219 udelay(40);
3220 break;
3221 }
3222 }
3223
3224 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3225 TG3_PHY_REV_BCM5401_B0 &&
3226 !(bmsr & BMSR_LSTATUS) &&
3227 tp->link_config.active_speed == SPEED_1000) {
3228 err = tg3_phy_reset(tp);
3229 if (!err)
3230 err = tg3_init_5401phy_dsp(tp);
3231 if (err)
3232 return err;
3233 }
3234 }
3235 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3236 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3237 /* 5701 {A0,B0} CRC bug workaround */
3238 tg3_writephy(tp, 0x15, 0x0a75);
3239 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3240 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3241 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3242 }
3243
3244 /* Clear pending interrupts... */
3245 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3246 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3247
3248 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3249 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3250 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3251 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3252
3253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3255 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3256 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3257 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3258 else
3259 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3260 }
3261
3262 current_link_up = 0;
3263 current_speed = SPEED_INVALID;
3264 current_duplex = DUPLEX_INVALID;
3265
3266 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3267 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3268 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3269 if (!(val & (1 << 10))) {
3270 val |= (1 << 10);
3271 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3272 goto relink;
3273 }
3274 }
3275
3276 bmsr = 0;
3277 for (i = 0; i < 100; i++) {
3278 tg3_readphy(tp, MII_BMSR, &bmsr);
3279 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3280 (bmsr & BMSR_LSTATUS))
3281 break;
3282 udelay(40);
3283 }
3284
3285 if (bmsr & BMSR_LSTATUS) {
3286 u32 aux_stat, bmcr;
3287
3288 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3289 for (i = 0; i < 2000; i++) {
3290 udelay(10);
3291 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3292 aux_stat)
3293 break;
3294 }
3295
3296 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3297 &current_speed,
3298 &current_duplex);
3299
3300 bmcr = 0;
3301 for (i = 0; i < 200; i++) {
3302 tg3_readphy(tp, MII_BMCR, &bmcr);
3303 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3304 continue;
3305 if (bmcr && bmcr != 0x7fff)
3306 break;
3307 udelay(10);
3308 }
3309
3310 lcl_adv = 0;
3311 rmt_adv = 0;
3312
3313 tp->link_config.active_speed = current_speed;
3314 tp->link_config.active_duplex = current_duplex;
3315
3316 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3317 if ((bmcr & BMCR_ANENABLE) &&
3318 tg3_copper_is_advertising_all(tp,
3319 tp->link_config.advertising)) {
3320 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3321 &rmt_adv))
3322 current_link_up = 1;
3323 }
3324 } else {
3325 if (!(bmcr & BMCR_ANENABLE) &&
3326 tp->link_config.speed == current_speed &&
3327 tp->link_config.duplex == current_duplex &&
3328 tp->link_config.flowctrl ==
3329 tp->link_config.active_flowctrl) {
3330 current_link_up = 1;
3331 }
3332 }
3333
3334 if (current_link_up == 1 &&
3335 tp->link_config.active_duplex == DUPLEX_FULL)
3336 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3337 }
3338
3339 relink:
3340 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3341 tg3_phy_copper_begin(tp);
3342
3343 tg3_readphy(tp, MII_BMSR, &bmsr);
3344 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3345 (bmsr & BMSR_LSTATUS))
3346 current_link_up = 1;
3347 }
3348
3349 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3350 if (current_link_up == 1) {
3351 if (tp->link_config.active_speed == SPEED_100 ||
3352 tp->link_config.active_speed == SPEED_10)
3353 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3354 else
3355 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3356 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3357 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3358 else
3359 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3360
3361 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3362 if (tp->link_config.active_duplex == DUPLEX_HALF)
3363 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3364
3365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3366 if (current_link_up == 1 &&
3367 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3368 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3369 else
3370 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3371 }
3372
3373 /* ??? Without this setting Netgear GA302T PHY does not
3374 * ??? send/receive packets...
3375 */
3376 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3377 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3378 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3379 tw32_f(MAC_MI_MODE, tp->mi_mode);
3380 udelay(80);
3381 }
3382
3383 tw32_f(MAC_MODE, tp->mac_mode);
3384 udelay(40);
3385
3386 tg3_phy_eee_adjust(tp, current_link_up);
3387
3388 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3389 /* Polled via timer. */
3390 tw32_f(MAC_EVENT, 0);
3391 } else {
3392 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3393 }
3394 udelay(40);
3395
3396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3397 current_link_up == 1 &&
3398 tp->link_config.active_speed == SPEED_1000 &&
3399 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3400 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3401 udelay(120);
3402 tw32_f(MAC_STATUS,
3403 (MAC_STATUS_SYNC_CHANGED |
3404 MAC_STATUS_CFG_CHANGED));
3405 udelay(40);
3406 tg3_write_mem(tp,
3407 NIC_SRAM_FIRMWARE_MBOX,
3408 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3409 }
3410
3411 /* Prevent send BD corruption. */
3412 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3413 u16 oldlnkctl, newlnkctl;
3414
3415 pci_read_config_word(tp->pdev,
3416 tp->pcie_cap + PCI_EXP_LNKCTL,
3417 &oldlnkctl);
3418 if (tp->link_config.active_speed == SPEED_100 ||
3419 tp->link_config.active_speed == SPEED_10)
3420 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3421 else
3422 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3423 if (newlnkctl != oldlnkctl)
3424 pci_write_config_word(tp->pdev,
3425 tp->pcie_cap + PCI_EXP_LNKCTL,
3426 newlnkctl);
3427 }
3428
3429 if (current_link_up != netif_carrier_ok(tp->dev)) {
3430 if (current_link_up)
3431 netif_carrier_on(tp->dev);
3432 else
3433 netif_carrier_off(tp->dev);
3434 tg3_link_report(tp);
3435 }
3436
3437 return 0;
3438 }
3439
3440 struct tg3_fiber_aneginfo {
3441 int state;
3442 #define ANEG_STATE_UNKNOWN 0
3443 #define ANEG_STATE_AN_ENABLE 1
3444 #define ANEG_STATE_RESTART_INIT 2
3445 #define ANEG_STATE_RESTART 3
3446 #define ANEG_STATE_DISABLE_LINK_OK 4
3447 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3448 #define ANEG_STATE_ABILITY_DETECT 6
3449 #define ANEG_STATE_ACK_DETECT_INIT 7
3450 #define ANEG_STATE_ACK_DETECT 8
3451 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3452 #define ANEG_STATE_COMPLETE_ACK 10
3453 #define ANEG_STATE_IDLE_DETECT_INIT 11
3454 #define ANEG_STATE_IDLE_DETECT 12
3455 #define ANEG_STATE_LINK_OK 13
3456 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3457 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3458
3459 u32 flags;
3460 #define MR_AN_ENABLE 0x00000001
3461 #define MR_RESTART_AN 0x00000002
3462 #define MR_AN_COMPLETE 0x00000004
3463 #define MR_PAGE_RX 0x00000008
3464 #define MR_NP_LOADED 0x00000010
3465 #define MR_TOGGLE_TX 0x00000020
3466 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3467 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3468 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3469 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3470 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3471 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3472 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3473 #define MR_TOGGLE_RX 0x00002000
3474 #define MR_NP_RX 0x00004000
3475
3476 #define MR_LINK_OK 0x80000000
3477
3478 unsigned long link_time, cur_time;
3479
3480 u32 ability_match_cfg;
3481 int ability_match_count;
3482
3483 char ability_match, idle_match, ack_match;
3484
3485 u32 txconfig, rxconfig;
3486 #define ANEG_CFG_NP 0x00000080
3487 #define ANEG_CFG_ACK 0x00000040
3488 #define ANEG_CFG_RF2 0x00000020
3489 #define ANEG_CFG_RF1 0x00000010
3490 #define ANEG_CFG_PS2 0x00000001
3491 #define ANEG_CFG_PS1 0x00008000
3492 #define ANEG_CFG_HD 0x00004000
3493 #define ANEG_CFG_FD 0x00002000
3494 #define ANEG_CFG_INVAL 0x00001f06
3495
3496 };
3497 #define ANEG_OK 0
3498 #define ANEG_DONE 1
3499 #define ANEG_TIMER_ENAB 2
3500 #define ANEG_FAILED -1
3501
3502 #define ANEG_STATE_SETTLE_TIME 10000
3503
3504 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3505 struct tg3_fiber_aneginfo *ap)
3506 {
3507 u16 flowctrl;
3508 unsigned long delta;
3509 u32 rx_cfg_reg;
3510 int ret;
3511
3512 if (ap->state == ANEG_STATE_UNKNOWN) {
3513 ap->rxconfig = 0;
3514 ap->link_time = 0;
3515 ap->cur_time = 0;
3516 ap->ability_match_cfg = 0;
3517 ap->ability_match_count = 0;
3518 ap->ability_match = 0;
3519 ap->idle_match = 0;
3520 ap->ack_match = 0;
3521 }
3522 ap->cur_time++;
3523
3524 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3525 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3526
3527 if (rx_cfg_reg != ap->ability_match_cfg) {
3528 ap->ability_match_cfg = rx_cfg_reg;
3529 ap->ability_match = 0;
3530 ap->ability_match_count = 0;
3531 } else {
3532 if (++ap->ability_match_count > 1) {
3533 ap->ability_match = 1;
3534 ap->ability_match_cfg = rx_cfg_reg;
3535 }
3536 }
3537 if (rx_cfg_reg & ANEG_CFG_ACK)
3538 ap->ack_match = 1;
3539 else
3540 ap->ack_match = 0;
3541
3542 ap->idle_match = 0;
3543 } else {
3544 ap->idle_match = 1;
3545 ap->ability_match_cfg = 0;
3546 ap->ability_match_count = 0;
3547 ap->ability_match = 0;
3548 ap->ack_match = 0;
3549
3550 rx_cfg_reg = 0;
3551 }
3552
3553 ap->rxconfig = rx_cfg_reg;
3554 ret = ANEG_OK;
3555
3556 switch (ap->state) {
3557 case ANEG_STATE_UNKNOWN:
3558 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3559 ap->state = ANEG_STATE_AN_ENABLE;
3560
3561 /* fallthru */
3562 case ANEG_STATE_AN_ENABLE:
3563 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3564 if (ap->flags & MR_AN_ENABLE) {
3565 ap->link_time = 0;
3566 ap->cur_time = 0;
3567 ap->ability_match_cfg = 0;
3568 ap->ability_match_count = 0;
3569 ap->ability_match = 0;
3570 ap->idle_match = 0;
3571 ap->ack_match = 0;
3572
3573 ap->state = ANEG_STATE_RESTART_INIT;
3574 } else {
3575 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3576 }
3577 break;
3578
3579 case ANEG_STATE_RESTART_INIT:
3580 ap->link_time = ap->cur_time;
3581 ap->flags &= ~(MR_NP_LOADED);
3582 ap->txconfig = 0;
3583 tw32(MAC_TX_AUTO_NEG, 0);
3584 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3586 udelay(40);
3587
3588 ret = ANEG_TIMER_ENAB;
3589 ap->state = ANEG_STATE_RESTART;
3590
3591 /* fallthru */
3592 case ANEG_STATE_RESTART:
3593 delta = ap->cur_time - ap->link_time;
3594 if (delta > ANEG_STATE_SETTLE_TIME)
3595 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3596 else
3597 ret = ANEG_TIMER_ENAB;
3598 break;
3599
3600 case ANEG_STATE_DISABLE_LINK_OK:
3601 ret = ANEG_DONE;
3602 break;
3603
3604 case ANEG_STATE_ABILITY_DETECT_INIT:
3605 ap->flags &= ~(MR_TOGGLE_TX);
3606 ap->txconfig = ANEG_CFG_FD;
3607 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3608 if (flowctrl & ADVERTISE_1000XPAUSE)
3609 ap->txconfig |= ANEG_CFG_PS1;
3610 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3611 ap->txconfig |= ANEG_CFG_PS2;
3612 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3613 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3614 tw32_f(MAC_MODE, tp->mac_mode);
3615 udelay(40);
3616
3617 ap->state = ANEG_STATE_ABILITY_DETECT;
3618 break;
3619
3620 case ANEG_STATE_ABILITY_DETECT:
3621 if (ap->ability_match != 0 && ap->rxconfig != 0)
3622 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3623 break;
3624
3625 case ANEG_STATE_ACK_DETECT_INIT:
3626 ap->txconfig |= ANEG_CFG_ACK;
3627 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3628 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3629 tw32_f(MAC_MODE, tp->mac_mode);
3630 udelay(40);
3631
3632 ap->state = ANEG_STATE_ACK_DETECT;
3633
3634 /* fallthru */
3635 case ANEG_STATE_ACK_DETECT:
3636 if (ap->ack_match != 0) {
3637 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3638 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3639 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3640 } else {
3641 ap->state = ANEG_STATE_AN_ENABLE;
3642 }
3643 } else if (ap->ability_match != 0 &&
3644 ap->rxconfig == 0) {
3645 ap->state = ANEG_STATE_AN_ENABLE;
3646 }
3647 break;
3648
3649 case ANEG_STATE_COMPLETE_ACK_INIT:
3650 if (ap->rxconfig & ANEG_CFG_INVAL) {
3651 ret = ANEG_FAILED;
3652 break;
3653 }
3654 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3655 MR_LP_ADV_HALF_DUPLEX |
3656 MR_LP_ADV_SYM_PAUSE |
3657 MR_LP_ADV_ASYM_PAUSE |
3658 MR_LP_ADV_REMOTE_FAULT1 |
3659 MR_LP_ADV_REMOTE_FAULT2 |
3660 MR_LP_ADV_NEXT_PAGE |
3661 MR_TOGGLE_RX |
3662 MR_NP_RX);
3663 if (ap->rxconfig & ANEG_CFG_FD)
3664 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3665 if (ap->rxconfig & ANEG_CFG_HD)
3666 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3667 if (ap->rxconfig & ANEG_CFG_PS1)
3668 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3669 if (ap->rxconfig & ANEG_CFG_PS2)
3670 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3671 if (ap->rxconfig & ANEG_CFG_RF1)
3672 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3673 if (ap->rxconfig & ANEG_CFG_RF2)
3674 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3675 if (ap->rxconfig & ANEG_CFG_NP)
3676 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3677
3678 ap->link_time = ap->cur_time;
3679
3680 ap->flags ^= (MR_TOGGLE_TX);
3681 if (ap->rxconfig & 0x0008)
3682 ap->flags |= MR_TOGGLE_RX;
3683 if (ap->rxconfig & ANEG_CFG_NP)
3684 ap->flags |= MR_NP_RX;
3685 ap->flags |= MR_PAGE_RX;
3686
3687 ap->state = ANEG_STATE_COMPLETE_ACK;
3688 ret = ANEG_TIMER_ENAB;
3689 break;
3690
3691 case ANEG_STATE_COMPLETE_ACK:
3692 if (ap->ability_match != 0 &&
3693 ap->rxconfig == 0) {
3694 ap->state = ANEG_STATE_AN_ENABLE;
3695 break;
3696 }
3697 delta = ap->cur_time - ap->link_time;
3698 if (delta > ANEG_STATE_SETTLE_TIME) {
3699 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3700 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3701 } else {
3702 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3703 !(ap->flags & MR_NP_RX)) {
3704 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3705 } else {
3706 ret = ANEG_FAILED;
3707 }
3708 }
3709 }
3710 break;
3711
3712 case ANEG_STATE_IDLE_DETECT_INIT:
3713 ap->link_time = ap->cur_time;
3714 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3715 tw32_f(MAC_MODE, tp->mac_mode);
3716 udelay(40);
3717
3718 ap->state = ANEG_STATE_IDLE_DETECT;
3719 ret = ANEG_TIMER_ENAB;
3720 break;
3721
3722 case ANEG_STATE_IDLE_DETECT:
3723 if (ap->ability_match != 0 &&
3724 ap->rxconfig == 0) {
3725 ap->state = ANEG_STATE_AN_ENABLE;
3726 break;
3727 }
3728 delta = ap->cur_time - ap->link_time;
3729 if (delta > ANEG_STATE_SETTLE_TIME) {
3730 /* XXX another gem from the Broadcom driver :( */
3731 ap->state = ANEG_STATE_LINK_OK;
3732 }
3733 break;
3734
3735 case ANEG_STATE_LINK_OK:
3736 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3737 ret = ANEG_DONE;
3738 break;
3739
3740 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3741 /* ??? unimplemented */
3742 break;
3743
3744 case ANEG_STATE_NEXT_PAGE_WAIT:
3745 /* ??? unimplemented */
3746 break;
3747
3748 default:
3749 ret = ANEG_FAILED;
3750 break;
3751 }
3752
3753 return ret;
3754 }
3755
3756 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3757 {
3758 int res = 0;
3759 struct tg3_fiber_aneginfo aninfo;
3760 int status = ANEG_FAILED;
3761 unsigned int tick;
3762 u32 tmp;
3763
3764 tw32_f(MAC_TX_AUTO_NEG, 0);
3765
3766 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3767 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3768 udelay(40);
3769
3770 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3771 udelay(40);
3772
3773 memset(&aninfo, 0, sizeof(aninfo));
3774 aninfo.flags |= MR_AN_ENABLE;
3775 aninfo.state = ANEG_STATE_UNKNOWN;
3776 aninfo.cur_time = 0;
3777 tick = 0;
3778 while (++tick < 195000) {
3779 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3780 if (status == ANEG_DONE || status == ANEG_FAILED)
3781 break;
3782
3783 udelay(1);
3784 }
3785
3786 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3787 tw32_f(MAC_MODE, tp->mac_mode);
3788 udelay(40);
3789
3790 *txflags = aninfo.txconfig;
3791 *rxflags = aninfo.flags;
3792
3793 if (status == ANEG_DONE &&
3794 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3795 MR_LP_ADV_FULL_DUPLEX)))
3796 res = 1;
3797
3798 return res;
3799 }
3800
3801 static void tg3_init_bcm8002(struct tg3 *tp)
3802 {
3803 u32 mac_status = tr32(MAC_STATUS);
3804 int i;
3805
3806 /* Reset when initting first time or we have a link. */
3807 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3808 !(mac_status & MAC_STATUS_PCS_SYNCED))
3809 return;
3810
3811 /* Set PLL lock range. */
3812 tg3_writephy(tp, 0x16, 0x8007);
3813
3814 /* SW reset */
3815 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3816
3817 /* Wait for reset to complete. */
3818 /* XXX schedule_timeout() ... */
3819 for (i = 0; i < 500; i++)
3820 udelay(10);
3821
3822 /* Config mode; select PMA/Ch 1 regs. */
3823 tg3_writephy(tp, 0x10, 0x8411);
3824
3825 /* Enable auto-lock and comdet, select txclk for tx. */
3826 tg3_writephy(tp, 0x11, 0x0a10);
3827
3828 tg3_writephy(tp, 0x18, 0x00a0);
3829 tg3_writephy(tp, 0x16, 0x41ff);
3830
3831 /* Assert and deassert POR. */
3832 tg3_writephy(tp, 0x13, 0x0400);
3833 udelay(40);
3834 tg3_writephy(tp, 0x13, 0x0000);
3835
3836 tg3_writephy(tp, 0x11, 0x0a50);
3837 udelay(40);
3838 tg3_writephy(tp, 0x11, 0x0a10);
3839
3840 /* Wait for signal to stabilize */
3841 /* XXX schedule_timeout() ... */
3842 for (i = 0; i < 15000; i++)
3843 udelay(10);
3844
3845 /* Deselect the channel register so we can read the PHYID
3846 * later.
3847 */
3848 tg3_writephy(tp, 0x10, 0x8011);
3849 }
3850
3851 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3852 {
3853 u16 flowctrl;
3854 u32 sg_dig_ctrl, sg_dig_status;
3855 u32 serdes_cfg, expected_sg_dig_ctrl;
3856 int workaround, port_a;
3857 int current_link_up;
3858
3859 serdes_cfg = 0;
3860 expected_sg_dig_ctrl = 0;
3861 workaround = 0;
3862 port_a = 1;
3863 current_link_up = 0;
3864
3865 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3866 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3867 workaround = 1;
3868 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3869 port_a = 0;
3870
3871 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3872 /* preserve bits 20-23 for voltage regulator */
3873 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3874 }
3875
3876 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3877
3878 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3879 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3880 if (workaround) {
3881 u32 val = serdes_cfg;
3882
3883 if (port_a)
3884 val |= 0xc010000;
3885 else
3886 val |= 0x4010000;
3887 tw32_f(MAC_SERDES_CFG, val);
3888 }
3889
3890 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3891 }
3892 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3893 tg3_setup_flow_control(tp, 0, 0);
3894 current_link_up = 1;
3895 }
3896 goto out;
3897 }
3898
3899 /* Want auto-negotiation. */
3900 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3901
3902 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3903 if (flowctrl & ADVERTISE_1000XPAUSE)
3904 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3905 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3906 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3907
3908 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3909 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3910 tp->serdes_counter &&
3911 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3912 MAC_STATUS_RCVD_CFG)) ==
3913 MAC_STATUS_PCS_SYNCED)) {
3914 tp->serdes_counter--;
3915 current_link_up = 1;
3916 goto out;
3917 }
3918 restart_autoneg:
3919 if (workaround)
3920 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3921 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3922 udelay(5);
3923 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3924
3925 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3926 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3927 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3928 MAC_STATUS_SIGNAL_DET)) {
3929 sg_dig_status = tr32(SG_DIG_STATUS);
3930 mac_status = tr32(MAC_STATUS);
3931
3932 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3933 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3934 u32 local_adv = 0, remote_adv = 0;
3935
3936 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3937 local_adv |= ADVERTISE_1000XPAUSE;
3938 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3939 local_adv |= ADVERTISE_1000XPSE_ASYM;
3940
3941 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3942 remote_adv |= LPA_1000XPAUSE;
3943 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3944 remote_adv |= LPA_1000XPAUSE_ASYM;
3945
3946 tg3_setup_flow_control(tp, local_adv, remote_adv);
3947 current_link_up = 1;
3948 tp->serdes_counter = 0;
3949 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3950 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3951 if (tp->serdes_counter)
3952 tp->serdes_counter--;
3953 else {
3954 if (workaround) {
3955 u32 val = serdes_cfg;
3956
3957 if (port_a)
3958 val |= 0xc010000;
3959 else
3960 val |= 0x4010000;
3961
3962 tw32_f(MAC_SERDES_CFG, val);
3963 }
3964
3965 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3966 udelay(40);
3967
3968 /* Link parallel detection - link is up */
3969 /* only if we have PCS_SYNC and not */
3970 /* receiving config code words */
3971 mac_status = tr32(MAC_STATUS);
3972 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3973 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3974 tg3_setup_flow_control(tp, 0, 0);
3975 current_link_up = 1;
3976 tp->phy_flags |=
3977 TG3_PHYFLG_PARALLEL_DETECT;
3978 tp->serdes_counter =
3979 SERDES_PARALLEL_DET_TIMEOUT;
3980 } else
3981 goto restart_autoneg;
3982 }
3983 }
3984 } else {
3985 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3986 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3987 }
3988
3989 out:
3990 return current_link_up;
3991 }
3992
3993 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3994 {
3995 int current_link_up = 0;
3996
3997 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3998 goto out;
3999
4000 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4001 u32 txflags, rxflags;
4002 int i;
4003
4004 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4005 u32 local_adv = 0, remote_adv = 0;
4006
4007 if (txflags & ANEG_CFG_PS1)
4008 local_adv |= ADVERTISE_1000XPAUSE;
4009 if (txflags & ANEG_CFG_PS2)
4010 local_adv |= ADVERTISE_1000XPSE_ASYM;
4011
4012 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4013 remote_adv |= LPA_1000XPAUSE;
4014 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4015 remote_adv |= LPA_1000XPAUSE_ASYM;
4016
4017 tg3_setup_flow_control(tp, local_adv, remote_adv);
4018
4019 current_link_up = 1;
4020 }
4021 for (i = 0; i < 30; i++) {
4022 udelay(20);
4023 tw32_f(MAC_STATUS,
4024 (MAC_STATUS_SYNC_CHANGED |
4025 MAC_STATUS_CFG_CHANGED));
4026 udelay(40);
4027 if ((tr32(MAC_STATUS) &
4028 (MAC_STATUS_SYNC_CHANGED |
4029 MAC_STATUS_CFG_CHANGED)) == 0)
4030 break;
4031 }
4032
4033 mac_status = tr32(MAC_STATUS);
4034 if (current_link_up == 0 &&
4035 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4036 !(mac_status & MAC_STATUS_RCVD_CFG))
4037 current_link_up = 1;
4038 } else {
4039 tg3_setup_flow_control(tp, 0, 0);
4040
4041 /* Forcing 1000FD link up. */
4042 current_link_up = 1;
4043
4044 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4045 udelay(40);
4046
4047 tw32_f(MAC_MODE, tp->mac_mode);
4048 udelay(40);
4049 }
4050
4051 out:
4052 return current_link_up;
4053 }
4054
4055 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4056 {
4057 u32 orig_pause_cfg;
4058 u16 orig_active_speed;
4059 u8 orig_active_duplex;
4060 u32 mac_status;
4061 int current_link_up;
4062 int i;
4063
4064 orig_pause_cfg = tp->link_config.active_flowctrl;
4065 orig_active_speed = tp->link_config.active_speed;
4066 orig_active_duplex = tp->link_config.active_duplex;
4067
4068 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4069 netif_carrier_ok(tp->dev) &&
4070 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4071 mac_status = tr32(MAC_STATUS);
4072 mac_status &= (MAC_STATUS_PCS_SYNCED |
4073 MAC_STATUS_SIGNAL_DET |
4074 MAC_STATUS_CFG_CHANGED |
4075 MAC_STATUS_RCVD_CFG);
4076 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4077 MAC_STATUS_SIGNAL_DET)) {
4078 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4079 MAC_STATUS_CFG_CHANGED));
4080 return 0;
4081 }
4082 }
4083
4084 tw32_f(MAC_TX_AUTO_NEG, 0);
4085
4086 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4087 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4088 tw32_f(MAC_MODE, tp->mac_mode);
4089 udelay(40);
4090
4091 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4092 tg3_init_bcm8002(tp);
4093
4094 /* Enable link change event even when serdes polling. */
4095 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4096 udelay(40);
4097
4098 current_link_up = 0;
4099 mac_status = tr32(MAC_STATUS);
4100
4101 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4102 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4103 else
4104 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4105
4106 tp->napi[0].hw_status->status =
4107 (SD_STATUS_UPDATED |
4108 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4109
4110 for (i = 0; i < 100; i++) {
4111 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4112 MAC_STATUS_CFG_CHANGED));
4113 udelay(5);
4114 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4115 MAC_STATUS_CFG_CHANGED |
4116 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4117 break;
4118 }
4119
4120 mac_status = tr32(MAC_STATUS);
4121 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4122 current_link_up = 0;
4123 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4124 tp->serdes_counter == 0) {
4125 tw32_f(MAC_MODE, (tp->mac_mode |
4126 MAC_MODE_SEND_CONFIGS));
4127 udelay(1);
4128 tw32_f(MAC_MODE, tp->mac_mode);
4129 }
4130 }
4131
4132 if (current_link_up == 1) {
4133 tp->link_config.active_speed = SPEED_1000;
4134 tp->link_config.active_duplex = DUPLEX_FULL;
4135 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4136 LED_CTRL_LNKLED_OVERRIDE |
4137 LED_CTRL_1000MBPS_ON));
4138 } else {
4139 tp->link_config.active_speed = SPEED_INVALID;
4140 tp->link_config.active_duplex = DUPLEX_INVALID;
4141 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4142 LED_CTRL_LNKLED_OVERRIDE |
4143 LED_CTRL_TRAFFIC_OVERRIDE));
4144 }
4145
4146 if (current_link_up != netif_carrier_ok(tp->dev)) {
4147 if (current_link_up)
4148 netif_carrier_on(tp->dev);
4149 else
4150 netif_carrier_off(tp->dev);
4151 tg3_link_report(tp);
4152 } else {
4153 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4154 if (orig_pause_cfg != now_pause_cfg ||
4155 orig_active_speed != tp->link_config.active_speed ||
4156 orig_active_duplex != tp->link_config.active_duplex)
4157 tg3_link_report(tp);
4158 }
4159
4160 return 0;
4161 }
4162
4163 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4164 {
4165 int current_link_up, err = 0;
4166 u32 bmsr, bmcr;
4167 u16 current_speed;
4168 u8 current_duplex;
4169 u32 local_adv, remote_adv;
4170
4171 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4172 tw32_f(MAC_MODE, tp->mac_mode);
4173 udelay(40);
4174
4175 tw32(MAC_EVENT, 0);
4176
4177 tw32_f(MAC_STATUS,
4178 (MAC_STATUS_SYNC_CHANGED |
4179 MAC_STATUS_CFG_CHANGED |
4180 MAC_STATUS_MI_COMPLETION |
4181 MAC_STATUS_LNKSTATE_CHANGED));
4182 udelay(40);
4183
4184 if (force_reset)
4185 tg3_phy_reset(tp);
4186
4187 current_link_up = 0;
4188 current_speed = SPEED_INVALID;
4189 current_duplex = DUPLEX_INVALID;
4190
4191 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4192 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4194 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4195 bmsr |= BMSR_LSTATUS;
4196 else
4197 bmsr &= ~BMSR_LSTATUS;
4198 }
4199
4200 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4201
4202 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4203 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4204 /* do nothing, just check for link up at the end */
4205 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4206 u32 adv, new_adv;
4207
4208 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4209 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4210 ADVERTISE_1000XPAUSE |
4211 ADVERTISE_1000XPSE_ASYM |
4212 ADVERTISE_SLCT);
4213
4214 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4215
4216 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4217 new_adv |= ADVERTISE_1000XHALF;
4218 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4219 new_adv |= ADVERTISE_1000XFULL;
4220
4221 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4222 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4223 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4224 tg3_writephy(tp, MII_BMCR, bmcr);
4225
4226 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4227 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4228 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4229
4230 return err;
4231 }
4232 } else {
4233 u32 new_bmcr;
4234
4235 bmcr &= ~BMCR_SPEED1000;
4236 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4237
4238 if (tp->link_config.duplex == DUPLEX_FULL)
4239 new_bmcr |= BMCR_FULLDPLX;
4240
4241 if (new_bmcr != bmcr) {
4242 /* BMCR_SPEED1000 is a reserved bit that needs
4243 * to be set on write.
4244 */
4245 new_bmcr |= BMCR_SPEED1000;
4246
4247 /* Force a linkdown */
4248 if (netif_carrier_ok(tp->dev)) {
4249 u32 adv;
4250
4251 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4252 adv &= ~(ADVERTISE_1000XFULL |
4253 ADVERTISE_1000XHALF |
4254 ADVERTISE_SLCT);
4255 tg3_writephy(tp, MII_ADVERTISE, adv);
4256 tg3_writephy(tp, MII_BMCR, bmcr |
4257 BMCR_ANRESTART |
4258 BMCR_ANENABLE);
4259 udelay(10);
4260 netif_carrier_off(tp->dev);
4261 }
4262 tg3_writephy(tp, MII_BMCR, new_bmcr);
4263 bmcr = new_bmcr;
4264 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4265 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4266 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4267 ASIC_REV_5714) {
4268 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4269 bmsr |= BMSR_LSTATUS;
4270 else
4271 bmsr &= ~BMSR_LSTATUS;
4272 }
4273 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4274 }
4275 }
4276
4277 if (bmsr & BMSR_LSTATUS) {
4278 current_speed = SPEED_1000;
4279 current_link_up = 1;
4280 if (bmcr & BMCR_FULLDPLX)
4281 current_duplex = DUPLEX_FULL;
4282 else
4283 current_duplex = DUPLEX_HALF;
4284
4285 local_adv = 0;
4286 remote_adv = 0;
4287
4288 if (bmcr & BMCR_ANENABLE) {
4289 u32 common;
4290
4291 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4292 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4293 common = local_adv & remote_adv;
4294 if (common & (ADVERTISE_1000XHALF |
4295 ADVERTISE_1000XFULL)) {
4296 if (common & ADVERTISE_1000XFULL)
4297 current_duplex = DUPLEX_FULL;
4298 else
4299 current_duplex = DUPLEX_HALF;
4300 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4301 /* Link is up via parallel detect */
4302 } else {
4303 current_link_up = 0;
4304 }
4305 }
4306 }
4307
4308 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4309 tg3_setup_flow_control(tp, local_adv, remote_adv);
4310
4311 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4312 if (tp->link_config.active_duplex == DUPLEX_HALF)
4313 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4314
4315 tw32_f(MAC_MODE, tp->mac_mode);
4316 udelay(40);
4317
4318 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4319
4320 tp->link_config.active_speed = current_speed;
4321 tp->link_config.active_duplex = current_duplex;
4322
4323 if (current_link_up != netif_carrier_ok(tp->dev)) {
4324 if (current_link_up)
4325 netif_carrier_on(tp->dev);
4326 else {
4327 netif_carrier_off(tp->dev);
4328 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4329 }
4330 tg3_link_report(tp);
4331 }
4332 return err;
4333 }
4334
4335 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4336 {
4337 if (tp->serdes_counter) {
4338 /* Give autoneg time to complete. */
4339 tp->serdes_counter--;
4340 return;
4341 }
4342
4343 if (!netif_carrier_ok(tp->dev) &&
4344 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4345 u32 bmcr;
4346
4347 tg3_readphy(tp, MII_BMCR, &bmcr);
4348 if (bmcr & BMCR_ANENABLE) {
4349 u32 phy1, phy2;
4350
4351 /* Select shadow register 0x1f */
4352 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4353 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4354
4355 /* Select expansion interrupt status register */
4356 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4357 MII_TG3_DSP_EXP1_INT_STAT);
4358 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4359 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4360
4361 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4362 /* We have signal detect and not receiving
4363 * config code words, link is up by parallel
4364 * detection.
4365 */
4366
4367 bmcr &= ~BMCR_ANENABLE;
4368 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4369 tg3_writephy(tp, MII_BMCR, bmcr);
4370 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4371 }
4372 }
4373 } else if (netif_carrier_ok(tp->dev) &&
4374 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4375 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4376 u32 phy2;
4377
4378 /* Select expansion interrupt status register */
4379 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4380 MII_TG3_DSP_EXP1_INT_STAT);
4381 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4382 if (phy2 & 0x20) {
4383 u32 bmcr;
4384
4385 /* Config code words received, turn on autoneg. */
4386 tg3_readphy(tp, MII_BMCR, &bmcr);
4387 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4388
4389 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4390
4391 }
4392 }
4393 }
4394
4395 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4396 {
4397 int err;
4398
4399 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4400 err = tg3_setup_fiber_phy(tp, force_reset);
4401 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4402 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4403 else
4404 err = tg3_setup_copper_phy(tp, force_reset);
4405
4406 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4407 u32 val, scale;
4408
4409 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4410 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4411 scale = 65;
4412 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4413 scale = 6;
4414 else
4415 scale = 12;
4416
4417 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4418 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4419 tw32(GRC_MISC_CFG, val);
4420 }
4421
4422 if (tp->link_config.active_speed == SPEED_1000 &&
4423 tp->link_config.active_duplex == DUPLEX_HALF)
4424 tw32(MAC_TX_LENGTHS,
4425 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4426 (6 << TX_LENGTHS_IPG_SHIFT) |
4427 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4428 else
4429 tw32(MAC_TX_LENGTHS,
4430 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4431 (6 << TX_LENGTHS_IPG_SHIFT) |
4432 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4433
4434 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4435 if (netif_carrier_ok(tp->dev)) {
4436 tw32(HOSTCC_STAT_COAL_TICKS,
4437 tp->coal.stats_block_coalesce_usecs);
4438 } else {
4439 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4440 }
4441 }
4442
4443 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4444 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4445 if (!netif_carrier_ok(tp->dev))
4446 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4447 tp->pwrmgmt_thresh;
4448 else
4449 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4450 tw32(PCIE_PWR_MGMT_THRESH, val);
4451 }
4452
4453 return err;
4454 }
4455
4456 static inline int tg3_irq_sync(struct tg3 *tp)
4457 {
4458 return tp->irq_sync;
4459 }
4460
4461 /* This is called whenever we suspect that the system chipset is re-
4462 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4463 * is bogus tx completions. We try to recover by setting the
4464 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4465 * in the workqueue.
4466 */
4467 static void tg3_tx_recover(struct tg3 *tp)
4468 {
4469 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4470 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4471
4472 netdev_warn(tp->dev,
4473 "The system may be re-ordering memory-mapped I/O "
4474 "cycles to the network device, attempting to recover. "
4475 "Please report the problem to the driver maintainer "
4476 "and include system chipset information.\n");
4477
4478 spin_lock(&tp->lock);
4479 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4480 spin_unlock(&tp->lock);
4481 }
4482
4483 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4484 {
4485 /* Tell compiler to fetch tx indices from memory. */
4486 barrier();
4487 return tnapi->tx_pending -
4488 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4489 }
4490
4491 /* Tigon3 never reports partial packet sends. So we do not
4492 * need special logic to handle SKBs that have not had all
4493 * of their frags sent yet, like SunGEM does.
4494 */
4495 static void tg3_tx(struct tg3_napi *tnapi)
4496 {
4497 struct tg3 *tp = tnapi->tp;
4498 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4499 u32 sw_idx = tnapi->tx_cons;
4500 struct netdev_queue *txq;
4501 int index = tnapi - tp->napi;
4502
4503 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4504 index--;
4505
4506 txq = netdev_get_tx_queue(tp->dev, index);
4507
4508 while (sw_idx != hw_idx) {
4509 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4510 struct sk_buff *skb = ri->skb;
4511 int i, tx_bug = 0;
4512
4513 if (unlikely(skb == NULL)) {
4514 tg3_tx_recover(tp);
4515 return;
4516 }
4517
4518 pci_unmap_single(tp->pdev,
4519 dma_unmap_addr(ri, mapping),
4520 skb_headlen(skb),
4521 PCI_DMA_TODEVICE);
4522
4523 ri->skb = NULL;
4524
4525 sw_idx = NEXT_TX(sw_idx);
4526
4527 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4528 ri = &tnapi->tx_buffers[sw_idx];
4529 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4530 tx_bug = 1;
4531
4532 pci_unmap_page(tp->pdev,
4533 dma_unmap_addr(ri, mapping),
4534 skb_shinfo(skb)->frags[i].size,
4535 PCI_DMA_TODEVICE);
4536 sw_idx = NEXT_TX(sw_idx);
4537 }
4538
4539 dev_kfree_skb(skb);
4540
4541 if (unlikely(tx_bug)) {
4542 tg3_tx_recover(tp);
4543 return;
4544 }
4545 }
4546
4547 tnapi->tx_cons = sw_idx;
4548
4549 /* Need to make the tx_cons update visible to tg3_start_xmit()
4550 * before checking for netif_queue_stopped(). Without the
4551 * memory barrier, there is a small possibility that tg3_start_xmit()
4552 * will miss it and cause the queue to be stopped forever.
4553 */
4554 smp_mb();
4555
4556 if (unlikely(netif_tx_queue_stopped(txq) &&
4557 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4558 __netif_tx_lock(txq, smp_processor_id());
4559 if (netif_tx_queue_stopped(txq) &&
4560 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4561 netif_tx_wake_queue(txq);
4562 __netif_tx_unlock(txq);
4563 }
4564 }
4565
4566 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4567 {
4568 if (!ri->skb)
4569 return;
4570
4571 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4572 map_sz, PCI_DMA_FROMDEVICE);
4573 dev_kfree_skb_any(ri->skb);
4574 ri->skb = NULL;
4575 }
4576
4577 /* Returns size of skb allocated or < 0 on error.
4578 *
4579 * We only need to fill in the address because the other members
4580 * of the RX descriptor are invariant, see tg3_init_rings.
4581 *
4582 * Note the purposeful assymetry of cpu vs. chip accesses. For
4583 * posting buffers we only dirty the first cache line of the RX
4584 * descriptor (containing the address). Whereas for the RX status
4585 * buffers the cpu only reads the last cacheline of the RX descriptor
4586 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4587 */
4588 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4589 u32 opaque_key, u32 dest_idx_unmasked)
4590 {
4591 struct tg3_rx_buffer_desc *desc;
4592 struct ring_info *map;
4593 struct sk_buff *skb;
4594 dma_addr_t mapping;
4595 int skb_size, dest_idx;
4596
4597 switch (opaque_key) {
4598 case RXD_OPAQUE_RING_STD:
4599 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4600 desc = &tpr->rx_std[dest_idx];
4601 map = &tpr->rx_std_buffers[dest_idx];
4602 skb_size = tp->rx_pkt_map_sz;
4603 break;
4604
4605 case RXD_OPAQUE_RING_JUMBO:
4606 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4607 desc = &tpr->rx_jmb[dest_idx].std;
4608 map = &tpr->rx_jmb_buffers[dest_idx];
4609 skb_size = TG3_RX_JMB_MAP_SZ;
4610 break;
4611
4612 default:
4613 return -EINVAL;
4614 }
4615
4616 /* Do not overwrite any of the map or rp information
4617 * until we are sure we can commit to a new buffer.
4618 *
4619 * Callers depend upon this behavior and assume that
4620 * we leave everything unchanged if we fail.
4621 */
4622 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4623 if (skb == NULL)
4624 return -ENOMEM;
4625
4626 skb_reserve(skb, tp->rx_offset);
4627
4628 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4629 PCI_DMA_FROMDEVICE);
4630 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4631 dev_kfree_skb(skb);
4632 return -EIO;
4633 }
4634
4635 map->skb = skb;
4636 dma_unmap_addr_set(map, mapping, mapping);
4637
4638 desc->addr_hi = ((u64)mapping >> 32);
4639 desc->addr_lo = ((u64)mapping & 0xffffffff);
4640
4641 return skb_size;
4642 }
4643
4644 /* We only need to move over in the address because the other
4645 * members of the RX descriptor are invariant. See notes above
4646 * tg3_alloc_rx_skb for full details.
4647 */
4648 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4649 struct tg3_rx_prodring_set *dpr,
4650 u32 opaque_key, int src_idx,
4651 u32 dest_idx_unmasked)
4652 {
4653 struct tg3 *tp = tnapi->tp;
4654 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4655 struct ring_info *src_map, *dest_map;
4656 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4657 int dest_idx;
4658
4659 switch (opaque_key) {
4660 case RXD_OPAQUE_RING_STD:
4661 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4662 dest_desc = &dpr->rx_std[dest_idx];
4663 dest_map = &dpr->rx_std_buffers[dest_idx];
4664 src_desc = &spr->rx_std[src_idx];
4665 src_map = &spr->rx_std_buffers[src_idx];
4666 break;
4667
4668 case RXD_OPAQUE_RING_JUMBO:
4669 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4670 dest_desc = &dpr->rx_jmb[dest_idx].std;
4671 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4672 src_desc = &spr->rx_jmb[src_idx].std;
4673 src_map = &spr->rx_jmb_buffers[src_idx];
4674 break;
4675
4676 default:
4677 return;
4678 }
4679
4680 dest_map->skb = src_map->skb;
4681 dma_unmap_addr_set(dest_map, mapping,
4682 dma_unmap_addr(src_map, mapping));
4683 dest_desc->addr_hi = src_desc->addr_hi;
4684 dest_desc->addr_lo = src_desc->addr_lo;
4685
4686 /* Ensure that the update to the skb happens after the physical
4687 * addresses have been transferred to the new BD location.
4688 */
4689 smp_wmb();
4690
4691 src_map->skb = NULL;
4692 }
4693
4694 /* The RX ring scheme is composed of multiple rings which post fresh
4695 * buffers to the chip, and one special ring the chip uses to report
4696 * status back to the host.
4697 *
4698 * The special ring reports the status of received packets to the
4699 * host. The chip does not write into the original descriptor the
4700 * RX buffer was obtained from. The chip simply takes the original
4701 * descriptor as provided by the host, updates the status and length
4702 * field, then writes this into the next status ring entry.
4703 *
4704 * Each ring the host uses to post buffers to the chip is described
4705 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4706 * it is first placed into the on-chip ram. When the packet's length
4707 * is known, it walks down the TG3_BDINFO entries to select the ring.
4708 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4709 * which is within the range of the new packet's length is chosen.
4710 *
4711 * The "separate ring for rx status" scheme may sound queer, but it makes
4712 * sense from a cache coherency perspective. If only the host writes
4713 * to the buffer post rings, and only the chip writes to the rx status
4714 * rings, then cache lines never move beyond shared-modified state.
4715 * If both the host and chip were to write into the same ring, cache line
4716 * eviction could occur since both entities want it in an exclusive state.
4717 */
4718 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4719 {
4720 struct tg3 *tp = tnapi->tp;
4721 u32 work_mask, rx_std_posted = 0;
4722 u32 std_prod_idx, jmb_prod_idx;
4723 u32 sw_idx = tnapi->rx_rcb_ptr;
4724 u16 hw_idx;
4725 int received;
4726 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4727
4728 hw_idx = *(tnapi->rx_rcb_prod_idx);
4729 /*
4730 * We need to order the read of hw_idx and the read of
4731 * the opaque cookie.
4732 */
4733 rmb();
4734 work_mask = 0;
4735 received = 0;
4736 std_prod_idx = tpr->rx_std_prod_idx;
4737 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4738 while (sw_idx != hw_idx && budget > 0) {
4739 struct ring_info *ri;
4740 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4741 unsigned int len;
4742 struct sk_buff *skb;
4743 dma_addr_t dma_addr;
4744 u32 opaque_key, desc_idx, *post_ptr;
4745
4746 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4747 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4748 if (opaque_key == RXD_OPAQUE_RING_STD) {
4749 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4750 dma_addr = dma_unmap_addr(ri, mapping);
4751 skb = ri->skb;
4752 post_ptr = &std_prod_idx;
4753 rx_std_posted++;
4754 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4755 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4756 dma_addr = dma_unmap_addr(ri, mapping);
4757 skb = ri->skb;
4758 post_ptr = &jmb_prod_idx;
4759 } else
4760 goto next_pkt_nopost;
4761
4762 work_mask |= opaque_key;
4763
4764 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4765 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4766 drop_it:
4767 tg3_recycle_rx(tnapi, tpr, opaque_key,
4768 desc_idx, *post_ptr);
4769 drop_it_no_recycle:
4770 /* Other statistics kept track of by card. */
4771 tp->rx_dropped++;
4772 goto next_pkt;
4773 }
4774
4775 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4776 ETH_FCS_LEN;
4777
4778 if (len > TG3_RX_COPY_THRESH(tp)) {
4779 int skb_size;
4780
4781 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4782 *post_ptr);
4783 if (skb_size < 0)
4784 goto drop_it;
4785
4786 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4787 PCI_DMA_FROMDEVICE);
4788
4789 /* Ensure that the update to the skb happens
4790 * after the usage of the old DMA mapping.
4791 */
4792 smp_wmb();
4793
4794 ri->skb = NULL;
4795
4796 skb_put(skb, len);
4797 } else {
4798 struct sk_buff *copy_skb;
4799
4800 tg3_recycle_rx(tnapi, tpr, opaque_key,
4801 desc_idx, *post_ptr);
4802
4803 copy_skb = netdev_alloc_skb(tp->dev, len +
4804 TG3_RAW_IP_ALIGN);
4805 if (copy_skb == NULL)
4806 goto drop_it_no_recycle;
4807
4808 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4809 skb_put(copy_skb, len);
4810 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4811 skb_copy_from_linear_data(skb, copy_skb->data, len);
4812 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4813
4814 /* We'll reuse the original ring buffer. */
4815 skb = copy_skb;
4816 }
4817
4818 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4819 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4820 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4821 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4822 skb->ip_summed = CHECKSUM_UNNECESSARY;
4823 else
4824 skb_checksum_none_assert(skb);
4825
4826 skb->protocol = eth_type_trans(skb, tp->dev);
4827
4828 if (len > (tp->dev->mtu + ETH_HLEN) &&
4829 skb->protocol != htons(ETH_P_8021Q)) {
4830 dev_kfree_skb(skb);
4831 goto drop_it_no_recycle;
4832 }
4833
4834 if (desc->type_flags & RXD_FLAG_VLAN &&
4835 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4836 __vlan_hwaccel_put_tag(skb,
4837 desc->err_vlan & RXD_VLAN_MASK);
4838
4839 napi_gro_receive(&tnapi->napi, skb);
4840
4841 received++;
4842 budget--;
4843
4844 next_pkt:
4845 (*post_ptr)++;
4846
4847 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4848 tpr->rx_std_prod_idx = std_prod_idx &
4849 tp->rx_std_ring_mask;
4850 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4851 tpr->rx_std_prod_idx);
4852 work_mask &= ~RXD_OPAQUE_RING_STD;
4853 rx_std_posted = 0;
4854 }
4855 next_pkt_nopost:
4856 sw_idx++;
4857 sw_idx &= tp->rx_ret_ring_mask;
4858
4859 /* Refresh hw_idx to see if there is new work */
4860 if (sw_idx == hw_idx) {
4861 hw_idx = *(tnapi->rx_rcb_prod_idx);
4862 rmb();
4863 }
4864 }
4865
4866 /* ACK the status ring. */
4867 tnapi->rx_rcb_ptr = sw_idx;
4868 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4869
4870 /* Refill RX ring(s). */
4871 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4872 if (work_mask & RXD_OPAQUE_RING_STD) {
4873 tpr->rx_std_prod_idx = std_prod_idx &
4874 tp->rx_std_ring_mask;
4875 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4876 tpr->rx_std_prod_idx);
4877 }
4878 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4879 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4880 tp->rx_jmb_ring_mask;
4881 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4882 tpr->rx_jmb_prod_idx);
4883 }
4884 mmiowb();
4885 } else if (work_mask) {
4886 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4887 * updated before the producer indices can be updated.
4888 */
4889 smp_wmb();
4890
4891 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4892 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4893
4894 if (tnapi != &tp->napi[1])
4895 napi_schedule(&tp->napi[1].napi);
4896 }
4897
4898 return received;
4899 }
4900
4901 static void tg3_poll_link(struct tg3 *tp)
4902 {
4903 /* handle link change and other phy events */
4904 if (!(tp->tg3_flags &
4905 (TG3_FLAG_USE_LINKCHG_REG |
4906 TG3_FLAG_POLL_SERDES))) {
4907 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4908
4909 if (sblk->status & SD_STATUS_LINK_CHG) {
4910 sblk->status = SD_STATUS_UPDATED |
4911 (sblk->status & ~SD_STATUS_LINK_CHG);
4912 spin_lock(&tp->lock);
4913 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4914 tw32_f(MAC_STATUS,
4915 (MAC_STATUS_SYNC_CHANGED |
4916 MAC_STATUS_CFG_CHANGED |
4917 MAC_STATUS_MI_COMPLETION |
4918 MAC_STATUS_LNKSTATE_CHANGED));
4919 udelay(40);
4920 } else
4921 tg3_setup_phy(tp, 0);
4922 spin_unlock(&tp->lock);
4923 }
4924 }
4925 }
4926
4927 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4928 struct tg3_rx_prodring_set *dpr,
4929 struct tg3_rx_prodring_set *spr)
4930 {
4931 u32 si, di, cpycnt, src_prod_idx;
4932 int i, err = 0;
4933
4934 while (1) {
4935 src_prod_idx = spr->rx_std_prod_idx;
4936
4937 /* Make sure updates to the rx_std_buffers[] entries and the
4938 * standard producer index are seen in the correct order.
4939 */
4940 smp_rmb();
4941
4942 if (spr->rx_std_cons_idx == src_prod_idx)
4943 break;
4944
4945 if (spr->rx_std_cons_idx < src_prod_idx)
4946 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4947 else
4948 cpycnt = tp->rx_std_ring_mask + 1 -
4949 spr->rx_std_cons_idx;
4950
4951 cpycnt = min(cpycnt,
4952 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4953
4954 si = spr->rx_std_cons_idx;
4955 di = dpr->rx_std_prod_idx;
4956
4957 for (i = di; i < di + cpycnt; i++) {
4958 if (dpr->rx_std_buffers[i].skb) {
4959 cpycnt = i - di;
4960 err = -ENOSPC;
4961 break;
4962 }
4963 }
4964
4965 if (!cpycnt)
4966 break;
4967
4968 /* Ensure that updates to the rx_std_buffers ring and the
4969 * shadowed hardware producer ring from tg3_recycle_skb() are
4970 * ordered correctly WRT the skb check above.
4971 */
4972 smp_rmb();
4973
4974 memcpy(&dpr->rx_std_buffers[di],
4975 &spr->rx_std_buffers[si],
4976 cpycnt * sizeof(struct ring_info));
4977
4978 for (i = 0; i < cpycnt; i++, di++, si++) {
4979 struct tg3_rx_buffer_desc *sbd, *dbd;
4980 sbd = &spr->rx_std[si];
4981 dbd = &dpr->rx_std[di];
4982 dbd->addr_hi = sbd->addr_hi;
4983 dbd->addr_lo = sbd->addr_lo;
4984 }
4985
4986 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4987 tp->rx_std_ring_mask;
4988 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4989 tp->rx_std_ring_mask;
4990 }
4991
4992 while (1) {
4993 src_prod_idx = spr->rx_jmb_prod_idx;
4994
4995 /* Make sure updates to the rx_jmb_buffers[] entries and
4996 * the jumbo producer index are seen in the correct order.
4997 */
4998 smp_rmb();
4999
5000 if (spr->rx_jmb_cons_idx == src_prod_idx)
5001 break;
5002
5003 if (spr->rx_jmb_cons_idx < src_prod_idx)
5004 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5005 else
5006 cpycnt = tp->rx_jmb_ring_mask + 1 -
5007 spr->rx_jmb_cons_idx;
5008
5009 cpycnt = min(cpycnt,
5010 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5011
5012 si = spr->rx_jmb_cons_idx;
5013 di = dpr->rx_jmb_prod_idx;
5014
5015 for (i = di; i < di + cpycnt; i++) {
5016 if (dpr->rx_jmb_buffers[i].skb) {
5017 cpycnt = i - di;
5018 err = -ENOSPC;
5019 break;
5020 }
5021 }
5022
5023 if (!cpycnt)
5024 break;
5025
5026 /* Ensure that updates to the rx_jmb_buffers ring and the
5027 * shadowed hardware producer ring from tg3_recycle_skb() are
5028 * ordered correctly WRT the skb check above.
5029 */
5030 smp_rmb();
5031
5032 memcpy(&dpr->rx_jmb_buffers[di],
5033 &spr->rx_jmb_buffers[si],
5034 cpycnt * sizeof(struct ring_info));
5035
5036 for (i = 0; i < cpycnt; i++, di++, si++) {
5037 struct tg3_rx_buffer_desc *sbd, *dbd;
5038 sbd = &spr->rx_jmb[si].std;
5039 dbd = &dpr->rx_jmb[di].std;
5040 dbd->addr_hi = sbd->addr_hi;
5041 dbd->addr_lo = sbd->addr_lo;
5042 }
5043
5044 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5045 tp->rx_jmb_ring_mask;
5046 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5047 tp->rx_jmb_ring_mask;
5048 }
5049
5050 return err;
5051 }
5052
5053 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5054 {
5055 struct tg3 *tp = tnapi->tp;
5056
5057 /* run TX completion thread */
5058 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5059 tg3_tx(tnapi);
5060 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5061 return work_done;
5062 }
5063
5064 /* run RX thread, within the bounds set by NAPI.
5065 * All RX "locking" is done by ensuring outside
5066 * code synchronizes with tg3->napi.poll()
5067 */
5068 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5069 work_done += tg3_rx(tnapi, budget - work_done);
5070
5071 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5072 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5073 int i, err = 0;
5074 u32 std_prod_idx = dpr->rx_std_prod_idx;
5075 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5076
5077 for (i = 1; i < tp->irq_cnt; i++)
5078 err |= tg3_rx_prodring_xfer(tp, dpr,
5079 &tp->napi[i].prodring);
5080
5081 wmb();
5082
5083 if (std_prod_idx != dpr->rx_std_prod_idx)
5084 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5085 dpr->rx_std_prod_idx);
5086
5087 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5088 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5089 dpr->rx_jmb_prod_idx);
5090
5091 mmiowb();
5092
5093 if (err)
5094 tw32_f(HOSTCC_MODE, tp->coal_now);
5095 }
5096
5097 return work_done;
5098 }
5099
5100 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5101 {
5102 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5103 struct tg3 *tp = tnapi->tp;
5104 int work_done = 0;
5105 struct tg3_hw_status *sblk = tnapi->hw_status;
5106
5107 while (1) {
5108 work_done = tg3_poll_work(tnapi, work_done, budget);
5109
5110 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5111 goto tx_recovery;
5112
5113 if (unlikely(work_done >= budget))
5114 break;
5115
5116 /* tp->last_tag is used in tg3_int_reenable() below
5117 * to tell the hw how much work has been processed,
5118 * so we must read it before checking for more work.
5119 */
5120 tnapi->last_tag = sblk->status_tag;
5121 tnapi->last_irq_tag = tnapi->last_tag;
5122 rmb();
5123
5124 /* check for RX/TX work to do */
5125 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5126 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5127 napi_complete(napi);
5128 /* Reenable interrupts. */
5129 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5130 mmiowb();
5131 break;
5132 }
5133 }
5134
5135 return work_done;
5136
5137 tx_recovery:
5138 /* work_done is guaranteed to be less than budget. */
5139 napi_complete(napi);
5140 schedule_work(&tp->reset_task);
5141 return work_done;
5142 }
5143
5144 static int tg3_poll(struct napi_struct *napi, int budget)
5145 {
5146 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5147 struct tg3 *tp = tnapi->tp;
5148 int work_done = 0;
5149 struct tg3_hw_status *sblk = tnapi->hw_status;
5150
5151 while (1) {
5152 tg3_poll_link(tp);
5153
5154 work_done = tg3_poll_work(tnapi, work_done, budget);
5155
5156 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5157 goto tx_recovery;
5158
5159 if (unlikely(work_done >= budget))
5160 break;
5161
5162 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5163 /* tp->last_tag is used in tg3_int_reenable() below
5164 * to tell the hw how much work has been processed,
5165 * so we must read it before checking for more work.
5166 */
5167 tnapi->last_tag = sblk->status_tag;
5168 tnapi->last_irq_tag = tnapi->last_tag;
5169 rmb();
5170 } else
5171 sblk->status &= ~SD_STATUS_UPDATED;
5172
5173 if (likely(!tg3_has_work(tnapi))) {
5174 napi_complete(napi);
5175 tg3_int_reenable(tnapi);
5176 break;
5177 }
5178 }
5179
5180 return work_done;
5181
5182 tx_recovery:
5183 /* work_done is guaranteed to be less than budget. */
5184 napi_complete(napi);
5185 schedule_work(&tp->reset_task);
5186 return work_done;
5187 }
5188
5189 static void tg3_napi_disable(struct tg3 *tp)
5190 {
5191 int i;
5192
5193 for (i = tp->irq_cnt - 1; i >= 0; i--)
5194 napi_disable(&tp->napi[i].napi);
5195 }
5196
5197 static void tg3_napi_enable(struct tg3 *tp)
5198 {
5199 int i;
5200
5201 for (i = 0; i < tp->irq_cnt; i++)
5202 napi_enable(&tp->napi[i].napi);
5203 }
5204
5205 static void tg3_napi_init(struct tg3 *tp)
5206 {
5207 int i;
5208
5209 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5210 for (i = 1; i < tp->irq_cnt; i++)
5211 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5212 }
5213
5214 static void tg3_napi_fini(struct tg3 *tp)
5215 {
5216 int i;
5217
5218 for (i = 0; i < tp->irq_cnt; i++)
5219 netif_napi_del(&tp->napi[i].napi);
5220 }
5221
5222 static inline void tg3_netif_stop(struct tg3 *tp)
5223 {
5224 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5225 tg3_napi_disable(tp);
5226 netif_tx_disable(tp->dev);
5227 }
5228
5229 static inline void tg3_netif_start(struct tg3 *tp)
5230 {
5231 /* NOTE: unconditional netif_tx_wake_all_queues is only
5232 * appropriate so long as all callers are assured to
5233 * have free tx slots (such as after tg3_init_hw)
5234 */
5235 netif_tx_wake_all_queues(tp->dev);
5236
5237 tg3_napi_enable(tp);
5238 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5239 tg3_enable_ints(tp);
5240 }
5241
5242 static void tg3_irq_quiesce(struct tg3 *tp)
5243 {
5244 int i;
5245
5246 BUG_ON(tp->irq_sync);
5247
5248 tp->irq_sync = 1;
5249 smp_mb();
5250
5251 for (i = 0; i < tp->irq_cnt; i++)
5252 synchronize_irq(tp->napi[i].irq_vec);
5253 }
5254
5255 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5256 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5257 * with as well. Most of the time, this is not necessary except when
5258 * shutting down the device.
5259 */
5260 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5261 {
5262 spin_lock_bh(&tp->lock);
5263 if (irq_sync)
5264 tg3_irq_quiesce(tp);
5265 }
5266
5267 static inline void tg3_full_unlock(struct tg3 *tp)
5268 {
5269 spin_unlock_bh(&tp->lock);
5270 }
5271
5272 /* One-shot MSI handler - Chip automatically disables interrupt
5273 * after sending MSI so driver doesn't have to do it.
5274 */
5275 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5276 {
5277 struct tg3_napi *tnapi = dev_id;
5278 struct tg3 *tp = tnapi->tp;
5279
5280 prefetch(tnapi->hw_status);
5281 if (tnapi->rx_rcb)
5282 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5283
5284 if (likely(!tg3_irq_sync(tp)))
5285 napi_schedule(&tnapi->napi);
5286
5287 return IRQ_HANDLED;
5288 }
5289
5290 /* MSI ISR - No need to check for interrupt sharing and no need to
5291 * flush status block and interrupt mailbox. PCI ordering rules
5292 * guarantee that MSI will arrive after the status block.
5293 */
5294 static irqreturn_t tg3_msi(int irq, void *dev_id)
5295 {
5296 struct tg3_napi *tnapi = dev_id;
5297 struct tg3 *tp = tnapi->tp;
5298
5299 prefetch(tnapi->hw_status);
5300 if (tnapi->rx_rcb)
5301 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5302 /*
5303 * Writing any value to intr-mbox-0 clears PCI INTA# and
5304 * chip-internal interrupt pending events.
5305 * Writing non-zero to intr-mbox-0 additional tells the
5306 * NIC to stop sending us irqs, engaging "in-intr-handler"
5307 * event coalescing.
5308 */
5309 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5310 if (likely(!tg3_irq_sync(tp)))
5311 napi_schedule(&tnapi->napi);
5312
5313 return IRQ_RETVAL(1);
5314 }
5315
5316 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5317 {
5318 struct tg3_napi *tnapi = dev_id;
5319 struct tg3 *tp = tnapi->tp;
5320 struct tg3_hw_status *sblk = tnapi->hw_status;
5321 unsigned int handled = 1;
5322
5323 /* In INTx mode, it is possible for the interrupt to arrive at
5324 * the CPU before the status block posted prior to the interrupt.
5325 * Reading the PCI State register will confirm whether the
5326 * interrupt is ours and will flush the status block.
5327 */
5328 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5329 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5330 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5331 handled = 0;
5332 goto out;
5333 }
5334 }
5335
5336 /*
5337 * Writing any value to intr-mbox-0 clears PCI INTA# and
5338 * chip-internal interrupt pending events.
5339 * Writing non-zero to intr-mbox-0 additional tells the
5340 * NIC to stop sending us irqs, engaging "in-intr-handler"
5341 * event coalescing.
5342 *
5343 * Flush the mailbox to de-assert the IRQ immediately to prevent
5344 * spurious interrupts. The flush impacts performance but
5345 * excessive spurious interrupts can be worse in some cases.
5346 */
5347 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5348 if (tg3_irq_sync(tp))
5349 goto out;
5350 sblk->status &= ~SD_STATUS_UPDATED;
5351 if (likely(tg3_has_work(tnapi))) {
5352 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5353 napi_schedule(&tnapi->napi);
5354 } else {
5355 /* No work, shared interrupt perhaps? re-enable
5356 * interrupts, and flush that PCI write
5357 */
5358 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5359 0x00000000);
5360 }
5361 out:
5362 return IRQ_RETVAL(handled);
5363 }
5364
5365 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5366 {
5367 struct tg3_napi *tnapi = dev_id;
5368 struct tg3 *tp = tnapi->tp;
5369 struct tg3_hw_status *sblk = tnapi->hw_status;
5370 unsigned int handled = 1;
5371
5372 /* In INTx mode, it is possible for the interrupt to arrive at
5373 * the CPU before the status block posted prior to the interrupt.
5374 * Reading the PCI State register will confirm whether the
5375 * interrupt is ours and will flush the status block.
5376 */
5377 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5378 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5379 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5380 handled = 0;
5381 goto out;
5382 }
5383 }
5384
5385 /*
5386 * writing any value to intr-mbox-0 clears PCI INTA# and
5387 * chip-internal interrupt pending events.
5388 * writing non-zero to intr-mbox-0 additional tells the
5389 * NIC to stop sending us irqs, engaging "in-intr-handler"
5390 * event coalescing.
5391 *
5392 * Flush the mailbox to de-assert the IRQ immediately to prevent
5393 * spurious interrupts. The flush impacts performance but
5394 * excessive spurious interrupts can be worse in some cases.
5395 */
5396 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5397
5398 /*
5399 * In a shared interrupt configuration, sometimes other devices'
5400 * interrupts will scream. We record the current status tag here
5401 * so that the above check can report that the screaming interrupts
5402 * are unhandled. Eventually they will be silenced.
5403 */
5404 tnapi->last_irq_tag = sblk->status_tag;
5405
5406 if (tg3_irq_sync(tp))
5407 goto out;
5408
5409 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5410
5411 napi_schedule(&tnapi->napi);
5412
5413 out:
5414 return IRQ_RETVAL(handled);
5415 }
5416
5417 /* ISR for interrupt test */
5418 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5419 {
5420 struct tg3_napi *tnapi = dev_id;
5421 struct tg3 *tp = tnapi->tp;
5422 struct tg3_hw_status *sblk = tnapi->hw_status;
5423
5424 if ((sblk->status & SD_STATUS_UPDATED) ||
5425 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5426 tg3_disable_ints(tp);
5427 return IRQ_RETVAL(1);
5428 }
5429 return IRQ_RETVAL(0);
5430 }
5431
5432 static int tg3_init_hw(struct tg3 *, int);
5433 static int tg3_halt(struct tg3 *, int, int);
5434
5435 /* Restart hardware after configuration changes, self-test, etc.
5436 * Invoked with tp->lock held.
5437 */
5438 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5439 __releases(tp->lock)
5440 __acquires(tp->lock)
5441 {
5442 int err;
5443
5444 err = tg3_init_hw(tp, reset_phy);
5445 if (err) {
5446 netdev_err(tp->dev,
5447 "Failed to re-initialize device, aborting\n");
5448 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5449 tg3_full_unlock(tp);
5450 del_timer_sync(&tp->timer);
5451 tp->irq_sync = 0;
5452 tg3_napi_enable(tp);
5453 dev_close(tp->dev);
5454 tg3_full_lock(tp, 0);
5455 }
5456 return err;
5457 }
5458
5459 #ifdef CONFIG_NET_POLL_CONTROLLER
5460 static void tg3_poll_controller(struct net_device *dev)
5461 {
5462 int i;
5463 struct tg3 *tp = netdev_priv(dev);
5464
5465 for (i = 0; i < tp->irq_cnt; i++)
5466 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5467 }
5468 #endif
5469
5470 static void tg3_reset_task(struct work_struct *work)
5471 {
5472 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5473 int err;
5474 unsigned int restart_timer;
5475
5476 tg3_full_lock(tp, 0);
5477
5478 if (!netif_running(tp->dev)) {
5479 tg3_full_unlock(tp);
5480 return;
5481 }
5482
5483 tg3_full_unlock(tp);
5484
5485 tg3_phy_stop(tp);
5486
5487 tg3_netif_stop(tp);
5488
5489 tg3_full_lock(tp, 1);
5490
5491 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5492 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5493
5494 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5495 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5496 tp->write32_rx_mbox = tg3_write_flush_reg32;
5497 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5498 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5499 }
5500
5501 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5502 err = tg3_init_hw(tp, 1);
5503 if (err)
5504 goto out;
5505
5506 tg3_netif_start(tp);
5507
5508 if (restart_timer)
5509 mod_timer(&tp->timer, jiffies + 1);
5510
5511 out:
5512 tg3_full_unlock(tp);
5513
5514 if (!err)
5515 tg3_phy_start(tp);
5516 }
5517
5518 static void tg3_dump_short_state(struct tg3 *tp)
5519 {
5520 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5521 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5522 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5523 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5524 }
5525
5526 static void tg3_tx_timeout(struct net_device *dev)
5527 {
5528 struct tg3 *tp = netdev_priv(dev);
5529
5530 if (netif_msg_tx_err(tp)) {
5531 netdev_err(dev, "transmit timed out, resetting\n");
5532 tg3_dump_short_state(tp);
5533 }
5534
5535 schedule_work(&tp->reset_task);
5536 }
5537
5538 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5539 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5540 {
5541 u32 base = (u32) mapping & 0xffffffff;
5542
5543 return (base > 0xffffdcc0) && (base + len + 8 < base);
5544 }
5545
5546 /* Test for DMA addresses > 40-bit */
5547 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5548 int len)
5549 {
5550 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5551 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5552 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5553 return 0;
5554 #else
5555 return 0;
5556 #endif
5557 }
5558
5559 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5560
5561 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5562 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5563 struct sk_buff *skb, u32 last_plus_one,
5564 u32 *start, u32 base_flags, u32 mss)
5565 {
5566 struct tg3 *tp = tnapi->tp;
5567 struct sk_buff *new_skb;
5568 dma_addr_t new_addr = 0;
5569 u32 entry = *start;
5570 int i, ret = 0;
5571
5572 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5573 new_skb = skb_copy(skb, GFP_ATOMIC);
5574 else {
5575 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5576
5577 new_skb = skb_copy_expand(skb,
5578 skb_headroom(skb) + more_headroom,
5579 skb_tailroom(skb), GFP_ATOMIC);
5580 }
5581
5582 if (!new_skb) {
5583 ret = -1;
5584 } else {
5585 /* New SKB is guaranteed to be linear. */
5586 entry = *start;
5587 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5588 PCI_DMA_TODEVICE);
5589 /* Make sure the mapping succeeded */
5590 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5591 ret = -1;
5592 dev_kfree_skb(new_skb);
5593 new_skb = NULL;
5594
5595 /* Make sure new skb does not cross any 4G boundaries.
5596 * Drop the packet if it does.
5597 */
5598 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5599 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5600 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5601 PCI_DMA_TODEVICE);
5602 ret = -1;
5603 dev_kfree_skb(new_skb);
5604 new_skb = NULL;
5605 } else {
5606 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5607 base_flags, 1 | (mss << 1));
5608 *start = NEXT_TX(entry);
5609 }
5610 }
5611
5612 /* Now clean up the sw ring entries. */
5613 i = 0;
5614 while (entry != last_plus_one) {
5615 int len;
5616
5617 if (i == 0)
5618 len = skb_headlen(skb);
5619 else
5620 len = skb_shinfo(skb)->frags[i-1].size;
5621
5622 pci_unmap_single(tp->pdev,
5623 dma_unmap_addr(&tnapi->tx_buffers[entry],
5624 mapping),
5625 len, PCI_DMA_TODEVICE);
5626 if (i == 0) {
5627 tnapi->tx_buffers[entry].skb = new_skb;
5628 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5629 new_addr);
5630 } else {
5631 tnapi->tx_buffers[entry].skb = NULL;
5632 }
5633 entry = NEXT_TX(entry);
5634 i++;
5635 }
5636
5637 dev_kfree_skb(skb);
5638
5639 return ret;
5640 }
5641
5642 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5643 dma_addr_t mapping, int len, u32 flags,
5644 u32 mss_and_is_end)
5645 {
5646 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5647 int is_end = (mss_and_is_end & 0x1);
5648 u32 mss = (mss_and_is_end >> 1);
5649 u32 vlan_tag = 0;
5650
5651 if (is_end)
5652 flags |= TXD_FLAG_END;
5653 if (flags & TXD_FLAG_VLAN) {
5654 vlan_tag = flags >> 16;
5655 flags &= 0xffff;
5656 }
5657 vlan_tag |= (mss << TXD_MSS_SHIFT);
5658
5659 txd->addr_hi = ((u64) mapping >> 32);
5660 txd->addr_lo = ((u64) mapping & 0xffffffff);
5661 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5662 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5663 }
5664
5665 /* hard_start_xmit for devices that don't have any bugs and
5666 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5667 */
5668 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5669 struct net_device *dev)
5670 {
5671 struct tg3 *tp = netdev_priv(dev);
5672 u32 len, entry, base_flags, mss;
5673 dma_addr_t mapping;
5674 struct tg3_napi *tnapi;
5675 struct netdev_queue *txq;
5676 unsigned int i, last;
5677
5678 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5679 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5680 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5681 tnapi++;
5682
5683 /* We are running in BH disabled context with netif_tx_lock
5684 * and TX reclaim runs via tp->napi.poll inside of a software
5685 * interrupt. Furthermore, IRQ processing runs lockless so we have
5686 * no IRQ context deadlocks to worry about either. Rejoice!
5687 */
5688 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5689 if (!netif_tx_queue_stopped(txq)) {
5690 netif_tx_stop_queue(txq);
5691
5692 /* This is a hard error, log it. */
5693 netdev_err(dev,
5694 "BUG! Tx Ring full when queue awake!\n");
5695 }
5696 return NETDEV_TX_BUSY;
5697 }
5698
5699 entry = tnapi->tx_prod;
5700 base_flags = 0;
5701 mss = skb_shinfo(skb)->gso_size;
5702 if (mss) {
5703 int tcp_opt_len, ip_tcp_len;
5704 u32 hdrlen;
5705
5706 if (skb_header_cloned(skb) &&
5707 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5708 dev_kfree_skb(skb);
5709 goto out_unlock;
5710 }
5711
5712 if (skb_is_gso_v6(skb)) {
5713 hdrlen = skb_headlen(skb) - ETH_HLEN;
5714 } else {
5715 struct iphdr *iph = ip_hdr(skb);
5716
5717 tcp_opt_len = tcp_optlen(skb);
5718 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5719
5720 iph->check = 0;
5721 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5722 hdrlen = ip_tcp_len + tcp_opt_len;
5723 }
5724
5725 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5726 mss |= (hdrlen & 0xc) << 12;
5727 if (hdrlen & 0x10)
5728 base_flags |= 0x00000010;
5729 base_flags |= (hdrlen & 0x3e0) << 5;
5730 } else
5731 mss |= hdrlen << 9;
5732
5733 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5734 TXD_FLAG_CPU_POST_DMA);
5735
5736 tcp_hdr(skb)->check = 0;
5737
5738 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5739 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5740 }
5741
5742 if (vlan_tx_tag_present(skb))
5743 base_flags |= (TXD_FLAG_VLAN |
5744 (vlan_tx_tag_get(skb) << 16));
5745
5746 len = skb_headlen(skb);
5747
5748 /* Queue skb data, a.k.a. the main skb fragment. */
5749 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5750 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5751 dev_kfree_skb(skb);
5752 goto out_unlock;
5753 }
5754
5755 tnapi->tx_buffers[entry].skb = skb;
5756 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5757
5758 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5759 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5760 base_flags |= TXD_FLAG_JMB_PKT;
5761
5762 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5763 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5764
5765 entry = NEXT_TX(entry);
5766
5767 /* Now loop through additional data fragments, and queue them. */
5768 if (skb_shinfo(skb)->nr_frags > 0) {
5769 last = skb_shinfo(skb)->nr_frags - 1;
5770 for (i = 0; i <= last; i++) {
5771 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5772
5773 len = frag->size;
5774 mapping = pci_map_page(tp->pdev,
5775 frag->page,
5776 frag->page_offset,
5777 len, PCI_DMA_TODEVICE);
5778 if (pci_dma_mapping_error(tp->pdev, mapping))
5779 goto dma_error;
5780
5781 tnapi->tx_buffers[entry].skb = NULL;
5782 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5783 mapping);
5784
5785 tg3_set_txd(tnapi, entry, mapping, len,
5786 base_flags, (i == last) | (mss << 1));
5787
5788 entry = NEXT_TX(entry);
5789 }
5790 }
5791
5792 /* Packets are ready, update Tx producer idx local and on card. */
5793 tw32_tx_mbox(tnapi->prodmbox, entry);
5794
5795 tnapi->tx_prod = entry;
5796 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5797 netif_tx_stop_queue(txq);
5798
5799 /* netif_tx_stop_queue() must be done before checking
5800 * checking tx index in tg3_tx_avail() below, because in
5801 * tg3_tx(), we update tx index before checking for
5802 * netif_tx_queue_stopped().
5803 */
5804 smp_mb();
5805 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5806 netif_tx_wake_queue(txq);
5807 }
5808
5809 out_unlock:
5810 mmiowb();
5811
5812 return NETDEV_TX_OK;
5813
5814 dma_error:
5815 last = i;
5816 entry = tnapi->tx_prod;
5817 tnapi->tx_buffers[entry].skb = NULL;
5818 pci_unmap_single(tp->pdev,
5819 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5820 skb_headlen(skb),
5821 PCI_DMA_TODEVICE);
5822 for (i = 0; i <= last; i++) {
5823 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5824 entry = NEXT_TX(entry);
5825
5826 pci_unmap_page(tp->pdev,
5827 dma_unmap_addr(&tnapi->tx_buffers[entry],
5828 mapping),
5829 frag->size, PCI_DMA_TODEVICE);
5830 }
5831
5832 dev_kfree_skb(skb);
5833 return NETDEV_TX_OK;
5834 }
5835
5836 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5837 struct net_device *);
5838
5839 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5840 * TSO header is greater than 80 bytes.
5841 */
5842 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5843 {
5844 struct sk_buff *segs, *nskb;
5845 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5846
5847 /* Estimate the number of fragments in the worst case */
5848 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5849 netif_stop_queue(tp->dev);
5850
5851 /* netif_tx_stop_queue() must be done before checking
5852 * checking tx index in tg3_tx_avail() below, because in
5853 * tg3_tx(), we update tx index before checking for
5854 * netif_tx_queue_stopped().
5855 */
5856 smp_mb();
5857 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5858 return NETDEV_TX_BUSY;
5859
5860 netif_wake_queue(tp->dev);
5861 }
5862
5863 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5864 if (IS_ERR(segs))
5865 goto tg3_tso_bug_end;
5866
5867 do {
5868 nskb = segs;
5869 segs = segs->next;
5870 nskb->next = NULL;
5871 tg3_start_xmit_dma_bug(nskb, tp->dev);
5872 } while (segs);
5873
5874 tg3_tso_bug_end:
5875 dev_kfree_skb(skb);
5876
5877 return NETDEV_TX_OK;
5878 }
5879
5880 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5881 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5882 */
5883 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5884 struct net_device *dev)
5885 {
5886 struct tg3 *tp = netdev_priv(dev);
5887 u32 len, entry, base_flags, mss;
5888 int would_hit_hwbug;
5889 dma_addr_t mapping;
5890 struct tg3_napi *tnapi;
5891 struct netdev_queue *txq;
5892 unsigned int i, last;
5893
5894 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5895 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5896 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5897 tnapi++;
5898
5899 /* We are running in BH disabled context with netif_tx_lock
5900 * and TX reclaim runs via tp->napi.poll inside of a software
5901 * interrupt. Furthermore, IRQ processing runs lockless so we have
5902 * no IRQ context deadlocks to worry about either. Rejoice!
5903 */
5904 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5905 if (!netif_tx_queue_stopped(txq)) {
5906 netif_tx_stop_queue(txq);
5907
5908 /* This is a hard error, log it. */
5909 netdev_err(dev,
5910 "BUG! Tx Ring full when queue awake!\n");
5911 }
5912 return NETDEV_TX_BUSY;
5913 }
5914
5915 entry = tnapi->tx_prod;
5916 base_flags = 0;
5917 if (skb->ip_summed == CHECKSUM_PARTIAL)
5918 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5919
5920 mss = skb_shinfo(skb)->gso_size;
5921 if (mss) {
5922 struct iphdr *iph;
5923 u32 tcp_opt_len, hdr_len;
5924
5925 if (skb_header_cloned(skb) &&
5926 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5927 dev_kfree_skb(skb);
5928 goto out_unlock;
5929 }
5930
5931 iph = ip_hdr(skb);
5932 tcp_opt_len = tcp_optlen(skb);
5933
5934 if (skb_is_gso_v6(skb)) {
5935 hdr_len = skb_headlen(skb) - ETH_HLEN;
5936 } else {
5937 u32 ip_tcp_len;
5938
5939 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5940 hdr_len = ip_tcp_len + tcp_opt_len;
5941
5942 iph->check = 0;
5943 iph->tot_len = htons(mss + hdr_len);
5944 }
5945
5946 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5947 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5948 return tg3_tso_bug(tp, skb);
5949
5950 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5951 TXD_FLAG_CPU_POST_DMA);
5952
5953 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5954 tcp_hdr(skb)->check = 0;
5955 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5956 } else
5957 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5958 iph->daddr, 0,
5959 IPPROTO_TCP,
5960 0);
5961
5962 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5963 mss |= (hdr_len & 0xc) << 12;
5964 if (hdr_len & 0x10)
5965 base_flags |= 0x00000010;
5966 base_flags |= (hdr_len & 0x3e0) << 5;
5967 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5968 mss |= hdr_len << 9;
5969 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5971 if (tcp_opt_len || iph->ihl > 5) {
5972 int tsflags;
5973
5974 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5975 mss |= (tsflags << 11);
5976 }
5977 } else {
5978 if (tcp_opt_len || iph->ihl > 5) {
5979 int tsflags;
5980
5981 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5982 base_flags |= tsflags << 12;
5983 }
5984 }
5985 }
5986
5987 if (vlan_tx_tag_present(skb))
5988 base_flags |= (TXD_FLAG_VLAN |
5989 (vlan_tx_tag_get(skb) << 16));
5990
5991 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5992 !mss && skb->len > VLAN_ETH_FRAME_LEN)
5993 base_flags |= TXD_FLAG_JMB_PKT;
5994
5995 len = skb_headlen(skb);
5996
5997 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5998 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5999 dev_kfree_skb(skb);
6000 goto out_unlock;
6001 }
6002
6003 tnapi->tx_buffers[entry].skb = skb;
6004 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6005
6006 would_hit_hwbug = 0;
6007
6008 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6009 would_hit_hwbug = 1;
6010
6011 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6012 tg3_4g_overflow_test(mapping, len))
6013 would_hit_hwbug = 1;
6014
6015 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6016 tg3_40bit_overflow_test(tp, mapping, len))
6017 would_hit_hwbug = 1;
6018
6019 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6020 would_hit_hwbug = 1;
6021
6022 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6023 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6024
6025 entry = NEXT_TX(entry);
6026
6027 /* Now loop through additional data fragments, and queue them. */
6028 if (skb_shinfo(skb)->nr_frags > 0) {
6029 last = skb_shinfo(skb)->nr_frags - 1;
6030 for (i = 0; i <= last; i++) {
6031 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6032
6033 len = frag->size;
6034 mapping = pci_map_page(tp->pdev,
6035 frag->page,
6036 frag->page_offset,
6037 len, PCI_DMA_TODEVICE);
6038
6039 tnapi->tx_buffers[entry].skb = NULL;
6040 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6041 mapping);
6042 if (pci_dma_mapping_error(tp->pdev, mapping))
6043 goto dma_error;
6044
6045 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6046 len <= 8)
6047 would_hit_hwbug = 1;
6048
6049 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6050 tg3_4g_overflow_test(mapping, len))
6051 would_hit_hwbug = 1;
6052
6053 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6054 tg3_40bit_overflow_test(tp, mapping, len))
6055 would_hit_hwbug = 1;
6056
6057 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6058 tg3_set_txd(tnapi, entry, mapping, len,
6059 base_flags, (i == last)|(mss << 1));
6060 else
6061 tg3_set_txd(tnapi, entry, mapping, len,
6062 base_flags, (i == last));
6063
6064 entry = NEXT_TX(entry);
6065 }
6066 }
6067
6068 if (would_hit_hwbug) {
6069 u32 last_plus_one = entry;
6070 u32 start;
6071
6072 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6073 start &= (TG3_TX_RING_SIZE - 1);
6074
6075 /* If the workaround fails due to memory/mapping
6076 * failure, silently drop this packet.
6077 */
6078 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6079 &start, base_flags, mss))
6080 goto out_unlock;
6081
6082 entry = start;
6083 }
6084
6085 /* Packets are ready, update Tx producer idx local and on card. */
6086 tw32_tx_mbox(tnapi->prodmbox, entry);
6087
6088 tnapi->tx_prod = entry;
6089 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6090 netif_tx_stop_queue(txq);
6091
6092 /* netif_tx_stop_queue() must be done before checking
6093 * checking tx index in tg3_tx_avail() below, because in
6094 * tg3_tx(), we update tx index before checking for
6095 * netif_tx_queue_stopped().
6096 */
6097 smp_mb();
6098 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6099 netif_tx_wake_queue(txq);
6100 }
6101
6102 out_unlock:
6103 mmiowb();
6104
6105 return NETDEV_TX_OK;
6106
6107 dma_error:
6108 last = i;
6109 entry = tnapi->tx_prod;
6110 tnapi->tx_buffers[entry].skb = NULL;
6111 pci_unmap_single(tp->pdev,
6112 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6113 skb_headlen(skb),
6114 PCI_DMA_TODEVICE);
6115 for (i = 0; i <= last; i++) {
6116 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6117 entry = NEXT_TX(entry);
6118
6119 pci_unmap_page(tp->pdev,
6120 dma_unmap_addr(&tnapi->tx_buffers[entry],
6121 mapping),
6122 frag->size, PCI_DMA_TODEVICE);
6123 }
6124
6125 dev_kfree_skb(skb);
6126 return NETDEV_TX_OK;
6127 }
6128
6129 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6130 int new_mtu)
6131 {
6132 dev->mtu = new_mtu;
6133
6134 if (new_mtu > ETH_DATA_LEN) {
6135 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6136 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6137 ethtool_op_set_tso(dev, 0);
6138 } else {
6139 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6140 }
6141 } else {
6142 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6143 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6144 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6145 }
6146 }
6147
6148 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6149 {
6150 struct tg3 *tp = netdev_priv(dev);
6151 int err;
6152
6153 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6154 return -EINVAL;
6155
6156 if (!netif_running(dev)) {
6157 /* We'll just catch it later when the
6158 * device is up'd.
6159 */
6160 tg3_set_mtu(dev, tp, new_mtu);
6161 return 0;
6162 }
6163
6164 tg3_phy_stop(tp);
6165
6166 tg3_netif_stop(tp);
6167
6168 tg3_full_lock(tp, 1);
6169
6170 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6171
6172 tg3_set_mtu(dev, tp, new_mtu);
6173
6174 err = tg3_restart_hw(tp, 0);
6175
6176 if (!err)
6177 tg3_netif_start(tp);
6178
6179 tg3_full_unlock(tp);
6180
6181 if (!err)
6182 tg3_phy_start(tp);
6183
6184 return err;
6185 }
6186
6187 static void tg3_rx_prodring_free(struct tg3 *tp,
6188 struct tg3_rx_prodring_set *tpr)
6189 {
6190 int i;
6191
6192 if (tpr != &tp->napi[0].prodring) {
6193 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6194 i = (i + 1) & tp->rx_std_ring_mask)
6195 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6196 tp->rx_pkt_map_sz);
6197
6198 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6199 for (i = tpr->rx_jmb_cons_idx;
6200 i != tpr->rx_jmb_prod_idx;
6201 i = (i + 1) & tp->rx_jmb_ring_mask) {
6202 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6203 TG3_RX_JMB_MAP_SZ);
6204 }
6205 }
6206
6207 return;
6208 }
6209
6210 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6211 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6212 tp->rx_pkt_map_sz);
6213
6214 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6215 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6216 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6217 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6218 TG3_RX_JMB_MAP_SZ);
6219 }
6220 }
6221
6222 /* Initialize rx rings for packet processing.
6223 *
6224 * The chip has been shut down and the driver detached from
6225 * the networking, so no interrupts or new tx packets will
6226 * end up in the driver. tp->{tx,}lock are held and thus
6227 * we may not sleep.
6228 */
6229 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6230 struct tg3_rx_prodring_set *tpr)
6231 {
6232 u32 i, rx_pkt_dma_sz;
6233
6234 tpr->rx_std_cons_idx = 0;
6235 tpr->rx_std_prod_idx = 0;
6236 tpr->rx_jmb_cons_idx = 0;
6237 tpr->rx_jmb_prod_idx = 0;
6238
6239 if (tpr != &tp->napi[0].prodring) {
6240 memset(&tpr->rx_std_buffers[0], 0,
6241 TG3_RX_STD_BUFF_RING_SIZE(tp));
6242 if (tpr->rx_jmb_buffers)
6243 memset(&tpr->rx_jmb_buffers[0], 0,
6244 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6245 goto done;
6246 }
6247
6248 /* Zero out all descriptors. */
6249 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6250
6251 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6252 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6253 tp->dev->mtu > ETH_DATA_LEN)
6254 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6255 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6256
6257 /* Initialize invariants of the rings, we only set this
6258 * stuff once. This works because the card does not
6259 * write into the rx buffer posting rings.
6260 */
6261 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6262 struct tg3_rx_buffer_desc *rxd;
6263
6264 rxd = &tpr->rx_std[i];
6265 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6266 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6267 rxd->opaque = (RXD_OPAQUE_RING_STD |
6268 (i << RXD_OPAQUE_INDEX_SHIFT));
6269 }
6270
6271 /* Now allocate fresh SKBs for each rx ring. */
6272 for (i = 0; i < tp->rx_pending; i++) {
6273 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6274 netdev_warn(tp->dev,
6275 "Using a smaller RX standard ring. Only "
6276 "%d out of %d buffers were allocated "
6277 "successfully\n", i, tp->rx_pending);
6278 if (i == 0)
6279 goto initfail;
6280 tp->rx_pending = i;
6281 break;
6282 }
6283 }
6284
6285 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6286 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6287 goto done;
6288
6289 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6290
6291 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6292 goto done;
6293
6294 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6295 struct tg3_rx_buffer_desc *rxd;
6296
6297 rxd = &tpr->rx_jmb[i].std;
6298 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6299 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6300 RXD_FLAG_JUMBO;
6301 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6302 (i << RXD_OPAQUE_INDEX_SHIFT));
6303 }
6304
6305 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6306 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6307 netdev_warn(tp->dev,
6308 "Using a smaller RX jumbo ring. Only %d "
6309 "out of %d buffers were allocated "
6310 "successfully\n", i, tp->rx_jumbo_pending);
6311 if (i == 0)
6312 goto initfail;
6313 tp->rx_jumbo_pending = i;
6314 break;
6315 }
6316 }
6317
6318 done:
6319 return 0;
6320
6321 initfail:
6322 tg3_rx_prodring_free(tp, tpr);
6323 return -ENOMEM;
6324 }
6325
6326 static void tg3_rx_prodring_fini(struct tg3 *tp,
6327 struct tg3_rx_prodring_set *tpr)
6328 {
6329 kfree(tpr->rx_std_buffers);
6330 tpr->rx_std_buffers = NULL;
6331 kfree(tpr->rx_jmb_buffers);
6332 tpr->rx_jmb_buffers = NULL;
6333 if (tpr->rx_std) {
6334 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6335 tpr->rx_std, tpr->rx_std_mapping);
6336 tpr->rx_std = NULL;
6337 }
6338 if (tpr->rx_jmb) {
6339 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6340 tpr->rx_jmb, tpr->rx_jmb_mapping);
6341 tpr->rx_jmb = NULL;
6342 }
6343 }
6344
6345 static int tg3_rx_prodring_init(struct tg3 *tp,
6346 struct tg3_rx_prodring_set *tpr)
6347 {
6348 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6349 GFP_KERNEL);
6350 if (!tpr->rx_std_buffers)
6351 return -ENOMEM;
6352
6353 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6354 TG3_RX_STD_RING_BYTES(tp),
6355 &tpr->rx_std_mapping,
6356 GFP_KERNEL);
6357 if (!tpr->rx_std)
6358 goto err_out;
6359
6360 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6361 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6362 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6363 GFP_KERNEL);
6364 if (!tpr->rx_jmb_buffers)
6365 goto err_out;
6366
6367 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6368 TG3_RX_JMB_RING_BYTES(tp),
6369 &tpr->rx_jmb_mapping,
6370 GFP_KERNEL);
6371 if (!tpr->rx_jmb)
6372 goto err_out;
6373 }
6374
6375 return 0;
6376
6377 err_out:
6378 tg3_rx_prodring_fini(tp, tpr);
6379 return -ENOMEM;
6380 }
6381
6382 /* Free up pending packets in all rx/tx rings.
6383 *
6384 * The chip has been shut down and the driver detached from
6385 * the networking, so no interrupts or new tx packets will
6386 * end up in the driver. tp->{tx,}lock is not held and we are not
6387 * in an interrupt context and thus may sleep.
6388 */
6389 static void tg3_free_rings(struct tg3 *tp)
6390 {
6391 int i, j;
6392
6393 for (j = 0; j < tp->irq_cnt; j++) {
6394 struct tg3_napi *tnapi = &tp->napi[j];
6395
6396 tg3_rx_prodring_free(tp, &tnapi->prodring);
6397
6398 if (!tnapi->tx_buffers)
6399 continue;
6400
6401 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6402 struct ring_info *txp;
6403 struct sk_buff *skb;
6404 unsigned int k;
6405
6406 txp = &tnapi->tx_buffers[i];
6407 skb = txp->skb;
6408
6409 if (skb == NULL) {
6410 i++;
6411 continue;
6412 }
6413
6414 pci_unmap_single(tp->pdev,
6415 dma_unmap_addr(txp, mapping),
6416 skb_headlen(skb),
6417 PCI_DMA_TODEVICE);
6418 txp->skb = NULL;
6419
6420 i++;
6421
6422 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6423 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6424 pci_unmap_page(tp->pdev,
6425 dma_unmap_addr(txp, mapping),
6426 skb_shinfo(skb)->frags[k].size,
6427 PCI_DMA_TODEVICE);
6428 i++;
6429 }
6430
6431 dev_kfree_skb_any(skb);
6432 }
6433 }
6434 }
6435
6436 /* Initialize tx/rx rings for packet processing.
6437 *
6438 * The chip has been shut down and the driver detached from
6439 * the networking, so no interrupts or new tx packets will
6440 * end up in the driver. tp->{tx,}lock are held and thus
6441 * we may not sleep.
6442 */
6443 static int tg3_init_rings(struct tg3 *tp)
6444 {
6445 int i;
6446
6447 /* Free up all the SKBs. */
6448 tg3_free_rings(tp);
6449
6450 for (i = 0; i < tp->irq_cnt; i++) {
6451 struct tg3_napi *tnapi = &tp->napi[i];
6452
6453 tnapi->last_tag = 0;
6454 tnapi->last_irq_tag = 0;
6455 tnapi->hw_status->status = 0;
6456 tnapi->hw_status->status_tag = 0;
6457 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6458
6459 tnapi->tx_prod = 0;
6460 tnapi->tx_cons = 0;
6461 if (tnapi->tx_ring)
6462 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6463
6464 tnapi->rx_rcb_ptr = 0;
6465 if (tnapi->rx_rcb)
6466 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6467
6468 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6469 tg3_free_rings(tp);
6470 return -ENOMEM;
6471 }
6472 }
6473
6474 return 0;
6475 }
6476
6477 /*
6478 * Must not be invoked with interrupt sources disabled and
6479 * the hardware shutdown down.
6480 */
6481 static void tg3_free_consistent(struct tg3 *tp)
6482 {
6483 int i;
6484
6485 for (i = 0; i < tp->irq_cnt; i++) {
6486 struct tg3_napi *tnapi = &tp->napi[i];
6487
6488 if (tnapi->tx_ring) {
6489 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6490 tnapi->tx_ring, tnapi->tx_desc_mapping);
6491 tnapi->tx_ring = NULL;
6492 }
6493
6494 kfree(tnapi->tx_buffers);
6495 tnapi->tx_buffers = NULL;
6496
6497 if (tnapi->rx_rcb) {
6498 dma_free_coherent(&tp->pdev->dev,
6499 TG3_RX_RCB_RING_BYTES(tp),
6500 tnapi->rx_rcb,
6501 tnapi->rx_rcb_mapping);
6502 tnapi->rx_rcb = NULL;
6503 }
6504
6505 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6506
6507 if (tnapi->hw_status) {
6508 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6509 tnapi->hw_status,
6510 tnapi->status_mapping);
6511 tnapi->hw_status = NULL;
6512 }
6513 }
6514
6515 if (tp->hw_stats) {
6516 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6517 tp->hw_stats, tp->stats_mapping);
6518 tp->hw_stats = NULL;
6519 }
6520 }
6521
6522 /*
6523 * Must not be invoked with interrupt sources disabled and
6524 * the hardware shutdown down. Can sleep.
6525 */
6526 static int tg3_alloc_consistent(struct tg3 *tp)
6527 {
6528 int i;
6529
6530 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6531 sizeof(struct tg3_hw_stats),
6532 &tp->stats_mapping,
6533 GFP_KERNEL);
6534 if (!tp->hw_stats)
6535 goto err_out;
6536
6537 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6538
6539 for (i = 0; i < tp->irq_cnt; i++) {
6540 struct tg3_napi *tnapi = &tp->napi[i];
6541 struct tg3_hw_status *sblk;
6542
6543 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6544 TG3_HW_STATUS_SIZE,
6545 &tnapi->status_mapping,
6546 GFP_KERNEL);
6547 if (!tnapi->hw_status)
6548 goto err_out;
6549
6550 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6551 sblk = tnapi->hw_status;
6552
6553 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6554 goto err_out;
6555
6556 /* If multivector TSS is enabled, vector 0 does not handle
6557 * tx interrupts. Don't allocate any resources for it.
6558 */
6559 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6560 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6561 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6562 TG3_TX_RING_SIZE,
6563 GFP_KERNEL);
6564 if (!tnapi->tx_buffers)
6565 goto err_out;
6566
6567 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6568 TG3_TX_RING_BYTES,
6569 &tnapi->tx_desc_mapping,
6570 GFP_KERNEL);
6571 if (!tnapi->tx_ring)
6572 goto err_out;
6573 }
6574
6575 /*
6576 * When RSS is enabled, the status block format changes
6577 * slightly. The "rx_jumbo_consumer", "reserved",
6578 * and "rx_mini_consumer" members get mapped to the
6579 * other three rx return ring producer indexes.
6580 */
6581 switch (i) {
6582 default:
6583 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6584 break;
6585 case 2:
6586 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6587 break;
6588 case 3:
6589 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6590 break;
6591 case 4:
6592 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6593 break;
6594 }
6595
6596 /*
6597 * If multivector RSS is enabled, vector 0 does not handle
6598 * rx or tx interrupts. Don't allocate any resources for it.
6599 */
6600 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6601 continue;
6602
6603 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6604 TG3_RX_RCB_RING_BYTES(tp),
6605 &tnapi->rx_rcb_mapping,
6606 GFP_KERNEL);
6607 if (!tnapi->rx_rcb)
6608 goto err_out;
6609
6610 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6611 }
6612
6613 return 0;
6614
6615 err_out:
6616 tg3_free_consistent(tp);
6617 return -ENOMEM;
6618 }
6619
6620 #define MAX_WAIT_CNT 1000
6621
6622 /* To stop a block, clear the enable bit and poll till it
6623 * clears. tp->lock is held.
6624 */
6625 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6626 {
6627 unsigned int i;
6628 u32 val;
6629
6630 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6631 switch (ofs) {
6632 case RCVLSC_MODE:
6633 case DMAC_MODE:
6634 case MBFREE_MODE:
6635 case BUFMGR_MODE:
6636 case MEMARB_MODE:
6637 /* We can't enable/disable these bits of the
6638 * 5705/5750, just say success.
6639 */
6640 return 0;
6641
6642 default:
6643 break;
6644 }
6645 }
6646
6647 val = tr32(ofs);
6648 val &= ~enable_bit;
6649 tw32_f(ofs, val);
6650
6651 for (i = 0; i < MAX_WAIT_CNT; i++) {
6652 udelay(100);
6653 val = tr32(ofs);
6654 if ((val & enable_bit) == 0)
6655 break;
6656 }
6657
6658 if (i == MAX_WAIT_CNT && !silent) {
6659 dev_err(&tp->pdev->dev,
6660 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6661 ofs, enable_bit);
6662 return -ENODEV;
6663 }
6664
6665 return 0;
6666 }
6667
6668 /* tp->lock is held. */
6669 static int tg3_abort_hw(struct tg3 *tp, int silent)
6670 {
6671 int i, err;
6672
6673 tg3_disable_ints(tp);
6674
6675 tp->rx_mode &= ~RX_MODE_ENABLE;
6676 tw32_f(MAC_RX_MODE, tp->rx_mode);
6677 udelay(10);
6678
6679 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6680 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6681 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6682 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6683 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6684 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6685
6686 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6689 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6690 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6691 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6692 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6693
6694 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6695 tw32_f(MAC_MODE, tp->mac_mode);
6696 udelay(40);
6697
6698 tp->tx_mode &= ~TX_MODE_ENABLE;
6699 tw32_f(MAC_TX_MODE, tp->tx_mode);
6700
6701 for (i = 0; i < MAX_WAIT_CNT; i++) {
6702 udelay(100);
6703 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6704 break;
6705 }
6706 if (i >= MAX_WAIT_CNT) {
6707 dev_err(&tp->pdev->dev,
6708 "%s timed out, TX_MODE_ENABLE will not clear "
6709 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6710 err |= -ENODEV;
6711 }
6712
6713 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6714 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6715 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6716
6717 tw32(FTQ_RESET, 0xffffffff);
6718 tw32(FTQ_RESET, 0x00000000);
6719
6720 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6721 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6722
6723 for (i = 0; i < tp->irq_cnt; i++) {
6724 struct tg3_napi *tnapi = &tp->napi[i];
6725 if (tnapi->hw_status)
6726 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6727 }
6728 if (tp->hw_stats)
6729 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730
6731 return err;
6732 }
6733
6734 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6735 {
6736 int i;
6737 u32 apedata;
6738
6739 /* NCSI does not support APE events */
6740 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6741 return;
6742
6743 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6744 if (apedata != APE_SEG_SIG_MAGIC)
6745 return;
6746
6747 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6748 if (!(apedata & APE_FW_STATUS_READY))
6749 return;
6750
6751 /* Wait for up to 1 millisecond for APE to service previous event. */
6752 for (i = 0; i < 10; i++) {
6753 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6754 return;
6755
6756 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6757
6758 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6759 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6760 event | APE_EVENT_STATUS_EVENT_PENDING);
6761
6762 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6763
6764 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6765 break;
6766
6767 udelay(100);
6768 }
6769
6770 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6771 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6772 }
6773
6774 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6775 {
6776 u32 event;
6777 u32 apedata;
6778
6779 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6780 return;
6781
6782 switch (kind) {
6783 case RESET_KIND_INIT:
6784 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6785 APE_HOST_SEG_SIG_MAGIC);
6786 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6787 APE_HOST_SEG_LEN_MAGIC);
6788 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6789 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6790 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6791 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6792 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6793 APE_HOST_BEHAV_NO_PHYLOCK);
6794 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6795 TG3_APE_HOST_DRVR_STATE_START);
6796
6797 event = APE_EVENT_STATUS_STATE_START;
6798 break;
6799 case RESET_KIND_SHUTDOWN:
6800 /* With the interface we are currently using,
6801 * APE does not track driver state. Wiping
6802 * out the HOST SEGMENT SIGNATURE forces
6803 * the APE to assume OS absent status.
6804 */
6805 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6806
6807 if (device_may_wakeup(&tp->pdev->dev) &&
6808 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6809 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6810 TG3_APE_HOST_WOL_SPEED_AUTO);
6811 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6812 } else
6813 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6814
6815 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6816
6817 event = APE_EVENT_STATUS_STATE_UNLOAD;
6818 break;
6819 case RESET_KIND_SUSPEND:
6820 event = APE_EVENT_STATUS_STATE_SUSPEND;
6821 break;
6822 default:
6823 return;
6824 }
6825
6826 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6827
6828 tg3_ape_send_event(tp, event);
6829 }
6830
6831 /* tp->lock is held. */
6832 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6833 {
6834 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6835 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6836
6837 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6838 switch (kind) {
6839 case RESET_KIND_INIT:
6840 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6841 DRV_STATE_START);
6842 break;
6843
6844 case RESET_KIND_SHUTDOWN:
6845 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6846 DRV_STATE_UNLOAD);
6847 break;
6848
6849 case RESET_KIND_SUSPEND:
6850 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6851 DRV_STATE_SUSPEND);
6852 break;
6853
6854 default:
6855 break;
6856 }
6857 }
6858
6859 if (kind == RESET_KIND_INIT ||
6860 kind == RESET_KIND_SUSPEND)
6861 tg3_ape_driver_state_change(tp, kind);
6862 }
6863
6864 /* tp->lock is held. */
6865 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6866 {
6867 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6868 switch (kind) {
6869 case RESET_KIND_INIT:
6870 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6871 DRV_STATE_START_DONE);
6872 break;
6873
6874 case RESET_KIND_SHUTDOWN:
6875 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6876 DRV_STATE_UNLOAD_DONE);
6877 break;
6878
6879 default:
6880 break;
6881 }
6882 }
6883
6884 if (kind == RESET_KIND_SHUTDOWN)
6885 tg3_ape_driver_state_change(tp, kind);
6886 }
6887
6888 /* tp->lock is held. */
6889 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6890 {
6891 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6892 switch (kind) {
6893 case RESET_KIND_INIT:
6894 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6895 DRV_STATE_START);
6896 break;
6897
6898 case RESET_KIND_SHUTDOWN:
6899 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6900 DRV_STATE_UNLOAD);
6901 break;
6902
6903 case RESET_KIND_SUSPEND:
6904 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905 DRV_STATE_SUSPEND);
6906 break;
6907
6908 default:
6909 break;
6910 }
6911 }
6912 }
6913
6914 static int tg3_poll_fw(struct tg3 *tp)
6915 {
6916 int i;
6917 u32 val;
6918
6919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6920 /* Wait up to 20ms for init done. */
6921 for (i = 0; i < 200; i++) {
6922 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6923 return 0;
6924 udelay(100);
6925 }
6926 return -ENODEV;
6927 }
6928
6929 /* Wait for firmware initialization to complete. */
6930 for (i = 0; i < 100000; i++) {
6931 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6932 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6933 break;
6934 udelay(10);
6935 }
6936
6937 /* Chip might not be fitted with firmware. Some Sun onboard
6938 * parts are configured like that. So don't signal the timeout
6939 * of the above loop as an error, but do report the lack of
6940 * running firmware once.
6941 */
6942 if (i >= 100000 &&
6943 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6944 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6945
6946 netdev_info(tp->dev, "No firmware running\n");
6947 }
6948
6949 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6950 /* The 57765 A0 needs a little more
6951 * time to do some important work.
6952 */
6953 mdelay(10);
6954 }
6955
6956 return 0;
6957 }
6958
6959 /* Save PCI command register before chip reset */
6960 static void tg3_save_pci_state(struct tg3 *tp)
6961 {
6962 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6963 }
6964
6965 /* Restore PCI state after chip reset */
6966 static void tg3_restore_pci_state(struct tg3 *tp)
6967 {
6968 u32 val;
6969
6970 /* Re-enable indirect register accesses. */
6971 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6972 tp->misc_host_ctrl);
6973
6974 /* Set MAX PCI retry to zero. */
6975 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6976 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6977 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6978 val |= PCISTATE_RETRY_SAME_DMA;
6979 /* Allow reads and writes to the APE register and memory space. */
6980 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6981 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6982 PCISTATE_ALLOW_APE_SHMEM_WR |
6983 PCISTATE_ALLOW_APE_PSPACE_WR;
6984 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6985
6986 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6987
6988 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6989 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6990 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6991 else {
6992 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6993 tp->pci_cacheline_sz);
6994 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6995 tp->pci_lat_timer);
6996 }
6997 }
6998
6999 /* Make sure PCI-X relaxed ordering bit is clear. */
7000 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7001 u16 pcix_cmd;
7002
7003 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7004 &pcix_cmd);
7005 pcix_cmd &= ~PCI_X_CMD_ERO;
7006 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7007 pcix_cmd);
7008 }
7009
7010 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7011
7012 /* Chip reset on 5780 will reset MSI enable bit,
7013 * so need to restore it.
7014 */
7015 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7016 u16 ctrl;
7017
7018 pci_read_config_word(tp->pdev,
7019 tp->msi_cap + PCI_MSI_FLAGS,
7020 &ctrl);
7021 pci_write_config_word(tp->pdev,
7022 tp->msi_cap + PCI_MSI_FLAGS,
7023 ctrl | PCI_MSI_FLAGS_ENABLE);
7024 val = tr32(MSGINT_MODE);
7025 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7026 }
7027 }
7028 }
7029
7030 static void tg3_stop_fw(struct tg3 *);
7031
7032 /* tp->lock is held. */
7033 static int tg3_chip_reset(struct tg3 *tp)
7034 {
7035 u32 val;
7036 void (*write_op)(struct tg3 *, u32, u32);
7037 int i, err;
7038
7039 tg3_nvram_lock(tp);
7040
7041 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7042
7043 /* No matching tg3_nvram_unlock() after this because
7044 * chip reset below will undo the nvram lock.
7045 */
7046 tp->nvram_lock_cnt = 0;
7047
7048 /* GRC_MISC_CFG core clock reset will clear the memory
7049 * enable bit in PCI register 4 and the MSI enable bit
7050 * on some chips, so we save relevant registers here.
7051 */
7052 tg3_save_pci_state(tp);
7053
7054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7055 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7056 tw32(GRC_FASTBOOT_PC, 0);
7057
7058 /*
7059 * We must avoid the readl() that normally takes place.
7060 * It locks machines, causes machine checks, and other
7061 * fun things. So, temporarily disable the 5701
7062 * hardware workaround, while we do the reset.
7063 */
7064 write_op = tp->write32;
7065 if (write_op == tg3_write_flush_reg32)
7066 tp->write32 = tg3_write32;
7067
7068 /* Prevent the irq handler from reading or writing PCI registers
7069 * during chip reset when the memory enable bit in the PCI command
7070 * register may be cleared. The chip does not generate interrupt
7071 * at this time, but the irq handler may still be called due to irq
7072 * sharing or irqpoll.
7073 */
7074 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7075 for (i = 0; i < tp->irq_cnt; i++) {
7076 struct tg3_napi *tnapi = &tp->napi[i];
7077 if (tnapi->hw_status) {
7078 tnapi->hw_status->status = 0;
7079 tnapi->hw_status->status_tag = 0;
7080 }
7081 tnapi->last_tag = 0;
7082 tnapi->last_irq_tag = 0;
7083 }
7084 smp_mb();
7085
7086 for (i = 0; i < tp->irq_cnt; i++)
7087 synchronize_irq(tp->napi[i].irq_vec);
7088
7089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7090 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7091 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7092 }
7093
7094 /* do the reset */
7095 val = GRC_MISC_CFG_CORECLK_RESET;
7096
7097 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7098 /* Force PCIe 1.0a mode */
7099 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7100 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7101 tr32(TG3_PCIE_PHY_TSTCTL) ==
7102 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7103 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7104
7105 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7106 tw32(GRC_MISC_CFG, (1 << 29));
7107 val |= (1 << 29);
7108 }
7109 }
7110
7111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7112 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7113 tw32(GRC_VCPU_EXT_CTRL,
7114 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7115 }
7116
7117 /* Manage gphy power for all CPMU absent PCIe devices. */
7118 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7119 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7120 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7121
7122 tw32(GRC_MISC_CFG, val);
7123
7124 /* restore 5701 hardware bug workaround write method */
7125 tp->write32 = write_op;
7126
7127 /* Unfortunately, we have to delay before the PCI read back.
7128 * Some 575X chips even will not respond to a PCI cfg access
7129 * when the reset command is given to the chip.
7130 *
7131 * How do these hardware designers expect things to work
7132 * properly if the PCI write is posted for a long period
7133 * of time? It is always necessary to have some method by
7134 * which a register read back can occur to push the write
7135 * out which does the reset.
7136 *
7137 * For most tg3 variants the trick below was working.
7138 * Ho hum...
7139 */
7140 udelay(120);
7141
7142 /* Flush PCI posted writes. The normal MMIO registers
7143 * are inaccessible at this time so this is the only
7144 * way to make this reliably (actually, this is no longer
7145 * the case, see above). I tried to use indirect
7146 * register read/write but this upset some 5701 variants.
7147 */
7148 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7149
7150 udelay(120);
7151
7152 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7153 u16 val16;
7154
7155 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7156 int i;
7157 u32 cfg_val;
7158
7159 /* Wait for link training to complete. */
7160 for (i = 0; i < 5000; i++)
7161 udelay(100);
7162
7163 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7164 pci_write_config_dword(tp->pdev, 0xc4,
7165 cfg_val | (1 << 15));
7166 }
7167
7168 /* Clear the "no snoop" and "relaxed ordering" bits. */
7169 pci_read_config_word(tp->pdev,
7170 tp->pcie_cap + PCI_EXP_DEVCTL,
7171 &val16);
7172 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7173 PCI_EXP_DEVCTL_NOSNOOP_EN);
7174 /*
7175 * Older PCIe devices only support the 128 byte
7176 * MPS setting. Enforce the restriction.
7177 */
7178 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7179 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7180 pci_write_config_word(tp->pdev,
7181 tp->pcie_cap + PCI_EXP_DEVCTL,
7182 val16);
7183
7184 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7185
7186 /* Clear error status */
7187 pci_write_config_word(tp->pdev,
7188 tp->pcie_cap + PCI_EXP_DEVSTA,
7189 PCI_EXP_DEVSTA_CED |
7190 PCI_EXP_DEVSTA_NFED |
7191 PCI_EXP_DEVSTA_FED |
7192 PCI_EXP_DEVSTA_URD);
7193 }
7194
7195 tg3_restore_pci_state(tp);
7196
7197 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7198
7199 val = 0;
7200 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7201 val = tr32(MEMARB_MODE);
7202 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7203
7204 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7205 tg3_stop_fw(tp);
7206 tw32(0x5000, 0x400);
7207 }
7208
7209 tw32(GRC_MODE, tp->grc_mode);
7210
7211 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7212 val = tr32(0xc4);
7213
7214 tw32(0xc4, val | (1 << 15));
7215 }
7216
7217 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7219 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7220 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7221 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7222 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7223 }
7224
7225 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7226 tp->mac_mode = MAC_MODE_APE_TX_EN |
7227 MAC_MODE_APE_RX_EN |
7228 MAC_MODE_TDE_ENABLE;
7229
7230 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7231 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7232 val = tp->mac_mode;
7233 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7234 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7235 val = tp->mac_mode;
7236 } else
7237 val = 0;
7238
7239 tw32_f(MAC_MODE, val);
7240 udelay(40);
7241
7242 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7243
7244 err = tg3_poll_fw(tp);
7245 if (err)
7246 return err;
7247
7248 tg3_mdio_start(tp);
7249
7250 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7251 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7252 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7253 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7254 val = tr32(0x7c00);
7255
7256 tw32(0x7c00, val | (1 << 25));
7257 }
7258
7259 /* Reprobe ASF enable state. */
7260 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7261 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7262 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7263 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7264 u32 nic_cfg;
7265
7266 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7267 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7268 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7269 tp->last_event_jiffies = jiffies;
7270 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7271 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7272 }
7273 }
7274
7275 return 0;
7276 }
7277
7278 /* tp->lock is held. */
7279 static void tg3_stop_fw(struct tg3 *tp)
7280 {
7281 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7282 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7283 /* Wait for RX cpu to ACK the previous event. */
7284 tg3_wait_for_event_ack(tp);
7285
7286 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7287
7288 tg3_generate_fw_event(tp);
7289
7290 /* Wait for RX cpu to ACK this event. */
7291 tg3_wait_for_event_ack(tp);
7292 }
7293 }
7294
7295 /* tp->lock is held. */
7296 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7297 {
7298 int err;
7299
7300 tg3_stop_fw(tp);
7301
7302 tg3_write_sig_pre_reset(tp, kind);
7303
7304 tg3_abort_hw(tp, silent);
7305 err = tg3_chip_reset(tp);
7306
7307 __tg3_set_mac_addr(tp, 0);
7308
7309 tg3_write_sig_legacy(tp, kind);
7310 tg3_write_sig_post_reset(tp, kind);
7311
7312 if (err)
7313 return err;
7314
7315 return 0;
7316 }
7317
7318 #define RX_CPU_SCRATCH_BASE 0x30000
7319 #define RX_CPU_SCRATCH_SIZE 0x04000
7320 #define TX_CPU_SCRATCH_BASE 0x34000
7321 #define TX_CPU_SCRATCH_SIZE 0x04000
7322
7323 /* tp->lock is held. */
7324 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7325 {
7326 int i;
7327
7328 BUG_ON(offset == TX_CPU_BASE &&
7329 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7330
7331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7332 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7333
7334 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7335 return 0;
7336 }
7337 if (offset == RX_CPU_BASE) {
7338 for (i = 0; i < 10000; i++) {
7339 tw32(offset + CPU_STATE, 0xffffffff);
7340 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7341 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7342 break;
7343 }
7344
7345 tw32(offset + CPU_STATE, 0xffffffff);
7346 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7347 udelay(10);
7348 } else {
7349 for (i = 0; i < 10000; i++) {
7350 tw32(offset + CPU_STATE, 0xffffffff);
7351 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7352 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7353 break;
7354 }
7355 }
7356
7357 if (i >= 10000) {
7358 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7359 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7360 return -ENODEV;
7361 }
7362
7363 /* Clear firmware's nvram arbitration. */
7364 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7365 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7366 return 0;
7367 }
7368
7369 struct fw_info {
7370 unsigned int fw_base;
7371 unsigned int fw_len;
7372 const __be32 *fw_data;
7373 };
7374
7375 /* tp->lock is held. */
7376 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7377 int cpu_scratch_size, struct fw_info *info)
7378 {
7379 int err, lock_err, i;
7380 void (*write_op)(struct tg3 *, u32, u32);
7381
7382 if (cpu_base == TX_CPU_BASE &&
7383 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7384 netdev_err(tp->dev,
7385 "%s: Trying to load TX cpu firmware which is 5705\n",
7386 __func__);
7387 return -EINVAL;
7388 }
7389
7390 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7391 write_op = tg3_write_mem;
7392 else
7393 write_op = tg3_write_indirect_reg32;
7394
7395 /* It is possible that bootcode is still loading at this point.
7396 * Get the nvram lock first before halting the cpu.
7397 */
7398 lock_err = tg3_nvram_lock(tp);
7399 err = tg3_halt_cpu(tp, cpu_base);
7400 if (!lock_err)
7401 tg3_nvram_unlock(tp);
7402 if (err)
7403 goto out;
7404
7405 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7406 write_op(tp, cpu_scratch_base + i, 0);
7407 tw32(cpu_base + CPU_STATE, 0xffffffff);
7408 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7409 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7410 write_op(tp, (cpu_scratch_base +
7411 (info->fw_base & 0xffff) +
7412 (i * sizeof(u32))),
7413 be32_to_cpu(info->fw_data[i]));
7414
7415 err = 0;
7416
7417 out:
7418 return err;
7419 }
7420
7421 /* tp->lock is held. */
7422 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7423 {
7424 struct fw_info info;
7425 const __be32 *fw_data;
7426 int err, i;
7427
7428 fw_data = (void *)tp->fw->data;
7429
7430 /* Firmware blob starts with version numbers, followed by
7431 start address and length. We are setting complete length.
7432 length = end_address_of_bss - start_address_of_text.
7433 Remainder is the blob to be loaded contiguously
7434 from start address. */
7435
7436 info.fw_base = be32_to_cpu(fw_data[1]);
7437 info.fw_len = tp->fw->size - 12;
7438 info.fw_data = &fw_data[3];
7439
7440 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7441 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7442 &info);
7443 if (err)
7444 return err;
7445
7446 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7447 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7448 &info);
7449 if (err)
7450 return err;
7451
7452 /* Now startup only the RX cpu. */
7453 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7454 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7455
7456 for (i = 0; i < 5; i++) {
7457 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7458 break;
7459 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7460 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7461 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7462 udelay(1000);
7463 }
7464 if (i >= 5) {
7465 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7466 "should be %08x\n", __func__,
7467 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7468 return -ENODEV;
7469 }
7470 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7471 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7472
7473 return 0;
7474 }
7475
7476 /* 5705 needs a special version of the TSO firmware. */
7477
7478 /* tp->lock is held. */
7479 static int tg3_load_tso_firmware(struct tg3 *tp)
7480 {
7481 struct fw_info info;
7482 const __be32 *fw_data;
7483 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7484 int err, i;
7485
7486 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7487 return 0;
7488
7489 fw_data = (void *)tp->fw->data;
7490
7491 /* Firmware blob starts with version numbers, followed by
7492 start address and length. We are setting complete length.
7493 length = end_address_of_bss - start_address_of_text.
7494 Remainder is the blob to be loaded contiguously
7495 from start address. */
7496
7497 info.fw_base = be32_to_cpu(fw_data[1]);
7498 cpu_scratch_size = tp->fw_len;
7499 info.fw_len = tp->fw->size - 12;
7500 info.fw_data = &fw_data[3];
7501
7502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7503 cpu_base = RX_CPU_BASE;
7504 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7505 } else {
7506 cpu_base = TX_CPU_BASE;
7507 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7508 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7509 }
7510
7511 err = tg3_load_firmware_cpu(tp, cpu_base,
7512 cpu_scratch_base, cpu_scratch_size,
7513 &info);
7514 if (err)
7515 return err;
7516
7517 /* Now startup the cpu. */
7518 tw32(cpu_base + CPU_STATE, 0xffffffff);
7519 tw32_f(cpu_base + CPU_PC, info.fw_base);
7520
7521 for (i = 0; i < 5; i++) {
7522 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7523 break;
7524 tw32(cpu_base + CPU_STATE, 0xffffffff);
7525 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7526 tw32_f(cpu_base + CPU_PC, info.fw_base);
7527 udelay(1000);
7528 }
7529 if (i >= 5) {
7530 netdev_err(tp->dev,
7531 "%s fails to set CPU PC, is %08x should be %08x\n",
7532 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7533 return -ENODEV;
7534 }
7535 tw32(cpu_base + CPU_STATE, 0xffffffff);
7536 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7537 return 0;
7538 }
7539
7540
7541 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7542 {
7543 struct tg3 *tp = netdev_priv(dev);
7544 struct sockaddr *addr = p;
7545 int err = 0, skip_mac_1 = 0;
7546
7547 if (!is_valid_ether_addr(addr->sa_data))
7548 return -EINVAL;
7549
7550 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7551
7552 if (!netif_running(dev))
7553 return 0;
7554
7555 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7556 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7557
7558 addr0_high = tr32(MAC_ADDR_0_HIGH);
7559 addr0_low = tr32(MAC_ADDR_0_LOW);
7560 addr1_high = tr32(MAC_ADDR_1_HIGH);
7561 addr1_low = tr32(MAC_ADDR_1_LOW);
7562
7563 /* Skip MAC addr 1 if ASF is using it. */
7564 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7565 !(addr1_high == 0 && addr1_low == 0))
7566 skip_mac_1 = 1;
7567 }
7568 spin_lock_bh(&tp->lock);
7569 __tg3_set_mac_addr(tp, skip_mac_1);
7570 spin_unlock_bh(&tp->lock);
7571
7572 return err;
7573 }
7574
7575 /* tp->lock is held. */
7576 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7577 dma_addr_t mapping, u32 maxlen_flags,
7578 u32 nic_addr)
7579 {
7580 tg3_write_mem(tp,
7581 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7582 ((u64) mapping >> 32));
7583 tg3_write_mem(tp,
7584 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7585 ((u64) mapping & 0xffffffff));
7586 tg3_write_mem(tp,
7587 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7588 maxlen_flags);
7589
7590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7591 tg3_write_mem(tp,
7592 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7593 nic_addr);
7594 }
7595
7596 static void __tg3_set_rx_mode(struct net_device *);
7597 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7598 {
7599 int i;
7600
7601 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7602 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7603 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7604 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7605 } else {
7606 tw32(HOSTCC_TXCOL_TICKS, 0);
7607 tw32(HOSTCC_TXMAX_FRAMES, 0);
7608 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7609 }
7610
7611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7612 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7613 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7614 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7615 } else {
7616 tw32(HOSTCC_RXCOL_TICKS, 0);
7617 tw32(HOSTCC_RXMAX_FRAMES, 0);
7618 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7619 }
7620
7621 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7622 u32 val = ec->stats_block_coalesce_usecs;
7623
7624 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7625 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7626
7627 if (!netif_carrier_ok(tp->dev))
7628 val = 0;
7629
7630 tw32(HOSTCC_STAT_COAL_TICKS, val);
7631 }
7632
7633 for (i = 0; i < tp->irq_cnt - 1; i++) {
7634 u32 reg;
7635
7636 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7637 tw32(reg, ec->rx_coalesce_usecs);
7638 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7639 tw32(reg, ec->rx_max_coalesced_frames);
7640 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7641 tw32(reg, ec->rx_max_coalesced_frames_irq);
7642
7643 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7644 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7645 tw32(reg, ec->tx_coalesce_usecs);
7646 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7647 tw32(reg, ec->tx_max_coalesced_frames);
7648 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7649 tw32(reg, ec->tx_max_coalesced_frames_irq);
7650 }
7651 }
7652
7653 for (; i < tp->irq_max - 1; i++) {
7654 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7655 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7656 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7657
7658 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7659 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7660 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7661 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7662 }
7663 }
7664 }
7665
7666 /* tp->lock is held. */
7667 static void tg3_rings_reset(struct tg3 *tp)
7668 {
7669 int i;
7670 u32 stblk, txrcb, rxrcb, limit;
7671 struct tg3_napi *tnapi = &tp->napi[0];
7672
7673 /* Disable all transmit rings but the first. */
7674 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7675 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7676 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7677 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7678 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7679 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7680 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7681 else
7682 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7683
7684 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7685 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7686 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7687 BDINFO_FLAGS_DISABLED);
7688
7689
7690 /* Disable all receive return rings but the first. */
7691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7692 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7693 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7694 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7695 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7696 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7697 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7698 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7699 else
7700 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7701
7702 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7703 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7704 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7705 BDINFO_FLAGS_DISABLED);
7706
7707 /* Disable interrupts */
7708 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7709
7710 /* Zero mailbox registers. */
7711 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7712 for (i = 1; i < tp->irq_max; i++) {
7713 tp->napi[i].tx_prod = 0;
7714 tp->napi[i].tx_cons = 0;
7715 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7716 tw32_mailbox(tp->napi[i].prodmbox, 0);
7717 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7718 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7719 }
7720 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7721 tw32_mailbox(tp->napi[0].prodmbox, 0);
7722 } else {
7723 tp->napi[0].tx_prod = 0;
7724 tp->napi[0].tx_cons = 0;
7725 tw32_mailbox(tp->napi[0].prodmbox, 0);
7726 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7727 }
7728
7729 /* Make sure the NIC-based send BD rings are disabled. */
7730 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7731 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7732 for (i = 0; i < 16; i++)
7733 tw32_tx_mbox(mbox + i * 8, 0);
7734 }
7735
7736 txrcb = NIC_SRAM_SEND_RCB;
7737 rxrcb = NIC_SRAM_RCV_RET_RCB;
7738
7739 /* Clear status block in ram. */
7740 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7741
7742 /* Set status block DMA address */
7743 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7744 ((u64) tnapi->status_mapping >> 32));
7745 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7746 ((u64) tnapi->status_mapping & 0xffffffff));
7747
7748 if (tnapi->tx_ring) {
7749 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7750 (TG3_TX_RING_SIZE <<
7751 BDINFO_FLAGS_MAXLEN_SHIFT),
7752 NIC_SRAM_TX_BUFFER_DESC);
7753 txrcb += TG3_BDINFO_SIZE;
7754 }
7755
7756 if (tnapi->rx_rcb) {
7757 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7758 (tp->rx_ret_ring_mask + 1) <<
7759 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7760 rxrcb += TG3_BDINFO_SIZE;
7761 }
7762
7763 stblk = HOSTCC_STATBLCK_RING1;
7764
7765 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7766 u64 mapping = (u64)tnapi->status_mapping;
7767 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7768 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7769
7770 /* Clear status block in ram. */
7771 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7772
7773 if (tnapi->tx_ring) {
7774 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7775 (TG3_TX_RING_SIZE <<
7776 BDINFO_FLAGS_MAXLEN_SHIFT),
7777 NIC_SRAM_TX_BUFFER_DESC);
7778 txrcb += TG3_BDINFO_SIZE;
7779 }
7780
7781 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7782 ((tp->rx_ret_ring_mask + 1) <<
7783 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7784
7785 stblk += 8;
7786 rxrcb += TG3_BDINFO_SIZE;
7787 }
7788 }
7789
7790 /* tp->lock is held. */
7791 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7792 {
7793 u32 val, rdmac_mode;
7794 int i, err, limit;
7795 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7796
7797 tg3_disable_ints(tp);
7798
7799 tg3_stop_fw(tp);
7800
7801 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7802
7803 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7804 tg3_abort_hw(tp, 1);
7805
7806 /* Enable MAC control of LPI */
7807 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7808 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7809 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7810 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7811
7812 tw32_f(TG3_CPMU_EEE_CTRL,
7813 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7814
7815 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7816 TG3_CPMU_EEEMD_LPI_IN_TX |
7817 TG3_CPMU_EEEMD_LPI_IN_RX |
7818 TG3_CPMU_EEEMD_EEE_ENABLE;
7819
7820 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7821 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7822
7823 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7824 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7825
7826 tw32_f(TG3_CPMU_EEE_MODE, val);
7827
7828 tw32_f(TG3_CPMU_EEE_DBTMR1,
7829 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7830 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7831
7832 tw32_f(TG3_CPMU_EEE_DBTMR2,
7833 TG3_CPMU_DBTMR2_APE_TX_2047US |
7834 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7835 }
7836
7837 if (reset_phy)
7838 tg3_phy_reset(tp);
7839
7840 err = tg3_chip_reset(tp);
7841 if (err)
7842 return err;
7843
7844 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7845
7846 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7847 val = tr32(TG3_CPMU_CTRL);
7848 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7849 tw32(TG3_CPMU_CTRL, val);
7850
7851 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7852 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7853 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7854 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7855
7856 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7857 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7858 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7859 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7860
7861 val = tr32(TG3_CPMU_HST_ACC);
7862 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7863 val |= CPMU_HST_ACC_MACCLK_6_25;
7864 tw32(TG3_CPMU_HST_ACC, val);
7865 }
7866
7867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7868 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7869 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7870 PCIE_PWR_MGMT_L1_THRESH_4MS;
7871 tw32(PCIE_PWR_MGMT_THRESH, val);
7872
7873 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7874 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7875
7876 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7877
7878 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7879 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7880 }
7881
7882 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7883 u32 grc_mode = tr32(GRC_MODE);
7884
7885 /* Access the lower 1K of PL PCIE block registers. */
7886 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7887 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7888
7889 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7890 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7891 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7892
7893 tw32(GRC_MODE, grc_mode);
7894 }
7895
7896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7897 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7898 u32 grc_mode = tr32(GRC_MODE);
7899
7900 /* Access the lower 1K of PL PCIE block registers. */
7901 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7902 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7903
7904 val = tr32(TG3_PCIE_TLDLPL_PORT +
7905 TG3_PCIE_PL_LO_PHYCTL5);
7906 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7907 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7908
7909 tw32(GRC_MODE, grc_mode);
7910 }
7911
7912 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7913 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7914 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7915 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7916 }
7917
7918 /* This works around an issue with Athlon chipsets on
7919 * B3 tigon3 silicon. This bit has no effect on any
7920 * other revision. But do not set this on PCI Express
7921 * chips and don't even touch the clocks if the CPMU is present.
7922 */
7923 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7924 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7925 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7926 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7927 }
7928
7929 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7930 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7931 val = tr32(TG3PCI_PCISTATE);
7932 val |= PCISTATE_RETRY_SAME_DMA;
7933 tw32(TG3PCI_PCISTATE, val);
7934 }
7935
7936 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7937 /* Allow reads and writes to the
7938 * APE register and memory space.
7939 */
7940 val = tr32(TG3PCI_PCISTATE);
7941 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7942 PCISTATE_ALLOW_APE_SHMEM_WR |
7943 PCISTATE_ALLOW_APE_PSPACE_WR;
7944 tw32(TG3PCI_PCISTATE, val);
7945 }
7946
7947 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7948 /* Enable some hw fixes. */
7949 val = tr32(TG3PCI_MSI_DATA);
7950 val |= (1 << 26) | (1 << 28) | (1 << 29);
7951 tw32(TG3PCI_MSI_DATA, val);
7952 }
7953
7954 /* Descriptor ring init may make accesses to the
7955 * NIC SRAM area to setup the TX descriptors, so we
7956 * can only do this after the hardware has been
7957 * successfully reset.
7958 */
7959 err = tg3_init_rings(tp);
7960 if (err)
7961 return err;
7962
7963 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7964 val = tr32(TG3PCI_DMA_RW_CTRL) &
7965 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7966 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7967 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7968 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7969 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7970 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7971 /* This value is determined during the probe time DMA
7972 * engine test, tg3_test_dma.
7973 */
7974 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7975 }
7976
7977 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7978 GRC_MODE_4X_NIC_SEND_RINGS |
7979 GRC_MODE_NO_TX_PHDR_CSUM |
7980 GRC_MODE_NO_RX_PHDR_CSUM);
7981 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7982
7983 /* Pseudo-header checksum is done by hardware logic and not
7984 * the offload processers, so make the chip do the pseudo-
7985 * header checksums on receive. For transmit it is more
7986 * convenient to do the pseudo-header checksum in software
7987 * as Linux does that on transmit for us in all cases.
7988 */
7989 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7990
7991 tw32(GRC_MODE,
7992 tp->grc_mode |
7993 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7994
7995 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7996 val = tr32(GRC_MISC_CFG);
7997 val &= ~0xff;
7998 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7999 tw32(GRC_MISC_CFG, val);
8000
8001 /* Initialize MBUF/DESC pool. */
8002 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8003 /* Do nothing. */
8004 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8005 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8007 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8008 else
8009 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8010 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8011 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8012 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8013 int fw_len;
8014
8015 fw_len = tp->fw_len;
8016 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8017 tw32(BUFMGR_MB_POOL_ADDR,
8018 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8019 tw32(BUFMGR_MB_POOL_SIZE,
8020 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8021 }
8022
8023 if (tp->dev->mtu <= ETH_DATA_LEN) {
8024 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8025 tp->bufmgr_config.mbuf_read_dma_low_water);
8026 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8027 tp->bufmgr_config.mbuf_mac_rx_low_water);
8028 tw32(BUFMGR_MB_HIGH_WATER,
8029 tp->bufmgr_config.mbuf_high_water);
8030 } else {
8031 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8032 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8033 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8034 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8035 tw32(BUFMGR_MB_HIGH_WATER,
8036 tp->bufmgr_config.mbuf_high_water_jumbo);
8037 }
8038 tw32(BUFMGR_DMA_LOW_WATER,
8039 tp->bufmgr_config.dma_low_water);
8040 tw32(BUFMGR_DMA_HIGH_WATER,
8041 tp->bufmgr_config.dma_high_water);
8042
8043 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8045 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8046 tw32(BUFMGR_MODE, val);
8047 for (i = 0; i < 2000; i++) {
8048 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8049 break;
8050 udelay(10);
8051 }
8052 if (i >= 2000) {
8053 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8054 return -ENODEV;
8055 }
8056
8057 /* Setup replenish threshold. */
8058 val = tp->rx_pending / 8;
8059 if (val == 0)
8060 val = 1;
8061 else if (val > tp->rx_std_max_post)
8062 val = tp->rx_std_max_post;
8063 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8064 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8065 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8066
8067 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8068 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8069 }
8070
8071 tw32(RCVBDI_STD_THRESH, val);
8072
8073 /* Initialize TG3_BDINFO's at:
8074 * RCVDBDI_STD_BD: standard eth size rx ring
8075 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8076 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8077 *
8078 * like so:
8079 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8080 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8081 * ring attribute flags
8082 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8083 *
8084 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8085 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8086 *
8087 * The size of each ring is fixed in the firmware, but the location is
8088 * configurable.
8089 */
8090 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8091 ((u64) tpr->rx_std_mapping >> 32));
8092 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8093 ((u64) tpr->rx_std_mapping & 0xffffffff));
8094 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8095 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8096 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8097 NIC_SRAM_RX_BUFFER_DESC);
8098
8099 /* Disable the mini ring */
8100 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8101 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8102 BDINFO_FLAGS_DISABLED);
8103
8104 /* Program the jumbo buffer descriptor ring control
8105 * blocks on those devices that have them.
8106 */
8107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8108 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8109 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8110 /* Setup replenish threshold. */
8111 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8112
8113 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8114 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8115 ((u64) tpr->rx_jmb_mapping >> 32));
8116 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8117 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8118 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8119 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8120 BDINFO_FLAGS_USE_EXT_RECV);
8121 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8123 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8124 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8125 } else {
8126 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8127 BDINFO_FLAGS_DISABLED);
8128 }
8129
8130 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8131 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8132 val = RX_STD_MAX_SIZE_5705;
8133 else
8134 val = RX_STD_MAX_SIZE_5717;
8135 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8136 val |= (TG3_RX_STD_DMA_SZ << 2);
8137 } else
8138 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8139 } else
8140 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8141
8142 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8143
8144 tpr->rx_std_prod_idx = tp->rx_pending;
8145 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8146
8147 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8148 tp->rx_jumbo_pending : 0;
8149 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8150
8151 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8152 tw32(STD_REPLENISH_LWM, 32);
8153 tw32(JMB_REPLENISH_LWM, 16);
8154 }
8155
8156 tg3_rings_reset(tp);
8157
8158 /* Initialize MAC address and backoff seed. */
8159 __tg3_set_mac_addr(tp, 0);
8160
8161 /* MTU + ethernet header + FCS + optional VLAN tag */
8162 tw32(MAC_RX_MTU_SIZE,
8163 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8164
8165 /* The slot time is changed by tg3_setup_phy if we
8166 * run at gigabit with half duplex.
8167 */
8168 tw32(MAC_TX_LENGTHS,
8169 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8170 (6 << TX_LENGTHS_IPG_SHIFT) |
8171 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8172
8173 /* Receive rules. */
8174 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8175 tw32(RCVLPC_CONFIG, 0x0181);
8176
8177 /* Calculate RDMAC_MODE setting early, we need it to determine
8178 * the RCVLPC_STATE_ENABLE mask.
8179 */
8180 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8181 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8182 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8183 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8184 RDMAC_MODE_LNGREAD_ENAB);
8185
8186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8187 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8188
8189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8192 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8193 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8194 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8195
8196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8197 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8198 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8200 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8201 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8202 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8203 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8204 }
8205 }
8206
8207 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8208 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8209
8210 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8211 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8212
8213 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8214 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8215 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8216 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8217
8218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8222 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8223 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8225 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8226 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8227 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8228 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8229 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8230 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8231 }
8232 tw32(TG3_RDMA_RSRVCTRL_REG,
8233 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8234 }
8235
8236 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8237 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8238 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8239 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8240 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8241 }
8242
8243 /* Receive/send statistics. */
8244 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8245 val = tr32(RCVLPC_STATS_ENABLE);
8246 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8247 tw32(RCVLPC_STATS_ENABLE, val);
8248 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8249 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8250 val = tr32(RCVLPC_STATS_ENABLE);
8251 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8252 tw32(RCVLPC_STATS_ENABLE, val);
8253 } else {
8254 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8255 }
8256 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8257 tw32(SNDDATAI_STATSENAB, 0xffffff);
8258 tw32(SNDDATAI_STATSCTRL,
8259 (SNDDATAI_SCTRL_ENABLE |
8260 SNDDATAI_SCTRL_FASTUPD));
8261
8262 /* Setup host coalescing engine. */
8263 tw32(HOSTCC_MODE, 0);
8264 for (i = 0; i < 2000; i++) {
8265 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8266 break;
8267 udelay(10);
8268 }
8269
8270 __tg3_set_coalesce(tp, &tp->coal);
8271
8272 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8273 /* Status/statistics block address. See tg3_timer,
8274 * the tg3_periodic_fetch_stats call there, and
8275 * tg3_get_stats to see how this works for 5705/5750 chips.
8276 */
8277 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8278 ((u64) tp->stats_mapping >> 32));
8279 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8280 ((u64) tp->stats_mapping & 0xffffffff));
8281 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8282
8283 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8284
8285 /* Clear statistics and status block memory areas */
8286 for (i = NIC_SRAM_STATS_BLK;
8287 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8288 i += sizeof(u32)) {
8289 tg3_write_mem(tp, i, 0);
8290 udelay(40);
8291 }
8292 }
8293
8294 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8295
8296 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8297 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8298 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8299 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8300
8301 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8302 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8303 /* reset to prevent losing 1st rx packet intermittently */
8304 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8305 udelay(10);
8306 }
8307
8308 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8309 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8310 else
8311 tp->mac_mode = 0;
8312 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8313 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8314 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8315 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8316 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8317 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8318 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8319 udelay(40);
8320
8321 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8322 * If TG3_FLG2_IS_NIC is zero, we should read the
8323 * register to preserve the GPIO settings for LOMs. The GPIOs,
8324 * whether used as inputs or outputs, are set by boot code after
8325 * reset.
8326 */
8327 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8328 u32 gpio_mask;
8329
8330 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8331 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8332 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8333
8334 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8335 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8336 GRC_LCLCTRL_GPIO_OUTPUT3;
8337
8338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8339 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8340
8341 tp->grc_local_ctrl &= ~gpio_mask;
8342 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8343
8344 /* GPIO1 must be driven high for eeprom write protect */
8345 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8346 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8347 GRC_LCLCTRL_GPIO_OUTPUT1);
8348 }
8349 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8350 udelay(100);
8351
8352 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8353 tp->irq_cnt > 1) {
8354 val = tr32(MSGINT_MODE);
8355 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8356 tw32(MSGINT_MODE, val);
8357 }
8358
8359 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8360 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8361 udelay(40);
8362 }
8363
8364 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8365 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8366 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8367 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8368 WDMAC_MODE_LNGREAD_ENAB);
8369
8370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8371 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8372 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8373 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8374 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8375 /* nothing */
8376 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8377 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8378 val |= WDMAC_MODE_RX_ACCEL;
8379 }
8380 }
8381
8382 /* Enable host coalescing bug fix */
8383 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8384 val |= WDMAC_MODE_STATUS_TAG_FIX;
8385
8386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8387 val |= WDMAC_MODE_BURST_ALL_DATA;
8388
8389 tw32_f(WDMAC_MODE, val);
8390 udelay(40);
8391
8392 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8393 u16 pcix_cmd;
8394
8395 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8396 &pcix_cmd);
8397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8398 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8399 pcix_cmd |= PCI_X_CMD_READ_2K;
8400 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8401 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8402 pcix_cmd |= PCI_X_CMD_READ_2K;
8403 }
8404 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8405 pcix_cmd);
8406 }
8407
8408 tw32_f(RDMAC_MODE, rdmac_mode);
8409 udelay(40);
8410
8411 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8412 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8413 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8414
8415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8416 tw32(SNDDATAC_MODE,
8417 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8418 else
8419 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8420
8421 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8422 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8423 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8426 val |= RCVDBDI_MODE_LRG_RING_SZ;
8427 tw32(RCVDBDI_MODE, val);
8428 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8429 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8430 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8431 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8432 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8433 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8434 tw32(SNDBDI_MODE, val);
8435 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8436
8437 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8438 err = tg3_load_5701_a0_firmware_fix(tp);
8439 if (err)
8440 return err;
8441 }
8442
8443 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8444 err = tg3_load_tso_firmware(tp);
8445 if (err)
8446 return err;
8447 }
8448
8449 tp->tx_mode = TX_MODE_ENABLE;
8450 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8452 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8453 tw32_f(MAC_TX_MODE, tp->tx_mode);
8454 udelay(100);
8455
8456 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8457 u32 reg = MAC_RSS_INDIR_TBL_0;
8458 u8 *ent = (u8 *)&val;
8459
8460 /* Setup the indirection table */
8461 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8462 int idx = i % sizeof(val);
8463
8464 ent[idx] = i % (tp->irq_cnt - 1);
8465 if (idx == sizeof(val) - 1) {
8466 tw32(reg, val);
8467 reg += 4;
8468 }
8469 }
8470
8471 /* Setup the "secret" hash key. */
8472 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8473 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8474 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8475 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8476 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8477 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8478 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8479 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8480 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8481 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8482 }
8483
8484 tp->rx_mode = RX_MODE_ENABLE;
8485 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8486 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8487
8488 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8489 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8490 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8491 RX_MODE_RSS_IPV6_HASH_EN |
8492 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8493 RX_MODE_RSS_IPV4_HASH_EN |
8494 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8495
8496 tw32_f(MAC_RX_MODE, tp->rx_mode);
8497 udelay(10);
8498
8499 tw32(MAC_LED_CTRL, tp->led_ctrl);
8500
8501 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8502 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8503 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8504 udelay(10);
8505 }
8506 tw32_f(MAC_RX_MODE, tp->rx_mode);
8507 udelay(10);
8508
8509 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8510 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8511 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8512 /* Set drive transmission level to 1.2V */
8513 /* only if the signal pre-emphasis bit is not set */
8514 val = tr32(MAC_SERDES_CFG);
8515 val &= 0xfffff000;
8516 val |= 0x880;
8517 tw32(MAC_SERDES_CFG, val);
8518 }
8519 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8520 tw32(MAC_SERDES_CFG, 0x616000);
8521 }
8522
8523 /* Prevent chip from dropping frames when flow control
8524 * is enabled.
8525 */
8526 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8527 val = 1;
8528 else
8529 val = 2;
8530 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8531
8532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8533 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8534 /* Use hardware link auto-negotiation */
8535 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8536 }
8537
8538 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8539 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8540 u32 tmp;
8541
8542 tmp = tr32(SERDES_RX_CTRL);
8543 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8544 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8545 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8546 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8547 }
8548
8549 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8550 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8551 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8552 tp->link_config.speed = tp->link_config.orig_speed;
8553 tp->link_config.duplex = tp->link_config.orig_duplex;
8554 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8555 }
8556
8557 err = tg3_setup_phy(tp, 0);
8558 if (err)
8559 return err;
8560
8561 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8562 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8563 u32 tmp;
8564
8565 /* Clear CRC stats. */
8566 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8567 tg3_writephy(tp, MII_TG3_TEST1,
8568 tmp | MII_TG3_TEST1_CRC_EN);
8569 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8570 }
8571 }
8572 }
8573
8574 __tg3_set_rx_mode(tp->dev);
8575
8576 /* Initialize receive rules. */
8577 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8578 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8579 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8580 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8581
8582 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8583 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8584 limit = 8;
8585 else
8586 limit = 16;
8587 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8588 limit -= 4;
8589 switch (limit) {
8590 case 16:
8591 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8592 case 15:
8593 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8594 case 14:
8595 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8596 case 13:
8597 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8598 case 12:
8599 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8600 case 11:
8601 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8602 case 10:
8603 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8604 case 9:
8605 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8606 case 8:
8607 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8608 case 7:
8609 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8610 case 6:
8611 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8612 case 5:
8613 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8614 case 4:
8615 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8616 case 3:
8617 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8618 case 2:
8619 case 1:
8620
8621 default:
8622 break;
8623 }
8624
8625 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8626 /* Write our heartbeat update interval to APE. */
8627 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8628 APE_HOST_HEARTBEAT_INT_DISABLE);
8629
8630 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8631
8632 return 0;
8633 }
8634
8635 /* Called at device open time to get the chip ready for
8636 * packet processing. Invoked with tp->lock held.
8637 */
8638 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8639 {
8640 tg3_switch_clocks(tp);
8641
8642 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8643
8644 return tg3_reset_hw(tp, reset_phy);
8645 }
8646
8647 #define TG3_STAT_ADD32(PSTAT, REG) \
8648 do { u32 __val = tr32(REG); \
8649 (PSTAT)->low += __val; \
8650 if ((PSTAT)->low < __val) \
8651 (PSTAT)->high += 1; \
8652 } while (0)
8653
8654 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8655 {
8656 struct tg3_hw_stats *sp = tp->hw_stats;
8657
8658 if (!netif_carrier_ok(tp->dev))
8659 return;
8660
8661 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8662 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8663 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8664 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8665 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8666 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8667 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8668 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8669 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8670 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8671 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8672 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8673 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8674
8675 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8676 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8677 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8678 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8679 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8680 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8681 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8682 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8683 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8684 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8685 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8686 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8687 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8688 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8689
8690 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8691 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8692 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8693 }
8694
8695 static void tg3_timer(unsigned long __opaque)
8696 {
8697 struct tg3 *tp = (struct tg3 *) __opaque;
8698
8699 if (tp->irq_sync)
8700 goto restart_timer;
8701
8702 spin_lock(&tp->lock);
8703
8704 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8705 /* All of this garbage is because when using non-tagged
8706 * IRQ status the mailbox/status_block protocol the chip
8707 * uses with the cpu is race prone.
8708 */
8709 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8710 tw32(GRC_LOCAL_CTRL,
8711 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8712 } else {
8713 tw32(HOSTCC_MODE, tp->coalesce_mode |
8714 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8715 }
8716
8717 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8718 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8719 spin_unlock(&tp->lock);
8720 schedule_work(&tp->reset_task);
8721 return;
8722 }
8723 }
8724
8725 /* This part only runs once per second. */
8726 if (!--tp->timer_counter) {
8727 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8728 tg3_periodic_fetch_stats(tp);
8729
8730 if (tp->setlpicnt && !--tp->setlpicnt) {
8731 u32 val = tr32(TG3_CPMU_EEE_MODE);
8732 tw32(TG3_CPMU_EEE_MODE,
8733 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8734 }
8735
8736 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8737 u32 mac_stat;
8738 int phy_event;
8739
8740 mac_stat = tr32(MAC_STATUS);
8741
8742 phy_event = 0;
8743 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8744 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8745 phy_event = 1;
8746 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8747 phy_event = 1;
8748
8749 if (phy_event)
8750 tg3_setup_phy(tp, 0);
8751 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8752 u32 mac_stat = tr32(MAC_STATUS);
8753 int need_setup = 0;
8754
8755 if (netif_carrier_ok(tp->dev) &&
8756 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8757 need_setup = 1;
8758 }
8759 if (!netif_carrier_ok(tp->dev) &&
8760 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8761 MAC_STATUS_SIGNAL_DET))) {
8762 need_setup = 1;
8763 }
8764 if (need_setup) {
8765 if (!tp->serdes_counter) {
8766 tw32_f(MAC_MODE,
8767 (tp->mac_mode &
8768 ~MAC_MODE_PORT_MODE_MASK));
8769 udelay(40);
8770 tw32_f(MAC_MODE, tp->mac_mode);
8771 udelay(40);
8772 }
8773 tg3_setup_phy(tp, 0);
8774 }
8775 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8776 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8777 tg3_serdes_parallel_detect(tp);
8778 }
8779
8780 tp->timer_counter = tp->timer_multiplier;
8781 }
8782
8783 /* Heartbeat is only sent once every 2 seconds.
8784 *
8785 * The heartbeat is to tell the ASF firmware that the host
8786 * driver is still alive. In the event that the OS crashes,
8787 * ASF needs to reset the hardware to free up the FIFO space
8788 * that may be filled with rx packets destined for the host.
8789 * If the FIFO is full, ASF will no longer function properly.
8790 *
8791 * Unintended resets have been reported on real time kernels
8792 * where the timer doesn't run on time. Netpoll will also have
8793 * same problem.
8794 *
8795 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8796 * to check the ring condition when the heartbeat is expiring
8797 * before doing the reset. This will prevent most unintended
8798 * resets.
8799 */
8800 if (!--tp->asf_counter) {
8801 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8802 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8803 tg3_wait_for_event_ack(tp);
8804
8805 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8806 FWCMD_NICDRV_ALIVE3);
8807 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8808 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8809 TG3_FW_UPDATE_TIMEOUT_SEC);
8810
8811 tg3_generate_fw_event(tp);
8812 }
8813 tp->asf_counter = tp->asf_multiplier;
8814 }
8815
8816 spin_unlock(&tp->lock);
8817
8818 restart_timer:
8819 tp->timer.expires = jiffies + tp->timer_offset;
8820 add_timer(&tp->timer);
8821 }
8822
8823 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8824 {
8825 irq_handler_t fn;
8826 unsigned long flags;
8827 char *name;
8828 struct tg3_napi *tnapi = &tp->napi[irq_num];
8829
8830 if (tp->irq_cnt == 1)
8831 name = tp->dev->name;
8832 else {
8833 name = &tnapi->irq_lbl[0];
8834 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8835 name[IFNAMSIZ-1] = 0;
8836 }
8837
8838 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8839 fn = tg3_msi;
8840 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8841 fn = tg3_msi_1shot;
8842 flags = 0;
8843 } else {
8844 fn = tg3_interrupt;
8845 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8846 fn = tg3_interrupt_tagged;
8847 flags = IRQF_SHARED;
8848 }
8849
8850 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8851 }
8852
8853 static int tg3_test_interrupt(struct tg3 *tp)
8854 {
8855 struct tg3_napi *tnapi = &tp->napi[0];
8856 struct net_device *dev = tp->dev;
8857 int err, i, intr_ok = 0;
8858 u32 val;
8859
8860 if (!netif_running(dev))
8861 return -ENODEV;
8862
8863 tg3_disable_ints(tp);
8864
8865 free_irq(tnapi->irq_vec, tnapi);
8866
8867 /*
8868 * Turn off MSI one shot mode. Otherwise this test has no
8869 * observable way to know whether the interrupt was delivered.
8870 */
8871 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8872 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8873 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8874 tw32(MSGINT_MODE, val);
8875 }
8876
8877 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8878 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8879 if (err)
8880 return err;
8881
8882 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8883 tg3_enable_ints(tp);
8884
8885 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8886 tnapi->coal_now);
8887
8888 for (i = 0; i < 5; i++) {
8889 u32 int_mbox, misc_host_ctrl;
8890
8891 int_mbox = tr32_mailbox(tnapi->int_mbox);
8892 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8893
8894 if ((int_mbox != 0) ||
8895 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8896 intr_ok = 1;
8897 break;
8898 }
8899
8900 msleep(10);
8901 }
8902
8903 tg3_disable_ints(tp);
8904
8905 free_irq(tnapi->irq_vec, tnapi);
8906
8907 err = tg3_request_irq(tp, 0);
8908
8909 if (err)
8910 return err;
8911
8912 if (intr_ok) {
8913 /* Reenable MSI one shot mode. */
8914 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8915 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8916 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8917 tw32(MSGINT_MODE, val);
8918 }
8919 return 0;
8920 }
8921
8922 return -EIO;
8923 }
8924
8925 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8926 * successfully restored
8927 */
8928 static int tg3_test_msi(struct tg3 *tp)
8929 {
8930 int err;
8931 u16 pci_cmd;
8932
8933 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8934 return 0;
8935
8936 /* Turn off SERR reporting in case MSI terminates with Master
8937 * Abort.
8938 */
8939 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8940 pci_write_config_word(tp->pdev, PCI_COMMAND,
8941 pci_cmd & ~PCI_COMMAND_SERR);
8942
8943 err = tg3_test_interrupt(tp);
8944
8945 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8946
8947 if (!err)
8948 return 0;
8949
8950 /* other failures */
8951 if (err != -EIO)
8952 return err;
8953
8954 /* MSI test failed, go back to INTx mode */
8955 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8956 "to INTx mode. Please report this failure to the PCI "
8957 "maintainer and include system chipset information\n");
8958
8959 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8960
8961 pci_disable_msi(tp->pdev);
8962
8963 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8964 tp->napi[0].irq_vec = tp->pdev->irq;
8965
8966 err = tg3_request_irq(tp, 0);
8967 if (err)
8968 return err;
8969
8970 /* Need to reset the chip because the MSI cycle may have terminated
8971 * with Master Abort.
8972 */
8973 tg3_full_lock(tp, 1);
8974
8975 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8976 err = tg3_init_hw(tp, 1);
8977
8978 tg3_full_unlock(tp);
8979
8980 if (err)
8981 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8982
8983 return err;
8984 }
8985
8986 static int tg3_request_firmware(struct tg3 *tp)
8987 {
8988 const __be32 *fw_data;
8989
8990 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8991 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8992 tp->fw_needed);
8993 return -ENOENT;
8994 }
8995
8996 fw_data = (void *)tp->fw->data;
8997
8998 /* Firmware blob starts with version numbers, followed by
8999 * start address and _full_ length including BSS sections
9000 * (which must be longer than the actual data, of course
9001 */
9002
9003 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9004 if (tp->fw_len < (tp->fw->size - 12)) {
9005 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9006 tp->fw_len, tp->fw_needed);
9007 release_firmware(tp->fw);
9008 tp->fw = NULL;
9009 return -EINVAL;
9010 }
9011
9012 /* We no longer need firmware; we have it. */
9013 tp->fw_needed = NULL;
9014 return 0;
9015 }
9016
9017 static bool tg3_enable_msix(struct tg3 *tp)
9018 {
9019 int i, rc, cpus = num_online_cpus();
9020 struct msix_entry msix_ent[tp->irq_max];
9021
9022 if (cpus == 1)
9023 /* Just fallback to the simpler MSI mode. */
9024 return false;
9025
9026 /*
9027 * We want as many rx rings enabled as there are cpus.
9028 * The first MSIX vector only deals with link interrupts, etc,
9029 * so we add one to the number of vectors we are requesting.
9030 */
9031 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9032
9033 for (i = 0; i < tp->irq_max; i++) {
9034 msix_ent[i].entry = i;
9035 msix_ent[i].vector = 0;
9036 }
9037
9038 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9039 if (rc < 0) {
9040 return false;
9041 } else if (rc != 0) {
9042 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9043 return false;
9044 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9045 tp->irq_cnt, rc);
9046 tp->irq_cnt = rc;
9047 }
9048
9049 for (i = 0; i < tp->irq_max; i++)
9050 tp->napi[i].irq_vec = msix_ent[i].vector;
9051
9052 netif_set_real_num_tx_queues(tp->dev, 1);
9053 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9054 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9055 pci_disable_msix(tp->pdev);
9056 return false;
9057 }
9058
9059 if (tp->irq_cnt > 1) {
9060 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9061 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9062 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9063 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9064 }
9065 }
9066
9067 return true;
9068 }
9069
9070 static void tg3_ints_init(struct tg3 *tp)
9071 {
9072 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9073 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9074 /* All MSI supporting chips should support tagged
9075 * status. Assert that this is the case.
9076 */
9077 netdev_warn(tp->dev,
9078 "MSI without TAGGED_STATUS? Not using MSI\n");
9079 goto defcfg;
9080 }
9081
9082 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9083 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9084 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9085 pci_enable_msi(tp->pdev) == 0)
9086 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9087
9088 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9089 u32 msi_mode = tr32(MSGINT_MODE);
9090 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9091 tp->irq_cnt > 1)
9092 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9093 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9094 }
9095 defcfg:
9096 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9097 tp->irq_cnt = 1;
9098 tp->napi[0].irq_vec = tp->pdev->irq;
9099 netif_set_real_num_tx_queues(tp->dev, 1);
9100 netif_set_real_num_rx_queues(tp->dev, 1);
9101 }
9102 }
9103
9104 static void tg3_ints_fini(struct tg3 *tp)
9105 {
9106 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9107 pci_disable_msix(tp->pdev);
9108 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9109 pci_disable_msi(tp->pdev);
9110 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9111 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9112 }
9113
9114 static int tg3_open(struct net_device *dev)
9115 {
9116 struct tg3 *tp = netdev_priv(dev);
9117 int i, err;
9118
9119 if (tp->fw_needed) {
9120 err = tg3_request_firmware(tp);
9121 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9122 if (err)
9123 return err;
9124 } else if (err) {
9125 netdev_warn(tp->dev, "TSO capability disabled\n");
9126 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9127 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9128 netdev_notice(tp->dev, "TSO capability restored\n");
9129 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9130 }
9131 }
9132
9133 netif_carrier_off(tp->dev);
9134
9135 err = tg3_power_up(tp);
9136 if (err)
9137 return err;
9138
9139 tg3_full_lock(tp, 0);
9140
9141 tg3_disable_ints(tp);
9142 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9143
9144 tg3_full_unlock(tp);
9145
9146 /*
9147 * Setup interrupts first so we know how
9148 * many NAPI resources to allocate
9149 */
9150 tg3_ints_init(tp);
9151
9152 /* The placement of this call is tied
9153 * to the setup and use of Host TX descriptors.
9154 */
9155 err = tg3_alloc_consistent(tp);
9156 if (err)
9157 goto err_out1;
9158
9159 tg3_napi_init(tp);
9160
9161 tg3_napi_enable(tp);
9162
9163 for (i = 0; i < tp->irq_cnt; i++) {
9164 struct tg3_napi *tnapi = &tp->napi[i];
9165 err = tg3_request_irq(tp, i);
9166 if (err) {
9167 for (i--; i >= 0; i--)
9168 free_irq(tnapi->irq_vec, tnapi);
9169 break;
9170 }
9171 }
9172
9173 if (err)
9174 goto err_out2;
9175
9176 tg3_full_lock(tp, 0);
9177
9178 err = tg3_init_hw(tp, 1);
9179 if (err) {
9180 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9181 tg3_free_rings(tp);
9182 } else {
9183 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9184 tp->timer_offset = HZ;
9185 else
9186 tp->timer_offset = HZ / 10;
9187
9188 BUG_ON(tp->timer_offset > HZ);
9189 tp->timer_counter = tp->timer_multiplier =
9190 (HZ / tp->timer_offset);
9191 tp->asf_counter = tp->asf_multiplier =
9192 ((HZ / tp->timer_offset) * 2);
9193
9194 init_timer(&tp->timer);
9195 tp->timer.expires = jiffies + tp->timer_offset;
9196 tp->timer.data = (unsigned long) tp;
9197 tp->timer.function = tg3_timer;
9198 }
9199
9200 tg3_full_unlock(tp);
9201
9202 if (err)
9203 goto err_out3;
9204
9205 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9206 err = tg3_test_msi(tp);
9207
9208 if (err) {
9209 tg3_full_lock(tp, 0);
9210 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9211 tg3_free_rings(tp);
9212 tg3_full_unlock(tp);
9213
9214 goto err_out2;
9215 }
9216
9217 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9218 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9219 u32 val = tr32(PCIE_TRANSACTION_CFG);
9220
9221 tw32(PCIE_TRANSACTION_CFG,
9222 val | PCIE_TRANS_CFG_1SHOT_MSI);
9223 }
9224 }
9225
9226 tg3_phy_start(tp);
9227
9228 tg3_full_lock(tp, 0);
9229
9230 add_timer(&tp->timer);
9231 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9232 tg3_enable_ints(tp);
9233
9234 tg3_full_unlock(tp);
9235
9236 netif_tx_start_all_queues(dev);
9237
9238 return 0;
9239
9240 err_out3:
9241 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9242 struct tg3_napi *tnapi = &tp->napi[i];
9243 free_irq(tnapi->irq_vec, tnapi);
9244 }
9245
9246 err_out2:
9247 tg3_napi_disable(tp);
9248 tg3_napi_fini(tp);
9249 tg3_free_consistent(tp);
9250
9251 err_out1:
9252 tg3_ints_fini(tp);
9253 return err;
9254 }
9255
9256 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9257 struct rtnl_link_stats64 *);
9258 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9259
9260 static int tg3_close(struct net_device *dev)
9261 {
9262 int i;
9263 struct tg3 *tp = netdev_priv(dev);
9264
9265 tg3_napi_disable(tp);
9266 cancel_work_sync(&tp->reset_task);
9267
9268 netif_tx_stop_all_queues(dev);
9269
9270 del_timer_sync(&tp->timer);
9271
9272 tg3_phy_stop(tp);
9273
9274 tg3_full_lock(tp, 1);
9275
9276 tg3_disable_ints(tp);
9277
9278 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9279 tg3_free_rings(tp);
9280 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9281
9282 tg3_full_unlock(tp);
9283
9284 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9285 struct tg3_napi *tnapi = &tp->napi[i];
9286 free_irq(tnapi->irq_vec, tnapi);
9287 }
9288
9289 tg3_ints_fini(tp);
9290
9291 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9292
9293 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9294 sizeof(tp->estats_prev));
9295
9296 tg3_napi_fini(tp);
9297
9298 tg3_free_consistent(tp);
9299
9300 tg3_power_down(tp);
9301
9302 netif_carrier_off(tp->dev);
9303
9304 return 0;
9305 }
9306
9307 static inline u64 get_stat64(tg3_stat64_t *val)
9308 {
9309 return ((u64)val->high << 32) | ((u64)val->low);
9310 }
9311
9312 static u64 calc_crc_errors(struct tg3 *tp)
9313 {
9314 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9315
9316 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9317 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9319 u32 val;
9320
9321 spin_lock_bh(&tp->lock);
9322 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9323 tg3_writephy(tp, MII_TG3_TEST1,
9324 val | MII_TG3_TEST1_CRC_EN);
9325 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9326 } else
9327 val = 0;
9328 spin_unlock_bh(&tp->lock);
9329
9330 tp->phy_crc_errors += val;
9331
9332 return tp->phy_crc_errors;
9333 }
9334
9335 return get_stat64(&hw_stats->rx_fcs_errors);
9336 }
9337
9338 #define ESTAT_ADD(member) \
9339 estats->member = old_estats->member + \
9340 get_stat64(&hw_stats->member)
9341
9342 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9343 {
9344 struct tg3_ethtool_stats *estats = &tp->estats;
9345 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9346 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9347
9348 if (!hw_stats)
9349 return old_estats;
9350
9351 ESTAT_ADD(rx_octets);
9352 ESTAT_ADD(rx_fragments);
9353 ESTAT_ADD(rx_ucast_packets);
9354 ESTAT_ADD(rx_mcast_packets);
9355 ESTAT_ADD(rx_bcast_packets);
9356 ESTAT_ADD(rx_fcs_errors);
9357 ESTAT_ADD(rx_align_errors);
9358 ESTAT_ADD(rx_xon_pause_rcvd);
9359 ESTAT_ADD(rx_xoff_pause_rcvd);
9360 ESTAT_ADD(rx_mac_ctrl_rcvd);
9361 ESTAT_ADD(rx_xoff_entered);
9362 ESTAT_ADD(rx_frame_too_long_errors);
9363 ESTAT_ADD(rx_jabbers);
9364 ESTAT_ADD(rx_undersize_packets);
9365 ESTAT_ADD(rx_in_length_errors);
9366 ESTAT_ADD(rx_out_length_errors);
9367 ESTAT_ADD(rx_64_or_less_octet_packets);
9368 ESTAT_ADD(rx_65_to_127_octet_packets);
9369 ESTAT_ADD(rx_128_to_255_octet_packets);
9370 ESTAT_ADD(rx_256_to_511_octet_packets);
9371 ESTAT_ADD(rx_512_to_1023_octet_packets);
9372 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9373 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9374 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9375 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9376 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9377
9378 ESTAT_ADD(tx_octets);
9379 ESTAT_ADD(tx_collisions);
9380 ESTAT_ADD(tx_xon_sent);
9381 ESTAT_ADD(tx_xoff_sent);
9382 ESTAT_ADD(tx_flow_control);
9383 ESTAT_ADD(tx_mac_errors);
9384 ESTAT_ADD(tx_single_collisions);
9385 ESTAT_ADD(tx_mult_collisions);
9386 ESTAT_ADD(tx_deferred);
9387 ESTAT_ADD(tx_excessive_collisions);
9388 ESTAT_ADD(tx_late_collisions);
9389 ESTAT_ADD(tx_collide_2times);
9390 ESTAT_ADD(tx_collide_3times);
9391 ESTAT_ADD(tx_collide_4times);
9392 ESTAT_ADD(tx_collide_5times);
9393 ESTAT_ADD(tx_collide_6times);
9394 ESTAT_ADD(tx_collide_7times);
9395 ESTAT_ADD(tx_collide_8times);
9396 ESTAT_ADD(tx_collide_9times);
9397 ESTAT_ADD(tx_collide_10times);
9398 ESTAT_ADD(tx_collide_11times);
9399 ESTAT_ADD(tx_collide_12times);
9400 ESTAT_ADD(tx_collide_13times);
9401 ESTAT_ADD(tx_collide_14times);
9402 ESTAT_ADD(tx_collide_15times);
9403 ESTAT_ADD(tx_ucast_packets);
9404 ESTAT_ADD(tx_mcast_packets);
9405 ESTAT_ADD(tx_bcast_packets);
9406 ESTAT_ADD(tx_carrier_sense_errors);
9407 ESTAT_ADD(tx_discards);
9408 ESTAT_ADD(tx_errors);
9409
9410 ESTAT_ADD(dma_writeq_full);
9411 ESTAT_ADD(dma_write_prioq_full);
9412 ESTAT_ADD(rxbds_empty);
9413 ESTAT_ADD(rx_discards);
9414 ESTAT_ADD(rx_errors);
9415 ESTAT_ADD(rx_threshold_hit);
9416
9417 ESTAT_ADD(dma_readq_full);
9418 ESTAT_ADD(dma_read_prioq_full);
9419 ESTAT_ADD(tx_comp_queue_full);
9420
9421 ESTAT_ADD(ring_set_send_prod_index);
9422 ESTAT_ADD(ring_status_update);
9423 ESTAT_ADD(nic_irqs);
9424 ESTAT_ADD(nic_avoided_irqs);
9425 ESTAT_ADD(nic_tx_threshold_hit);
9426
9427 return estats;
9428 }
9429
9430 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9431 struct rtnl_link_stats64 *stats)
9432 {
9433 struct tg3 *tp = netdev_priv(dev);
9434 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9435 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9436
9437 if (!hw_stats)
9438 return old_stats;
9439
9440 stats->rx_packets = old_stats->rx_packets +
9441 get_stat64(&hw_stats->rx_ucast_packets) +
9442 get_stat64(&hw_stats->rx_mcast_packets) +
9443 get_stat64(&hw_stats->rx_bcast_packets);
9444
9445 stats->tx_packets = old_stats->tx_packets +
9446 get_stat64(&hw_stats->tx_ucast_packets) +
9447 get_stat64(&hw_stats->tx_mcast_packets) +
9448 get_stat64(&hw_stats->tx_bcast_packets);
9449
9450 stats->rx_bytes = old_stats->rx_bytes +
9451 get_stat64(&hw_stats->rx_octets);
9452 stats->tx_bytes = old_stats->tx_bytes +
9453 get_stat64(&hw_stats->tx_octets);
9454
9455 stats->rx_errors = old_stats->rx_errors +
9456 get_stat64(&hw_stats->rx_errors);
9457 stats->tx_errors = old_stats->tx_errors +
9458 get_stat64(&hw_stats->tx_errors) +
9459 get_stat64(&hw_stats->tx_mac_errors) +
9460 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9461 get_stat64(&hw_stats->tx_discards);
9462
9463 stats->multicast = old_stats->multicast +
9464 get_stat64(&hw_stats->rx_mcast_packets);
9465 stats->collisions = old_stats->collisions +
9466 get_stat64(&hw_stats->tx_collisions);
9467
9468 stats->rx_length_errors = old_stats->rx_length_errors +
9469 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9470 get_stat64(&hw_stats->rx_undersize_packets);
9471
9472 stats->rx_over_errors = old_stats->rx_over_errors +
9473 get_stat64(&hw_stats->rxbds_empty);
9474 stats->rx_frame_errors = old_stats->rx_frame_errors +
9475 get_stat64(&hw_stats->rx_align_errors);
9476 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9477 get_stat64(&hw_stats->tx_discards);
9478 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9479 get_stat64(&hw_stats->tx_carrier_sense_errors);
9480
9481 stats->rx_crc_errors = old_stats->rx_crc_errors +
9482 calc_crc_errors(tp);
9483
9484 stats->rx_missed_errors = old_stats->rx_missed_errors +
9485 get_stat64(&hw_stats->rx_discards);
9486
9487 stats->rx_dropped = tp->rx_dropped;
9488
9489 return stats;
9490 }
9491
9492 static inline u32 calc_crc(unsigned char *buf, int len)
9493 {
9494 u32 reg;
9495 u32 tmp;
9496 int j, k;
9497
9498 reg = 0xffffffff;
9499
9500 for (j = 0; j < len; j++) {
9501 reg ^= buf[j];
9502
9503 for (k = 0; k < 8; k++) {
9504 tmp = reg & 0x01;
9505
9506 reg >>= 1;
9507
9508 if (tmp)
9509 reg ^= 0xedb88320;
9510 }
9511 }
9512
9513 return ~reg;
9514 }
9515
9516 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9517 {
9518 /* accept or reject all multicast frames */
9519 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9520 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9521 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9522 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9523 }
9524
9525 static void __tg3_set_rx_mode(struct net_device *dev)
9526 {
9527 struct tg3 *tp = netdev_priv(dev);
9528 u32 rx_mode;
9529
9530 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9531 RX_MODE_KEEP_VLAN_TAG);
9532
9533 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9534 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9535 * flag clear.
9536 */
9537 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9538 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9539 #endif
9540
9541 if (dev->flags & IFF_PROMISC) {
9542 /* Promiscuous mode. */
9543 rx_mode |= RX_MODE_PROMISC;
9544 } else if (dev->flags & IFF_ALLMULTI) {
9545 /* Accept all multicast. */
9546 tg3_set_multi(tp, 1);
9547 } else if (netdev_mc_empty(dev)) {
9548 /* Reject all multicast. */
9549 tg3_set_multi(tp, 0);
9550 } else {
9551 /* Accept one or more multicast(s). */
9552 struct netdev_hw_addr *ha;
9553 u32 mc_filter[4] = { 0, };
9554 u32 regidx;
9555 u32 bit;
9556 u32 crc;
9557
9558 netdev_for_each_mc_addr(ha, dev) {
9559 crc = calc_crc(ha->addr, ETH_ALEN);
9560 bit = ~crc & 0x7f;
9561 regidx = (bit & 0x60) >> 5;
9562 bit &= 0x1f;
9563 mc_filter[regidx] |= (1 << bit);
9564 }
9565
9566 tw32(MAC_HASH_REG_0, mc_filter[0]);
9567 tw32(MAC_HASH_REG_1, mc_filter[1]);
9568 tw32(MAC_HASH_REG_2, mc_filter[2]);
9569 tw32(MAC_HASH_REG_3, mc_filter[3]);
9570 }
9571
9572 if (rx_mode != tp->rx_mode) {
9573 tp->rx_mode = rx_mode;
9574 tw32_f(MAC_RX_MODE, rx_mode);
9575 udelay(10);
9576 }
9577 }
9578
9579 static void tg3_set_rx_mode(struct net_device *dev)
9580 {
9581 struct tg3 *tp = netdev_priv(dev);
9582
9583 if (!netif_running(dev))
9584 return;
9585
9586 tg3_full_lock(tp, 0);
9587 __tg3_set_rx_mode(dev);
9588 tg3_full_unlock(tp);
9589 }
9590
9591 #define TG3_REGDUMP_LEN (32 * 1024)
9592
9593 static int tg3_get_regs_len(struct net_device *dev)
9594 {
9595 return TG3_REGDUMP_LEN;
9596 }
9597
9598 static void tg3_get_regs(struct net_device *dev,
9599 struct ethtool_regs *regs, void *_p)
9600 {
9601 u32 *p = _p;
9602 struct tg3 *tp = netdev_priv(dev);
9603 u8 *orig_p = _p;
9604 int i;
9605
9606 regs->version = 0;
9607
9608 memset(p, 0, TG3_REGDUMP_LEN);
9609
9610 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9611 return;
9612
9613 tg3_full_lock(tp, 0);
9614
9615 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9616 #define GET_REG32_LOOP(base, len) \
9617 do { p = (u32 *)(orig_p + (base)); \
9618 for (i = 0; i < len; i += 4) \
9619 __GET_REG32((base) + i); \
9620 } while (0)
9621 #define GET_REG32_1(reg) \
9622 do { p = (u32 *)(orig_p + (reg)); \
9623 __GET_REG32((reg)); \
9624 } while (0)
9625
9626 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9627 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9628 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9629 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9630 GET_REG32_1(SNDDATAC_MODE);
9631 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9632 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9633 GET_REG32_1(SNDBDC_MODE);
9634 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9635 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9636 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9637 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9638 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9639 GET_REG32_1(RCVDCC_MODE);
9640 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9641 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9642 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9643 GET_REG32_1(MBFREE_MODE);
9644 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9645 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9646 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9647 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9648 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9649 GET_REG32_1(RX_CPU_MODE);
9650 GET_REG32_1(RX_CPU_STATE);
9651 GET_REG32_1(RX_CPU_PGMCTR);
9652 GET_REG32_1(RX_CPU_HWBKPT);
9653 GET_REG32_1(TX_CPU_MODE);
9654 GET_REG32_1(TX_CPU_STATE);
9655 GET_REG32_1(TX_CPU_PGMCTR);
9656 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9657 GET_REG32_LOOP(FTQ_RESET, 0x120);
9658 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9659 GET_REG32_1(DMAC_MODE);
9660 GET_REG32_LOOP(GRC_MODE, 0x4c);
9661 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9662 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9663
9664 #undef __GET_REG32
9665 #undef GET_REG32_LOOP
9666 #undef GET_REG32_1
9667
9668 tg3_full_unlock(tp);
9669 }
9670
9671 static int tg3_get_eeprom_len(struct net_device *dev)
9672 {
9673 struct tg3 *tp = netdev_priv(dev);
9674
9675 return tp->nvram_size;
9676 }
9677
9678 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9679 {
9680 struct tg3 *tp = netdev_priv(dev);
9681 int ret;
9682 u8 *pd;
9683 u32 i, offset, len, b_offset, b_count;
9684 __be32 val;
9685
9686 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9687 return -EINVAL;
9688
9689 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9690 return -EAGAIN;
9691
9692 offset = eeprom->offset;
9693 len = eeprom->len;
9694 eeprom->len = 0;
9695
9696 eeprom->magic = TG3_EEPROM_MAGIC;
9697
9698 if (offset & 3) {
9699 /* adjustments to start on required 4 byte boundary */
9700 b_offset = offset & 3;
9701 b_count = 4 - b_offset;
9702 if (b_count > len) {
9703 /* i.e. offset=1 len=2 */
9704 b_count = len;
9705 }
9706 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9707 if (ret)
9708 return ret;
9709 memcpy(data, ((char *)&val) + b_offset, b_count);
9710 len -= b_count;
9711 offset += b_count;
9712 eeprom->len += b_count;
9713 }
9714
9715 /* read bytes upto the last 4 byte boundary */
9716 pd = &data[eeprom->len];
9717 for (i = 0; i < (len - (len & 3)); i += 4) {
9718 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9719 if (ret) {
9720 eeprom->len += i;
9721 return ret;
9722 }
9723 memcpy(pd + i, &val, 4);
9724 }
9725 eeprom->len += i;
9726
9727 if (len & 3) {
9728 /* read last bytes not ending on 4 byte boundary */
9729 pd = &data[eeprom->len];
9730 b_count = len & 3;
9731 b_offset = offset + len - b_count;
9732 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9733 if (ret)
9734 return ret;
9735 memcpy(pd, &val, b_count);
9736 eeprom->len += b_count;
9737 }
9738 return 0;
9739 }
9740
9741 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9742
9743 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9744 {
9745 struct tg3 *tp = netdev_priv(dev);
9746 int ret;
9747 u32 offset, len, b_offset, odd_len;
9748 u8 *buf;
9749 __be32 start, end;
9750
9751 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9752 return -EAGAIN;
9753
9754 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9755 eeprom->magic != TG3_EEPROM_MAGIC)
9756 return -EINVAL;
9757
9758 offset = eeprom->offset;
9759 len = eeprom->len;
9760
9761 if ((b_offset = (offset & 3))) {
9762 /* adjustments to start on required 4 byte boundary */
9763 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9764 if (ret)
9765 return ret;
9766 len += b_offset;
9767 offset &= ~3;
9768 if (len < 4)
9769 len = 4;
9770 }
9771
9772 odd_len = 0;
9773 if (len & 3) {
9774 /* adjustments to end on required 4 byte boundary */
9775 odd_len = 1;
9776 len = (len + 3) & ~3;
9777 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9778 if (ret)
9779 return ret;
9780 }
9781
9782 buf = data;
9783 if (b_offset || odd_len) {
9784 buf = kmalloc(len, GFP_KERNEL);
9785 if (!buf)
9786 return -ENOMEM;
9787 if (b_offset)
9788 memcpy(buf, &start, 4);
9789 if (odd_len)
9790 memcpy(buf+len-4, &end, 4);
9791 memcpy(buf + b_offset, data, eeprom->len);
9792 }
9793
9794 ret = tg3_nvram_write_block(tp, offset, len, buf);
9795
9796 if (buf != data)
9797 kfree(buf);
9798
9799 return ret;
9800 }
9801
9802 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9803 {
9804 struct tg3 *tp = netdev_priv(dev);
9805
9806 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9807 struct phy_device *phydev;
9808 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9809 return -EAGAIN;
9810 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9811 return phy_ethtool_gset(phydev, cmd);
9812 }
9813
9814 cmd->supported = (SUPPORTED_Autoneg);
9815
9816 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9817 cmd->supported |= (SUPPORTED_1000baseT_Half |
9818 SUPPORTED_1000baseT_Full);
9819
9820 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9821 cmd->supported |= (SUPPORTED_100baseT_Half |
9822 SUPPORTED_100baseT_Full |
9823 SUPPORTED_10baseT_Half |
9824 SUPPORTED_10baseT_Full |
9825 SUPPORTED_TP);
9826 cmd->port = PORT_TP;
9827 } else {
9828 cmd->supported |= SUPPORTED_FIBRE;
9829 cmd->port = PORT_FIBRE;
9830 }
9831
9832 cmd->advertising = tp->link_config.advertising;
9833 if (netif_running(dev)) {
9834 cmd->speed = tp->link_config.active_speed;
9835 cmd->duplex = tp->link_config.active_duplex;
9836 } else {
9837 cmd->speed = SPEED_INVALID;
9838 cmd->duplex = DUPLEX_INVALID;
9839 }
9840 cmd->phy_address = tp->phy_addr;
9841 cmd->transceiver = XCVR_INTERNAL;
9842 cmd->autoneg = tp->link_config.autoneg;
9843 cmd->maxtxpkt = 0;
9844 cmd->maxrxpkt = 0;
9845 return 0;
9846 }
9847
9848 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9849 {
9850 struct tg3 *tp = netdev_priv(dev);
9851
9852 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9853 struct phy_device *phydev;
9854 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9855 return -EAGAIN;
9856 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9857 return phy_ethtool_sset(phydev, cmd);
9858 }
9859
9860 if (cmd->autoneg != AUTONEG_ENABLE &&
9861 cmd->autoneg != AUTONEG_DISABLE)
9862 return -EINVAL;
9863
9864 if (cmd->autoneg == AUTONEG_DISABLE &&
9865 cmd->duplex != DUPLEX_FULL &&
9866 cmd->duplex != DUPLEX_HALF)
9867 return -EINVAL;
9868
9869 if (cmd->autoneg == AUTONEG_ENABLE) {
9870 u32 mask = ADVERTISED_Autoneg |
9871 ADVERTISED_Pause |
9872 ADVERTISED_Asym_Pause;
9873
9874 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9875 mask |= ADVERTISED_1000baseT_Half |
9876 ADVERTISED_1000baseT_Full;
9877
9878 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9879 mask |= ADVERTISED_100baseT_Half |
9880 ADVERTISED_100baseT_Full |
9881 ADVERTISED_10baseT_Half |
9882 ADVERTISED_10baseT_Full |
9883 ADVERTISED_TP;
9884 else
9885 mask |= ADVERTISED_FIBRE;
9886
9887 if (cmd->advertising & ~mask)
9888 return -EINVAL;
9889
9890 mask &= (ADVERTISED_1000baseT_Half |
9891 ADVERTISED_1000baseT_Full |
9892 ADVERTISED_100baseT_Half |
9893 ADVERTISED_100baseT_Full |
9894 ADVERTISED_10baseT_Half |
9895 ADVERTISED_10baseT_Full);
9896
9897 cmd->advertising &= mask;
9898 } else {
9899 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9900 if (cmd->speed != SPEED_1000)
9901 return -EINVAL;
9902
9903 if (cmd->duplex != DUPLEX_FULL)
9904 return -EINVAL;
9905 } else {
9906 if (cmd->speed != SPEED_100 &&
9907 cmd->speed != SPEED_10)
9908 return -EINVAL;
9909 }
9910 }
9911
9912 tg3_full_lock(tp, 0);
9913
9914 tp->link_config.autoneg = cmd->autoneg;
9915 if (cmd->autoneg == AUTONEG_ENABLE) {
9916 tp->link_config.advertising = (cmd->advertising |
9917 ADVERTISED_Autoneg);
9918 tp->link_config.speed = SPEED_INVALID;
9919 tp->link_config.duplex = DUPLEX_INVALID;
9920 } else {
9921 tp->link_config.advertising = 0;
9922 tp->link_config.speed = cmd->speed;
9923 tp->link_config.duplex = cmd->duplex;
9924 }
9925
9926 tp->link_config.orig_speed = tp->link_config.speed;
9927 tp->link_config.orig_duplex = tp->link_config.duplex;
9928 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9929
9930 if (netif_running(dev))
9931 tg3_setup_phy(tp, 1);
9932
9933 tg3_full_unlock(tp);
9934
9935 return 0;
9936 }
9937
9938 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9939 {
9940 struct tg3 *tp = netdev_priv(dev);
9941
9942 strcpy(info->driver, DRV_MODULE_NAME);
9943 strcpy(info->version, DRV_MODULE_VERSION);
9944 strcpy(info->fw_version, tp->fw_ver);
9945 strcpy(info->bus_info, pci_name(tp->pdev));
9946 }
9947
9948 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9949 {
9950 struct tg3 *tp = netdev_priv(dev);
9951
9952 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9953 device_can_wakeup(&tp->pdev->dev))
9954 wol->supported = WAKE_MAGIC;
9955 else
9956 wol->supported = 0;
9957 wol->wolopts = 0;
9958 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9959 device_can_wakeup(&tp->pdev->dev))
9960 wol->wolopts = WAKE_MAGIC;
9961 memset(&wol->sopass, 0, sizeof(wol->sopass));
9962 }
9963
9964 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9965 {
9966 struct tg3 *tp = netdev_priv(dev);
9967 struct device *dp = &tp->pdev->dev;
9968
9969 if (wol->wolopts & ~WAKE_MAGIC)
9970 return -EINVAL;
9971 if ((wol->wolopts & WAKE_MAGIC) &&
9972 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9973 return -EINVAL;
9974
9975 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9976
9977 spin_lock_bh(&tp->lock);
9978 if (device_may_wakeup(dp))
9979 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9980 else
9981 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9982 spin_unlock_bh(&tp->lock);
9983
9984
9985 return 0;
9986 }
9987
9988 static u32 tg3_get_msglevel(struct net_device *dev)
9989 {
9990 struct tg3 *tp = netdev_priv(dev);
9991 return tp->msg_enable;
9992 }
9993
9994 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9995 {
9996 struct tg3 *tp = netdev_priv(dev);
9997 tp->msg_enable = value;
9998 }
9999
10000 static int tg3_set_tso(struct net_device *dev, u32 value)
10001 {
10002 struct tg3 *tp = netdev_priv(dev);
10003
10004 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10005 if (value)
10006 return -EINVAL;
10007 return 0;
10008 }
10009 if ((dev->features & NETIF_F_IPV6_CSUM) &&
10010 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10011 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10012 if (value) {
10013 dev->features |= NETIF_F_TSO6;
10014 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10016 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10017 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10020 dev->features |= NETIF_F_TSO_ECN;
10021 } else
10022 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10023 }
10024 return ethtool_op_set_tso(dev, value);
10025 }
10026
10027 static int tg3_nway_reset(struct net_device *dev)
10028 {
10029 struct tg3 *tp = netdev_priv(dev);
10030 int r;
10031
10032 if (!netif_running(dev))
10033 return -EAGAIN;
10034
10035 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10036 return -EINVAL;
10037
10038 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10039 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10040 return -EAGAIN;
10041 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10042 } else {
10043 u32 bmcr;
10044
10045 spin_lock_bh(&tp->lock);
10046 r = -EINVAL;
10047 tg3_readphy(tp, MII_BMCR, &bmcr);
10048 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10049 ((bmcr & BMCR_ANENABLE) ||
10050 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10052 BMCR_ANENABLE);
10053 r = 0;
10054 }
10055 spin_unlock_bh(&tp->lock);
10056 }
10057
10058 return r;
10059 }
10060
10061 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10062 {
10063 struct tg3 *tp = netdev_priv(dev);
10064
10065 ering->rx_max_pending = tp->rx_std_ring_mask;
10066 ering->rx_mini_max_pending = 0;
10067 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10068 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10069 else
10070 ering->rx_jumbo_max_pending = 0;
10071
10072 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10073
10074 ering->rx_pending = tp->rx_pending;
10075 ering->rx_mini_pending = 0;
10076 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10077 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10078 else
10079 ering->rx_jumbo_pending = 0;
10080
10081 ering->tx_pending = tp->napi[0].tx_pending;
10082 }
10083
10084 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10085 {
10086 struct tg3 *tp = netdev_priv(dev);
10087 int i, irq_sync = 0, err = 0;
10088
10089 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10090 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10091 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10092 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10093 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10094 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10095 return -EINVAL;
10096
10097 if (netif_running(dev)) {
10098 tg3_phy_stop(tp);
10099 tg3_netif_stop(tp);
10100 irq_sync = 1;
10101 }
10102
10103 tg3_full_lock(tp, irq_sync);
10104
10105 tp->rx_pending = ering->rx_pending;
10106
10107 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10108 tp->rx_pending > 63)
10109 tp->rx_pending = 63;
10110 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10111
10112 for (i = 0; i < tp->irq_max; i++)
10113 tp->napi[i].tx_pending = ering->tx_pending;
10114
10115 if (netif_running(dev)) {
10116 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10117 err = tg3_restart_hw(tp, 1);
10118 if (!err)
10119 tg3_netif_start(tp);
10120 }
10121
10122 tg3_full_unlock(tp);
10123
10124 if (irq_sync && !err)
10125 tg3_phy_start(tp);
10126
10127 return err;
10128 }
10129
10130 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10131 {
10132 struct tg3 *tp = netdev_priv(dev);
10133
10134 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10135
10136 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10137 epause->rx_pause = 1;
10138 else
10139 epause->rx_pause = 0;
10140
10141 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10142 epause->tx_pause = 1;
10143 else
10144 epause->tx_pause = 0;
10145 }
10146
10147 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10148 {
10149 struct tg3 *tp = netdev_priv(dev);
10150 int err = 0;
10151
10152 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10153 u32 newadv;
10154 struct phy_device *phydev;
10155
10156 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10157
10158 if (!(phydev->supported & SUPPORTED_Pause) ||
10159 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10160 (epause->rx_pause != epause->tx_pause)))
10161 return -EINVAL;
10162
10163 tp->link_config.flowctrl = 0;
10164 if (epause->rx_pause) {
10165 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10166
10167 if (epause->tx_pause) {
10168 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10169 newadv = ADVERTISED_Pause;
10170 } else
10171 newadv = ADVERTISED_Pause |
10172 ADVERTISED_Asym_Pause;
10173 } else if (epause->tx_pause) {
10174 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10175 newadv = ADVERTISED_Asym_Pause;
10176 } else
10177 newadv = 0;
10178
10179 if (epause->autoneg)
10180 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10181 else
10182 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10183
10184 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10185 u32 oldadv = phydev->advertising &
10186 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10187 if (oldadv != newadv) {
10188 phydev->advertising &=
10189 ~(ADVERTISED_Pause |
10190 ADVERTISED_Asym_Pause);
10191 phydev->advertising |= newadv;
10192 if (phydev->autoneg) {
10193 /*
10194 * Always renegotiate the link to
10195 * inform our link partner of our
10196 * flow control settings, even if the
10197 * flow control is forced. Let
10198 * tg3_adjust_link() do the final
10199 * flow control setup.
10200 */
10201 return phy_start_aneg(phydev);
10202 }
10203 }
10204
10205 if (!epause->autoneg)
10206 tg3_setup_flow_control(tp, 0, 0);
10207 } else {
10208 tp->link_config.orig_advertising &=
10209 ~(ADVERTISED_Pause |
10210 ADVERTISED_Asym_Pause);
10211 tp->link_config.orig_advertising |= newadv;
10212 }
10213 } else {
10214 int irq_sync = 0;
10215
10216 if (netif_running(dev)) {
10217 tg3_netif_stop(tp);
10218 irq_sync = 1;
10219 }
10220
10221 tg3_full_lock(tp, irq_sync);
10222
10223 if (epause->autoneg)
10224 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10225 else
10226 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10227 if (epause->rx_pause)
10228 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10229 else
10230 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10231 if (epause->tx_pause)
10232 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10233 else
10234 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10235
10236 if (netif_running(dev)) {
10237 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10238 err = tg3_restart_hw(tp, 1);
10239 if (!err)
10240 tg3_netif_start(tp);
10241 }
10242
10243 tg3_full_unlock(tp);
10244 }
10245
10246 return err;
10247 }
10248
10249 static u32 tg3_get_rx_csum(struct net_device *dev)
10250 {
10251 struct tg3 *tp = netdev_priv(dev);
10252 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10253 }
10254
10255 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10256 {
10257 struct tg3 *tp = netdev_priv(dev);
10258
10259 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10260 if (data != 0)
10261 return -EINVAL;
10262 return 0;
10263 }
10264
10265 spin_lock_bh(&tp->lock);
10266 if (data)
10267 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10268 else
10269 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10270 spin_unlock_bh(&tp->lock);
10271
10272 return 0;
10273 }
10274
10275 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10276 {
10277 struct tg3 *tp = netdev_priv(dev);
10278
10279 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10280 if (data != 0)
10281 return -EINVAL;
10282 return 0;
10283 }
10284
10285 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10286 ethtool_op_set_tx_ipv6_csum(dev, data);
10287 else
10288 ethtool_op_set_tx_csum(dev, data);
10289
10290 return 0;
10291 }
10292
10293 static int tg3_get_sset_count(struct net_device *dev, int sset)
10294 {
10295 switch (sset) {
10296 case ETH_SS_TEST:
10297 return TG3_NUM_TEST;
10298 case ETH_SS_STATS:
10299 return TG3_NUM_STATS;
10300 default:
10301 return -EOPNOTSUPP;
10302 }
10303 }
10304
10305 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10306 {
10307 switch (stringset) {
10308 case ETH_SS_STATS:
10309 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10310 break;
10311 case ETH_SS_TEST:
10312 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10313 break;
10314 default:
10315 WARN_ON(1); /* we need a WARN() */
10316 break;
10317 }
10318 }
10319
10320 static int tg3_phys_id(struct net_device *dev, u32 data)
10321 {
10322 struct tg3 *tp = netdev_priv(dev);
10323 int i;
10324
10325 if (!netif_running(tp->dev))
10326 return -EAGAIN;
10327
10328 if (data == 0)
10329 data = UINT_MAX / 2;
10330
10331 for (i = 0; i < (data * 2); i++) {
10332 if ((i % 2) == 0)
10333 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10334 LED_CTRL_1000MBPS_ON |
10335 LED_CTRL_100MBPS_ON |
10336 LED_CTRL_10MBPS_ON |
10337 LED_CTRL_TRAFFIC_OVERRIDE |
10338 LED_CTRL_TRAFFIC_BLINK |
10339 LED_CTRL_TRAFFIC_LED);
10340
10341 else
10342 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10343 LED_CTRL_TRAFFIC_OVERRIDE);
10344
10345 if (msleep_interruptible(500))
10346 break;
10347 }
10348 tw32(MAC_LED_CTRL, tp->led_ctrl);
10349 return 0;
10350 }
10351
10352 static void tg3_get_ethtool_stats(struct net_device *dev,
10353 struct ethtool_stats *estats, u64 *tmp_stats)
10354 {
10355 struct tg3 *tp = netdev_priv(dev);
10356 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10357 }
10358
10359 #define NVRAM_TEST_SIZE 0x100
10360 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10361 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10362 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10363 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10364 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10365
10366 static int tg3_test_nvram(struct tg3 *tp)
10367 {
10368 u32 csum, magic;
10369 __be32 *buf;
10370 int i, j, k, err = 0, size;
10371
10372 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10373 return 0;
10374
10375 if (tg3_nvram_read(tp, 0, &magic) != 0)
10376 return -EIO;
10377
10378 if (magic == TG3_EEPROM_MAGIC)
10379 size = NVRAM_TEST_SIZE;
10380 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10381 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10382 TG3_EEPROM_SB_FORMAT_1) {
10383 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10384 case TG3_EEPROM_SB_REVISION_0:
10385 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10386 break;
10387 case TG3_EEPROM_SB_REVISION_2:
10388 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10389 break;
10390 case TG3_EEPROM_SB_REVISION_3:
10391 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10392 break;
10393 default:
10394 return 0;
10395 }
10396 } else
10397 return 0;
10398 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10399 size = NVRAM_SELFBOOT_HW_SIZE;
10400 else
10401 return -EIO;
10402
10403 buf = kmalloc(size, GFP_KERNEL);
10404 if (buf == NULL)
10405 return -ENOMEM;
10406
10407 err = -EIO;
10408 for (i = 0, j = 0; i < size; i += 4, j++) {
10409 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10410 if (err)
10411 break;
10412 }
10413 if (i < size)
10414 goto out;
10415
10416 /* Selfboot format */
10417 magic = be32_to_cpu(buf[0]);
10418 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10419 TG3_EEPROM_MAGIC_FW) {
10420 u8 *buf8 = (u8 *) buf, csum8 = 0;
10421
10422 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10423 TG3_EEPROM_SB_REVISION_2) {
10424 /* For rev 2, the csum doesn't include the MBA. */
10425 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10426 csum8 += buf8[i];
10427 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10428 csum8 += buf8[i];
10429 } else {
10430 for (i = 0; i < size; i++)
10431 csum8 += buf8[i];
10432 }
10433
10434 if (csum8 == 0) {
10435 err = 0;
10436 goto out;
10437 }
10438
10439 err = -EIO;
10440 goto out;
10441 }
10442
10443 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10444 TG3_EEPROM_MAGIC_HW) {
10445 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10446 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10447 u8 *buf8 = (u8 *) buf;
10448
10449 /* Separate the parity bits and the data bytes. */
10450 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10451 if ((i == 0) || (i == 8)) {
10452 int l;
10453 u8 msk;
10454
10455 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10456 parity[k++] = buf8[i] & msk;
10457 i++;
10458 } else if (i == 16) {
10459 int l;
10460 u8 msk;
10461
10462 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10463 parity[k++] = buf8[i] & msk;
10464 i++;
10465
10466 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10467 parity[k++] = buf8[i] & msk;
10468 i++;
10469 }
10470 data[j++] = buf8[i];
10471 }
10472
10473 err = -EIO;
10474 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10475 u8 hw8 = hweight8(data[i]);
10476
10477 if ((hw8 & 0x1) && parity[i])
10478 goto out;
10479 else if (!(hw8 & 0x1) && !parity[i])
10480 goto out;
10481 }
10482 err = 0;
10483 goto out;
10484 }
10485
10486 err = -EIO;
10487
10488 /* Bootstrap checksum at offset 0x10 */
10489 csum = calc_crc((unsigned char *) buf, 0x10);
10490 if (csum != le32_to_cpu(buf[0x10/4]))
10491 goto out;
10492
10493 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10494 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10495 if (csum != le32_to_cpu(buf[0xfc/4]))
10496 goto out;
10497
10498 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10499 /* The data is in little-endian format in NVRAM.
10500 * Use the big-endian read routines to preserve
10501 * the byte order as it exists in NVRAM.
10502 */
10503 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10504 goto out;
10505 }
10506
10507 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10508 PCI_VPD_LRDT_RO_DATA);
10509 if (i > 0) {
10510 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10511 if (j < 0)
10512 goto out;
10513
10514 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10515 goto out;
10516
10517 i += PCI_VPD_LRDT_TAG_SIZE;
10518 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10519 PCI_VPD_RO_KEYWORD_CHKSUM);
10520 if (j > 0) {
10521 u8 csum8 = 0;
10522
10523 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10524
10525 for (i = 0; i <= j; i++)
10526 csum8 += ((u8 *)buf)[i];
10527
10528 if (csum8)
10529 goto out;
10530 }
10531 }
10532
10533 err = 0;
10534
10535 out:
10536 kfree(buf);
10537 return err;
10538 }
10539
10540 #define TG3_SERDES_TIMEOUT_SEC 2
10541 #define TG3_COPPER_TIMEOUT_SEC 6
10542
10543 static int tg3_test_link(struct tg3 *tp)
10544 {
10545 int i, max;
10546
10547 if (!netif_running(tp->dev))
10548 return -ENODEV;
10549
10550 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10551 max = TG3_SERDES_TIMEOUT_SEC;
10552 else
10553 max = TG3_COPPER_TIMEOUT_SEC;
10554
10555 for (i = 0; i < max; i++) {
10556 if (netif_carrier_ok(tp->dev))
10557 return 0;
10558
10559 if (msleep_interruptible(1000))
10560 break;
10561 }
10562
10563 return -EIO;
10564 }
10565
10566 /* Only test the commonly used registers */
10567 static int tg3_test_registers(struct tg3 *tp)
10568 {
10569 int i, is_5705, is_5750;
10570 u32 offset, read_mask, write_mask, val, save_val, read_val;
10571 static struct {
10572 u16 offset;
10573 u16 flags;
10574 #define TG3_FL_5705 0x1
10575 #define TG3_FL_NOT_5705 0x2
10576 #define TG3_FL_NOT_5788 0x4
10577 #define TG3_FL_NOT_5750 0x8
10578 u32 read_mask;
10579 u32 write_mask;
10580 } reg_tbl[] = {
10581 /* MAC Control Registers */
10582 { MAC_MODE, TG3_FL_NOT_5705,
10583 0x00000000, 0x00ef6f8c },
10584 { MAC_MODE, TG3_FL_5705,
10585 0x00000000, 0x01ef6b8c },
10586 { MAC_STATUS, TG3_FL_NOT_5705,
10587 0x03800107, 0x00000000 },
10588 { MAC_STATUS, TG3_FL_5705,
10589 0x03800100, 0x00000000 },
10590 { MAC_ADDR_0_HIGH, 0x0000,
10591 0x00000000, 0x0000ffff },
10592 { MAC_ADDR_0_LOW, 0x0000,
10593 0x00000000, 0xffffffff },
10594 { MAC_RX_MTU_SIZE, 0x0000,
10595 0x00000000, 0x0000ffff },
10596 { MAC_TX_MODE, 0x0000,
10597 0x00000000, 0x00000070 },
10598 { MAC_TX_LENGTHS, 0x0000,
10599 0x00000000, 0x00003fff },
10600 { MAC_RX_MODE, TG3_FL_NOT_5705,
10601 0x00000000, 0x000007fc },
10602 { MAC_RX_MODE, TG3_FL_5705,
10603 0x00000000, 0x000007dc },
10604 { MAC_HASH_REG_0, 0x0000,
10605 0x00000000, 0xffffffff },
10606 { MAC_HASH_REG_1, 0x0000,
10607 0x00000000, 0xffffffff },
10608 { MAC_HASH_REG_2, 0x0000,
10609 0x00000000, 0xffffffff },
10610 { MAC_HASH_REG_3, 0x0000,
10611 0x00000000, 0xffffffff },
10612
10613 /* Receive Data and Receive BD Initiator Control Registers. */
10614 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10615 0x00000000, 0xffffffff },
10616 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10617 0x00000000, 0xffffffff },
10618 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10619 0x00000000, 0x00000003 },
10620 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10621 0x00000000, 0xffffffff },
10622 { RCVDBDI_STD_BD+0, 0x0000,
10623 0x00000000, 0xffffffff },
10624 { RCVDBDI_STD_BD+4, 0x0000,
10625 0x00000000, 0xffffffff },
10626 { RCVDBDI_STD_BD+8, 0x0000,
10627 0x00000000, 0xffff0002 },
10628 { RCVDBDI_STD_BD+0xc, 0x0000,
10629 0x00000000, 0xffffffff },
10630
10631 /* Receive BD Initiator Control Registers. */
10632 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10633 0x00000000, 0xffffffff },
10634 { RCVBDI_STD_THRESH, TG3_FL_5705,
10635 0x00000000, 0x000003ff },
10636 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10637 0x00000000, 0xffffffff },
10638
10639 /* Host Coalescing Control Registers. */
10640 { HOSTCC_MODE, TG3_FL_NOT_5705,
10641 0x00000000, 0x00000004 },
10642 { HOSTCC_MODE, TG3_FL_5705,
10643 0x00000000, 0x000000f6 },
10644 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10645 0x00000000, 0xffffffff },
10646 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10647 0x00000000, 0x000003ff },
10648 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10649 0x00000000, 0xffffffff },
10650 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10651 0x00000000, 0x000003ff },
10652 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10653 0x00000000, 0xffffffff },
10654 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10655 0x00000000, 0x000000ff },
10656 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10657 0x00000000, 0xffffffff },
10658 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10659 0x00000000, 0x000000ff },
10660 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10661 0x00000000, 0xffffffff },
10662 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10663 0x00000000, 0xffffffff },
10664 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10665 0x00000000, 0xffffffff },
10666 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10667 0x00000000, 0x000000ff },
10668 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10669 0x00000000, 0xffffffff },
10670 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10671 0x00000000, 0x000000ff },
10672 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10673 0x00000000, 0xffffffff },
10674 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10675 0x00000000, 0xffffffff },
10676 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10677 0x00000000, 0xffffffff },
10678 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10679 0x00000000, 0xffffffff },
10680 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10681 0x00000000, 0xffffffff },
10682 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10683 0xffffffff, 0x00000000 },
10684 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10685 0xffffffff, 0x00000000 },
10686
10687 /* Buffer Manager Control Registers. */
10688 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10689 0x00000000, 0x007fff80 },
10690 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10691 0x00000000, 0x007fffff },
10692 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10693 0x00000000, 0x0000003f },
10694 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10695 0x00000000, 0x000001ff },
10696 { BUFMGR_MB_HIGH_WATER, 0x0000,
10697 0x00000000, 0x000001ff },
10698 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10699 0xffffffff, 0x00000000 },
10700 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10701 0xffffffff, 0x00000000 },
10702
10703 /* Mailbox Registers */
10704 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10705 0x00000000, 0x000001ff },
10706 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10707 0x00000000, 0x000001ff },
10708 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10709 0x00000000, 0x000007ff },
10710 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10711 0x00000000, 0x000001ff },
10712
10713 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10714 };
10715
10716 is_5705 = is_5750 = 0;
10717 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10718 is_5705 = 1;
10719 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10720 is_5750 = 1;
10721 }
10722
10723 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10724 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10725 continue;
10726
10727 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10728 continue;
10729
10730 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10731 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10732 continue;
10733
10734 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10735 continue;
10736
10737 offset = (u32) reg_tbl[i].offset;
10738 read_mask = reg_tbl[i].read_mask;
10739 write_mask = reg_tbl[i].write_mask;
10740
10741 /* Save the original register content */
10742 save_val = tr32(offset);
10743
10744 /* Determine the read-only value. */
10745 read_val = save_val & read_mask;
10746
10747 /* Write zero to the register, then make sure the read-only bits
10748 * are not changed and the read/write bits are all zeros.
10749 */
10750 tw32(offset, 0);
10751
10752 val = tr32(offset);
10753
10754 /* Test the read-only and read/write bits. */
10755 if (((val & read_mask) != read_val) || (val & write_mask))
10756 goto out;
10757
10758 /* Write ones to all the bits defined by RdMask and WrMask, then
10759 * make sure the read-only bits are not changed and the
10760 * read/write bits are all ones.
10761 */
10762 tw32(offset, read_mask | write_mask);
10763
10764 val = tr32(offset);
10765
10766 /* Test the read-only bits. */
10767 if ((val & read_mask) != read_val)
10768 goto out;
10769
10770 /* Test the read/write bits. */
10771 if ((val & write_mask) != write_mask)
10772 goto out;
10773
10774 tw32(offset, save_val);
10775 }
10776
10777 return 0;
10778
10779 out:
10780 if (netif_msg_hw(tp))
10781 netdev_err(tp->dev,
10782 "Register test failed at offset %x\n", offset);
10783 tw32(offset, save_val);
10784 return -EIO;
10785 }
10786
10787 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10788 {
10789 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10790 int i;
10791 u32 j;
10792
10793 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10794 for (j = 0; j < len; j += 4) {
10795 u32 val;
10796
10797 tg3_write_mem(tp, offset + j, test_pattern[i]);
10798 tg3_read_mem(tp, offset + j, &val);
10799 if (val != test_pattern[i])
10800 return -EIO;
10801 }
10802 }
10803 return 0;
10804 }
10805
10806 static int tg3_test_memory(struct tg3 *tp)
10807 {
10808 static struct mem_entry {
10809 u32 offset;
10810 u32 len;
10811 } mem_tbl_570x[] = {
10812 { 0x00000000, 0x00b50},
10813 { 0x00002000, 0x1c000},
10814 { 0xffffffff, 0x00000}
10815 }, mem_tbl_5705[] = {
10816 { 0x00000100, 0x0000c},
10817 { 0x00000200, 0x00008},
10818 { 0x00004000, 0x00800},
10819 { 0x00006000, 0x01000},
10820 { 0x00008000, 0x02000},
10821 { 0x00010000, 0x0e000},
10822 { 0xffffffff, 0x00000}
10823 }, mem_tbl_5755[] = {
10824 { 0x00000200, 0x00008},
10825 { 0x00004000, 0x00800},
10826 { 0x00006000, 0x00800},
10827 { 0x00008000, 0x02000},
10828 { 0x00010000, 0x0c000},
10829 { 0xffffffff, 0x00000}
10830 }, mem_tbl_5906[] = {
10831 { 0x00000200, 0x00008},
10832 { 0x00004000, 0x00400},
10833 { 0x00006000, 0x00400},
10834 { 0x00008000, 0x01000},
10835 { 0x00010000, 0x01000},
10836 { 0xffffffff, 0x00000}
10837 }, mem_tbl_5717[] = {
10838 { 0x00000200, 0x00008},
10839 { 0x00010000, 0x0a000},
10840 { 0x00020000, 0x13c00},
10841 { 0xffffffff, 0x00000}
10842 }, mem_tbl_57765[] = {
10843 { 0x00000200, 0x00008},
10844 { 0x00004000, 0x00800},
10845 { 0x00006000, 0x09800},
10846 { 0x00010000, 0x0a000},
10847 { 0xffffffff, 0x00000}
10848 };
10849 struct mem_entry *mem_tbl;
10850 int err = 0;
10851 int i;
10852
10853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10854 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10855 mem_tbl = mem_tbl_5717;
10856 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10857 mem_tbl = mem_tbl_57765;
10858 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10859 mem_tbl = mem_tbl_5755;
10860 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10861 mem_tbl = mem_tbl_5906;
10862 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10863 mem_tbl = mem_tbl_5705;
10864 else
10865 mem_tbl = mem_tbl_570x;
10866
10867 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10868 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10869 if (err)
10870 break;
10871 }
10872
10873 return err;
10874 }
10875
10876 #define TG3_MAC_LOOPBACK 0
10877 #define TG3_PHY_LOOPBACK 1
10878
10879 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10880 {
10881 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10882 u32 desc_idx, coal_now;
10883 struct sk_buff *skb, *rx_skb;
10884 u8 *tx_data;
10885 dma_addr_t map;
10886 int num_pkts, tx_len, rx_len, i, err;
10887 struct tg3_rx_buffer_desc *desc;
10888 struct tg3_napi *tnapi, *rnapi;
10889 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10890
10891 tnapi = &tp->napi[0];
10892 rnapi = &tp->napi[0];
10893 if (tp->irq_cnt > 1) {
10894 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10895 rnapi = &tp->napi[1];
10896 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10897 tnapi = &tp->napi[1];
10898 }
10899 coal_now = tnapi->coal_now | rnapi->coal_now;
10900
10901 if (loopback_mode == TG3_MAC_LOOPBACK) {
10902 /* HW errata - mac loopback fails in some cases on 5780.
10903 * Normal traffic and PHY loopback are not affected by
10904 * errata. Also, the MAC loopback test is deprecated for
10905 * all newer ASIC revisions.
10906 */
10907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10908 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10909 return 0;
10910
10911 mac_mode = tp->mac_mode &
10912 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10913 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10914 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10915 mac_mode |= MAC_MODE_LINK_POLARITY;
10916 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10917 mac_mode |= MAC_MODE_PORT_MODE_MII;
10918 else
10919 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10920 tw32(MAC_MODE, mac_mode);
10921 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10922 u32 val;
10923
10924 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10925 tg3_phy_fet_toggle_apd(tp, false);
10926 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10927 } else
10928 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10929
10930 tg3_phy_toggle_automdix(tp, 0);
10931
10932 tg3_writephy(tp, MII_BMCR, val);
10933 udelay(40);
10934
10935 mac_mode = tp->mac_mode &
10936 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10937 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10938 tg3_writephy(tp, MII_TG3_FET_PTEST,
10939 MII_TG3_FET_PTEST_FRC_TX_LINK |
10940 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10941 /* The write needs to be flushed for the AC131 */
10942 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10943 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10944 mac_mode |= MAC_MODE_PORT_MODE_MII;
10945 } else
10946 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10947
10948 /* reset to prevent losing 1st rx packet intermittently */
10949 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10950 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10951 udelay(10);
10952 tw32_f(MAC_RX_MODE, tp->rx_mode);
10953 }
10954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10955 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10956 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10957 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10958 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10959 mac_mode |= MAC_MODE_LINK_POLARITY;
10960 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10961 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10962 }
10963 tw32(MAC_MODE, mac_mode);
10964
10965 /* Wait for link */
10966 for (i = 0; i < 100; i++) {
10967 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
10968 break;
10969 mdelay(1);
10970 }
10971 } else {
10972 return -EINVAL;
10973 }
10974
10975 err = -EIO;
10976
10977 tx_len = 1514;
10978 skb = netdev_alloc_skb(tp->dev, tx_len);
10979 if (!skb)
10980 return -ENOMEM;
10981
10982 tx_data = skb_put(skb, tx_len);
10983 memcpy(tx_data, tp->dev->dev_addr, 6);
10984 memset(tx_data + 6, 0x0, 8);
10985
10986 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10987
10988 for (i = 14; i < tx_len; i++)
10989 tx_data[i] = (u8) (i & 0xff);
10990
10991 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10992 if (pci_dma_mapping_error(tp->pdev, map)) {
10993 dev_kfree_skb(skb);
10994 return -EIO;
10995 }
10996
10997 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10998 rnapi->coal_now);
10999
11000 udelay(10);
11001
11002 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11003
11004 num_pkts = 0;
11005
11006 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11007
11008 tnapi->tx_prod++;
11009 num_pkts++;
11010
11011 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11012 tr32_mailbox(tnapi->prodmbox);
11013
11014 udelay(10);
11015
11016 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11017 for (i = 0; i < 35; i++) {
11018 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11019 coal_now);
11020
11021 udelay(10);
11022
11023 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11024 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11025 if ((tx_idx == tnapi->tx_prod) &&
11026 (rx_idx == (rx_start_idx + num_pkts)))
11027 break;
11028 }
11029
11030 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11031 dev_kfree_skb(skb);
11032
11033 if (tx_idx != tnapi->tx_prod)
11034 goto out;
11035
11036 if (rx_idx != rx_start_idx + num_pkts)
11037 goto out;
11038
11039 desc = &rnapi->rx_rcb[rx_start_idx];
11040 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11041 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11042 if (opaque_key != RXD_OPAQUE_RING_STD)
11043 goto out;
11044
11045 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11046 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11047 goto out;
11048
11049 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11050 if (rx_len != tx_len)
11051 goto out;
11052
11053 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11054
11055 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11056 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11057
11058 for (i = 14; i < tx_len; i++) {
11059 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11060 goto out;
11061 }
11062 err = 0;
11063
11064 /* tg3_free_rings will unmap and free the rx_skb */
11065 out:
11066 return err;
11067 }
11068
11069 #define TG3_MAC_LOOPBACK_FAILED 1
11070 #define TG3_PHY_LOOPBACK_FAILED 2
11071 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11072 TG3_PHY_LOOPBACK_FAILED)
11073
11074 static int tg3_test_loopback(struct tg3 *tp)
11075 {
11076 int err = 0;
11077 u32 eee_cap, cpmuctrl = 0;
11078
11079 if (!netif_running(tp->dev))
11080 return TG3_LOOPBACK_FAILED;
11081
11082 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11083 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11084
11085 err = tg3_reset_hw(tp, 1);
11086 if (err) {
11087 err = TG3_LOOPBACK_FAILED;
11088 goto done;
11089 }
11090
11091 /* Turn off gphy autopowerdown. */
11092 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11093 tg3_phy_toggle_apd(tp, false);
11094
11095 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11096 int i;
11097 u32 status;
11098
11099 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11100
11101 /* Wait for up to 40 microseconds to acquire lock. */
11102 for (i = 0; i < 4; i++) {
11103 status = tr32(TG3_CPMU_MUTEX_GNT);
11104 if (status == CPMU_MUTEX_GNT_DRIVER)
11105 break;
11106 udelay(10);
11107 }
11108
11109 if (status != CPMU_MUTEX_GNT_DRIVER) {
11110 err = TG3_LOOPBACK_FAILED;
11111 goto done;
11112 }
11113
11114 /* Turn off link-based power management. */
11115 cpmuctrl = tr32(TG3_CPMU_CTRL);
11116 tw32(TG3_CPMU_CTRL,
11117 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11118 CPMU_CTRL_LINK_AWARE_MODE));
11119 }
11120
11121 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11122 err |= TG3_MAC_LOOPBACK_FAILED;
11123
11124 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11125 tw32(TG3_CPMU_CTRL, cpmuctrl);
11126
11127 /* Release the mutex */
11128 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11129 }
11130
11131 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11132 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11133 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11134 err |= TG3_PHY_LOOPBACK_FAILED;
11135 }
11136
11137 /* Re-enable gphy autopowerdown. */
11138 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11139 tg3_phy_toggle_apd(tp, true);
11140
11141 done:
11142 tp->phy_flags |= eee_cap;
11143
11144 return err;
11145 }
11146
11147 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11148 u64 *data)
11149 {
11150 struct tg3 *tp = netdev_priv(dev);
11151
11152 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11153 tg3_power_up(tp);
11154
11155 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11156
11157 if (tg3_test_nvram(tp) != 0) {
11158 etest->flags |= ETH_TEST_FL_FAILED;
11159 data[0] = 1;
11160 }
11161 if (tg3_test_link(tp) != 0) {
11162 etest->flags |= ETH_TEST_FL_FAILED;
11163 data[1] = 1;
11164 }
11165 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11166 int err, err2 = 0, irq_sync = 0;
11167
11168 if (netif_running(dev)) {
11169 tg3_phy_stop(tp);
11170 tg3_netif_stop(tp);
11171 irq_sync = 1;
11172 }
11173
11174 tg3_full_lock(tp, irq_sync);
11175
11176 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11177 err = tg3_nvram_lock(tp);
11178 tg3_halt_cpu(tp, RX_CPU_BASE);
11179 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11180 tg3_halt_cpu(tp, TX_CPU_BASE);
11181 if (!err)
11182 tg3_nvram_unlock(tp);
11183
11184 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11185 tg3_phy_reset(tp);
11186
11187 if (tg3_test_registers(tp) != 0) {
11188 etest->flags |= ETH_TEST_FL_FAILED;
11189 data[2] = 1;
11190 }
11191 if (tg3_test_memory(tp) != 0) {
11192 etest->flags |= ETH_TEST_FL_FAILED;
11193 data[3] = 1;
11194 }
11195 if ((data[4] = tg3_test_loopback(tp)) != 0)
11196 etest->flags |= ETH_TEST_FL_FAILED;
11197
11198 tg3_full_unlock(tp);
11199
11200 if (tg3_test_interrupt(tp) != 0) {
11201 etest->flags |= ETH_TEST_FL_FAILED;
11202 data[5] = 1;
11203 }
11204
11205 tg3_full_lock(tp, 0);
11206
11207 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11208 if (netif_running(dev)) {
11209 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11210 err2 = tg3_restart_hw(tp, 1);
11211 if (!err2)
11212 tg3_netif_start(tp);
11213 }
11214
11215 tg3_full_unlock(tp);
11216
11217 if (irq_sync && !err2)
11218 tg3_phy_start(tp);
11219 }
11220 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11221 tg3_power_down(tp);
11222
11223 }
11224
11225 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11226 {
11227 struct mii_ioctl_data *data = if_mii(ifr);
11228 struct tg3 *tp = netdev_priv(dev);
11229 int err;
11230
11231 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11232 struct phy_device *phydev;
11233 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11234 return -EAGAIN;
11235 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11236 return phy_mii_ioctl(phydev, ifr, cmd);
11237 }
11238
11239 switch (cmd) {
11240 case SIOCGMIIPHY:
11241 data->phy_id = tp->phy_addr;
11242
11243 /* fallthru */
11244 case SIOCGMIIREG: {
11245 u32 mii_regval;
11246
11247 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11248 break; /* We have no PHY */
11249
11250 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11251 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11252 !netif_running(dev)))
11253 return -EAGAIN;
11254
11255 spin_lock_bh(&tp->lock);
11256 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11257 spin_unlock_bh(&tp->lock);
11258
11259 data->val_out = mii_regval;
11260
11261 return err;
11262 }
11263
11264 case SIOCSMIIREG:
11265 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11266 break; /* We have no PHY */
11267
11268 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11269 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11270 !netif_running(dev)))
11271 return -EAGAIN;
11272
11273 spin_lock_bh(&tp->lock);
11274 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11275 spin_unlock_bh(&tp->lock);
11276
11277 return err;
11278
11279 default:
11280 /* do nothing */
11281 break;
11282 }
11283 return -EOPNOTSUPP;
11284 }
11285
11286 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11287 {
11288 struct tg3 *tp = netdev_priv(dev);
11289
11290 memcpy(ec, &tp->coal, sizeof(*ec));
11291 return 0;
11292 }
11293
11294 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11295 {
11296 struct tg3 *tp = netdev_priv(dev);
11297 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11298 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11299
11300 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11301 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11302 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11303 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11304 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11305 }
11306
11307 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11308 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11309 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11310 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11311 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11312 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11313 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11314 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11315 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11316 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11317 return -EINVAL;
11318
11319 /* No rx interrupts will be generated if both are zero */
11320 if ((ec->rx_coalesce_usecs == 0) &&
11321 (ec->rx_max_coalesced_frames == 0))
11322 return -EINVAL;
11323
11324 /* No tx interrupts will be generated if both are zero */
11325 if ((ec->tx_coalesce_usecs == 0) &&
11326 (ec->tx_max_coalesced_frames == 0))
11327 return -EINVAL;
11328
11329 /* Only copy relevant parameters, ignore all others. */
11330 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11331 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11332 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11333 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11334 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11335 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11336 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11337 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11338 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11339
11340 if (netif_running(dev)) {
11341 tg3_full_lock(tp, 0);
11342 __tg3_set_coalesce(tp, &tp->coal);
11343 tg3_full_unlock(tp);
11344 }
11345 return 0;
11346 }
11347
11348 static const struct ethtool_ops tg3_ethtool_ops = {
11349 .get_settings = tg3_get_settings,
11350 .set_settings = tg3_set_settings,
11351 .get_drvinfo = tg3_get_drvinfo,
11352 .get_regs_len = tg3_get_regs_len,
11353 .get_regs = tg3_get_regs,
11354 .get_wol = tg3_get_wol,
11355 .set_wol = tg3_set_wol,
11356 .get_msglevel = tg3_get_msglevel,
11357 .set_msglevel = tg3_set_msglevel,
11358 .nway_reset = tg3_nway_reset,
11359 .get_link = ethtool_op_get_link,
11360 .get_eeprom_len = tg3_get_eeprom_len,
11361 .get_eeprom = tg3_get_eeprom,
11362 .set_eeprom = tg3_set_eeprom,
11363 .get_ringparam = tg3_get_ringparam,
11364 .set_ringparam = tg3_set_ringparam,
11365 .get_pauseparam = tg3_get_pauseparam,
11366 .set_pauseparam = tg3_set_pauseparam,
11367 .get_rx_csum = tg3_get_rx_csum,
11368 .set_rx_csum = tg3_set_rx_csum,
11369 .set_tx_csum = tg3_set_tx_csum,
11370 .set_sg = ethtool_op_set_sg,
11371 .set_tso = tg3_set_tso,
11372 .self_test = tg3_self_test,
11373 .get_strings = tg3_get_strings,
11374 .phys_id = tg3_phys_id,
11375 .get_ethtool_stats = tg3_get_ethtool_stats,
11376 .get_coalesce = tg3_get_coalesce,
11377 .set_coalesce = tg3_set_coalesce,
11378 .get_sset_count = tg3_get_sset_count,
11379 };
11380
11381 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11382 {
11383 u32 cursize, val, magic;
11384
11385 tp->nvram_size = EEPROM_CHIP_SIZE;
11386
11387 if (tg3_nvram_read(tp, 0, &magic) != 0)
11388 return;
11389
11390 if ((magic != TG3_EEPROM_MAGIC) &&
11391 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11392 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11393 return;
11394
11395 /*
11396 * Size the chip by reading offsets at increasing powers of two.
11397 * When we encounter our validation signature, we know the addressing
11398 * has wrapped around, and thus have our chip size.
11399 */
11400 cursize = 0x10;
11401
11402 while (cursize < tp->nvram_size) {
11403 if (tg3_nvram_read(tp, cursize, &val) != 0)
11404 return;
11405
11406 if (val == magic)
11407 break;
11408
11409 cursize <<= 1;
11410 }
11411
11412 tp->nvram_size = cursize;
11413 }
11414
11415 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11416 {
11417 u32 val;
11418
11419 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11420 tg3_nvram_read(tp, 0, &val) != 0)
11421 return;
11422
11423 /* Selfboot format */
11424 if (val != TG3_EEPROM_MAGIC) {
11425 tg3_get_eeprom_size(tp);
11426 return;
11427 }
11428
11429 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11430 if (val != 0) {
11431 /* This is confusing. We want to operate on the
11432 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11433 * call will read from NVRAM and byteswap the data
11434 * according to the byteswapping settings for all
11435 * other register accesses. This ensures the data we
11436 * want will always reside in the lower 16-bits.
11437 * However, the data in NVRAM is in LE format, which
11438 * means the data from the NVRAM read will always be
11439 * opposite the endianness of the CPU. The 16-bit
11440 * byteswap then brings the data to CPU endianness.
11441 */
11442 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11443 return;
11444 }
11445 }
11446 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11447 }
11448
11449 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11450 {
11451 u32 nvcfg1;
11452
11453 nvcfg1 = tr32(NVRAM_CFG1);
11454 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11455 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11456 } else {
11457 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11458 tw32(NVRAM_CFG1, nvcfg1);
11459 }
11460
11461 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11462 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11463 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11464 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11465 tp->nvram_jedecnum = JEDEC_ATMEL;
11466 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11467 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11468 break;
11469 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11470 tp->nvram_jedecnum = JEDEC_ATMEL;
11471 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11472 break;
11473 case FLASH_VENDOR_ATMEL_EEPROM:
11474 tp->nvram_jedecnum = JEDEC_ATMEL;
11475 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11476 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477 break;
11478 case FLASH_VENDOR_ST:
11479 tp->nvram_jedecnum = JEDEC_ST;
11480 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11481 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11482 break;
11483 case FLASH_VENDOR_SAIFUN:
11484 tp->nvram_jedecnum = JEDEC_SAIFUN;
11485 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11486 break;
11487 case FLASH_VENDOR_SST_SMALL:
11488 case FLASH_VENDOR_SST_LARGE:
11489 tp->nvram_jedecnum = JEDEC_SST;
11490 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11491 break;
11492 }
11493 } else {
11494 tp->nvram_jedecnum = JEDEC_ATMEL;
11495 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11496 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497 }
11498 }
11499
11500 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11501 {
11502 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11503 case FLASH_5752PAGE_SIZE_256:
11504 tp->nvram_pagesize = 256;
11505 break;
11506 case FLASH_5752PAGE_SIZE_512:
11507 tp->nvram_pagesize = 512;
11508 break;
11509 case FLASH_5752PAGE_SIZE_1K:
11510 tp->nvram_pagesize = 1024;
11511 break;
11512 case FLASH_5752PAGE_SIZE_2K:
11513 tp->nvram_pagesize = 2048;
11514 break;
11515 case FLASH_5752PAGE_SIZE_4K:
11516 tp->nvram_pagesize = 4096;
11517 break;
11518 case FLASH_5752PAGE_SIZE_264:
11519 tp->nvram_pagesize = 264;
11520 break;
11521 case FLASH_5752PAGE_SIZE_528:
11522 tp->nvram_pagesize = 528;
11523 break;
11524 }
11525 }
11526
11527 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11528 {
11529 u32 nvcfg1;
11530
11531 nvcfg1 = tr32(NVRAM_CFG1);
11532
11533 /* NVRAM protection for TPM */
11534 if (nvcfg1 & (1 << 27))
11535 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11536
11537 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11538 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11539 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11540 tp->nvram_jedecnum = JEDEC_ATMEL;
11541 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11542 break;
11543 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11544 tp->nvram_jedecnum = JEDEC_ATMEL;
11545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11547 break;
11548 case FLASH_5752VENDOR_ST_M45PE10:
11549 case FLASH_5752VENDOR_ST_M45PE20:
11550 case FLASH_5752VENDOR_ST_M45PE40:
11551 tp->nvram_jedecnum = JEDEC_ST;
11552 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11553 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11554 break;
11555 }
11556
11557 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11558 tg3_nvram_get_pagesize(tp, nvcfg1);
11559 } else {
11560 /* For eeprom, set pagesize to maximum eeprom size */
11561 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11562
11563 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11564 tw32(NVRAM_CFG1, nvcfg1);
11565 }
11566 }
11567
11568 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11569 {
11570 u32 nvcfg1, protect = 0;
11571
11572 nvcfg1 = tr32(NVRAM_CFG1);
11573
11574 /* NVRAM protection for TPM */
11575 if (nvcfg1 & (1 << 27)) {
11576 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11577 protect = 1;
11578 }
11579
11580 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11581 switch (nvcfg1) {
11582 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11583 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11584 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11585 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11586 tp->nvram_jedecnum = JEDEC_ATMEL;
11587 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11588 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11589 tp->nvram_pagesize = 264;
11590 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11591 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11592 tp->nvram_size = (protect ? 0x3e200 :
11593 TG3_NVRAM_SIZE_512KB);
11594 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11595 tp->nvram_size = (protect ? 0x1f200 :
11596 TG3_NVRAM_SIZE_256KB);
11597 else
11598 tp->nvram_size = (protect ? 0x1f200 :
11599 TG3_NVRAM_SIZE_128KB);
11600 break;
11601 case FLASH_5752VENDOR_ST_M45PE10:
11602 case FLASH_5752VENDOR_ST_M45PE20:
11603 case FLASH_5752VENDOR_ST_M45PE40:
11604 tp->nvram_jedecnum = JEDEC_ST;
11605 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11606 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11607 tp->nvram_pagesize = 256;
11608 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11609 tp->nvram_size = (protect ?
11610 TG3_NVRAM_SIZE_64KB :
11611 TG3_NVRAM_SIZE_128KB);
11612 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11613 tp->nvram_size = (protect ?
11614 TG3_NVRAM_SIZE_64KB :
11615 TG3_NVRAM_SIZE_256KB);
11616 else
11617 tp->nvram_size = (protect ?
11618 TG3_NVRAM_SIZE_128KB :
11619 TG3_NVRAM_SIZE_512KB);
11620 break;
11621 }
11622 }
11623
11624 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11625 {
11626 u32 nvcfg1;
11627
11628 nvcfg1 = tr32(NVRAM_CFG1);
11629
11630 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11631 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11632 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11633 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11634 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11635 tp->nvram_jedecnum = JEDEC_ATMEL;
11636 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11637 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11638
11639 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11640 tw32(NVRAM_CFG1, nvcfg1);
11641 break;
11642 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11643 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11644 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11645 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11646 tp->nvram_jedecnum = JEDEC_ATMEL;
11647 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11648 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11649 tp->nvram_pagesize = 264;
11650 break;
11651 case FLASH_5752VENDOR_ST_M45PE10:
11652 case FLASH_5752VENDOR_ST_M45PE20:
11653 case FLASH_5752VENDOR_ST_M45PE40:
11654 tp->nvram_jedecnum = JEDEC_ST;
11655 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11656 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11657 tp->nvram_pagesize = 256;
11658 break;
11659 }
11660 }
11661
11662 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11663 {
11664 u32 nvcfg1, protect = 0;
11665
11666 nvcfg1 = tr32(NVRAM_CFG1);
11667
11668 /* NVRAM protection for TPM */
11669 if (nvcfg1 & (1 << 27)) {
11670 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11671 protect = 1;
11672 }
11673
11674 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11675 switch (nvcfg1) {
11676 case FLASH_5761VENDOR_ATMEL_ADB021D:
11677 case FLASH_5761VENDOR_ATMEL_ADB041D:
11678 case FLASH_5761VENDOR_ATMEL_ADB081D:
11679 case FLASH_5761VENDOR_ATMEL_ADB161D:
11680 case FLASH_5761VENDOR_ATMEL_MDB021D:
11681 case FLASH_5761VENDOR_ATMEL_MDB041D:
11682 case FLASH_5761VENDOR_ATMEL_MDB081D:
11683 case FLASH_5761VENDOR_ATMEL_MDB161D:
11684 tp->nvram_jedecnum = JEDEC_ATMEL;
11685 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11686 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11687 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11688 tp->nvram_pagesize = 256;
11689 break;
11690 case FLASH_5761VENDOR_ST_A_M45PE20:
11691 case FLASH_5761VENDOR_ST_A_M45PE40:
11692 case FLASH_5761VENDOR_ST_A_M45PE80:
11693 case FLASH_5761VENDOR_ST_A_M45PE16:
11694 case FLASH_5761VENDOR_ST_M_M45PE20:
11695 case FLASH_5761VENDOR_ST_M_M45PE40:
11696 case FLASH_5761VENDOR_ST_M_M45PE80:
11697 case FLASH_5761VENDOR_ST_M_M45PE16:
11698 tp->nvram_jedecnum = JEDEC_ST;
11699 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11700 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11701 tp->nvram_pagesize = 256;
11702 break;
11703 }
11704
11705 if (protect) {
11706 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11707 } else {
11708 switch (nvcfg1) {
11709 case FLASH_5761VENDOR_ATMEL_ADB161D:
11710 case FLASH_5761VENDOR_ATMEL_MDB161D:
11711 case FLASH_5761VENDOR_ST_A_M45PE16:
11712 case FLASH_5761VENDOR_ST_M_M45PE16:
11713 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11714 break;
11715 case FLASH_5761VENDOR_ATMEL_ADB081D:
11716 case FLASH_5761VENDOR_ATMEL_MDB081D:
11717 case FLASH_5761VENDOR_ST_A_M45PE80:
11718 case FLASH_5761VENDOR_ST_M_M45PE80:
11719 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11720 break;
11721 case FLASH_5761VENDOR_ATMEL_ADB041D:
11722 case FLASH_5761VENDOR_ATMEL_MDB041D:
11723 case FLASH_5761VENDOR_ST_A_M45PE40:
11724 case FLASH_5761VENDOR_ST_M_M45PE40:
11725 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11726 break;
11727 case FLASH_5761VENDOR_ATMEL_ADB021D:
11728 case FLASH_5761VENDOR_ATMEL_MDB021D:
11729 case FLASH_5761VENDOR_ST_A_M45PE20:
11730 case FLASH_5761VENDOR_ST_M_M45PE20:
11731 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11732 break;
11733 }
11734 }
11735 }
11736
11737 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11738 {
11739 tp->nvram_jedecnum = JEDEC_ATMEL;
11740 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11741 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11742 }
11743
11744 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11745 {
11746 u32 nvcfg1;
11747
11748 nvcfg1 = tr32(NVRAM_CFG1);
11749
11750 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11751 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11752 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11753 tp->nvram_jedecnum = JEDEC_ATMEL;
11754 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11756
11757 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11758 tw32(NVRAM_CFG1, nvcfg1);
11759 return;
11760 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11761 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11762 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11763 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11764 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11765 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11766 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11767 tp->nvram_jedecnum = JEDEC_ATMEL;
11768 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11769 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11770
11771 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11772 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11773 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11774 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11775 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11776 break;
11777 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11778 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11779 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11780 break;
11781 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11782 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11783 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11784 break;
11785 }
11786 break;
11787 case FLASH_5752VENDOR_ST_M45PE10:
11788 case FLASH_5752VENDOR_ST_M45PE20:
11789 case FLASH_5752VENDOR_ST_M45PE40:
11790 tp->nvram_jedecnum = JEDEC_ST;
11791 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11792 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11793
11794 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11795 case FLASH_5752VENDOR_ST_M45PE10:
11796 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11797 break;
11798 case FLASH_5752VENDOR_ST_M45PE20:
11799 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11800 break;
11801 case FLASH_5752VENDOR_ST_M45PE40:
11802 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11803 break;
11804 }
11805 break;
11806 default:
11807 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11808 return;
11809 }
11810
11811 tg3_nvram_get_pagesize(tp, nvcfg1);
11812 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11813 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11814 }
11815
11816
11817 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11818 {
11819 u32 nvcfg1;
11820
11821 nvcfg1 = tr32(NVRAM_CFG1);
11822
11823 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11824 case FLASH_5717VENDOR_ATMEL_EEPROM:
11825 case FLASH_5717VENDOR_MICRO_EEPROM:
11826 tp->nvram_jedecnum = JEDEC_ATMEL;
11827 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11828 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11829
11830 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11831 tw32(NVRAM_CFG1, nvcfg1);
11832 return;
11833 case FLASH_5717VENDOR_ATMEL_MDB011D:
11834 case FLASH_5717VENDOR_ATMEL_ADB011B:
11835 case FLASH_5717VENDOR_ATMEL_ADB011D:
11836 case FLASH_5717VENDOR_ATMEL_MDB021D:
11837 case FLASH_5717VENDOR_ATMEL_ADB021B:
11838 case FLASH_5717VENDOR_ATMEL_ADB021D:
11839 case FLASH_5717VENDOR_ATMEL_45USPT:
11840 tp->nvram_jedecnum = JEDEC_ATMEL;
11841 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11842 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11843
11844 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11845 case FLASH_5717VENDOR_ATMEL_MDB021D:
11846 case FLASH_5717VENDOR_ATMEL_ADB021B:
11847 case FLASH_5717VENDOR_ATMEL_ADB021D:
11848 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11849 break;
11850 default:
11851 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11852 break;
11853 }
11854 break;
11855 case FLASH_5717VENDOR_ST_M_M25PE10:
11856 case FLASH_5717VENDOR_ST_A_M25PE10:
11857 case FLASH_5717VENDOR_ST_M_M45PE10:
11858 case FLASH_5717VENDOR_ST_A_M45PE10:
11859 case FLASH_5717VENDOR_ST_M_M25PE20:
11860 case FLASH_5717VENDOR_ST_A_M25PE20:
11861 case FLASH_5717VENDOR_ST_M_M45PE20:
11862 case FLASH_5717VENDOR_ST_A_M45PE20:
11863 case FLASH_5717VENDOR_ST_25USPT:
11864 case FLASH_5717VENDOR_ST_45USPT:
11865 tp->nvram_jedecnum = JEDEC_ST;
11866 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11867 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11868
11869 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11870 case FLASH_5717VENDOR_ST_M_M25PE20:
11871 case FLASH_5717VENDOR_ST_A_M25PE20:
11872 case FLASH_5717VENDOR_ST_M_M45PE20:
11873 case FLASH_5717VENDOR_ST_A_M45PE20:
11874 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11875 break;
11876 default:
11877 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11878 break;
11879 }
11880 break;
11881 default:
11882 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11883 return;
11884 }
11885
11886 tg3_nvram_get_pagesize(tp, nvcfg1);
11887 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11888 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11889 }
11890
11891 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11892 static void __devinit tg3_nvram_init(struct tg3 *tp)
11893 {
11894 tw32_f(GRC_EEPROM_ADDR,
11895 (EEPROM_ADDR_FSM_RESET |
11896 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11897 EEPROM_ADDR_CLKPERD_SHIFT)));
11898
11899 msleep(1);
11900
11901 /* Enable seeprom accesses. */
11902 tw32_f(GRC_LOCAL_CTRL,
11903 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11904 udelay(100);
11905
11906 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11907 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11908 tp->tg3_flags |= TG3_FLAG_NVRAM;
11909
11910 if (tg3_nvram_lock(tp)) {
11911 netdev_warn(tp->dev,
11912 "Cannot get nvram lock, %s failed\n",
11913 __func__);
11914 return;
11915 }
11916 tg3_enable_nvram_access(tp);
11917
11918 tp->nvram_size = 0;
11919
11920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11921 tg3_get_5752_nvram_info(tp);
11922 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11923 tg3_get_5755_nvram_info(tp);
11924 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11926 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11927 tg3_get_5787_nvram_info(tp);
11928 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11929 tg3_get_5761_nvram_info(tp);
11930 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11931 tg3_get_5906_nvram_info(tp);
11932 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11934 tg3_get_57780_nvram_info(tp);
11935 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11937 tg3_get_5717_nvram_info(tp);
11938 else
11939 tg3_get_nvram_info(tp);
11940
11941 if (tp->nvram_size == 0)
11942 tg3_get_nvram_size(tp);
11943
11944 tg3_disable_nvram_access(tp);
11945 tg3_nvram_unlock(tp);
11946
11947 } else {
11948 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11949
11950 tg3_get_eeprom_size(tp);
11951 }
11952 }
11953
11954 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11955 u32 offset, u32 len, u8 *buf)
11956 {
11957 int i, j, rc = 0;
11958 u32 val;
11959
11960 for (i = 0; i < len; i += 4) {
11961 u32 addr;
11962 __be32 data;
11963
11964 addr = offset + i;
11965
11966 memcpy(&data, buf + i, 4);
11967
11968 /*
11969 * The SEEPROM interface expects the data to always be opposite
11970 * the native endian format. We accomplish this by reversing
11971 * all the operations that would have been performed on the
11972 * data from a call to tg3_nvram_read_be32().
11973 */
11974 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11975
11976 val = tr32(GRC_EEPROM_ADDR);
11977 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11978
11979 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11980 EEPROM_ADDR_READ);
11981 tw32(GRC_EEPROM_ADDR, val |
11982 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11983 (addr & EEPROM_ADDR_ADDR_MASK) |
11984 EEPROM_ADDR_START |
11985 EEPROM_ADDR_WRITE);
11986
11987 for (j = 0; j < 1000; j++) {
11988 val = tr32(GRC_EEPROM_ADDR);
11989
11990 if (val & EEPROM_ADDR_COMPLETE)
11991 break;
11992 msleep(1);
11993 }
11994 if (!(val & EEPROM_ADDR_COMPLETE)) {
11995 rc = -EBUSY;
11996 break;
11997 }
11998 }
11999
12000 return rc;
12001 }
12002
12003 /* offset and length are dword aligned */
12004 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12005 u8 *buf)
12006 {
12007 int ret = 0;
12008 u32 pagesize = tp->nvram_pagesize;
12009 u32 pagemask = pagesize - 1;
12010 u32 nvram_cmd;
12011 u8 *tmp;
12012
12013 tmp = kmalloc(pagesize, GFP_KERNEL);
12014 if (tmp == NULL)
12015 return -ENOMEM;
12016
12017 while (len) {
12018 int j;
12019 u32 phy_addr, page_off, size;
12020
12021 phy_addr = offset & ~pagemask;
12022
12023 for (j = 0; j < pagesize; j += 4) {
12024 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12025 (__be32 *) (tmp + j));
12026 if (ret)
12027 break;
12028 }
12029 if (ret)
12030 break;
12031
12032 page_off = offset & pagemask;
12033 size = pagesize;
12034 if (len < size)
12035 size = len;
12036
12037 len -= size;
12038
12039 memcpy(tmp + page_off, buf, size);
12040
12041 offset = offset + (pagesize - page_off);
12042
12043 tg3_enable_nvram_access(tp);
12044
12045 /*
12046 * Before we can erase the flash page, we need
12047 * to issue a special "write enable" command.
12048 */
12049 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12050
12051 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12052 break;
12053
12054 /* Erase the target page */
12055 tw32(NVRAM_ADDR, phy_addr);
12056
12057 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12058 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12059
12060 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12061 break;
12062
12063 /* Issue another write enable to start the write. */
12064 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12065
12066 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12067 break;
12068
12069 for (j = 0; j < pagesize; j += 4) {
12070 __be32 data;
12071
12072 data = *((__be32 *) (tmp + j));
12073
12074 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12075
12076 tw32(NVRAM_ADDR, phy_addr + j);
12077
12078 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12079 NVRAM_CMD_WR;
12080
12081 if (j == 0)
12082 nvram_cmd |= NVRAM_CMD_FIRST;
12083 else if (j == (pagesize - 4))
12084 nvram_cmd |= NVRAM_CMD_LAST;
12085
12086 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12087 break;
12088 }
12089 if (ret)
12090 break;
12091 }
12092
12093 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12094 tg3_nvram_exec_cmd(tp, nvram_cmd);
12095
12096 kfree(tmp);
12097
12098 return ret;
12099 }
12100
12101 /* offset and length are dword aligned */
12102 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12103 u8 *buf)
12104 {
12105 int i, ret = 0;
12106
12107 for (i = 0; i < len; i += 4, offset += 4) {
12108 u32 page_off, phy_addr, nvram_cmd;
12109 __be32 data;
12110
12111 memcpy(&data, buf + i, 4);
12112 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12113
12114 page_off = offset % tp->nvram_pagesize;
12115
12116 phy_addr = tg3_nvram_phys_addr(tp, offset);
12117
12118 tw32(NVRAM_ADDR, phy_addr);
12119
12120 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12121
12122 if (page_off == 0 || i == 0)
12123 nvram_cmd |= NVRAM_CMD_FIRST;
12124 if (page_off == (tp->nvram_pagesize - 4))
12125 nvram_cmd |= NVRAM_CMD_LAST;
12126
12127 if (i == (len - 4))
12128 nvram_cmd |= NVRAM_CMD_LAST;
12129
12130 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12131 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12132 (tp->nvram_jedecnum == JEDEC_ST) &&
12133 (nvram_cmd & NVRAM_CMD_FIRST)) {
12134
12135 if ((ret = tg3_nvram_exec_cmd(tp,
12136 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12137 NVRAM_CMD_DONE)))
12138
12139 break;
12140 }
12141 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12142 /* We always do complete word writes to eeprom. */
12143 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12144 }
12145
12146 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12147 break;
12148 }
12149 return ret;
12150 }
12151
12152 /* offset and length are dword aligned */
12153 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12154 {
12155 int ret;
12156
12157 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12158 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12159 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12160 udelay(40);
12161 }
12162
12163 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12164 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12165 } else {
12166 u32 grc_mode;
12167
12168 ret = tg3_nvram_lock(tp);
12169 if (ret)
12170 return ret;
12171
12172 tg3_enable_nvram_access(tp);
12173 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12174 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12175 tw32(NVRAM_WRITE1, 0x406);
12176
12177 grc_mode = tr32(GRC_MODE);
12178 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12179
12180 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12181 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12182
12183 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12184 buf);
12185 } else {
12186 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12187 buf);
12188 }
12189
12190 grc_mode = tr32(GRC_MODE);
12191 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12192
12193 tg3_disable_nvram_access(tp);
12194 tg3_nvram_unlock(tp);
12195 }
12196
12197 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12198 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12199 udelay(40);
12200 }
12201
12202 return ret;
12203 }
12204
12205 struct subsys_tbl_ent {
12206 u16 subsys_vendor, subsys_devid;
12207 u32 phy_id;
12208 };
12209
12210 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12211 /* Broadcom boards. */
12212 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12213 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12214 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12215 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12216 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12217 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12218 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12219 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12220 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12221 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12222 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12223 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12224 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12225 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12226 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12227 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12228 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12229 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12230 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12231 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12232 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12233 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12234
12235 /* 3com boards. */
12236 { TG3PCI_SUBVENDOR_ID_3COM,
12237 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12238 { TG3PCI_SUBVENDOR_ID_3COM,
12239 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12240 { TG3PCI_SUBVENDOR_ID_3COM,
12241 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12242 { TG3PCI_SUBVENDOR_ID_3COM,
12243 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12244 { TG3PCI_SUBVENDOR_ID_3COM,
12245 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12246
12247 /* DELL boards. */
12248 { TG3PCI_SUBVENDOR_ID_DELL,
12249 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12250 { TG3PCI_SUBVENDOR_ID_DELL,
12251 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12252 { TG3PCI_SUBVENDOR_ID_DELL,
12253 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12254 { TG3PCI_SUBVENDOR_ID_DELL,
12255 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12256
12257 /* Compaq boards. */
12258 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12259 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12260 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12261 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12262 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12263 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12264 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12265 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12266 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12267 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12268
12269 /* IBM boards. */
12270 { TG3PCI_SUBVENDOR_ID_IBM,
12271 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12272 };
12273
12274 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12275 {
12276 int i;
12277
12278 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12279 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12280 tp->pdev->subsystem_vendor) &&
12281 (subsys_id_to_phy_id[i].subsys_devid ==
12282 tp->pdev->subsystem_device))
12283 return &subsys_id_to_phy_id[i];
12284 }
12285 return NULL;
12286 }
12287
12288 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12289 {
12290 u32 val;
12291 u16 pmcsr;
12292
12293 /* On some early chips the SRAM cannot be accessed in D3hot state,
12294 * so need make sure we're in D0.
12295 */
12296 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12297 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12298 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12299 msleep(1);
12300
12301 /* Make sure register accesses (indirect or otherwise)
12302 * will function correctly.
12303 */
12304 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12305 tp->misc_host_ctrl);
12306
12307 /* The memory arbiter has to be enabled in order for SRAM accesses
12308 * to succeed. Normally on powerup the tg3 chip firmware will make
12309 * sure it is enabled, but other entities such as system netboot
12310 * code might disable it.
12311 */
12312 val = tr32(MEMARB_MODE);
12313 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12314
12315 tp->phy_id = TG3_PHY_ID_INVALID;
12316 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12317
12318 /* Assume an onboard device and WOL capable by default. */
12319 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12320
12321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12322 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12323 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12324 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12325 }
12326 val = tr32(VCPU_CFGSHDW);
12327 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12328 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12329 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12330 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12331 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12332 goto done;
12333 }
12334
12335 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12336 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12337 u32 nic_cfg, led_cfg;
12338 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12339 int eeprom_phy_serdes = 0;
12340
12341 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12342 tp->nic_sram_data_cfg = nic_cfg;
12343
12344 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12345 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12347 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12348 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12349 (ver > 0) && (ver < 0x100))
12350 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12351
12352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12353 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12354
12355 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12356 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12357 eeprom_phy_serdes = 1;
12358
12359 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12360 if (nic_phy_id != 0) {
12361 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12362 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12363
12364 eeprom_phy_id = (id1 >> 16) << 10;
12365 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12366 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12367 } else
12368 eeprom_phy_id = 0;
12369
12370 tp->phy_id = eeprom_phy_id;
12371 if (eeprom_phy_serdes) {
12372 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12373 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12374 else
12375 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12376 }
12377
12378 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12379 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12380 SHASTA_EXT_LED_MODE_MASK);
12381 else
12382 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12383
12384 switch (led_cfg) {
12385 default:
12386 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12387 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12388 break;
12389
12390 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12391 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12392 break;
12393
12394 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12395 tp->led_ctrl = LED_CTRL_MODE_MAC;
12396
12397 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12398 * read on some older 5700/5701 bootcode.
12399 */
12400 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12401 ASIC_REV_5700 ||
12402 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12403 ASIC_REV_5701)
12404 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12405
12406 break;
12407
12408 case SHASTA_EXT_LED_SHARED:
12409 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12410 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12411 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12412 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12413 LED_CTRL_MODE_PHY_2);
12414 break;
12415
12416 case SHASTA_EXT_LED_MAC:
12417 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12418 break;
12419
12420 case SHASTA_EXT_LED_COMBO:
12421 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12422 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12423 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12424 LED_CTRL_MODE_PHY_2);
12425 break;
12426
12427 }
12428
12429 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12430 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12431 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12432 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12433
12434 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12435 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12436
12437 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12438 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12439 if ((tp->pdev->subsystem_vendor ==
12440 PCI_VENDOR_ID_ARIMA) &&
12441 (tp->pdev->subsystem_device == 0x205a ||
12442 tp->pdev->subsystem_device == 0x2063))
12443 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12444 } else {
12445 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12446 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12447 }
12448
12449 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12450 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12451 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12452 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12453 }
12454
12455 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12456 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12457 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12458
12459 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12460 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12461 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12462
12463 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12464 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12465 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12466
12467 if (cfg2 & (1 << 17))
12468 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12469
12470 /* serdes signal pre-emphasis in register 0x590 set by */
12471 /* bootcode if bit 18 is set */
12472 if (cfg2 & (1 << 18))
12473 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12474
12475 if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
12476 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12477 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12478 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12479 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12480
12481 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12482 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12483 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12484 u32 cfg3;
12485
12486 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12487 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12488 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12489 }
12490
12491 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12492 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12493 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12494 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12495 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12496 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12497 }
12498 done:
12499 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12500 device_set_wakeup_enable(&tp->pdev->dev,
12501 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12502 else
12503 device_set_wakeup_capable(&tp->pdev->dev, false);
12504 }
12505
12506 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12507 {
12508 int i;
12509 u32 val;
12510
12511 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12512 tw32(OTP_CTRL, cmd);
12513
12514 /* Wait for up to 1 ms for command to execute. */
12515 for (i = 0; i < 100; i++) {
12516 val = tr32(OTP_STATUS);
12517 if (val & OTP_STATUS_CMD_DONE)
12518 break;
12519 udelay(10);
12520 }
12521
12522 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12523 }
12524
12525 /* Read the gphy configuration from the OTP region of the chip. The gphy
12526 * configuration is a 32-bit value that straddles the alignment boundary.
12527 * We do two 32-bit reads and then shift and merge the results.
12528 */
12529 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12530 {
12531 u32 bhalf_otp, thalf_otp;
12532
12533 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12534
12535 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12536 return 0;
12537
12538 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12539
12540 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12541 return 0;
12542
12543 thalf_otp = tr32(OTP_READ_DATA);
12544
12545 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12546
12547 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12548 return 0;
12549
12550 bhalf_otp = tr32(OTP_READ_DATA);
12551
12552 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12553 }
12554
12555 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12556 {
12557 u32 adv = ADVERTISED_Autoneg |
12558 ADVERTISED_Pause;
12559
12560 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12561 adv |= ADVERTISED_1000baseT_Half |
12562 ADVERTISED_1000baseT_Full;
12563
12564 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12565 adv |= ADVERTISED_100baseT_Half |
12566 ADVERTISED_100baseT_Full |
12567 ADVERTISED_10baseT_Half |
12568 ADVERTISED_10baseT_Full |
12569 ADVERTISED_TP;
12570 else
12571 adv |= ADVERTISED_FIBRE;
12572
12573 tp->link_config.advertising = adv;
12574 tp->link_config.speed = SPEED_INVALID;
12575 tp->link_config.duplex = DUPLEX_INVALID;
12576 tp->link_config.autoneg = AUTONEG_ENABLE;
12577 tp->link_config.active_speed = SPEED_INVALID;
12578 tp->link_config.active_duplex = DUPLEX_INVALID;
12579 tp->link_config.orig_speed = SPEED_INVALID;
12580 tp->link_config.orig_duplex = DUPLEX_INVALID;
12581 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12582 }
12583
12584 static int __devinit tg3_phy_probe(struct tg3 *tp)
12585 {
12586 u32 hw_phy_id_1, hw_phy_id_2;
12587 u32 hw_phy_id, hw_phy_id_masked;
12588 int err;
12589
12590 /* flow control autonegotiation is default behavior */
12591 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12592 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12593
12594 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12595 return tg3_phy_init(tp);
12596
12597 /* Reading the PHY ID register can conflict with ASF
12598 * firmware access to the PHY hardware.
12599 */
12600 err = 0;
12601 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12602 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12603 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12604 } else {
12605 /* Now read the physical PHY_ID from the chip and verify
12606 * that it is sane. If it doesn't look good, we fall back
12607 * to either the hard-coded table based PHY_ID and failing
12608 * that the value found in the eeprom area.
12609 */
12610 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12611 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12612
12613 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12614 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12615 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12616
12617 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12618 }
12619
12620 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12621 tp->phy_id = hw_phy_id;
12622 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12623 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12624 else
12625 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12626 } else {
12627 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12628 /* Do nothing, phy ID already set up in
12629 * tg3_get_eeprom_hw_cfg().
12630 */
12631 } else {
12632 struct subsys_tbl_ent *p;
12633
12634 /* No eeprom signature? Try the hardcoded
12635 * subsys device table.
12636 */
12637 p = tg3_lookup_by_subsys(tp);
12638 if (!p)
12639 return -ENODEV;
12640
12641 tp->phy_id = p->phy_id;
12642 if (!tp->phy_id ||
12643 tp->phy_id == TG3_PHY_ID_BCM8002)
12644 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12645 }
12646 }
12647
12648 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12649 ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12650 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12651 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12652 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12653 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12654
12655 tg3_phy_init_link_config(tp);
12656
12657 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12658 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12659 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12660 u32 bmsr, adv_reg, tg3_ctrl, mask;
12661
12662 tg3_readphy(tp, MII_BMSR, &bmsr);
12663 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12664 (bmsr & BMSR_LSTATUS))
12665 goto skip_phy_reset;
12666
12667 err = tg3_phy_reset(tp);
12668 if (err)
12669 return err;
12670
12671 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12672 ADVERTISE_100HALF | ADVERTISE_100FULL |
12673 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12674 tg3_ctrl = 0;
12675 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12676 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12677 MII_TG3_CTRL_ADV_1000_FULL);
12678 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12679 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12680 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12681 MII_TG3_CTRL_ENABLE_AS_MASTER);
12682 }
12683
12684 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12685 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12686 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12687 if (!tg3_copper_is_advertising_all(tp, mask)) {
12688 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12689
12690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12691 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12692
12693 tg3_writephy(tp, MII_BMCR,
12694 BMCR_ANENABLE | BMCR_ANRESTART);
12695 }
12696 tg3_phy_set_wirespeed(tp);
12697
12698 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12699 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12700 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12701 }
12702
12703 skip_phy_reset:
12704 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12705 err = tg3_init_5401phy_dsp(tp);
12706 if (err)
12707 return err;
12708
12709 err = tg3_init_5401phy_dsp(tp);
12710 }
12711
12712 return err;
12713 }
12714
12715 static void __devinit tg3_read_vpd(struct tg3 *tp)
12716 {
12717 u8 *vpd_data;
12718 unsigned int block_end, rosize, len;
12719 int j, i = 0;
12720 u32 magic;
12721
12722 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12723 tg3_nvram_read(tp, 0x0, &magic))
12724 goto out_no_vpd;
12725
12726 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12727 if (!vpd_data)
12728 goto out_no_vpd;
12729
12730 if (magic == TG3_EEPROM_MAGIC) {
12731 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12732 u32 tmp;
12733
12734 /* The data is in little-endian format in NVRAM.
12735 * Use the big-endian read routines to preserve
12736 * the byte order as it exists in NVRAM.
12737 */
12738 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12739 goto out_not_found;
12740
12741 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12742 }
12743 } else {
12744 ssize_t cnt;
12745 unsigned int pos = 0;
12746
12747 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12748 cnt = pci_read_vpd(tp->pdev, pos,
12749 TG3_NVM_VPD_LEN - pos,
12750 &vpd_data[pos]);
12751 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12752 cnt = 0;
12753 else if (cnt < 0)
12754 goto out_not_found;
12755 }
12756 if (pos != TG3_NVM_VPD_LEN)
12757 goto out_not_found;
12758 }
12759
12760 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12761 PCI_VPD_LRDT_RO_DATA);
12762 if (i < 0)
12763 goto out_not_found;
12764
12765 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12766 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12767 i += PCI_VPD_LRDT_TAG_SIZE;
12768
12769 if (block_end > TG3_NVM_VPD_LEN)
12770 goto out_not_found;
12771
12772 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12773 PCI_VPD_RO_KEYWORD_MFR_ID);
12774 if (j > 0) {
12775 len = pci_vpd_info_field_size(&vpd_data[j]);
12776
12777 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12778 if (j + len > block_end || len != 4 ||
12779 memcmp(&vpd_data[j], "1028", 4))
12780 goto partno;
12781
12782 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12783 PCI_VPD_RO_KEYWORD_VENDOR0);
12784 if (j < 0)
12785 goto partno;
12786
12787 len = pci_vpd_info_field_size(&vpd_data[j]);
12788
12789 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12790 if (j + len > block_end)
12791 goto partno;
12792
12793 memcpy(tp->fw_ver, &vpd_data[j], len);
12794 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12795 }
12796
12797 partno:
12798 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12799 PCI_VPD_RO_KEYWORD_PARTNO);
12800 if (i < 0)
12801 goto out_not_found;
12802
12803 len = pci_vpd_info_field_size(&vpd_data[i]);
12804
12805 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12806 if (len > TG3_BPN_SIZE ||
12807 (len + i) > TG3_NVM_VPD_LEN)
12808 goto out_not_found;
12809
12810 memcpy(tp->board_part_number, &vpd_data[i], len);
12811
12812 out_not_found:
12813 kfree(vpd_data);
12814 if (tp->board_part_number[0])
12815 return;
12816
12817 out_no_vpd:
12818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12819 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12820 strcpy(tp->board_part_number, "BCM5717");
12821 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12822 strcpy(tp->board_part_number, "BCM5718");
12823 else
12824 goto nomatch;
12825 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12826 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12827 strcpy(tp->board_part_number, "BCM57780");
12828 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12829 strcpy(tp->board_part_number, "BCM57760");
12830 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12831 strcpy(tp->board_part_number, "BCM57790");
12832 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12833 strcpy(tp->board_part_number, "BCM57788");
12834 else
12835 goto nomatch;
12836 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12837 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12838 strcpy(tp->board_part_number, "BCM57761");
12839 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12840 strcpy(tp->board_part_number, "BCM57765");
12841 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12842 strcpy(tp->board_part_number, "BCM57781");
12843 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12844 strcpy(tp->board_part_number, "BCM57785");
12845 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12846 strcpy(tp->board_part_number, "BCM57791");
12847 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12848 strcpy(tp->board_part_number, "BCM57795");
12849 else
12850 goto nomatch;
12851 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12852 strcpy(tp->board_part_number, "BCM95906");
12853 } else {
12854 nomatch:
12855 strcpy(tp->board_part_number, "none");
12856 }
12857 }
12858
12859 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12860 {
12861 u32 val;
12862
12863 if (tg3_nvram_read(tp, offset, &val) ||
12864 (val & 0xfc000000) != 0x0c000000 ||
12865 tg3_nvram_read(tp, offset + 4, &val) ||
12866 val != 0)
12867 return 0;
12868
12869 return 1;
12870 }
12871
12872 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12873 {
12874 u32 val, offset, start, ver_offset;
12875 int i, dst_off;
12876 bool newver = false;
12877
12878 if (tg3_nvram_read(tp, 0xc, &offset) ||
12879 tg3_nvram_read(tp, 0x4, &start))
12880 return;
12881
12882 offset = tg3_nvram_logical_addr(tp, offset);
12883
12884 if (tg3_nvram_read(tp, offset, &val))
12885 return;
12886
12887 if ((val & 0xfc000000) == 0x0c000000) {
12888 if (tg3_nvram_read(tp, offset + 4, &val))
12889 return;
12890
12891 if (val == 0)
12892 newver = true;
12893 }
12894
12895 dst_off = strlen(tp->fw_ver);
12896
12897 if (newver) {
12898 if (TG3_VER_SIZE - dst_off < 16 ||
12899 tg3_nvram_read(tp, offset + 8, &ver_offset))
12900 return;
12901
12902 offset = offset + ver_offset - start;
12903 for (i = 0; i < 16; i += 4) {
12904 __be32 v;
12905 if (tg3_nvram_read_be32(tp, offset + i, &v))
12906 return;
12907
12908 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12909 }
12910 } else {
12911 u32 major, minor;
12912
12913 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12914 return;
12915
12916 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12917 TG3_NVM_BCVER_MAJSFT;
12918 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12919 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12920 "v%d.%02d", major, minor);
12921 }
12922 }
12923
12924 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12925 {
12926 u32 val, major, minor;
12927
12928 /* Use native endian representation */
12929 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12930 return;
12931
12932 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12933 TG3_NVM_HWSB_CFG1_MAJSFT;
12934 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12935 TG3_NVM_HWSB_CFG1_MINSFT;
12936
12937 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12938 }
12939
12940 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12941 {
12942 u32 offset, major, minor, build;
12943
12944 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12945
12946 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12947 return;
12948
12949 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12950 case TG3_EEPROM_SB_REVISION_0:
12951 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12952 break;
12953 case TG3_EEPROM_SB_REVISION_2:
12954 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12955 break;
12956 case TG3_EEPROM_SB_REVISION_3:
12957 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12958 break;
12959 case TG3_EEPROM_SB_REVISION_4:
12960 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12961 break;
12962 case TG3_EEPROM_SB_REVISION_5:
12963 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12964 break;
12965 case TG3_EEPROM_SB_REVISION_6:
12966 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12967 break;
12968 default:
12969 return;
12970 }
12971
12972 if (tg3_nvram_read(tp, offset, &val))
12973 return;
12974
12975 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12976 TG3_EEPROM_SB_EDH_BLD_SHFT;
12977 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12978 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12979 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12980
12981 if (minor > 99 || build > 26)
12982 return;
12983
12984 offset = strlen(tp->fw_ver);
12985 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12986 " v%d.%02d", major, minor);
12987
12988 if (build > 0) {
12989 offset = strlen(tp->fw_ver);
12990 if (offset < TG3_VER_SIZE - 1)
12991 tp->fw_ver[offset] = 'a' + build - 1;
12992 }
12993 }
12994
12995 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12996 {
12997 u32 val, offset, start;
12998 int i, vlen;
12999
13000 for (offset = TG3_NVM_DIR_START;
13001 offset < TG3_NVM_DIR_END;
13002 offset += TG3_NVM_DIRENT_SIZE) {
13003 if (tg3_nvram_read(tp, offset, &val))
13004 return;
13005
13006 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13007 break;
13008 }
13009
13010 if (offset == TG3_NVM_DIR_END)
13011 return;
13012
13013 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13014 start = 0x08000000;
13015 else if (tg3_nvram_read(tp, offset - 4, &start))
13016 return;
13017
13018 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13019 !tg3_fw_img_is_valid(tp, offset) ||
13020 tg3_nvram_read(tp, offset + 8, &val))
13021 return;
13022
13023 offset += val - start;
13024
13025 vlen = strlen(tp->fw_ver);
13026
13027 tp->fw_ver[vlen++] = ',';
13028 tp->fw_ver[vlen++] = ' ';
13029
13030 for (i = 0; i < 4; i++) {
13031 __be32 v;
13032 if (tg3_nvram_read_be32(tp, offset, &v))
13033 return;
13034
13035 offset += sizeof(v);
13036
13037 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13038 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13039 break;
13040 }
13041
13042 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13043 vlen += sizeof(v);
13044 }
13045 }
13046
13047 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13048 {
13049 int vlen;
13050 u32 apedata;
13051 char *fwtype;
13052
13053 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13054 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
13055 return;
13056
13057 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13058 if (apedata != APE_SEG_SIG_MAGIC)
13059 return;
13060
13061 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13062 if (!(apedata & APE_FW_STATUS_READY))
13063 return;
13064
13065 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13066
13067 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13068 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13069 fwtype = "NCSI";
13070 } else {
13071 fwtype = "DASH";
13072 }
13073
13074 vlen = strlen(tp->fw_ver);
13075
13076 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13077 fwtype,
13078 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13079 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13080 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13081 (apedata & APE_FW_VERSION_BLDMSK));
13082 }
13083
13084 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13085 {
13086 u32 val;
13087 bool vpd_vers = false;
13088
13089 if (tp->fw_ver[0] != 0)
13090 vpd_vers = true;
13091
13092 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13093 strcat(tp->fw_ver, "sb");
13094 return;
13095 }
13096
13097 if (tg3_nvram_read(tp, 0, &val))
13098 return;
13099
13100 if (val == TG3_EEPROM_MAGIC)
13101 tg3_read_bc_ver(tp);
13102 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13103 tg3_read_sb_ver(tp, val);
13104 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13105 tg3_read_hwsb_ver(tp);
13106 else
13107 return;
13108
13109 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13110 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13111 goto done;
13112
13113 tg3_read_mgmtfw_ver(tp);
13114
13115 done:
13116 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13117 }
13118
13119 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13120
13121 static inline void vlan_features_add(struct net_device *dev, unsigned long flags)
13122 {
13123 dev->vlan_features |= flags;
13124 }
13125
13126 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13127 {
13128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13130 return 4096;
13131 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13132 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13133 return 1024;
13134 else
13135 return 512;
13136 }
13137
13138 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13139 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13140 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13141 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13142 { },
13143 };
13144
13145 static int __devinit tg3_get_invariants(struct tg3 *tp)
13146 {
13147 u32 misc_ctrl_reg;
13148 u32 pci_state_reg, grc_misc_cfg;
13149 u32 val;
13150 u16 pci_cmd;
13151 int err;
13152
13153 /* Force memory write invalidate off. If we leave it on,
13154 * then on 5700_BX chips we have to enable a workaround.
13155 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13156 * to match the cacheline size. The Broadcom driver have this
13157 * workaround but turns MWI off all the times so never uses
13158 * it. This seems to suggest that the workaround is insufficient.
13159 */
13160 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13161 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13162 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13163
13164 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13165 * has the register indirect write enable bit set before
13166 * we try to access any of the MMIO registers. It is also
13167 * critical that the PCI-X hw workaround situation is decided
13168 * before that as well.
13169 */
13170 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13171 &misc_ctrl_reg);
13172
13173 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13174 MISC_HOST_CTRL_CHIPREV_SHIFT);
13175 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13176 u32 prod_id_asic_rev;
13177
13178 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13179 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13180 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13181 pci_read_config_dword(tp->pdev,
13182 TG3PCI_GEN2_PRODID_ASICREV,
13183 &prod_id_asic_rev);
13184 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13186 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13187 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13188 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13189 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13190 pci_read_config_dword(tp->pdev,
13191 TG3PCI_GEN15_PRODID_ASICREV,
13192 &prod_id_asic_rev);
13193 else
13194 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13195 &prod_id_asic_rev);
13196
13197 tp->pci_chip_rev_id = prod_id_asic_rev;
13198 }
13199
13200 /* Wrong chip ID in 5752 A0. This code can be removed later
13201 * as A0 is not in production.
13202 */
13203 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13204 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13205
13206 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13207 * we need to disable memory and use config. cycles
13208 * only to access all registers. The 5702/03 chips
13209 * can mistakenly decode the special cycles from the
13210 * ICH chipsets as memory write cycles, causing corruption
13211 * of register and memory space. Only certain ICH bridges
13212 * will drive special cycles with non-zero data during the
13213 * address phase which can fall within the 5703's address
13214 * range. This is not an ICH bug as the PCI spec allows
13215 * non-zero address during special cycles. However, only
13216 * these ICH bridges are known to drive non-zero addresses
13217 * during special cycles.
13218 *
13219 * Since special cycles do not cross PCI bridges, we only
13220 * enable this workaround if the 5703 is on the secondary
13221 * bus of these ICH bridges.
13222 */
13223 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13224 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13225 static struct tg3_dev_id {
13226 u32 vendor;
13227 u32 device;
13228 u32 rev;
13229 } ich_chipsets[] = {
13230 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13231 PCI_ANY_ID },
13232 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13233 PCI_ANY_ID },
13234 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13235 0xa },
13236 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13237 PCI_ANY_ID },
13238 { },
13239 };
13240 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13241 struct pci_dev *bridge = NULL;
13242
13243 while (pci_id->vendor != 0) {
13244 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13245 bridge);
13246 if (!bridge) {
13247 pci_id++;
13248 continue;
13249 }
13250 if (pci_id->rev != PCI_ANY_ID) {
13251 if (bridge->revision > pci_id->rev)
13252 continue;
13253 }
13254 if (bridge->subordinate &&
13255 (bridge->subordinate->number ==
13256 tp->pdev->bus->number)) {
13257
13258 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13259 pci_dev_put(bridge);
13260 break;
13261 }
13262 }
13263 }
13264
13265 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13266 static struct tg3_dev_id {
13267 u32 vendor;
13268 u32 device;
13269 } bridge_chipsets[] = {
13270 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13271 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13272 { },
13273 };
13274 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13275 struct pci_dev *bridge = NULL;
13276
13277 while (pci_id->vendor != 0) {
13278 bridge = pci_get_device(pci_id->vendor,
13279 pci_id->device,
13280 bridge);
13281 if (!bridge) {
13282 pci_id++;
13283 continue;
13284 }
13285 if (bridge->subordinate &&
13286 (bridge->subordinate->number <=
13287 tp->pdev->bus->number) &&
13288 (bridge->subordinate->subordinate >=
13289 tp->pdev->bus->number)) {
13290 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13291 pci_dev_put(bridge);
13292 break;
13293 }
13294 }
13295 }
13296
13297 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13298 * DMA addresses > 40-bit. This bridge may have other additional
13299 * 57xx devices behind it in some 4-port NIC designs for example.
13300 * Any tg3 device found behind the bridge will also need the 40-bit
13301 * DMA workaround.
13302 */
13303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13305 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13306 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13307 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13308 } else {
13309 struct pci_dev *bridge = NULL;
13310
13311 do {
13312 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13313 PCI_DEVICE_ID_SERVERWORKS_EPB,
13314 bridge);
13315 if (bridge && bridge->subordinate &&
13316 (bridge->subordinate->number <=
13317 tp->pdev->bus->number) &&
13318 (bridge->subordinate->subordinate >=
13319 tp->pdev->bus->number)) {
13320 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13321 pci_dev_put(bridge);
13322 break;
13323 }
13324 } while (bridge);
13325 }
13326
13327 /* Initialize misc host control in PCI block. */
13328 tp->misc_host_ctrl |= (misc_ctrl_reg &
13329 MISC_HOST_CTRL_CHIPREV);
13330 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13331 tp->misc_host_ctrl);
13332
13333 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13335 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13336 tp->pdev_peer = tg3_find_peer(tp);
13337
13338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13339 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13340 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13341 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13342
13343 /* Intentionally exclude ASIC_REV_5906 */
13344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13350 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13351 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13352
13353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13356 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13357 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13358 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13359
13360 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13361 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13362 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13363
13364 /* 5700 B0 chips do not support checksumming correctly due
13365 * to hardware bugs.
13366 */
13367 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13368 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13369 else {
13370 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13371
13372 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13373 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13374 features |= NETIF_F_IPV6_CSUM;
13375 tp->dev->features |= features;
13376 vlan_features_add(tp->dev, features);
13377 }
13378
13379 /* Determine TSO capabilities */
13380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13381 ; /* Do nothing. HW bug. */
13382 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13383 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13384 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13386 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13387 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13388 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13389 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13390 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13391 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13392 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13393 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13394 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13395 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13397 tp->fw_needed = FIRMWARE_TG3TSO5;
13398 else
13399 tp->fw_needed = FIRMWARE_TG3TSO;
13400 }
13401
13402 tp->irq_max = 1;
13403
13404 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13405 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13406 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13407 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13408 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13409 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13410 tp->pdev_peer == tp->pdev))
13411 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13412
13413 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13414 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13415 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13416 }
13417
13418 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13419 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13420 tp->irq_max = TG3_IRQ_MAX_VECS;
13421 }
13422 }
13423
13424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13427 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13428 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13429 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13430 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13431 }
13432
13433 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
13434 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13435 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13436
13437 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13438 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13439 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13440 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13441
13442 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13443 &pci_state_reg);
13444
13445 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13446 if (tp->pcie_cap != 0) {
13447 u16 lnkctl;
13448
13449 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13450
13451 tp->pcie_readrq = 4096;
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13453 tp->pcie_readrq = 2048;
13454
13455 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13456
13457 pci_read_config_word(tp->pdev,
13458 tp->pcie_cap + PCI_EXP_LNKCTL,
13459 &lnkctl);
13460 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13462 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13465 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13466 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13467 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13468 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13469 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13470 }
13471 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13472 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13473 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13474 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13475 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13476 if (!tp->pcix_cap) {
13477 dev_err(&tp->pdev->dev,
13478 "Cannot find PCI-X capability, aborting\n");
13479 return -EIO;
13480 }
13481
13482 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13483 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13484 }
13485
13486 /* If we have an AMD 762 or VIA K8T800 chipset, write
13487 * reordering to the mailbox registers done by the host
13488 * controller can cause major troubles. We read back from
13489 * every mailbox register write to force the writes to be
13490 * posted to the chip in order.
13491 */
13492 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13493 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13494 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13495
13496 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13497 &tp->pci_cacheline_sz);
13498 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13499 &tp->pci_lat_timer);
13500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13501 tp->pci_lat_timer < 64) {
13502 tp->pci_lat_timer = 64;
13503 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13504 tp->pci_lat_timer);
13505 }
13506
13507 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13508 /* 5700 BX chips need to have their TX producer index
13509 * mailboxes written twice to workaround a bug.
13510 */
13511 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13512
13513 /* If we are in PCI-X mode, enable register write workaround.
13514 *
13515 * The workaround is to use indirect register accesses
13516 * for all chip writes not to mailbox registers.
13517 */
13518 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13519 u32 pm_reg;
13520
13521 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13522
13523 /* The chip can have it's power management PCI config
13524 * space registers clobbered due to this bug.
13525 * So explicitly force the chip into D0 here.
13526 */
13527 pci_read_config_dword(tp->pdev,
13528 tp->pm_cap + PCI_PM_CTRL,
13529 &pm_reg);
13530 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13531 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13532 pci_write_config_dword(tp->pdev,
13533 tp->pm_cap + PCI_PM_CTRL,
13534 pm_reg);
13535
13536 /* Also, force SERR#/PERR# in PCI command. */
13537 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13538 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13539 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13540 }
13541 }
13542
13543 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13544 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13545 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13546 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13547
13548 /* Chip-specific fixup from Broadcom driver */
13549 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13550 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13551 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13552 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13553 }
13554
13555 /* Default fast path register access methods */
13556 tp->read32 = tg3_read32;
13557 tp->write32 = tg3_write32;
13558 tp->read32_mbox = tg3_read32;
13559 tp->write32_mbox = tg3_write32;
13560 tp->write32_tx_mbox = tg3_write32;
13561 tp->write32_rx_mbox = tg3_write32;
13562
13563 /* Various workaround register access methods */
13564 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13565 tp->write32 = tg3_write_indirect_reg32;
13566 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13567 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13568 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13569 /*
13570 * Back to back register writes can cause problems on these
13571 * chips, the workaround is to read back all reg writes
13572 * except those to mailbox regs.
13573 *
13574 * See tg3_write_indirect_reg32().
13575 */
13576 tp->write32 = tg3_write_flush_reg32;
13577 }
13578
13579 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13580 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13581 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13582 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13583 tp->write32_rx_mbox = tg3_write_flush_reg32;
13584 }
13585
13586 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13587 tp->read32 = tg3_read_indirect_reg32;
13588 tp->write32 = tg3_write_indirect_reg32;
13589 tp->read32_mbox = tg3_read_indirect_mbox;
13590 tp->write32_mbox = tg3_write_indirect_mbox;
13591 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13592 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13593
13594 iounmap(tp->regs);
13595 tp->regs = NULL;
13596
13597 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13598 pci_cmd &= ~PCI_COMMAND_MEMORY;
13599 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13600 }
13601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13602 tp->read32_mbox = tg3_read32_mbox_5906;
13603 tp->write32_mbox = tg3_write32_mbox_5906;
13604 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13605 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13606 }
13607
13608 if (tp->write32 == tg3_write_indirect_reg32 ||
13609 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13610 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13612 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13613
13614 /* Get eeprom hw config before calling tg3_set_power_state().
13615 * In particular, the TG3_FLG2_IS_NIC flag must be
13616 * determined before calling tg3_set_power_state() so that
13617 * we know whether or not to switch out of Vaux power.
13618 * When the flag is set, it means that GPIO1 is used for eeprom
13619 * write protect and also implies that it is a LOM where GPIOs
13620 * are not used to switch power.
13621 */
13622 tg3_get_eeprom_hw_cfg(tp);
13623
13624 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13625 /* Allow reads and writes to the
13626 * APE register and memory space.
13627 */
13628 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13629 PCISTATE_ALLOW_APE_SHMEM_WR |
13630 PCISTATE_ALLOW_APE_PSPACE_WR;
13631 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13632 pci_state_reg);
13633 }
13634
13635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13639 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13640 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13641
13642 /* Set up tp->grc_local_ctrl before calling tg_power_up().
13643 * GPIO1 driven high will bring 5700's external PHY out of reset.
13644 * It is also used as eeprom write protect on LOMs.
13645 */
13646 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13647 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13648 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13649 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13650 GRC_LCLCTRL_GPIO_OUTPUT1);
13651 /* Unused GPIO3 must be driven as output on 5752 because there
13652 * are no pull-up resistors on unused GPIO pins.
13653 */
13654 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13655 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13656
13657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13660 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13661
13662 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13663 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13664 /* Turn off the debug UART. */
13665 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13666 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13667 /* Keep VMain power. */
13668 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13669 GRC_LCLCTRL_GPIO_OUTPUT0;
13670 }
13671
13672 /* Force the chip into D0. */
13673 err = tg3_power_up(tp);
13674 if (err) {
13675 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13676 return err;
13677 }
13678
13679 /* Derive initial jumbo mode from MTU assigned in
13680 * ether_setup() via the alloc_etherdev() call
13681 */
13682 if (tp->dev->mtu > ETH_DATA_LEN &&
13683 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13684 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13685
13686 /* Determine WakeOnLan speed to use. */
13687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13688 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13689 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13690 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13691 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13692 } else {
13693 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13694 }
13695
13696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13697 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13698
13699 /* A few boards don't want Ethernet@WireSpeed phy feature */
13700 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13701 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13702 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13703 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13704 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13705 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13706 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13707
13708 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13709 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13710 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13711 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13712 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13713
13714 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13715 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13716 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13717 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13718 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13719 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13720 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13723 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13724 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13725 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13726 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13727 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13728 } else
13729 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13730 }
13731
13732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13733 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13734 tp->phy_otp = tg3_read_otp_phycfg(tp);
13735 if (tp->phy_otp == 0)
13736 tp->phy_otp = TG3_OTP_DEFAULT;
13737 }
13738
13739 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13740 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13741 else
13742 tp->mi_mode = MAC_MI_MODE_BASE;
13743
13744 tp->coalesce_mode = 0;
13745 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13746 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13747 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13748
13749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13750 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13751 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13752
13753 err = tg3_mdio_init(tp);
13754 if (err)
13755 return err;
13756
13757 /* Initialize data/descriptor byte/word swapping. */
13758 val = tr32(GRC_MODE);
13759 val &= GRC_MODE_HOST_STACKUP;
13760 tw32(GRC_MODE, val | tp->grc_mode);
13761
13762 tg3_switch_clocks(tp);
13763
13764 /* Clear this out for sanity. */
13765 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13766
13767 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13768 &pci_state_reg);
13769 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13770 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13771 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13772
13773 if (chiprevid == CHIPREV_ID_5701_A0 ||
13774 chiprevid == CHIPREV_ID_5701_B0 ||
13775 chiprevid == CHIPREV_ID_5701_B2 ||
13776 chiprevid == CHIPREV_ID_5701_B5) {
13777 void __iomem *sram_base;
13778
13779 /* Write some dummy words into the SRAM status block
13780 * area, see if it reads back correctly. If the return
13781 * value is bad, force enable the PCIX workaround.
13782 */
13783 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13784
13785 writel(0x00000000, sram_base);
13786 writel(0x00000000, sram_base + 4);
13787 writel(0xffffffff, sram_base + 4);
13788 if (readl(sram_base) != 0x00000000)
13789 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13790 }
13791 }
13792
13793 udelay(50);
13794 tg3_nvram_init(tp);
13795
13796 grc_misc_cfg = tr32(GRC_MISC_CFG);
13797 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13798
13799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13800 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13801 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13802 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13803
13804 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13805 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13806 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13807 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13808 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13809 HOSTCC_MODE_CLRTICK_TXBD);
13810
13811 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13812 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13813 tp->misc_host_ctrl);
13814 }
13815
13816 /* Preserve the APE MAC_MODE bits */
13817 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13818 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13819 else
13820 tp->mac_mode = TG3_DEF_MAC_MODE;
13821
13822 /* these are limited to 10/100 only */
13823 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13824 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13825 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13826 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13827 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13828 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13829 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13830 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13831 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13832 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13833 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13834 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13835 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13837 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13838 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13839
13840 err = tg3_phy_probe(tp);
13841 if (err) {
13842 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13843 /* ... but do not return immediately ... */
13844 tg3_mdio_fini(tp);
13845 }
13846
13847 tg3_read_vpd(tp);
13848 tg3_read_fw_ver(tp);
13849
13850 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13851 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13852 } else {
13853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13854 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13855 else
13856 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13857 }
13858
13859 /* 5700 {AX,BX} chips have a broken status block link
13860 * change bit implementation, so we must use the
13861 * status register in those cases.
13862 */
13863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13864 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13865 else
13866 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13867
13868 /* The led_ctrl is set during tg3_phy_probe, here we might
13869 * have to force the link status polling mechanism based
13870 * upon subsystem IDs.
13871 */
13872 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13874 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13875 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13876 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13877 }
13878
13879 /* For all SERDES we poll the MAC status register. */
13880 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13881 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13882 else
13883 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13884
13885 tp->rx_offset = NET_IP_ALIGN;
13886 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13888 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13889 tp->rx_offset = 0;
13890 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13891 tp->rx_copy_thresh = ~(u16)0;
13892 #endif
13893 }
13894
13895 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13896 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13897 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13898
13899 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13900
13901 /* Increment the rx prod index on the rx std ring by at most
13902 * 8 for these chips to workaround hw errata.
13903 */
13904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13907 tp->rx_std_max_post = 8;
13908
13909 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13910 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13911 PCIE_PWR_MGMT_L1_THRESH_MSK;
13912
13913 return err;
13914 }
13915
13916 #ifdef CONFIG_SPARC
13917 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13918 {
13919 struct net_device *dev = tp->dev;
13920 struct pci_dev *pdev = tp->pdev;
13921 struct device_node *dp = pci_device_to_OF_node(pdev);
13922 const unsigned char *addr;
13923 int len;
13924
13925 addr = of_get_property(dp, "local-mac-address", &len);
13926 if (addr && len == 6) {
13927 memcpy(dev->dev_addr, addr, 6);
13928 memcpy(dev->perm_addr, dev->dev_addr, 6);
13929 return 0;
13930 }
13931 return -ENODEV;
13932 }
13933
13934 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13935 {
13936 struct net_device *dev = tp->dev;
13937
13938 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13939 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13940 return 0;
13941 }
13942 #endif
13943
13944 static int __devinit tg3_get_device_address(struct tg3 *tp)
13945 {
13946 struct net_device *dev = tp->dev;
13947 u32 hi, lo, mac_offset;
13948 int addr_ok = 0;
13949
13950 #ifdef CONFIG_SPARC
13951 if (!tg3_get_macaddr_sparc(tp))
13952 return 0;
13953 #endif
13954
13955 mac_offset = 0x7c;
13956 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13957 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13958 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13959 mac_offset = 0xcc;
13960 if (tg3_nvram_lock(tp))
13961 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13962 else
13963 tg3_nvram_unlock(tp);
13964 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13966 if (PCI_FUNC(tp->pdev->devfn) & 1)
13967 mac_offset = 0xcc;
13968 if (PCI_FUNC(tp->pdev->devfn) > 1)
13969 mac_offset += 0x18c;
13970 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13971 mac_offset = 0x10;
13972
13973 /* First try to get it from MAC address mailbox. */
13974 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13975 if ((hi >> 16) == 0x484b) {
13976 dev->dev_addr[0] = (hi >> 8) & 0xff;
13977 dev->dev_addr[1] = (hi >> 0) & 0xff;
13978
13979 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13980 dev->dev_addr[2] = (lo >> 24) & 0xff;
13981 dev->dev_addr[3] = (lo >> 16) & 0xff;
13982 dev->dev_addr[4] = (lo >> 8) & 0xff;
13983 dev->dev_addr[5] = (lo >> 0) & 0xff;
13984
13985 /* Some old bootcode may report a 0 MAC address in SRAM */
13986 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13987 }
13988 if (!addr_ok) {
13989 /* Next, try NVRAM. */
13990 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13991 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13992 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13993 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13994 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13995 }
13996 /* Finally just fetch it out of the MAC control regs. */
13997 else {
13998 hi = tr32(MAC_ADDR_0_HIGH);
13999 lo = tr32(MAC_ADDR_0_LOW);
14000
14001 dev->dev_addr[5] = lo & 0xff;
14002 dev->dev_addr[4] = (lo >> 8) & 0xff;
14003 dev->dev_addr[3] = (lo >> 16) & 0xff;
14004 dev->dev_addr[2] = (lo >> 24) & 0xff;
14005 dev->dev_addr[1] = hi & 0xff;
14006 dev->dev_addr[0] = (hi >> 8) & 0xff;
14007 }
14008 }
14009
14010 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14011 #ifdef CONFIG_SPARC
14012 if (!tg3_get_default_macaddr_sparc(tp))
14013 return 0;
14014 #endif
14015 return -EINVAL;
14016 }
14017 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14018 return 0;
14019 }
14020
14021 #define BOUNDARY_SINGLE_CACHELINE 1
14022 #define BOUNDARY_MULTI_CACHELINE 2
14023
14024 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14025 {
14026 int cacheline_size;
14027 u8 byte;
14028 int goal;
14029
14030 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14031 if (byte == 0)
14032 cacheline_size = 1024;
14033 else
14034 cacheline_size = (int) byte * 4;
14035
14036 /* On 5703 and later chips, the boundary bits have no
14037 * effect.
14038 */
14039 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14040 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14041 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14042 goto out;
14043
14044 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14045 goal = BOUNDARY_MULTI_CACHELINE;
14046 #else
14047 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14048 goal = BOUNDARY_SINGLE_CACHELINE;
14049 #else
14050 goal = 0;
14051 #endif
14052 #endif
14053
14054 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14055 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14056 goto out;
14057 }
14058
14059 if (!goal)
14060 goto out;
14061
14062 /* PCI controllers on most RISC systems tend to disconnect
14063 * when a device tries to burst across a cache-line boundary.
14064 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14065 *
14066 * Unfortunately, for PCI-E there are only limited
14067 * write-side controls for this, and thus for reads
14068 * we will still get the disconnects. We'll also waste
14069 * these PCI cycles for both read and write for chips
14070 * other than 5700 and 5701 which do not implement the
14071 * boundary bits.
14072 */
14073 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14074 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14075 switch (cacheline_size) {
14076 case 16:
14077 case 32:
14078 case 64:
14079 case 128:
14080 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14081 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14082 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14083 } else {
14084 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14085 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14086 }
14087 break;
14088
14089 case 256:
14090 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14091 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14092 break;
14093
14094 default:
14095 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14096 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14097 break;
14098 }
14099 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14100 switch (cacheline_size) {
14101 case 16:
14102 case 32:
14103 case 64:
14104 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14105 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14106 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14107 break;
14108 }
14109 /* fallthrough */
14110 case 128:
14111 default:
14112 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14113 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14114 break;
14115 }
14116 } else {
14117 switch (cacheline_size) {
14118 case 16:
14119 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14120 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14121 DMA_RWCTRL_WRITE_BNDRY_16);
14122 break;
14123 }
14124 /* fallthrough */
14125 case 32:
14126 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14127 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14128 DMA_RWCTRL_WRITE_BNDRY_32);
14129 break;
14130 }
14131 /* fallthrough */
14132 case 64:
14133 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14134 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14135 DMA_RWCTRL_WRITE_BNDRY_64);
14136 break;
14137 }
14138 /* fallthrough */
14139 case 128:
14140 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14141 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14142 DMA_RWCTRL_WRITE_BNDRY_128);
14143 break;
14144 }
14145 /* fallthrough */
14146 case 256:
14147 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14148 DMA_RWCTRL_WRITE_BNDRY_256);
14149 break;
14150 case 512:
14151 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14152 DMA_RWCTRL_WRITE_BNDRY_512);
14153 break;
14154 case 1024:
14155 default:
14156 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14157 DMA_RWCTRL_WRITE_BNDRY_1024);
14158 break;
14159 }
14160 }
14161
14162 out:
14163 return val;
14164 }
14165
14166 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14167 {
14168 struct tg3_internal_buffer_desc test_desc;
14169 u32 sram_dma_descs;
14170 int i, ret;
14171
14172 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14173
14174 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14175 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14176 tw32(RDMAC_STATUS, 0);
14177 tw32(WDMAC_STATUS, 0);
14178
14179 tw32(BUFMGR_MODE, 0);
14180 tw32(FTQ_RESET, 0);
14181
14182 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14183 test_desc.addr_lo = buf_dma & 0xffffffff;
14184 test_desc.nic_mbuf = 0x00002100;
14185 test_desc.len = size;
14186
14187 /*
14188 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14189 * the *second* time the tg3 driver was getting loaded after an
14190 * initial scan.
14191 *
14192 * Broadcom tells me:
14193 * ...the DMA engine is connected to the GRC block and a DMA
14194 * reset may affect the GRC block in some unpredictable way...
14195 * The behavior of resets to individual blocks has not been tested.
14196 *
14197 * Broadcom noted the GRC reset will also reset all sub-components.
14198 */
14199 if (to_device) {
14200 test_desc.cqid_sqid = (13 << 8) | 2;
14201
14202 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14203 udelay(40);
14204 } else {
14205 test_desc.cqid_sqid = (16 << 8) | 7;
14206
14207 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14208 udelay(40);
14209 }
14210 test_desc.flags = 0x00000005;
14211
14212 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14213 u32 val;
14214
14215 val = *(((u32 *)&test_desc) + i);
14216 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14217 sram_dma_descs + (i * sizeof(u32)));
14218 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14219 }
14220 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14221
14222 if (to_device)
14223 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14224 else
14225 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14226
14227 ret = -ENODEV;
14228 for (i = 0; i < 40; i++) {
14229 u32 val;
14230
14231 if (to_device)
14232 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14233 else
14234 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14235 if ((val & 0xffff) == sram_dma_descs) {
14236 ret = 0;
14237 break;
14238 }
14239
14240 udelay(100);
14241 }
14242
14243 return ret;
14244 }
14245
14246 #define TEST_BUFFER_SIZE 0x2000
14247
14248 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14249 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14250 { },
14251 };
14252
14253 static int __devinit tg3_test_dma(struct tg3 *tp)
14254 {
14255 dma_addr_t buf_dma;
14256 u32 *buf, saved_dma_rwctrl;
14257 int ret = 0;
14258
14259 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14260 &buf_dma, GFP_KERNEL);
14261 if (!buf) {
14262 ret = -ENOMEM;
14263 goto out_nofree;
14264 }
14265
14266 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14267 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14268
14269 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14270
14271 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14272 goto out;
14273
14274 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14275 /* DMA read watermark not used on PCIE */
14276 tp->dma_rwctrl |= 0x00180000;
14277 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14279 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14280 tp->dma_rwctrl |= 0x003f0000;
14281 else
14282 tp->dma_rwctrl |= 0x003f000f;
14283 } else {
14284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14286 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14287 u32 read_water = 0x7;
14288
14289 /* If the 5704 is behind the EPB bridge, we can
14290 * do the less restrictive ONE_DMA workaround for
14291 * better performance.
14292 */
14293 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14294 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14295 tp->dma_rwctrl |= 0x8000;
14296 else if (ccval == 0x6 || ccval == 0x7)
14297 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14298
14299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14300 read_water = 4;
14301 /* Set bit 23 to enable PCIX hw bug fix */
14302 tp->dma_rwctrl |=
14303 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14304 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14305 (1 << 23);
14306 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14307 /* 5780 always in PCIX mode */
14308 tp->dma_rwctrl |= 0x00144000;
14309 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14310 /* 5714 always in PCIX mode */
14311 tp->dma_rwctrl |= 0x00148000;
14312 } else {
14313 tp->dma_rwctrl |= 0x001b000f;
14314 }
14315 }
14316
14317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14319 tp->dma_rwctrl &= 0xfffffff0;
14320
14321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14322 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14323 /* Remove this if it causes problems for some boards. */
14324 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14325
14326 /* On 5700/5701 chips, we need to set this bit.
14327 * Otherwise the chip will issue cacheline transactions
14328 * to streamable DMA memory with not all the byte
14329 * enables turned on. This is an error on several
14330 * RISC PCI controllers, in particular sparc64.
14331 *
14332 * On 5703/5704 chips, this bit has been reassigned
14333 * a different meaning. In particular, it is used
14334 * on those chips to enable a PCI-X workaround.
14335 */
14336 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14337 }
14338
14339 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14340
14341 #if 0
14342 /* Unneeded, already done by tg3_get_invariants. */
14343 tg3_switch_clocks(tp);
14344 #endif
14345
14346 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14347 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14348 goto out;
14349
14350 /* It is best to perform DMA test with maximum write burst size
14351 * to expose the 5700/5701 write DMA bug.
14352 */
14353 saved_dma_rwctrl = tp->dma_rwctrl;
14354 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14355 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14356
14357 while (1) {
14358 u32 *p = buf, i;
14359
14360 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14361 p[i] = i;
14362
14363 /* Send the buffer to the chip. */
14364 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14365 if (ret) {
14366 dev_err(&tp->pdev->dev,
14367 "%s: Buffer write failed. err = %d\n",
14368 __func__, ret);
14369 break;
14370 }
14371
14372 #if 0
14373 /* validate data reached card RAM correctly. */
14374 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14375 u32 val;
14376 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14377 if (le32_to_cpu(val) != p[i]) {
14378 dev_err(&tp->pdev->dev,
14379 "%s: Buffer corrupted on device! "
14380 "(%d != %d)\n", __func__, val, i);
14381 /* ret = -ENODEV here? */
14382 }
14383 p[i] = 0;
14384 }
14385 #endif
14386 /* Now read it back. */
14387 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14388 if (ret) {
14389 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14390 "err = %d\n", __func__, ret);
14391 break;
14392 }
14393
14394 /* Verify it. */
14395 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14396 if (p[i] == i)
14397 continue;
14398
14399 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14400 DMA_RWCTRL_WRITE_BNDRY_16) {
14401 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14402 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14403 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14404 break;
14405 } else {
14406 dev_err(&tp->pdev->dev,
14407 "%s: Buffer corrupted on read back! "
14408 "(%d != %d)\n", __func__, p[i], i);
14409 ret = -ENODEV;
14410 goto out;
14411 }
14412 }
14413
14414 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14415 /* Success. */
14416 ret = 0;
14417 break;
14418 }
14419 }
14420 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14421 DMA_RWCTRL_WRITE_BNDRY_16) {
14422
14423 /* DMA test passed without adjusting DMA boundary,
14424 * now look for chipsets that are known to expose the
14425 * DMA bug without failing the test.
14426 */
14427 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14428 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14429 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14430 } else {
14431 /* Safe to use the calculated DMA boundary. */
14432 tp->dma_rwctrl = saved_dma_rwctrl;
14433 }
14434
14435 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14436 }
14437
14438 out:
14439 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14440 out_nofree:
14441 return ret;
14442 }
14443
14444 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14445 {
14446 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14447 tp->bufmgr_config.mbuf_read_dma_low_water =
14448 DEFAULT_MB_RDMA_LOW_WATER_5705;
14449 tp->bufmgr_config.mbuf_mac_rx_low_water =
14450 DEFAULT_MB_MACRX_LOW_WATER_57765;
14451 tp->bufmgr_config.mbuf_high_water =
14452 DEFAULT_MB_HIGH_WATER_57765;
14453
14454 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14455 DEFAULT_MB_RDMA_LOW_WATER_5705;
14456 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14457 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14458 tp->bufmgr_config.mbuf_high_water_jumbo =
14459 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14460 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14461 tp->bufmgr_config.mbuf_read_dma_low_water =
14462 DEFAULT_MB_RDMA_LOW_WATER_5705;
14463 tp->bufmgr_config.mbuf_mac_rx_low_water =
14464 DEFAULT_MB_MACRX_LOW_WATER_5705;
14465 tp->bufmgr_config.mbuf_high_water =
14466 DEFAULT_MB_HIGH_WATER_5705;
14467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14468 tp->bufmgr_config.mbuf_mac_rx_low_water =
14469 DEFAULT_MB_MACRX_LOW_WATER_5906;
14470 tp->bufmgr_config.mbuf_high_water =
14471 DEFAULT_MB_HIGH_WATER_5906;
14472 }
14473
14474 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14475 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14476 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14477 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14478 tp->bufmgr_config.mbuf_high_water_jumbo =
14479 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14480 } else {
14481 tp->bufmgr_config.mbuf_read_dma_low_water =
14482 DEFAULT_MB_RDMA_LOW_WATER;
14483 tp->bufmgr_config.mbuf_mac_rx_low_water =
14484 DEFAULT_MB_MACRX_LOW_WATER;
14485 tp->bufmgr_config.mbuf_high_water =
14486 DEFAULT_MB_HIGH_WATER;
14487
14488 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14489 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14490 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14491 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14492 tp->bufmgr_config.mbuf_high_water_jumbo =
14493 DEFAULT_MB_HIGH_WATER_JUMBO;
14494 }
14495
14496 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14497 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14498 }
14499
14500 static char * __devinit tg3_phy_string(struct tg3 *tp)
14501 {
14502 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14503 case TG3_PHY_ID_BCM5400: return "5400";
14504 case TG3_PHY_ID_BCM5401: return "5401";
14505 case TG3_PHY_ID_BCM5411: return "5411";
14506 case TG3_PHY_ID_BCM5701: return "5701";
14507 case TG3_PHY_ID_BCM5703: return "5703";
14508 case TG3_PHY_ID_BCM5704: return "5704";
14509 case TG3_PHY_ID_BCM5705: return "5705";
14510 case TG3_PHY_ID_BCM5750: return "5750";
14511 case TG3_PHY_ID_BCM5752: return "5752";
14512 case TG3_PHY_ID_BCM5714: return "5714";
14513 case TG3_PHY_ID_BCM5780: return "5780";
14514 case TG3_PHY_ID_BCM5755: return "5755";
14515 case TG3_PHY_ID_BCM5787: return "5787";
14516 case TG3_PHY_ID_BCM5784: return "5784";
14517 case TG3_PHY_ID_BCM5756: return "5722/5756";
14518 case TG3_PHY_ID_BCM5906: return "5906";
14519 case TG3_PHY_ID_BCM5761: return "5761";
14520 case TG3_PHY_ID_BCM5718C: return "5718C";
14521 case TG3_PHY_ID_BCM5718S: return "5718S";
14522 case TG3_PHY_ID_BCM57765: return "57765";
14523 case TG3_PHY_ID_BCM5719C: return "5719C";
14524 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14525 case 0: return "serdes";
14526 default: return "unknown";
14527 }
14528 }
14529
14530 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14531 {
14532 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14533 strcpy(str, "PCI Express");
14534 return str;
14535 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14536 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14537
14538 strcpy(str, "PCIX:");
14539
14540 if ((clock_ctrl == 7) ||
14541 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14542 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14543 strcat(str, "133MHz");
14544 else if (clock_ctrl == 0)
14545 strcat(str, "33MHz");
14546 else if (clock_ctrl == 2)
14547 strcat(str, "50MHz");
14548 else if (clock_ctrl == 4)
14549 strcat(str, "66MHz");
14550 else if (clock_ctrl == 6)
14551 strcat(str, "100MHz");
14552 } else {
14553 strcpy(str, "PCI:");
14554 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14555 strcat(str, "66MHz");
14556 else
14557 strcat(str, "33MHz");
14558 }
14559 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14560 strcat(str, ":32-bit");
14561 else
14562 strcat(str, ":64-bit");
14563 return str;
14564 }
14565
14566 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14567 {
14568 struct pci_dev *peer;
14569 unsigned int func, devnr = tp->pdev->devfn & ~7;
14570
14571 for (func = 0; func < 8; func++) {
14572 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14573 if (peer && peer != tp->pdev)
14574 break;
14575 pci_dev_put(peer);
14576 }
14577 /* 5704 can be configured in single-port mode, set peer to
14578 * tp->pdev in that case.
14579 */
14580 if (!peer) {
14581 peer = tp->pdev;
14582 return peer;
14583 }
14584
14585 /*
14586 * We don't need to keep the refcount elevated; there's no way
14587 * to remove one half of this device without removing the other
14588 */
14589 pci_dev_put(peer);
14590
14591 return peer;
14592 }
14593
14594 static void __devinit tg3_init_coal(struct tg3 *tp)
14595 {
14596 struct ethtool_coalesce *ec = &tp->coal;
14597
14598 memset(ec, 0, sizeof(*ec));
14599 ec->cmd = ETHTOOL_GCOALESCE;
14600 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14601 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14602 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14603 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14604 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14605 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14606 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14607 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14608 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14609
14610 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14611 HOSTCC_MODE_CLRTICK_TXBD)) {
14612 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14613 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14614 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14615 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14616 }
14617
14618 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14619 ec->rx_coalesce_usecs_irq = 0;
14620 ec->tx_coalesce_usecs_irq = 0;
14621 ec->stats_block_coalesce_usecs = 0;
14622 }
14623 }
14624
14625 static const struct net_device_ops tg3_netdev_ops = {
14626 .ndo_open = tg3_open,
14627 .ndo_stop = tg3_close,
14628 .ndo_start_xmit = tg3_start_xmit,
14629 .ndo_get_stats64 = tg3_get_stats64,
14630 .ndo_validate_addr = eth_validate_addr,
14631 .ndo_set_multicast_list = tg3_set_rx_mode,
14632 .ndo_set_mac_address = tg3_set_mac_addr,
14633 .ndo_do_ioctl = tg3_ioctl,
14634 .ndo_tx_timeout = tg3_tx_timeout,
14635 .ndo_change_mtu = tg3_change_mtu,
14636 #ifdef CONFIG_NET_POLL_CONTROLLER
14637 .ndo_poll_controller = tg3_poll_controller,
14638 #endif
14639 };
14640
14641 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14642 .ndo_open = tg3_open,
14643 .ndo_stop = tg3_close,
14644 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14645 .ndo_get_stats64 = tg3_get_stats64,
14646 .ndo_validate_addr = eth_validate_addr,
14647 .ndo_set_multicast_list = tg3_set_rx_mode,
14648 .ndo_set_mac_address = tg3_set_mac_addr,
14649 .ndo_do_ioctl = tg3_ioctl,
14650 .ndo_tx_timeout = tg3_tx_timeout,
14651 .ndo_change_mtu = tg3_change_mtu,
14652 #ifdef CONFIG_NET_POLL_CONTROLLER
14653 .ndo_poll_controller = tg3_poll_controller,
14654 #endif
14655 };
14656
14657 static int __devinit tg3_init_one(struct pci_dev *pdev,
14658 const struct pci_device_id *ent)
14659 {
14660 struct net_device *dev;
14661 struct tg3 *tp;
14662 int i, err, pm_cap;
14663 u32 sndmbx, rcvmbx, intmbx;
14664 char str[40];
14665 u64 dma_mask, persist_dma_mask;
14666
14667 printk_once(KERN_INFO "%s\n", version);
14668
14669 err = pci_enable_device(pdev);
14670 if (err) {
14671 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14672 return err;
14673 }
14674
14675 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14676 if (err) {
14677 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14678 goto err_out_disable_pdev;
14679 }
14680
14681 pci_set_master(pdev);
14682
14683 /* Find power-management capability. */
14684 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14685 if (pm_cap == 0) {
14686 dev_err(&pdev->dev,
14687 "Cannot find Power Management capability, aborting\n");
14688 err = -EIO;
14689 goto err_out_free_res;
14690 }
14691
14692 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14693 if (!dev) {
14694 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14695 err = -ENOMEM;
14696 goto err_out_free_res;
14697 }
14698
14699 SET_NETDEV_DEV(dev, &pdev->dev);
14700
14701 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14702
14703 tp = netdev_priv(dev);
14704 tp->pdev = pdev;
14705 tp->dev = dev;
14706 tp->pm_cap = pm_cap;
14707 tp->rx_mode = TG3_DEF_RX_MODE;
14708 tp->tx_mode = TG3_DEF_TX_MODE;
14709
14710 if (tg3_debug > 0)
14711 tp->msg_enable = tg3_debug;
14712 else
14713 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14714
14715 /* The word/byte swap controls here control register access byte
14716 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14717 * setting below.
14718 */
14719 tp->misc_host_ctrl =
14720 MISC_HOST_CTRL_MASK_PCI_INT |
14721 MISC_HOST_CTRL_WORD_SWAP |
14722 MISC_HOST_CTRL_INDIR_ACCESS |
14723 MISC_HOST_CTRL_PCISTATE_RW;
14724
14725 /* The NONFRM (non-frame) byte/word swap controls take effect
14726 * on descriptor entries, anything which isn't packet data.
14727 *
14728 * The StrongARM chips on the board (one for tx, one for rx)
14729 * are running in big-endian mode.
14730 */
14731 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14732 GRC_MODE_WSWAP_NONFRM_DATA);
14733 #ifdef __BIG_ENDIAN
14734 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14735 #endif
14736 spin_lock_init(&tp->lock);
14737 spin_lock_init(&tp->indirect_lock);
14738 INIT_WORK(&tp->reset_task, tg3_reset_task);
14739
14740 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14741 if (!tp->regs) {
14742 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14743 err = -ENOMEM;
14744 goto err_out_free_dev;
14745 }
14746
14747 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14748 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14749
14750 dev->ethtool_ops = &tg3_ethtool_ops;
14751 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14752 dev->irq = pdev->irq;
14753
14754 err = tg3_get_invariants(tp);
14755 if (err) {
14756 dev_err(&pdev->dev,
14757 "Problem fetching invariants of chip, aborting\n");
14758 goto err_out_iounmap;
14759 }
14760
14761 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14762 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14763 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14764 dev->netdev_ops = &tg3_netdev_ops;
14765 else
14766 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14767
14768
14769 /* The EPB bridge inside 5714, 5715, and 5780 and any
14770 * device behind the EPB cannot support DMA addresses > 40-bit.
14771 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14772 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14773 * do DMA address check in tg3_start_xmit().
14774 */
14775 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14776 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14777 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14778 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14779 #ifdef CONFIG_HIGHMEM
14780 dma_mask = DMA_BIT_MASK(64);
14781 #endif
14782 } else
14783 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14784
14785 /* Configure DMA attributes. */
14786 if (dma_mask > DMA_BIT_MASK(32)) {
14787 err = pci_set_dma_mask(pdev, dma_mask);
14788 if (!err) {
14789 dev->features |= NETIF_F_HIGHDMA;
14790 err = pci_set_consistent_dma_mask(pdev,
14791 persist_dma_mask);
14792 if (err < 0) {
14793 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14794 "DMA for consistent allocations\n");
14795 goto err_out_iounmap;
14796 }
14797 }
14798 }
14799 if (err || dma_mask == DMA_BIT_MASK(32)) {
14800 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14801 if (err) {
14802 dev_err(&pdev->dev,
14803 "No usable DMA configuration, aborting\n");
14804 goto err_out_iounmap;
14805 }
14806 }
14807
14808 tg3_init_bufmgr_config(tp);
14809
14810 /* Selectively allow TSO based on operating conditions */
14811 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14812 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14813 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14814 else {
14815 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14816 tp->fw_needed = NULL;
14817 }
14818
14819 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14820 tp->fw_needed = FIRMWARE_TG3;
14821
14822 /* TSO is on by default on chips that support hardware TSO.
14823 * Firmware TSO on older chips gives lower performance, so it
14824 * is off by default, but can be enabled using ethtool.
14825 */
14826 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14827 (dev->features & NETIF_F_IP_CSUM)) {
14828 dev->features |= NETIF_F_TSO;
14829 vlan_features_add(dev, NETIF_F_TSO);
14830 }
14831 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14832 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14833 if (dev->features & NETIF_F_IPV6_CSUM) {
14834 dev->features |= NETIF_F_TSO6;
14835 vlan_features_add(dev, NETIF_F_TSO6);
14836 }
14837 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14838 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14839 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14840 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14843 dev->features |= NETIF_F_TSO_ECN;
14844 vlan_features_add(dev, NETIF_F_TSO_ECN);
14845 }
14846 }
14847
14848 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14849 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14850 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14851 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14852 tp->rx_pending = 63;
14853 }
14854
14855 err = tg3_get_device_address(tp);
14856 if (err) {
14857 dev_err(&pdev->dev,
14858 "Could not obtain valid ethernet address, aborting\n");
14859 goto err_out_iounmap;
14860 }
14861
14862 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14863 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14864 if (!tp->aperegs) {
14865 dev_err(&pdev->dev,
14866 "Cannot map APE registers, aborting\n");
14867 err = -ENOMEM;
14868 goto err_out_iounmap;
14869 }
14870
14871 tg3_ape_lock_init(tp);
14872
14873 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14874 tg3_read_dash_ver(tp);
14875 }
14876
14877 /*
14878 * Reset chip in case UNDI or EFI driver did not shutdown
14879 * DMA self test will enable WDMAC and we'll see (spurious)
14880 * pending DMA on the PCI bus at that point.
14881 */
14882 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14883 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14884 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14885 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14886 }
14887
14888 err = tg3_test_dma(tp);
14889 if (err) {
14890 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14891 goto err_out_apeunmap;
14892 }
14893
14894 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14895 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14896 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14897 for (i = 0; i < tp->irq_max; i++) {
14898 struct tg3_napi *tnapi = &tp->napi[i];
14899
14900 tnapi->tp = tp;
14901 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14902
14903 tnapi->int_mbox = intmbx;
14904 if (i < 4)
14905 intmbx += 0x8;
14906 else
14907 intmbx += 0x4;
14908
14909 tnapi->consmbox = rcvmbx;
14910 tnapi->prodmbox = sndmbx;
14911
14912 if (i)
14913 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14914 else
14915 tnapi->coal_now = HOSTCC_MODE_NOW;
14916
14917 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14918 break;
14919
14920 /*
14921 * If we support MSIX, we'll be using RSS. If we're using
14922 * RSS, the first vector only handles link interrupts and the
14923 * remaining vectors handle rx and tx interrupts. Reuse the
14924 * mailbox values for the next iteration. The values we setup
14925 * above are still useful for the single vectored mode.
14926 */
14927 if (!i)
14928 continue;
14929
14930 rcvmbx += 0x8;
14931
14932 if (sndmbx & 0x4)
14933 sndmbx -= 0x4;
14934 else
14935 sndmbx += 0xc;
14936 }
14937
14938 tg3_init_coal(tp);
14939
14940 pci_set_drvdata(pdev, dev);
14941
14942 err = register_netdev(dev);
14943 if (err) {
14944 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14945 goto err_out_apeunmap;
14946 }
14947
14948 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14949 tp->board_part_number,
14950 tp->pci_chip_rev_id,
14951 tg3_bus_string(tp, str),
14952 dev->dev_addr);
14953
14954 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14955 struct phy_device *phydev;
14956 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14957 netdev_info(dev,
14958 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14959 phydev->drv->name, dev_name(&phydev->dev));
14960 } else {
14961 char *ethtype;
14962
14963 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14964 ethtype = "10/100Base-TX";
14965 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14966 ethtype = "1000Base-SX";
14967 else
14968 ethtype = "10/100/1000Base-T";
14969
14970 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14971 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14972 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14973 }
14974
14975 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14976 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14977 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14978 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14979 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14980 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14981 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14982 tp->dma_rwctrl,
14983 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14984 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14985
14986 return 0;
14987
14988 err_out_apeunmap:
14989 if (tp->aperegs) {
14990 iounmap(tp->aperegs);
14991 tp->aperegs = NULL;
14992 }
14993
14994 err_out_iounmap:
14995 if (tp->regs) {
14996 iounmap(tp->regs);
14997 tp->regs = NULL;
14998 }
14999
15000 err_out_free_dev:
15001 free_netdev(dev);
15002
15003 err_out_free_res:
15004 pci_release_regions(pdev);
15005
15006 err_out_disable_pdev:
15007 pci_disable_device(pdev);
15008 pci_set_drvdata(pdev, NULL);
15009 return err;
15010 }
15011
15012 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15013 {
15014 struct net_device *dev = pci_get_drvdata(pdev);
15015
15016 if (dev) {
15017 struct tg3 *tp = netdev_priv(dev);
15018
15019 if (tp->fw)
15020 release_firmware(tp->fw);
15021
15022 cancel_work_sync(&tp->reset_task);
15023
15024 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15025 tg3_phy_fini(tp);
15026 tg3_mdio_fini(tp);
15027 }
15028
15029 unregister_netdev(dev);
15030 if (tp->aperegs) {
15031 iounmap(tp->aperegs);
15032 tp->aperegs = NULL;
15033 }
15034 if (tp->regs) {
15035 iounmap(tp->regs);
15036 tp->regs = NULL;
15037 }
15038 free_netdev(dev);
15039 pci_release_regions(pdev);
15040 pci_disable_device(pdev);
15041 pci_set_drvdata(pdev, NULL);
15042 }
15043 }
15044
15045 #ifdef CONFIG_PM_SLEEP
15046 static int tg3_suspend(struct device *device)
15047 {
15048 struct pci_dev *pdev = to_pci_dev(device);
15049 struct net_device *dev = pci_get_drvdata(pdev);
15050 struct tg3 *tp = netdev_priv(dev);
15051 int err;
15052
15053 if (!netif_running(dev))
15054 return 0;
15055
15056 flush_work_sync(&tp->reset_task);
15057 tg3_phy_stop(tp);
15058 tg3_netif_stop(tp);
15059
15060 del_timer_sync(&tp->timer);
15061
15062 tg3_full_lock(tp, 1);
15063 tg3_disable_ints(tp);
15064 tg3_full_unlock(tp);
15065
15066 netif_device_detach(dev);
15067
15068 tg3_full_lock(tp, 0);
15069 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15070 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15071 tg3_full_unlock(tp);
15072
15073 err = tg3_power_down_prepare(tp);
15074 if (err) {
15075 int err2;
15076
15077 tg3_full_lock(tp, 0);
15078
15079 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15080 err2 = tg3_restart_hw(tp, 1);
15081 if (err2)
15082 goto out;
15083
15084 tp->timer.expires = jiffies + tp->timer_offset;
15085 add_timer(&tp->timer);
15086
15087 netif_device_attach(dev);
15088 tg3_netif_start(tp);
15089
15090 out:
15091 tg3_full_unlock(tp);
15092
15093 if (!err2)
15094 tg3_phy_start(tp);
15095 }
15096
15097 return err;
15098 }
15099
15100 static int tg3_resume(struct device *device)
15101 {
15102 struct pci_dev *pdev = to_pci_dev(device);
15103 struct net_device *dev = pci_get_drvdata(pdev);
15104 struct tg3 *tp = netdev_priv(dev);
15105 int err;
15106
15107 if (!netif_running(dev))
15108 return 0;
15109
15110 netif_device_attach(dev);
15111
15112 tg3_full_lock(tp, 0);
15113
15114 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15115 err = tg3_restart_hw(tp, 1);
15116 if (err)
15117 goto out;
15118
15119 tp->timer.expires = jiffies + tp->timer_offset;
15120 add_timer(&tp->timer);
15121
15122 tg3_netif_start(tp);
15123
15124 out:
15125 tg3_full_unlock(tp);
15126
15127 if (!err)
15128 tg3_phy_start(tp);
15129
15130 return err;
15131 }
15132
15133 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15134 #define TG3_PM_OPS (&tg3_pm_ops)
15135
15136 #else
15137
15138 #define TG3_PM_OPS NULL
15139
15140 #endif /* CONFIG_PM_SLEEP */
15141
15142 static struct pci_driver tg3_driver = {
15143 .name = DRV_MODULE_NAME,
15144 .id_table = tg3_pci_tbl,
15145 .probe = tg3_init_one,
15146 .remove = __devexit_p(tg3_remove_one),
15147 .driver.pm = TG3_PM_OPS,
15148 };
15149
15150 static int __init tg3_init(void)
15151 {
15152 return pci_register_driver(&tg3_driver);
15153 }
15154
15155 static void __exit tg3_cleanup(void)
15156 {
15157 pci_unregister_driver(&tg3_driver);
15158 }
15159
15160 module_init(tg3_init);
15161 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree