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drm/radeon/kms: fix mac g5 quirk
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
blob797c8bcbb6a4335924a8a3fe10abce4b8cb9f45f
1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447 }
448
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450 {
451 int edid_info, size;
452 struct edid *edid;
453 unsigned char *raw;
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
458 raw = rdev->bios + edid_info;
459 size = EDID_LENGTH * (raw[0x7e] + 1);
460 edid = kmalloc(size, GFP_KERNEL);
461 if (edid == NULL)
462 return false;
463
464 memcpy((unsigned char *)edid, raw, size);
465
466 if (!drm_edid_is_valid(edid)) {
467 kfree(edid);
468 return false;
469 }
470
471 rdev->mode_info.bios_hardcoded_edid = edid;
472 rdev->mode_info.bios_hardcoded_edid_size = size;
473 return true;
474 }
475
476 /* this is used for atom LCDs as well */
477 struct edid *
478 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
479 {
480 struct edid *edid;
481
482 if (rdev->mode_info.bios_hardcoded_edid) {
483 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
484 if (edid) {
485 memcpy((unsigned char *)edid,
486 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
487 rdev->mode_info.bios_hardcoded_edid_size);
488 return edid;
489 }
490 }
491 return NULL;
492 }
493
494 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
495 enum radeon_combios_ddc ddc,
496 u32 clk_mask,
497 u32 data_mask)
498 {
499 struct radeon_i2c_bus_rec i2c;
500 int ddc_line = 0;
501
502 /* ddc id = mask reg
503 * DDC_NONE_DETECTED = none
504 * DDC_DVI = RADEON_GPIO_DVI_DDC
505 * DDC_VGA = RADEON_GPIO_VGA_DDC
506 * DDC_LCD = RADEON_GPIOPAD_MASK
507 * DDC_GPIO = RADEON_MDGPIO_MASK
508 * r1xx
509 * DDC_MONID = RADEON_GPIO_MONID
510 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
511 * r200
512 * DDC_MONID = RADEON_GPIO_MONID
513 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
514 * r300/r350
515 * DDC_MONID = RADEON_GPIO_DVI_DDC
516 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
517 * rv2xx/rv3xx
518 * DDC_MONID = RADEON_GPIO_MONID
519 * DDC_CRT2 = RADEON_GPIO_MONID
520 * rs3xx/rs4xx
521 * DDC_MONID = RADEON_GPIOPAD_MASK
522 * DDC_CRT2 = RADEON_GPIO_MONID
523 */
524 switch (ddc) {
525 case DDC_NONE_DETECTED:
526 default:
527 ddc_line = 0;
528 break;
529 case DDC_DVI:
530 ddc_line = RADEON_GPIO_DVI_DDC;
531 break;
532 case DDC_VGA:
533 ddc_line = RADEON_GPIO_VGA_DDC;
534 break;
535 case DDC_LCD:
536 ddc_line = RADEON_GPIOPAD_MASK;
537 break;
538 case DDC_GPIO:
539 ddc_line = RADEON_MDGPIO_MASK;
540 break;
541 case DDC_MONID:
542 if (rdev->family == CHIP_RS300 ||
543 rdev->family == CHIP_RS400 ||
544 rdev->family == CHIP_RS480)
545 ddc_line = RADEON_GPIOPAD_MASK;
546 else if (rdev->family == CHIP_R300 ||
547 rdev->family == CHIP_R350) {
548 ddc_line = RADEON_GPIO_DVI_DDC;
549 ddc = DDC_DVI;
550 } else
551 ddc_line = RADEON_GPIO_MONID;
552 break;
553 case DDC_CRT2:
554 if (rdev->family == CHIP_R200 ||
555 rdev->family == CHIP_R300 ||
556 rdev->family == CHIP_R350) {
557 ddc_line = RADEON_GPIO_DVI_DDC;
558 ddc = DDC_DVI;
559 } else if (rdev->family == CHIP_RS300 ||
560 rdev->family == CHIP_RS400 ||
561 rdev->family == CHIP_RS480)
562 ddc_line = RADEON_GPIO_MONID;
563 else if (rdev->family >= CHIP_RV350) {
564 ddc_line = RADEON_GPIO_MONID;
565 ddc = DDC_MONID;
566 } else
567 ddc_line = RADEON_GPIO_CRT2_DDC;
568 break;
569 }
570
571 if (ddc_line == RADEON_GPIOPAD_MASK) {
572 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
573 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
574 i2c.a_clk_reg = RADEON_GPIOPAD_A;
575 i2c.a_data_reg = RADEON_GPIOPAD_A;
576 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
577 i2c.en_data_reg = RADEON_GPIOPAD_EN;
578 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
579 i2c.y_data_reg = RADEON_GPIOPAD_Y;
580 } else if (ddc_line == RADEON_MDGPIO_MASK) {
581 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
582 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
583 i2c.a_clk_reg = RADEON_MDGPIO_A;
584 i2c.a_data_reg = RADEON_MDGPIO_A;
585 i2c.en_clk_reg = RADEON_MDGPIO_EN;
586 i2c.en_data_reg = RADEON_MDGPIO_EN;
587 i2c.y_clk_reg = RADEON_MDGPIO_Y;
588 i2c.y_data_reg = RADEON_MDGPIO_Y;
589 } else {
590 i2c.mask_clk_reg = ddc_line;
591 i2c.mask_data_reg = ddc_line;
592 i2c.a_clk_reg = ddc_line;
593 i2c.a_data_reg = ddc_line;
594 i2c.en_clk_reg = ddc_line;
595 i2c.en_data_reg = ddc_line;
596 i2c.y_clk_reg = ddc_line;
597 i2c.y_data_reg = ddc_line;
598 }
599
600 if (clk_mask && data_mask) {
601 /* system specific masks */
602 i2c.mask_clk_mask = clk_mask;
603 i2c.mask_data_mask = data_mask;
604 i2c.a_clk_mask = clk_mask;
605 i2c.a_data_mask = data_mask;
606 i2c.en_clk_mask = clk_mask;
607 i2c.en_data_mask = data_mask;
608 i2c.y_clk_mask = clk_mask;
609 i2c.y_data_mask = data_mask;
610 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
611 (ddc_line == RADEON_MDGPIO_MASK)) {
612 /* default gpiopad masks */
613 i2c.mask_clk_mask = (0x20 << 8);
614 i2c.mask_data_mask = 0x80;
615 i2c.a_clk_mask = (0x20 << 8);
616 i2c.a_data_mask = 0x80;
617 i2c.en_clk_mask = (0x20 << 8);
618 i2c.en_data_mask = 0x80;
619 i2c.y_clk_mask = (0x20 << 8);
620 i2c.y_data_mask = 0x80;
621 } else {
622 /* default masks for ddc pads */
623 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
624 i2c.mask_data_mask = RADEON_GPIO_EN_0;
625 i2c.a_clk_mask = RADEON_GPIO_A_1;
626 i2c.a_data_mask = RADEON_GPIO_A_0;
627 i2c.en_clk_mask = RADEON_GPIO_EN_1;
628 i2c.en_data_mask = RADEON_GPIO_EN_0;
629 i2c.y_clk_mask = RADEON_GPIO_Y_1;
630 i2c.y_data_mask = RADEON_GPIO_Y_0;
631 }
632
633 switch (rdev->family) {
634 case CHIP_R100:
635 case CHIP_RV100:
636 case CHIP_RS100:
637 case CHIP_RV200:
638 case CHIP_RS200:
639 case CHIP_RS300:
640 switch (ddc_line) {
641 case RADEON_GPIO_DVI_DDC:
642 i2c.hw_capable = true;
643 break;
644 default:
645 i2c.hw_capable = false;
646 break;
647 }
648 break;
649 case CHIP_R200:
650 switch (ddc_line) {
651 case RADEON_GPIO_DVI_DDC:
652 case RADEON_GPIO_MONID:
653 i2c.hw_capable = true;
654 break;
655 default:
656 i2c.hw_capable = false;
657 break;
658 }
659 break;
660 case CHIP_RV250:
661 case CHIP_RV280:
662 switch (ddc_line) {
663 case RADEON_GPIO_VGA_DDC:
664 case RADEON_GPIO_DVI_DDC:
665 case RADEON_GPIO_CRT2_DDC:
666 i2c.hw_capable = true;
667 break;
668 default:
669 i2c.hw_capable = false;
670 break;
671 }
672 break;
673 case CHIP_R300:
674 case CHIP_R350:
675 switch (ddc_line) {
676 case RADEON_GPIO_VGA_DDC:
677 case RADEON_GPIO_DVI_DDC:
678 i2c.hw_capable = true;
679 break;
680 default:
681 i2c.hw_capable = false;
682 break;
683 }
684 break;
685 case CHIP_RV350:
686 case CHIP_RV380:
687 case CHIP_RS400:
688 case CHIP_RS480:
689 switch (ddc_line) {
690 case RADEON_GPIO_VGA_DDC:
691 case RADEON_GPIO_DVI_DDC:
692 i2c.hw_capable = true;
693 break;
694 case RADEON_GPIO_MONID:
695 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
696 * reliably on some pre-r4xx hardware; not sure why.
697 */
698 i2c.hw_capable = false;
699 break;
700 default:
701 i2c.hw_capable = false;
702 break;
703 }
704 break;
705 default:
706 i2c.hw_capable = false;
707 break;
708 }
709 i2c.mm_i2c = false;
710
711 i2c.i2c_id = ddc;
712 i2c.hpd = RADEON_HPD_NONE;
713
714 if (ddc_line)
715 i2c.valid = true;
716 else
717 i2c.valid = false;
718
719 return i2c;
720 }
721
722 void radeon_combios_i2c_init(struct radeon_device *rdev)
723 {
724 struct drm_device *dev = rdev->ddev;
725 struct radeon_i2c_bus_rec i2c;
726
727 /* actual hw pads
728 * r1xx/rs2xx/rs3xx
729 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
730 * r200
731 * 0x60, 0x64, 0x68, mm
732 * r300/r350
733 * 0x60, 0x64, mm
734 * rv2xx/rv3xx/rs4xx
735 * 0x60, 0x64, 0x68, gpiopads, mm
736 */
737
738 /* 0x60 */
739 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
740 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
741 /* 0x64 */
742 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
743 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
744
745 /* mm i2c */
746 i2c.valid = true;
747 i2c.hw_capable = true;
748 i2c.mm_i2c = true;
749 i2c.i2c_id = 0xa0;
750 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
751
752 if (rdev->family == CHIP_R300 ||
753 rdev->family == CHIP_R350) {
754 /* only 2 sw i2c pads */
755 } else if (rdev->family == CHIP_RS300 ||
756 rdev->family == CHIP_RS400 ||
757 rdev->family == CHIP_RS480) {
758 u16 offset;
759 u8 id, blocks, clk, data;
760 int i;
761
762 /* 0x68 */
763 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
764 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
765
766 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
767 if (offset) {
768 blocks = RBIOS8(offset + 2);
769 for (i = 0; i < blocks; i++) {
770 id = RBIOS8(offset + 3 + (i * 5) + 0);
771 if (id == 136) {
772 clk = RBIOS8(offset + 3 + (i * 5) + 3);
773 data = RBIOS8(offset + 3 + (i * 5) + 4);
774 /* gpiopad */
775 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
776 (1 << clk), (1 << data));
777 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
778 break;
779 }
780 }
781 }
782 } else if (rdev->family >= CHIP_R200) {
783 /* 0x68 */
784 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
785 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
786 } else {
787 /* 0x68 */
788 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
789 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
790 /* 0x6c */
791 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
792 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
793 }
794 }
795
796 bool radeon_combios_get_clock_info(struct drm_device *dev)
797 {
798 struct radeon_device *rdev = dev->dev_private;
799 uint16_t pll_info;
800 struct radeon_pll *p1pll = &rdev->clock.p1pll;
801 struct radeon_pll *p2pll = &rdev->clock.p2pll;
802 struct radeon_pll *spll = &rdev->clock.spll;
803 struct radeon_pll *mpll = &rdev->clock.mpll;
804 int8_t rev;
805 uint16_t sclk, mclk;
806
807 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
808 if (pll_info) {
809 rev = RBIOS8(pll_info);
810
811 /* pixel clocks */
812 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
813 p1pll->reference_div = RBIOS16(pll_info + 0x10);
814 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
815 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
816 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
817 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
818
819 if (rev > 9) {
820 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
821 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
822 } else {
823 p1pll->pll_in_min = 40;
824 p1pll->pll_in_max = 500;
825 }
826 *p2pll = *p1pll;
827
828 /* system clock */
829 spll->reference_freq = RBIOS16(pll_info + 0x1a);
830 spll->reference_div = RBIOS16(pll_info + 0x1c);
831 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
832 spll->pll_out_max = RBIOS32(pll_info + 0x22);
833
834 if (rev > 10) {
835 spll->pll_in_min = RBIOS32(pll_info + 0x48);
836 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
837 } else {
838 /* ??? */
839 spll->pll_in_min = 40;
840 spll->pll_in_max = 500;
841 }
842
843 /* memory clock */
844 mpll->reference_freq = RBIOS16(pll_info + 0x26);
845 mpll->reference_div = RBIOS16(pll_info + 0x28);
846 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
847 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
848
849 if (rev > 10) {
850 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
851 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
852 } else {
853 /* ??? */
854 mpll->pll_in_min = 40;
855 mpll->pll_in_max = 500;
856 }
857
858 /* default sclk/mclk */
859 sclk = RBIOS16(pll_info + 0xa);
860 mclk = RBIOS16(pll_info + 0x8);
861 if (sclk == 0)
862 sclk = 200 * 100;
863 if (mclk == 0)
864 mclk = 200 * 100;
865
866 rdev->clock.default_sclk = sclk;
867 rdev->clock.default_mclk = mclk;
868
869 if (RBIOS32(pll_info + 0x16))
870 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
871 else
872 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
873
874 return true;
875 }
876 return false;
877 }
878
879 bool radeon_combios_sideport_present(struct radeon_device *rdev)
880 {
881 struct drm_device *dev = rdev->ddev;
882 u16 igp_info;
883
884 /* sideport is AMD only */
885 if (rdev->family == CHIP_RS400)
886 return false;
887
888 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
889
890 if (igp_info) {
891 if (RBIOS16(igp_info + 0x4))
892 return true;
893 }
894 return false;
895 }
896
897 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
898 0x00000808, /* r100 */
899 0x00000808, /* rv100 */
900 0x00000808, /* rs100 */
901 0x00000808, /* rv200 */
902 0x00000808, /* rs200 */
903 0x00000808, /* r200 */
904 0x00000808, /* rv250 */
905 0x00000000, /* rs300 */
906 0x00000808, /* rv280 */
907 0x00000808, /* r300 */
908 0x00000808, /* r350 */
909 0x00000808, /* rv350 */
910 0x00000808, /* rv380 */
911 0x00000808, /* r420 */
912 0x00000808, /* r423 */
913 0x00000808, /* rv410 */
914 0x00000000, /* rs400 */
915 0x00000000, /* rs480 */
916 };
917
918 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
919 struct radeon_encoder_primary_dac *p_dac)
920 {
921 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
922 return;
923 }
924
925 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
926 radeon_encoder
927 *encoder)
928 {
929 struct drm_device *dev = encoder->base.dev;
930 struct radeon_device *rdev = dev->dev_private;
931 uint16_t dac_info;
932 uint8_t rev, bg, dac;
933 struct radeon_encoder_primary_dac *p_dac = NULL;
934 int found = 0;
935
936 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
937 GFP_KERNEL);
938
939 if (!p_dac)
940 return NULL;
941
942 /* check CRT table */
943 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
944 if (dac_info) {
945 rev = RBIOS8(dac_info) & 0x3;
946 if (rev < 2) {
947 bg = RBIOS8(dac_info + 0x2) & 0xf;
948 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
949 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
950 } else {
951 bg = RBIOS8(dac_info + 0x2) & 0xf;
952 dac = RBIOS8(dac_info + 0x3) & 0xf;
953 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
954 }
955 /* if the values are all zeros, use the table */
956 if (p_dac->ps2_pdac_adj)
957 found = 1;
958 }
959
960 if (!found) /* fallback to defaults */
961 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
962
963 return p_dac;
964 }
965
966 enum radeon_tv_std
967 radeon_combios_get_tv_info(struct radeon_device *rdev)
968 {
969 struct drm_device *dev = rdev->ddev;
970 uint16_t tv_info;
971 enum radeon_tv_std tv_std = TV_STD_NTSC;
972
973 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
974 if (tv_info) {
975 if (RBIOS8(tv_info + 6) == 'T') {
976 switch (RBIOS8(tv_info + 7) & 0xf) {
977 case 1:
978 tv_std = TV_STD_NTSC;
979 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
980 break;
981 case 2:
982 tv_std = TV_STD_PAL;
983 DRM_DEBUG_KMS("Default TV standard: PAL\n");
984 break;
985 case 3:
986 tv_std = TV_STD_PAL_M;
987 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
988 break;
989 case 4:
990 tv_std = TV_STD_PAL_60;
991 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
992 break;
993 case 5:
994 tv_std = TV_STD_NTSC_J;
995 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
996 break;
997 case 6:
998 tv_std = TV_STD_SCART_PAL;
999 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1000 break;
1001 default:
1002 tv_std = TV_STD_NTSC;
1003 DRM_DEBUG_KMS
1004 ("Unknown TV standard; defaulting to NTSC\n");
1005 break;
1006 }
1007
1008 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1009 case 0:
1010 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1011 break;
1012 case 1:
1013 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1014 break;
1015 case 2:
1016 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1017 break;
1018 case 3:
1019 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1020 break;
1021 default:
1022 break;
1023 }
1024 }
1025 }
1026 return tv_std;
1027 }
1028
1029 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1030 0x00000000, /* r100 */
1031 0x00280000, /* rv100 */
1032 0x00000000, /* rs100 */
1033 0x00880000, /* rv200 */
1034 0x00000000, /* rs200 */
1035 0x00000000, /* r200 */
1036 0x00770000, /* rv250 */
1037 0x00290000, /* rs300 */
1038 0x00560000, /* rv280 */
1039 0x00780000, /* r300 */
1040 0x00770000, /* r350 */
1041 0x00780000, /* rv350 */
1042 0x00780000, /* rv380 */
1043 0x01080000, /* r420 */
1044 0x01080000, /* r423 */
1045 0x01080000, /* rv410 */
1046 0x00780000, /* rs400 */
1047 0x00780000, /* rs480 */
1048 };
1049
1050 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1051 struct radeon_encoder_tv_dac *tv_dac)
1052 {
1053 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1054 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1055 tv_dac->ps2_tvdac_adj = 0x00880000;
1056 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1057 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058 return;
1059 }
1060
1061 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1062 radeon_encoder
1063 *encoder)
1064 {
1065 struct drm_device *dev = encoder->base.dev;
1066 struct radeon_device *rdev = dev->dev_private;
1067 uint16_t dac_info;
1068 uint8_t rev, bg, dac;
1069 struct radeon_encoder_tv_dac *tv_dac = NULL;
1070 int found = 0;
1071
1072 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1073 if (!tv_dac)
1074 return NULL;
1075
1076 /* first check TV table */
1077 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1078 if (dac_info) {
1079 rev = RBIOS8(dac_info + 0x3);
1080 if (rev > 4) {
1081 bg = RBIOS8(dac_info + 0xc) & 0xf;
1082 dac = RBIOS8(dac_info + 0xd) & 0xf;
1083 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1084
1085 bg = RBIOS8(dac_info + 0xe) & 0xf;
1086 dac = RBIOS8(dac_info + 0xf) & 0xf;
1087 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1088
1089 bg = RBIOS8(dac_info + 0x10) & 0xf;
1090 dac = RBIOS8(dac_info + 0x11) & 0xf;
1091 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1092 /* if the values are all zeros, use the table */
1093 if (tv_dac->ps2_tvdac_adj)
1094 found = 1;
1095 } else if (rev > 1) {
1096 bg = RBIOS8(dac_info + 0xc) & 0xf;
1097 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1098 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1099
1100 bg = RBIOS8(dac_info + 0xd) & 0xf;
1101 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1102 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1103
1104 bg = RBIOS8(dac_info + 0xe) & 0xf;
1105 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1106 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1107 /* if the values are all zeros, use the table */
1108 if (tv_dac->ps2_tvdac_adj)
1109 found = 1;
1110 }
1111 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1112 }
1113 if (!found) {
1114 /* then check CRT table */
1115 dac_info =
1116 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1117 if (dac_info) {
1118 rev = RBIOS8(dac_info) & 0x3;
1119 if (rev < 2) {
1120 bg = RBIOS8(dac_info + 0x3) & 0xf;
1121 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1122 tv_dac->ps2_tvdac_adj =
1123 (bg << 16) | (dac << 20);
1124 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1125 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1126 /* if the values are all zeros, use the table */
1127 if (tv_dac->ps2_tvdac_adj)
1128 found = 1;
1129 } else {
1130 bg = RBIOS8(dac_info + 0x4) & 0xf;
1131 dac = RBIOS8(dac_info + 0x5) & 0xf;
1132 tv_dac->ps2_tvdac_adj =
1133 (bg << 16) | (dac << 20);
1134 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1135 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1136 /* if the values are all zeros, use the table */
1137 if (tv_dac->ps2_tvdac_adj)
1138 found = 1;
1139 }
1140 } else {
1141 DRM_INFO("No TV DAC info found in BIOS\n");
1142 }
1143 }
1144
1145 if (!found) /* fallback to defaults */
1146 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1147
1148 return tv_dac;
1149 }
1150
1151 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1152 radeon_device
1153 *rdev)
1154 {
1155 struct radeon_encoder_lvds *lvds = NULL;
1156 uint32_t fp_vert_stretch, fp_horz_stretch;
1157 uint32_t ppll_div_sel, ppll_val;
1158 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1159
1160 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1161
1162 if (!lvds)
1163 return NULL;
1164
1165 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1166 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1167
1168 /* These should be fail-safe defaults, fingers crossed */
1169 lvds->panel_pwr_delay = 200;
1170 lvds->panel_vcc_delay = 2000;
1171
1172 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1173 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1174 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1175
1176 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1177 lvds->native_mode.vdisplay =
1178 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1179 RADEON_VERT_PANEL_SHIFT) + 1;
1180 else
1181 lvds->native_mode.vdisplay =
1182 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1183
1184 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1185 lvds->native_mode.hdisplay =
1186 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1187 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1188 else
1189 lvds->native_mode.hdisplay =
1190 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1191
1192 if ((lvds->native_mode.hdisplay < 640) ||
1193 (lvds->native_mode.vdisplay < 480)) {
1194 lvds->native_mode.hdisplay = 640;
1195 lvds->native_mode.vdisplay = 480;
1196 }
1197
1198 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1199 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1200 if ((ppll_val & 0x000707ff) == 0x1bb)
1201 lvds->use_bios_dividers = false;
1202 else {
1203 lvds->panel_ref_divider =
1204 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1205 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1206 lvds->panel_fb_divider = ppll_val & 0x7ff;
1207
1208 if ((lvds->panel_ref_divider != 0) &&
1209 (lvds->panel_fb_divider > 3))
1210 lvds->use_bios_dividers = true;
1211 }
1212 lvds->panel_vcc_delay = 200;
1213
1214 DRM_INFO("Panel info derived from registers\n");
1215 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1216 lvds->native_mode.vdisplay);
1217
1218 return lvds;
1219 }
1220
1221 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1222 *encoder)
1223 {
1224 struct drm_device *dev = encoder->base.dev;
1225 struct radeon_device *rdev = dev->dev_private;
1226 uint16_t lcd_info;
1227 uint32_t panel_setup;
1228 char stmp[30];
1229 int tmp, i;
1230 struct radeon_encoder_lvds *lvds = NULL;
1231
1232 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1233
1234 if (lcd_info) {
1235 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1236
1237 if (!lvds)
1238 return NULL;
1239
1240 for (i = 0; i < 24; i++)
1241 stmp[i] = RBIOS8(lcd_info + i + 1);
1242 stmp[24] = 0;
1243
1244 DRM_INFO("Panel ID String: %s\n", stmp);
1245
1246 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1247 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1248
1249 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1250 lvds->native_mode.vdisplay);
1251
1252 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1253 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1254
1255 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1256 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1257 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1258
1259 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1260 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1261 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1262 if ((lvds->panel_ref_divider != 0) &&
1263 (lvds->panel_fb_divider > 3))
1264 lvds->use_bios_dividers = true;
1265
1266 panel_setup = RBIOS32(lcd_info + 0x39);
1267 lvds->lvds_gen_cntl = 0xff00;
1268 if (panel_setup & 0x1)
1269 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1270
1271 if ((panel_setup >> 4) & 0x1)
1272 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1273
1274 switch ((panel_setup >> 8) & 0x7) {
1275 case 0:
1276 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1277 break;
1278 case 1:
1279 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1280 break;
1281 case 2:
1282 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1283 break;
1284 default:
1285 break;
1286 }
1287
1288 if ((panel_setup >> 16) & 0x1)
1289 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1290
1291 if ((panel_setup >> 17) & 0x1)
1292 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1293
1294 if ((panel_setup >> 18) & 0x1)
1295 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1296
1297 if ((panel_setup >> 23) & 0x1)
1298 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1299
1300 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1301
1302 for (i = 0; i < 32; i++) {
1303 tmp = RBIOS16(lcd_info + 64 + i * 2);
1304 if (tmp == 0)
1305 break;
1306
1307 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1308 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1309 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1310 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1311 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1312 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1313 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1314 (RBIOS8(tmp + 23) * 8);
1315
1316 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1317 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1318 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1319 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1320 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1321 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1322
1323 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1324 lvds->native_mode.flags = 0;
1325 /* set crtc values */
1326 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1327
1328 }
1329 }
1330 } else {
1331 DRM_INFO("No panel info found in BIOS\n");
1332 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1333 }
1334
1335 if (lvds)
1336 encoder->native_mode = lvds->native_mode;
1337 return lvds;
1338 }
1339
1340 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1341 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1342 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1343 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1344 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1345 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1346 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1347 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1348 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1349 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1350 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1351 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1352 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1353 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1354 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1355 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1356 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1357 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1358 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1359 };
1360
1361 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1362 struct radeon_encoder_int_tmds *tmds)
1363 {
1364 struct drm_device *dev = encoder->base.dev;
1365 struct radeon_device *rdev = dev->dev_private;
1366 int i;
1367
1368 for (i = 0; i < 4; i++) {
1369 tmds->tmds_pll[i].value =
1370 default_tmds_pll[rdev->family][i].value;
1371 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1372 }
1373
1374 return true;
1375 }
1376
1377 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1378 struct radeon_encoder_int_tmds *tmds)
1379 {
1380 struct drm_device *dev = encoder->base.dev;
1381 struct radeon_device *rdev = dev->dev_private;
1382 uint16_t tmds_info;
1383 int i, n;
1384 uint8_t ver;
1385
1386 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1387
1388 if (tmds_info) {
1389 ver = RBIOS8(tmds_info);
1390 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1391 if (ver == 3) {
1392 n = RBIOS8(tmds_info + 5) + 1;
1393 if (n > 4)
1394 n = 4;
1395 for (i = 0; i < n; i++) {
1396 tmds->tmds_pll[i].value =
1397 RBIOS32(tmds_info + i * 10 + 0x08);
1398 tmds->tmds_pll[i].freq =
1399 RBIOS16(tmds_info + i * 10 + 0x10);
1400 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1401 tmds->tmds_pll[i].freq,
1402 tmds->tmds_pll[i].value);
1403 }
1404 } else if (ver == 4) {
1405 int stride = 0;
1406 n = RBIOS8(tmds_info + 5) + 1;
1407 if (n > 4)
1408 n = 4;
1409 for (i = 0; i < n; i++) {
1410 tmds->tmds_pll[i].value =
1411 RBIOS32(tmds_info + stride + 0x08);
1412 tmds->tmds_pll[i].freq =
1413 RBIOS16(tmds_info + stride + 0x10);
1414 if (i == 0)
1415 stride += 10;
1416 else
1417 stride += 6;
1418 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1419 tmds->tmds_pll[i].freq,
1420 tmds->tmds_pll[i].value);
1421 }
1422 }
1423 } else {
1424 DRM_INFO("No TMDS info found in BIOS\n");
1425 return false;
1426 }
1427 return true;
1428 }
1429
1430 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1431 struct radeon_encoder_ext_tmds *tmds)
1432 {
1433 struct drm_device *dev = encoder->base.dev;
1434 struct radeon_device *rdev = dev->dev_private;
1435 struct radeon_i2c_bus_rec i2c_bus;
1436
1437 /* default for macs */
1438 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1439 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440
1441 /* XXX some macs have duallink chips */
1442 switch (rdev->mode_info.connector_table) {
1443 case CT_POWERBOOK_EXTERNAL:
1444 case CT_MINI_EXTERNAL:
1445 default:
1446 tmds->dvo_chip = DVO_SIL164;
1447 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1448 break;
1449 }
1450
1451 return true;
1452 }
1453
1454 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1455 struct radeon_encoder_ext_tmds *tmds)
1456 {
1457 struct drm_device *dev = encoder->base.dev;
1458 struct radeon_device *rdev = dev->dev_private;
1459 uint16_t offset;
1460 uint8_t ver;
1461 enum radeon_combios_ddc gpio;
1462 struct radeon_i2c_bus_rec i2c_bus;
1463
1464 tmds->i2c_bus = NULL;
1465 if (rdev->flags & RADEON_IS_IGP) {
1466 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1467 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1468 tmds->dvo_chip = DVO_SIL164;
1469 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1470 } else {
1471 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1472 if (offset) {
1473 ver = RBIOS8(offset);
1474 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1475 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1476 tmds->slave_addr >>= 1; /* 7 bit addressing */
1477 gpio = RBIOS8(offset + 4 + 3);
1478 if (gpio == DDC_LCD) {
1479 /* MM i2c */
1480 i2c_bus.valid = true;
1481 i2c_bus.hw_capable = true;
1482 i2c_bus.mm_i2c = true;
1483 i2c_bus.i2c_id = 0xa0;
1484 } else
1485 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1486 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1487 }
1488 }
1489
1490 if (!tmds->i2c_bus) {
1491 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1492 return false;
1493 }
1494
1495 return true;
1496 }
1497
1498 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1499 {
1500 struct radeon_device *rdev = dev->dev_private;
1501 struct radeon_i2c_bus_rec ddc_i2c;
1502 struct radeon_hpd hpd;
1503
1504 rdev->mode_info.connector_table = radeon_connector_table;
1505 if (rdev->mode_info.connector_table == CT_NONE) {
1506 #ifdef CONFIG_PPC_PMAC
1507 if (of_machine_is_compatible("PowerBook3,3")) {
1508 /* powerbook with VGA */
1509 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1510 } else if (of_machine_is_compatible("PowerBook3,4") ||
1511 of_machine_is_compatible("PowerBook3,5")) {
1512 /* powerbook with internal tmds */
1513 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1514 } else if (of_machine_is_compatible("PowerBook5,1") ||
1515 of_machine_is_compatible("PowerBook5,2") ||
1516 of_machine_is_compatible("PowerBook5,3") ||
1517 of_machine_is_compatible("PowerBook5,4") ||
1518 of_machine_is_compatible("PowerBook5,5")) {
1519 /* powerbook with external single link tmds (sil164) */
1520 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1521 } else if (of_machine_is_compatible("PowerBook5,6")) {
1522 /* powerbook with external dual or single link tmds */
1523 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1524 } else if (of_machine_is_compatible("PowerBook5,7") ||
1525 of_machine_is_compatible("PowerBook5,8") ||
1526 of_machine_is_compatible("PowerBook5,9")) {
1527 /* PowerBook6,2 ? */
1528 /* powerbook with external dual link tmds (sil1178?) */
1529 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1530 } else if (of_machine_is_compatible("PowerBook4,1") ||
1531 of_machine_is_compatible("PowerBook4,2") ||
1532 of_machine_is_compatible("PowerBook4,3") ||
1533 of_machine_is_compatible("PowerBook6,3") ||
1534 of_machine_is_compatible("PowerBook6,5") ||
1535 of_machine_is_compatible("PowerBook6,7")) {
1536 /* ibook */
1537 rdev->mode_info.connector_table = CT_IBOOK;
1538 } else if (of_machine_is_compatible("PowerMac4,4")) {
1539 /* emac */
1540 rdev->mode_info.connector_table = CT_EMAC;
1541 } else if (of_machine_is_compatible("PowerMac10,1")) {
1542 /* mini with internal tmds */
1543 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1544 } else if (of_machine_is_compatible("PowerMac10,2")) {
1545 /* mini with external tmds */
1546 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1547 } else if (of_machine_is_compatible("PowerMac12,1")) {
1548 /* PowerMac8,1 ? */
1549 /* imac g5 isight */
1550 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1551 } else if ((rdev->pdev->device == 0x4a48) &&
1552 (rdev->pdev->subsystem_vendor == 0x1002) &&
1553 (rdev->pdev->subsystem_device == 0x4a48)) {
1554 /* Mac X800 */
1555 rdev->mode_info.connector_table = CT_MAC_X800;
1556 } else if (of_machine_is_compatible("PowerMac7,2") ||
1557 of_machine_is_compatible("PowerMac7,3")) {
1558 /* Mac G5 9600 */
1559 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1560 } else
1561 #endif /* CONFIG_PPC_PMAC */
1562 #ifdef CONFIG_PPC64
1563 if (ASIC_IS_RN50(rdev))
1564 rdev->mode_info.connector_table = CT_RN50_POWER;
1565 else
1566 #endif
1567 rdev->mode_info.connector_table = CT_GENERIC;
1568 }
1569
1570 switch (rdev->mode_info.connector_table) {
1571 case CT_GENERIC:
1572 DRM_INFO("Connector Table: %d (generic)\n",
1573 rdev->mode_info.connector_table);
1574 /* these are the most common settings */
1575 if (rdev->flags & RADEON_SINGLE_CRTC) {
1576 /* VGA - primary dac */
1577 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1578 hpd.hpd = RADEON_HPD_NONE;
1579 radeon_add_legacy_encoder(dev,
1580 radeon_get_encoder_enum(dev,
1581 ATOM_DEVICE_CRT1_SUPPORT,
1582 1),
1583 ATOM_DEVICE_CRT1_SUPPORT);
1584 radeon_add_legacy_connector(dev, 0,
1585 ATOM_DEVICE_CRT1_SUPPORT,
1586 DRM_MODE_CONNECTOR_VGA,
1587 &ddc_i2c,
1588 CONNECTOR_OBJECT_ID_VGA,
1589 &hpd);
1590 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1591 /* LVDS */
1592 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1593 hpd.hpd = RADEON_HPD_NONE;
1594 radeon_add_legacy_encoder(dev,
1595 radeon_get_encoder_enum(dev,
1596 ATOM_DEVICE_LCD1_SUPPORT,
1597 0),
1598 ATOM_DEVICE_LCD1_SUPPORT);
1599 radeon_add_legacy_connector(dev, 0,
1600 ATOM_DEVICE_LCD1_SUPPORT,
1601 DRM_MODE_CONNECTOR_LVDS,
1602 &ddc_i2c,
1603 CONNECTOR_OBJECT_ID_LVDS,
1604 &hpd);
1605
1606 /* VGA - primary dac */
1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1608 hpd.hpd = RADEON_HPD_NONE;
1609 radeon_add_legacy_encoder(dev,
1610 radeon_get_encoder_enum(dev,
1611 ATOM_DEVICE_CRT1_SUPPORT,
1612 1),
1613 ATOM_DEVICE_CRT1_SUPPORT);
1614 radeon_add_legacy_connector(dev, 1,
1615 ATOM_DEVICE_CRT1_SUPPORT,
1616 DRM_MODE_CONNECTOR_VGA,
1617 &ddc_i2c,
1618 CONNECTOR_OBJECT_ID_VGA,
1619 &hpd);
1620 } else {
1621 /* DVI-I - tv dac, int tmds */
1622 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1623 hpd.hpd = RADEON_HPD_1;
1624 radeon_add_legacy_encoder(dev,
1625 radeon_get_encoder_enum(dev,
1626 ATOM_DEVICE_DFP1_SUPPORT,
1627 0),
1628 ATOM_DEVICE_DFP1_SUPPORT);
1629 radeon_add_legacy_encoder(dev,
1630 radeon_get_encoder_enum(dev,
1631 ATOM_DEVICE_CRT2_SUPPORT,
1632 2),
1633 ATOM_DEVICE_CRT2_SUPPORT);
1634 radeon_add_legacy_connector(dev, 0,
1635 ATOM_DEVICE_DFP1_SUPPORT |
1636 ATOM_DEVICE_CRT2_SUPPORT,
1637 DRM_MODE_CONNECTOR_DVII,
1638 &ddc_i2c,
1639 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1640 &hpd);
1641
1642 /* VGA - primary dac */
1643 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1644 hpd.hpd = RADEON_HPD_NONE;
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_enum(dev,
1647 ATOM_DEVICE_CRT1_SUPPORT,
1648 1),
1649 ATOM_DEVICE_CRT1_SUPPORT);
1650 radeon_add_legacy_connector(dev, 1,
1651 ATOM_DEVICE_CRT1_SUPPORT,
1652 DRM_MODE_CONNECTOR_VGA,
1653 &ddc_i2c,
1654 CONNECTOR_OBJECT_ID_VGA,
1655 &hpd);
1656 }
1657
1658 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1659 /* TV - tv dac */
1660 ddc_i2c.valid = false;
1661 hpd.hpd = RADEON_HPD_NONE;
1662 radeon_add_legacy_encoder(dev,
1663 radeon_get_encoder_enum(dev,
1664 ATOM_DEVICE_TV1_SUPPORT,
1665 2),
1666 ATOM_DEVICE_TV1_SUPPORT);
1667 radeon_add_legacy_connector(dev, 2,
1668 ATOM_DEVICE_TV1_SUPPORT,
1669 DRM_MODE_CONNECTOR_SVIDEO,
1670 &ddc_i2c,
1671 CONNECTOR_OBJECT_ID_SVIDEO,
1672 &hpd);
1673 }
1674 break;
1675 case CT_IBOOK:
1676 DRM_INFO("Connector Table: %d (ibook)\n",
1677 rdev->mode_info.connector_table);
1678 /* LVDS */
1679 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1680 hpd.hpd = RADEON_HPD_NONE;
1681 radeon_add_legacy_encoder(dev,
1682 radeon_get_encoder_enum(dev,
1683 ATOM_DEVICE_LCD1_SUPPORT,
1684 0),
1685 ATOM_DEVICE_LCD1_SUPPORT);
1686 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1687 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1688 CONNECTOR_OBJECT_ID_LVDS,
1689 &hpd);
1690 /* VGA - TV DAC */
1691 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1692 hpd.hpd = RADEON_HPD_NONE;
1693 radeon_add_legacy_encoder(dev,
1694 radeon_get_encoder_enum(dev,
1695 ATOM_DEVICE_CRT2_SUPPORT,
1696 2),
1697 ATOM_DEVICE_CRT2_SUPPORT);
1698 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1699 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1700 CONNECTOR_OBJECT_ID_VGA,
1701 &hpd);
1702 /* TV - TV DAC */
1703 ddc_i2c.valid = false;
1704 hpd.hpd = RADEON_HPD_NONE;
1705 radeon_add_legacy_encoder(dev,
1706 radeon_get_encoder_enum(dev,
1707 ATOM_DEVICE_TV1_SUPPORT,
1708 2),
1709 ATOM_DEVICE_TV1_SUPPORT);
1710 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1711 DRM_MODE_CONNECTOR_SVIDEO,
1712 &ddc_i2c,
1713 CONNECTOR_OBJECT_ID_SVIDEO,
1714 &hpd);
1715 break;
1716 case CT_POWERBOOK_EXTERNAL:
1717 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1718 rdev->mode_info.connector_table);
1719 /* LVDS */
1720 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1721 hpd.hpd = RADEON_HPD_NONE;
1722 radeon_add_legacy_encoder(dev,
1723 radeon_get_encoder_enum(dev,
1724 ATOM_DEVICE_LCD1_SUPPORT,
1725 0),
1726 ATOM_DEVICE_LCD1_SUPPORT);
1727 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1728 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1729 CONNECTOR_OBJECT_ID_LVDS,
1730 &hpd);
1731 /* DVI-I - primary dac, ext tmds */
1732 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1733 hpd.hpd = RADEON_HPD_2; /* ??? */
1734 radeon_add_legacy_encoder(dev,
1735 radeon_get_encoder_enum(dev,
1736 ATOM_DEVICE_DFP2_SUPPORT,
1737 0),
1738 ATOM_DEVICE_DFP2_SUPPORT);
1739 radeon_add_legacy_encoder(dev,
1740 radeon_get_encoder_enum(dev,
1741 ATOM_DEVICE_CRT1_SUPPORT,
1742 1),
1743 ATOM_DEVICE_CRT1_SUPPORT);
1744 /* XXX some are SL */
1745 radeon_add_legacy_connector(dev, 1,
1746 ATOM_DEVICE_DFP2_SUPPORT |
1747 ATOM_DEVICE_CRT1_SUPPORT,
1748 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1749 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1750 &hpd);
1751 /* TV - TV DAC */
1752 ddc_i2c.valid = false;
1753 hpd.hpd = RADEON_HPD_NONE;
1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_enum(dev,
1756 ATOM_DEVICE_TV1_SUPPORT,
1757 2),
1758 ATOM_DEVICE_TV1_SUPPORT);
1759 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1760 DRM_MODE_CONNECTOR_SVIDEO,
1761 &ddc_i2c,
1762 CONNECTOR_OBJECT_ID_SVIDEO,
1763 &hpd);
1764 break;
1765 case CT_POWERBOOK_INTERNAL:
1766 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1767 rdev->mode_info.connector_table);
1768 /* LVDS */
1769 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1770 hpd.hpd = RADEON_HPD_NONE;
1771 radeon_add_legacy_encoder(dev,
1772 radeon_get_encoder_enum(dev,
1773 ATOM_DEVICE_LCD1_SUPPORT,
1774 0),
1775 ATOM_DEVICE_LCD1_SUPPORT);
1776 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1777 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1778 CONNECTOR_OBJECT_ID_LVDS,
1779 &hpd);
1780 /* DVI-I - primary dac, int tmds */
1781 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1782 hpd.hpd = RADEON_HPD_1; /* ??? */
1783 radeon_add_legacy_encoder(dev,
1784 radeon_get_encoder_enum(dev,
1785 ATOM_DEVICE_DFP1_SUPPORT,
1786 0),
1787 ATOM_DEVICE_DFP1_SUPPORT);
1788 radeon_add_legacy_encoder(dev,
1789 radeon_get_encoder_enum(dev,
1790 ATOM_DEVICE_CRT1_SUPPORT,
1791 1),
1792 ATOM_DEVICE_CRT1_SUPPORT);
1793 radeon_add_legacy_connector(dev, 1,
1794 ATOM_DEVICE_DFP1_SUPPORT |
1795 ATOM_DEVICE_CRT1_SUPPORT,
1796 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1797 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1798 &hpd);
1799 /* TV - TV DAC */
1800 ddc_i2c.valid = false;
1801 hpd.hpd = RADEON_HPD_NONE;
1802 radeon_add_legacy_encoder(dev,
1803 radeon_get_encoder_enum(dev,
1804 ATOM_DEVICE_TV1_SUPPORT,
1805 2),
1806 ATOM_DEVICE_TV1_SUPPORT);
1807 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1808 DRM_MODE_CONNECTOR_SVIDEO,
1809 &ddc_i2c,
1810 CONNECTOR_OBJECT_ID_SVIDEO,
1811 &hpd);
1812 break;
1813 case CT_POWERBOOK_VGA:
1814 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1815 rdev->mode_info.connector_table);
1816 /* LVDS */
1817 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1818 hpd.hpd = RADEON_HPD_NONE;
1819 radeon_add_legacy_encoder(dev,
1820 radeon_get_encoder_enum(dev,
1821 ATOM_DEVICE_LCD1_SUPPORT,
1822 0),
1823 ATOM_DEVICE_LCD1_SUPPORT);
1824 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1825 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1826 CONNECTOR_OBJECT_ID_LVDS,
1827 &hpd);
1828 /* VGA - primary dac */
1829 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1830 hpd.hpd = RADEON_HPD_NONE;
1831 radeon_add_legacy_encoder(dev,
1832 radeon_get_encoder_enum(dev,
1833 ATOM_DEVICE_CRT1_SUPPORT,
1834 1),
1835 ATOM_DEVICE_CRT1_SUPPORT);
1836 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1837 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1838 CONNECTOR_OBJECT_ID_VGA,
1839 &hpd);
1840 /* TV - TV DAC */
1841 ddc_i2c.valid = false;
1842 hpd.hpd = RADEON_HPD_NONE;
1843 radeon_add_legacy_encoder(dev,
1844 radeon_get_encoder_enum(dev,
1845 ATOM_DEVICE_TV1_SUPPORT,
1846 2),
1847 ATOM_DEVICE_TV1_SUPPORT);
1848 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1849 DRM_MODE_CONNECTOR_SVIDEO,
1850 &ddc_i2c,
1851 CONNECTOR_OBJECT_ID_SVIDEO,
1852 &hpd);
1853 break;
1854 case CT_MINI_EXTERNAL:
1855 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1856 rdev->mode_info.connector_table);
1857 /* DVI-I - tv dac, ext tmds */
1858 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1859 hpd.hpd = RADEON_HPD_2; /* ??? */
1860 radeon_add_legacy_encoder(dev,
1861 radeon_get_encoder_enum(dev,
1862 ATOM_DEVICE_DFP2_SUPPORT,
1863 0),
1864 ATOM_DEVICE_DFP2_SUPPORT);
1865 radeon_add_legacy_encoder(dev,
1866 radeon_get_encoder_enum(dev,
1867 ATOM_DEVICE_CRT2_SUPPORT,
1868 2),
1869 ATOM_DEVICE_CRT2_SUPPORT);
1870 /* XXX are any DL? */
1871 radeon_add_legacy_connector(dev, 0,
1872 ATOM_DEVICE_DFP2_SUPPORT |
1873 ATOM_DEVICE_CRT2_SUPPORT,
1874 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1875 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1876 &hpd);
1877 /* TV - TV DAC */
1878 ddc_i2c.valid = false;
1879 hpd.hpd = RADEON_HPD_NONE;
1880 radeon_add_legacy_encoder(dev,
1881 radeon_get_encoder_enum(dev,
1882 ATOM_DEVICE_TV1_SUPPORT,
1883 2),
1884 ATOM_DEVICE_TV1_SUPPORT);
1885 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1886 DRM_MODE_CONNECTOR_SVIDEO,
1887 &ddc_i2c,
1888 CONNECTOR_OBJECT_ID_SVIDEO,
1889 &hpd);
1890 break;
1891 case CT_MINI_INTERNAL:
1892 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1893 rdev->mode_info.connector_table);
1894 /* DVI-I - tv dac, int tmds */
1895 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1896 hpd.hpd = RADEON_HPD_1; /* ??? */
1897 radeon_add_legacy_encoder(dev,
1898 radeon_get_encoder_enum(dev,
1899 ATOM_DEVICE_DFP1_SUPPORT,
1900 0),
1901 ATOM_DEVICE_DFP1_SUPPORT);
1902 radeon_add_legacy_encoder(dev,
1903 radeon_get_encoder_enum(dev,
1904 ATOM_DEVICE_CRT2_SUPPORT,
1905 2),
1906 ATOM_DEVICE_CRT2_SUPPORT);
1907 radeon_add_legacy_connector(dev, 0,
1908 ATOM_DEVICE_DFP1_SUPPORT |
1909 ATOM_DEVICE_CRT2_SUPPORT,
1910 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1911 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1912 &hpd);
1913 /* TV - TV DAC */
1914 ddc_i2c.valid = false;
1915 hpd.hpd = RADEON_HPD_NONE;
1916 radeon_add_legacy_encoder(dev,
1917 radeon_get_encoder_enum(dev,
1918 ATOM_DEVICE_TV1_SUPPORT,
1919 2),
1920 ATOM_DEVICE_TV1_SUPPORT);
1921 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1922 DRM_MODE_CONNECTOR_SVIDEO,
1923 &ddc_i2c,
1924 CONNECTOR_OBJECT_ID_SVIDEO,
1925 &hpd);
1926 break;
1927 case CT_IMAC_G5_ISIGHT:
1928 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1929 rdev->mode_info.connector_table);
1930 /* DVI-D - int tmds */
1931 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1932 hpd.hpd = RADEON_HPD_1; /* ??? */
1933 radeon_add_legacy_encoder(dev,
1934 radeon_get_encoder_enum(dev,
1935 ATOM_DEVICE_DFP1_SUPPORT,
1936 0),
1937 ATOM_DEVICE_DFP1_SUPPORT);
1938 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1939 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1940 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1941 &hpd);
1942 /* VGA - tv dac */
1943 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1944 hpd.hpd = RADEON_HPD_NONE;
1945 radeon_add_legacy_encoder(dev,
1946 radeon_get_encoder_enum(dev,
1947 ATOM_DEVICE_CRT2_SUPPORT,
1948 2),
1949 ATOM_DEVICE_CRT2_SUPPORT);
1950 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1951 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1952 CONNECTOR_OBJECT_ID_VGA,
1953 &hpd);
1954 /* TV - TV DAC */
1955 ddc_i2c.valid = false;
1956 hpd.hpd = RADEON_HPD_NONE;
1957 radeon_add_legacy_encoder(dev,
1958 radeon_get_encoder_enum(dev,
1959 ATOM_DEVICE_TV1_SUPPORT,
1960 2),
1961 ATOM_DEVICE_TV1_SUPPORT);
1962 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1963 DRM_MODE_CONNECTOR_SVIDEO,
1964 &ddc_i2c,
1965 CONNECTOR_OBJECT_ID_SVIDEO,
1966 &hpd);
1967 break;
1968 case CT_EMAC:
1969 DRM_INFO("Connector Table: %d (emac)\n",
1970 rdev->mode_info.connector_table);
1971 /* VGA - primary dac */
1972 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1973 hpd.hpd = RADEON_HPD_NONE;
1974 radeon_add_legacy_encoder(dev,
1975 radeon_get_encoder_enum(dev,
1976 ATOM_DEVICE_CRT1_SUPPORT,
1977 1),
1978 ATOM_DEVICE_CRT1_SUPPORT);
1979 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1980 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1981 CONNECTOR_OBJECT_ID_VGA,
1982 &hpd);
1983 /* VGA - tv dac */
1984 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1985 hpd.hpd = RADEON_HPD_NONE;
1986 radeon_add_legacy_encoder(dev,
1987 radeon_get_encoder_enum(dev,
1988 ATOM_DEVICE_CRT2_SUPPORT,
1989 2),
1990 ATOM_DEVICE_CRT2_SUPPORT);
1991 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1992 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1993 CONNECTOR_OBJECT_ID_VGA,
1994 &hpd);
1995 /* TV - TV DAC */
1996 ddc_i2c.valid = false;
1997 hpd.hpd = RADEON_HPD_NONE;
1998 radeon_add_legacy_encoder(dev,
1999 radeon_get_encoder_enum(dev,
2000 ATOM_DEVICE_TV1_SUPPORT,
2001 2),
2002 ATOM_DEVICE_TV1_SUPPORT);
2003 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2004 DRM_MODE_CONNECTOR_SVIDEO,
2005 &ddc_i2c,
2006 CONNECTOR_OBJECT_ID_SVIDEO,
2007 &hpd);
2008 break;
2009 case CT_RN50_POWER:
2010 DRM_INFO("Connector Table: %d (rn50-power)\n",
2011 rdev->mode_info.connector_table);
2012 /* VGA - primary dac */
2013 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2014 hpd.hpd = RADEON_HPD_NONE;
2015 radeon_add_legacy_encoder(dev,
2016 radeon_get_encoder_enum(dev,
2017 ATOM_DEVICE_CRT1_SUPPORT,
2018 1),
2019 ATOM_DEVICE_CRT1_SUPPORT);
2020 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2021 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2022 CONNECTOR_OBJECT_ID_VGA,
2023 &hpd);
2024 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2025 hpd.hpd = RADEON_HPD_NONE;
2026 radeon_add_legacy_encoder(dev,
2027 radeon_get_encoder_enum(dev,
2028 ATOM_DEVICE_CRT2_SUPPORT,
2029 2),
2030 ATOM_DEVICE_CRT2_SUPPORT);
2031 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2032 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2033 CONNECTOR_OBJECT_ID_VGA,
2034 &hpd);
2035 break;
2036 case CT_MAC_X800:
2037 DRM_INFO("Connector Table: %d (mac x800)\n",
2038 rdev->mode_info.connector_table);
2039 /* DVI - primary dac, internal tmds */
2040 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2041 hpd.hpd = RADEON_HPD_1; /* ??? */
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_enum(dev,
2044 ATOM_DEVICE_DFP1_SUPPORT,
2045 0),
2046 ATOM_DEVICE_DFP1_SUPPORT);
2047 radeon_add_legacy_encoder(dev,
2048 radeon_get_encoder_enum(dev,
2049 ATOM_DEVICE_CRT1_SUPPORT,
2050 1),
2051 ATOM_DEVICE_CRT1_SUPPORT);
2052 radeon_add_legacy_connector(dev, 0,
2053 ATOM_DEVICE_DFP1_SUPPORT |
2054 ATOM_DEVICE_CRT1_SUPPORT,
2055 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2056 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2057 &hpd);
2058 /* DVI - tv dac, dvo */
2059 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2060 hpd.hpd = RADEON_HPD_2; /* ??? */
2061 radeon_add_legacy_encoder(dev,
2062 radeon_get_encoder_enum(dev,
2063 ATOM_DEVICE_DFP2_SUPPORT,
2064 0),
2065 ATOM_DEVICE_DFP2_SUPPORT);
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_enum(dev,
2068 ATOM_DEVICE_CRT2_SUPPORT,
2069 2),
2070 ATOM_DEVICE_CRT2_SUPPORT);
2071 radeon_add_legacy_connector(dev, 1,
2072 ATOM_DEVICE_DFP2_SUPPORT |
2073 ATOM_DEVICE_CRT2_SUPPORT,
2074 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2075 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2076 &hpd);
2077 break;
2078 case CT_MAC_G5_9600:
2079 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2080 rdev->mode_info.connector_table);
2081 /* DVI - tv dac, dvo */
2082 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2083 hpd.hpd = RADEON_HPD_1; /* ??? */
2084 radeon_add_legacy_encoder(dev,
2085 radeon_get_encoder_enum(dev,
2086 ATOM_DEVICE_DFP2_SUPPORT,
2087 0),
2088 ATOM_DEVICE_DFP2_SUPPORT);
2089 radeon_add_legacy_encoder(dev,
2090 radeon_get_encoder_enum(dev,
2091 ATOM_DEVICE_CRT2_SUPPORT,
2092 2),
2093 ATOM_DEVICE_CRT2_SUPPORT);
2094 radeon_add_legacy_connector(dev, 0,
2095 ATOM_DEVICE_DFP2_SUPPORT |
2096 ATOM_DEVICE_CRT2_SUPPORT,
2097 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2098 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2099 &hpd);
2100 /* ADC - primary dac, internal tmds */
2101 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2102 hpd.hpd = RADEON_HPD_2; /* ??? */
2103 radeon_add_legacy_encoder(dev,
2104 radeon_get_encoder_enum(dev,
2105 ATOM_DEVICE_DFP1_SUPPORT,
2106 0),
2107 ATOM_DEVICE_DFP1_SUPPORT);
2108 radeon_add_legacy_encoder(dev,
2109 radeon_get_encoder_enum(dev,
2110 ATOM_DEVICE_CRT1_SUPPORT,
2111 1),
2112 ATOM_DEVICE_CRT1_SUPPORT);
2113 radeon_add_legacy_connector(dev, 1,
2114 ATOM_DEVICE_DFP1_SUPPORT |
2115 ATOM_DEVICE_CRT1_SUPPORT,
2116 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2117 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2118 &hpd);
2119 /* TV - TV DAC */
2120 ddc_i2c.valid = false;
2121 hpd.hpd = RADEON_HPD_NONE;
2122 radeon_add_legacy_encoder(dev,
2123 radeon_get_encoder_enum(dev,
2124 ATOM_DEVICE_TV1_SUPPORT,
2125 2),
2126 ATOM_DEVICE_TV1_SUPPORT);
2127 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2128 DRM_MODE_CONNECTOR_SVIDEO,
2129 &ddc_i2c,
2130 CONNECTOR_OBJECT_ID_SVIDEO,
2131 &hpd);
2132 break;
2133 default:
2134 DRM_INFO("Connector table: %d (invalid)\n",
2135 rdev->mode_info.connector_table);
2136 return false;
2137 }
2138
2139 radeon_link_encoder_connector(dev);
2140
2141 return true;
2142 }
2143
2144 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2145 int bios_index,
2146 enum radeon_combios_connector
2147 *legacy_connector,
2148 struct radeon_i2c_bus_rec *ddc_i2c,
2149 struct radeon_hpd *hpd)
2150 {
2151
2152 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2153 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2154 if (dev->pdev->device == 0x515e &&
2155 dev->pdev->subsystem_vendor == 0x1014) {
2156 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2157 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2158 return false;
2159 }
2160
2161 /* X300 card with extra non-existent DVI port */
2162 if (dev->pdev->device == 0x5B60 &&
2163 dev->pdev->subsystem_vendor == 0x17af &&
2164 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2165 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2166 return false;
2167 }
2168
2169 return true;
2170 }
2171
2172 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2173 {
2174 /* Acer 5102 has non-existent TV port */
2175 if (dev->pdev->device == 0x5975 &&
2176 dev->pdev->subsystem_vendor == 0x1025 &&
2177 dev->pdev->subsystem_device == 0x009f)
2178 return false;
2179
2180 /* HP dc5750 has non-existent TV port */
2181 if (dev->pdev->device == 0x5974 &&
2182 dev->pdev->subsystem_vendor == 0x103c &&
2183 dev->pdev->subsystem_device == 0x280a)
2184 return false;
2185
2186 /* MSI S270 has non-existent TV port */
2187 if (dev->pdev->device == 0x5955 &&
2188 dev->pdev->subsystem_vendor == 0x1462 &&
2189 dev->pdev->subsystem_device == 0x0131)
2190 return false;
2191
2192 return true;
2193 }
2194
2195 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2196 {
2197 struct radeon_device *rdev = dev->dev_private;
2198 uint32_t ext_tmds_info;
2199
2200 if (rdev->flags & RADEON_IS_IGP) {
2201 if (is_dvi_d)
2202 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2203 else
2204 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2205 }
2206 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2207 if (ext_tmds_info) {
2208 uint8_t rev = RBIOS8(ext_tmds_info);
2209 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2210 if (rev >= 3) {
2211 if (is_dvi_d)
2212 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2213 else
2214 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2215 } else {
2216 if (flags & 1) {
2217 if (is_dvi_d)
2218 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2219 else
2220 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2221 }
2222 }
2223 }
2224 if (is_dvi_d)
2225 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2226 else
2227 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2228 }
2229
2230 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2231 {
2232 struct radeon_device *rdev = dev->dev_private;
2233 uint32_t conn_info, entry, devices;
2234 uint16_t tmp, connector_object_id;
2235 enum radeon_combios_ddc ddc_type;
2236 enum radeon_combios_connector connector;
2237 int i = 0;
2238 struct radeon_i2c_bus_rec ddc_i2c;
2239 struct radeon_hpd hpd;
2240
2241 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2242 if (conn_info) {
2243 for (i = 0; i < 4; i++) {
2244 entry = conn_info + 2 + i * 2;
2245
2246 if (!RBIOS16(entry))
2247 break;
2248
2249 tmp = RBIOS16(entry);
2250
2251 connector = (tmp >> 12) & 0xf;
2252
2253 ddc_type = (tmp >> 8) & 0xf;
2254 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2255
2256 switch (connector) {
2257 case CONNECTOR_PROPRIETARY_LEGACY:
2258 case CONNECTOR_DVI_I_LEGACY:
2259 case CONNECTOR_DVI_D_LEGACY:
2260 if ((tmp >> 4) & 0x1)
2261 hpd.hpd = RADEON_HPD_2;
2262 else
2263 hpd.hpd = RADEON_HPD_1;
2264 break;
2265 default:
2266 hpd.hpd = RADEON_HPD_NONE;
2267 break;
2268 }
2269
2270 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2271 &ddc_i2c, &hpd))
2272 continue;
2273
2274 switch (connector) {
2275 case CONNECTOR_PROPRIETARY_LEGACY:
2276 if ((tmp >> 4) & 0x1)
2277 devices = ATOM_DEVICE_DFP2_SUPPORT;
2278 else
2279 devices = ATOM_DEVICE_DFP1_SUPPORT;
2280 radeon_add_legacy_encoder(dev,
2281 radeon_get_encoder_enum
2282 (dev, devices, 0),
2283 devices);
2284 radeon_add_legacy_connector(dev, i, devices,
2285 legacy_connector_convert
2286 [connector],
2287 &ddc_i2c,
2288 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2289 &hpd);
2290 break;
2291 case CONNECTOR_CRT_LEGACY:
2292 if (tmp & 0x1) {
2293 devices = ATOM_DEVICE_CRT2_SUPPORT;
2294 radeon_add_legacy_encoder(dev,
2295 radeon_get_encoder_enum
2296 (dev,
2297 ATOM_DEVICE_CRT2_SUPPORT,
2298 2),
2299 ATOM_DEVICE_CRT2_SUPPORT);
2300 } else {
2301 devices = ATOM_DEVICE_CRT1_SUPPORT;
2302 radeon_add_legacy_encoder(dev,
2303 radeon_get_encoder_enum
2304 (dev,
2305 ATOM_DEVICE_CRT1_SUPPORT,
2306 1),
2307 ATOM_DEVICE_CRT1_SUPPORT);
2308 }
2309 radeon_add_legacy_connector(dev,
2310 i,
2311 devices,
2312 legacy_connector_convert
2313 [connector],
2314 &ddc_i2c,
2315 CONNECTOR_OBJECT_ID_VGA,
2316 &hpd);
2317 break;
2318 case CONNECTOR_DVI_I_LEGACY:
2319 devices = 0;
2320 if (tmp & 0x1) {
2321 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2322 radeon_add_legacy_encoder(dev,
2323 radeon_get_encoder_enum
2324 (dev,
2325 ATOM_DEVICE_CRT2_SUPPORT,
2326 2),
2327 ATOM_DEVICE_CRT2_SUPPORT);
2328 } else {
2329 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2330 radeon_add_legacy_encoder(dev,
2331 radeon_get_encoder_enum
2332 (dev,
2333 ATOM_DEVICE_CRT1_SUPPORT,
2334 1),
2335 ATOM_DEVICE_CRT1_SUPPORT);
2336 }
2337 if ((tmp >> 4) & 0x1) {
2338 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2339 radeon_add_legacy_encoder(dev,
2340 radeon_get_encoder_enum
2341 (dev,
2342 ATOM_DEVICE_DFP2_SUPPORT,
2343 0),
2344 ATOM_DEVICE_DFP2_SUPPORT);
2345 connector_object_id = combios_check_dl_dvi(dev, 0);
2346 } else {
2347 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2348 radeon_add_legacy_encoder(dev,
2349 radeon_get_encoder_enum
2350 (dev,
2351 ATOM_DEVICE_DFP1_SUPPORT,
2352 0),
2353 ATOM_DEVICE_DFP1_SUPPORT);
2354 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2355 }
2356 radeon_add_legacy_connector(dev,
2357 i,
2358 devices,
2359 legacy_connector_convert
2360 [connector],
2361 &ddc_i2c,
2362 connector_object_id,
2363 &hpd);
2364 break;
2365 case CONNECTOR_DVI_D_LEGACY:
2366 if ((tmp >> 4) & 0x1) {
2367 devices = ATOM_DEVICE_DFP2_SUPPORT;
2368 connector_object_id = combios_check_dl_dvi(dev, 1);
2369 } else {
2370 devices = ATOM_DEVICE_DFP1_SUPPORT;
2371 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2372 }
2373 radeon_add_legacy_encoder(dev,
2374 radeon_get_encoder_enum
2375 (dev, devices, 0),
2376 devices);
2377 radeon_add_legacy_connector(dev, i, devices,
2378 legacy_connector_convert
2379 [connector],
2380 &ddc_i2c,
2381 connector_object_id,
2382 &hpd);
2383 break;
2384 case CONNECTOR_CTV_LEGACY:
2385 case CONNECTOR_STV_LEGACY:
2386 radeon_add_legacy_encoder(dev,
2387 radeon_get_encoder_enum
2388 (dev,
2389 ATOM_DEVICE_TV1_SUPPORT,
2390 2),
2391 ATOM_DEVICE_TV1_SUPPORT);
2392 radeon_add_legacy_connector(dev, i,
2393 ATOM_DEVICE_TV1_SUPPORT,
2394 legacy_connector_convert
2395 [connector],
2396 &ddc_i2c,
2397 CONNECTOR_OBJECT_ID_SVIDEO,
2398 &hpd);
2399 break;
2400 default:
2401 DRM_ERROR("Unknown connector type: %d\n",
2402 connector);
2403 continue;
2404 }
2405
2406 }
2407 } else {
2408 uint16_t tmds_info =
2409 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2410 if (tmds_info) {
2411 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2412
2413 radeon_add_legacy_encoder(dev,
2414 radeon_get_encoder_enum(dev,
2415 ATOM_DEVICE_CRT1_SUPPORT,
2416 1),
2417 ATOM_DEVICE_CRT1_SUPPORT);
2418 radeon_add_legacy_encoder(dev,
2419 radeon_get_encoder_enum(dev,
2420 ATOM_DEVICE_DFP1_SUPPORT,
2421 0),
2422 ATOM_DEVICE_DFP1_SUPPORT);
2423
2424 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2425 hpd.hpd = RADEON_HPD_1;
2426 radeon_add_legacy_connector(dev,
2427 0,
2428 ATOM_DEVICE_CRT1_SUPPORT |
2429 ATOM_DEVICE_DFP1_SUPPORT,
2430 DRM_MODE_CONNECTOR_DVII,
2431 &ddc_i2c,
2432 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2433 &hpd);
2434 } else {
2435 uint16_t crt_info =
2436 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2437 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2438 if (crt_info) {
2439 radeon_add_legacy_encoder(dev,
2440 radeon_get_encoder_enum(dev,
2441 ATOM_DEVICE_CRT1_SUPPORT,
2442 1),
2443 ATOM_DEVICE_CRT1_SUPPORT);
2444 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2445 hpd.hpd = RADEON_HPD_NONE;
2446 radeon_add_legacy_connector(dev,
2447 0,
2448 ATOM_DEVICE_CRT1_SUPPORT,
2449 DRM_MODE_CONNECTOR_VGA,
2450 &ddc_i2c,
2451 CONNECTOR_OBJECT_ID_VGA,
2452 &hpd);
2453 } else {
2454 DRM_DEBUG_KMS("No connector info found\n");
2455 return false;
2456 }
2457 }
2458 }
2459
2460 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2461 uint16_t lcd_info =
2462 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2463 if (lcd_info) {
2464 uint16_t lcd_ddc_info =
2465 combios_get_table_offset(dev,
2466 COMBIOS_LCD_DDC_INFO_TABLE);
2467
2468 radeon_add_legacy_encoder(dev,
2469 radeon_get_encoder_enum(dev,
2470 ATOM_DEVICE_LCD1_SUPPORT,
2471 0),
2472 ATOM_DEVICE_LCD1_SUPPORT);
2473
2474 if (lcd_ddc_info) {
2475 ddc_type = RBIOS8(lcd_ddc_info + 2);
2476 switch (ddc_type) {
2477 case DDC_LCD:
2478 ddc_i2c =
2479 combios_setup_i2c_bus(rdev,
2480 DDC_LCD,
2481 RBIOS32(lcd_ddc_info + 3),
2482 RBIOS32(lcd_ddc_info + 7));
2483 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2484 break;
2485 case DDC_GPIO:
2486 ddc_i2c =
2487 combios_setup_i2c_bus(rdev,
2488 DDC_GPIO,
2489 RBIOS32(lcd_ddc_info + 3),
2490 RBIOS32(lcd_ddc_info + 7));
2491 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2492 break;
2493 default:
2494 ddc_i2c =
2495 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2496 break;
2497 }
2498 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2499 } else
2500 ddc_i2c.valid = false;
2501
2502 hpd.hpd = RADEON_HPD_NONE;
2503 radeon_add_legacy_connector(dev,
2504 5,
2505 ATOM_DEVICE_LCD1_SUPPORT,
2506 DRM_MODE_CONNECTOR_LVDS,
2507 &ddc_i2c,
2508 CONNECTOR_OBJECT_ID_LVDS,
2509 &hpd);
2510 }
2511 }
2512
2513 /* check TV table */
2514 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2515 uint32_t tv_info =
2516 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2517 if (tv_info) {
2518 if (RBIOS8(tv_info + 6) == 'T') {
2519 if (radeon_apply_legacy_tv_quirks(dev)) {
2520 hpd.hpd = RADEON_HPD_NONE;
2521 ddc_i2c.valid = false;
2522 radeon_add_legacy_encoder(dev,
2523 radeon_get_encoder_enum
2524 (dev,
2525 ATOM_DEVICE_TV1_SUPPORT,
2526 2),
2527 ATOM_DEVICE_TV1_SUPPORT);
2528 radeon_add_legacy_connector(dev, 6,
2529 ATOM_DEVICE_TV1_SUPPORT,
2530 DRM_MODE_CONNECTOR_SVIDEO,
2531 &ddc_i2c,
2532 CONNECTOR_OBJECT_ID_SVIDEO,
2533 &hpd);
2534 }
2535 }
2536 }
2537 }
2538
2539 radeon_link_encoder_connector(dev);
2540
2541 return true;
2542 }
2543
2544 static const char *thermal_controller_names[] = {
2545 "NONE",
2546 "lm63",
2547 "adm1032",
2548 };
2549
2550 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2551 {
2552 struct drm_device *dev = rdev->ddev;
2553 u16 offset, misc, misc2 = 0;
2554 u8 rev, blocks, tmp;
2555 int state_index = 0;
2556
2557 rdev->pm.default_power_state_index = -1;
2558
2559 /* allocate 2 power states */
2560 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2561 if (!rdev->pm.power_state) {
2562 rdev->pm.default_power_state_index = state_index;
2563 rdev->pm.num_power_states = 0;
2564
2565 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2566 rdev->pm.current_clock_mode_index = 0;
2567 return;
2568 }
2569
2570 /* check for a thermal chip */
2571 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2572 if (offset) {
2573 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2574 struct radeon_i2c_bus_rec i2c_bus;
2575
2576 rev = RBIOS8(offset);
2577
2578 if (rev == 0) {
2579 thermal_controller = RBIOS8(offset + 3);
2580 gpio = RBIOS8(offset + 4) & 0x3f;
2581 i2c_addr = RBIOS8(offset + 5);
2582 } else if (rev == 1) {
2583 thermal_controller = RBIOS8(offset + 4);
2584 gpio = RBIOS8(offset + 5) & 0x3f;
2585 i2c_addr = RBIOS8(offset + 6);
2586 } else if (rev == 2) {
2587 thermal_controller = RBIOS8(offset + 4);
2588 gpio = RBIOS8(offset + 5) & 0x3f;
2589 i2c_addr = RBIOS8(offset + 6);
2590 clk_bit = RBIOS8(offset + 0xa);
2591 data_bit = RBIOS8(offset + 0xb);
2592 }
2593 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2594 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2595 thermal_controller_names[thermal_controller],
2596 i2c_addr >> 1);
2597 if (gpio == DDC_LCD) {
2598 /* MM i2c */
2599 i2c_bus.valid = true;
2600 i2c_bus.hw_capable = true;
2601 i2c_bus.mm_i2c = true;
2602 i2c_bus.i2c_id = 0xa0;
2603 } else if (gpio == DDC_GPIO)
2604 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2605 else
2606 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2607 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2608 if (rdev->pm.i2c_bus) {
2609 struct i2c_board_info info = { };
2610 const char *name = thermal_controller_names[thermal_controller];
2611 info.addr = i2c_addr >> 1;
2612 strlcpy(info.type, name, sizeof(info.type));
2613 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2614 }
2615 }
2616 }
2617
2618 if (rdev->flags & RADEON_IS_MOBILITY) {
2619 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2620 if (offset) {
2621 rev = RBIOS8(offset);
2622 blocks = RBIOS8(offset + 0x2);
2623 /* power mode 0 tends to be the only valid one */
2624 rdev->pm.power_state[state_index].num_clock_modes = 1;
2625 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2626 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2627 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2628 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2629 goto default_mode;
2630 rdev->pm.power_state[state_index].type =
2631 POWER_STATE_TYPE_BATTERY;
2632 misc = RBIOS16(offset + 0x5 + 0x0);
2633 if (rev > 4)
2634 misc2 = RBIOS16(offset + 0x5 + 0xe);
2635 rdev->pm.power_state[state_index].misc = misc;
2636 rdev->pm.power_state[state_index].misc2 = misc2;
2637 if (misc & 0x4) {
2638 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2639 if (misc & 0x8)
2640 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2641 true;
2642 else
2643 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2644 false;
2645 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2646 if (rev < 6) {
2647 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2648 RBIOS16(offset + 0x5 + 0xb) * 4;
2649 tmp = RBIOS8(offset + 0x5 + 0xd);
2650 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2651 } else {
2652 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2653 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2654 if (entries && voltage_table_offset) {
2655 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2656 RBIOS16(voltage_table_offset) * 4;
2657 tmp = RBIOS8(voltage_table_offset + 0x2);
2658 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2659 } else
2660 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2661 }
2662 switch ((misc2 & 0x700) >> 8) {
2663 case 0:
2664 default:
2665 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2666 break;
2667 case 1:
2668 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2669 break;
2670 case 2:
2671 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2672 break;
2673 case 3:
2674 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2675 break;
2676 case 4:
2677 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2678 break;
2679 }
2680 } else
2681 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2682 if (rev > 6)
2683 rdev->pm.power_state[state_index].pcie_lanes =
2684 RBIOS8(offset + 0x5 + 0x10);
2685 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2686 state_index++;
2687 } else {
2688 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2689 }
2690 } else {
2691 /* XXX figure out some good default low power mode for desktop cards */
2692 }
2693
2694 default_mode:
2695 /* add the default mode */
2696 rdev->pm.power_state[state_index].type =
2697 POWER_STATE_TYPE_DEFAULT;
2698 rdev->pm.power_state[state_index].num_clock_modes = 1;
2699 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2700 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2701 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2702 if ((state_index > 0) &&
2703 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2704 rdev->pm.power_state[state_index].clock_info[0].voltage =
2705 rdev->pm.power_state[0].clock_info[0].voltage;
2706 else
2707 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2708 rdev->pm.power_state[state_index].pcie_lanes = 16;
2709 rdev->pm.power_state[state_index].flags = 0;
2710 rdev->pm.default_power_state_index = state_index;
2711 rdev->pm.num_power_states = state_index + 1;
2712
2713 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2714 rdev->pm.current_clock_mode_index = 0;
2715 }
2716
2717 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2718 {
2719 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2720 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2721
2722 if (!tmds)
2723 return;
2724
2725 switch (tmds->dvo_chip) {
2726 case DVO_SIL164:
2727 /* sil 164 */
2728 radeon_i2c_put_byte(tmds->i2c_bus,
2729 tmds->slave_addr,
2730 0x08, 0x30);
2731 radeon_i2c_put_byte(tmds->i2c_bus,
2732 tmds->slave_addr,
2733 0x09, 0x00);
2734 radeon_i2c_put_byte(tmds->i2c_bus,
2735 tmds->slave_addr,
2736 0x0a, 0x90);
2737 radeon_i2c_put_byte(tmds->i2c_bus,
2738 tmds->slave_addr,
2739 0x0c, 0x89);
2740 radeon_i2c_put_byte(tmds->i2c_bus,
2741 tmds->slave_addr,
2742 0x08, 0x3b);
2743 break;
2744 case DVO_SIL1178:
2745 /* sil 1178 - untested */
2746 /*
2747 * 0x0f, 0x44
2748 * 0x0f, 0x4c
2749 * 0x0e, 0x01
2750 * 0x0a, 0x80
2751 * 0x09, 0x30
2752 * 0x0c, 0xc9
2753 * 0x0d, 0x70
2754 * 0x08, 0x32
2755 * 0x08, 0x33
2756 */
2757 break;
2758 default:
2759 break;
2760 }
2761
2762 }
2763
2764 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2765 {
2766 struct drm_device *dev = encoder->dev;
2767 struct radeon_device *rdev = dev->dev_private;
2768 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2769 uint16_t offset;
2770 uint8_t blocks, slave_addr, rev;
2771 uint32_t index, id;
2772 uint32_t reg, val, and_mask, or_mask;
2773 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2774
2775 if (!tmds)
2776 return false;
2777
2778 if (rdev->flags & RADEON_IS_IGP) {
2779 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2780 rev = RBIOS8(offset);
2781 if (offset) {
2782 rev = RBIOS8(offset);
2783 if (rev > 1) {
2784 blocks = RBIOS8(offset + 3);
2785 index = offset + 4;
2786 while (blocks > 0) {
2787 id = RBIOS16(index);
2788 index += 2;
2789 switch (id >> 13) {
2790 case 0:
2791 reg = (id & 0x1fff) * 4;
2792 val = RBIOS32(index);
2793 index += 4;
2794 WREG32(reg, val);
2795 break;
2796 case 2:
2797 reg = (id & 0x1fff) * 4;
2798 and_mask = RBIOS32(index);
2799 index += 4;
2800 or_mask = RBIOS32(index);
2801 index += 4;
2802 val = RREG32(reg);
2803 val = (val & and_mask) | or_mask;
2804 WREG32(reg, val);
2805 break;
2806 case 3:
2807 val = RBIOS16(index);
2808 index += 2;
2809 udelay(val);
2810 break;
2811 case 4:
2812 val = RBIOS16(index);
2813 index += 2;
2814 udelay(val * 1000);
2815 break;
2816 case 6:
2817 slave_addr = id & 0xff;
2818 slave_addr >>= 1; /* 7 bit addressing */
2819 index++;
2820 reg = RBIOS8(index);
2821 index++;
2822 val = RBIOS8(index);
2823 index++;
2824 radeon_i2c_put_byte(tmds->i2c_bus,
2825 slave_addr,
2826 reg, val);
2827 break;
2828 default:
2829 DRM_ERROR("Unknown id %d\n", id >> 13);
2830 break;
2831 }
2832 blocks--;
2833 }
2834 return true;
2835 }
2836 }
2837 } else {
2838 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2839 if (offset) {
2840 index = offset + 10;
2841 id = RBIOS16(index);
2842 while (id != 0xffff) {
2843 index += 2;
2844 switch (id >> 13) {
2845 case 0:
2846 reg = (id & 0x1fff) * 4;
2847 val = RBIOS32(index);
2848 WREG32(reg, val);
2849 break;
2850 case 2:
2851 reg = (id & 0x1fff) * 4;
2852 and_mask = RBIOS32(index);
2853 index += 4;
2854 or_mask = RBIOS32(index);
2855 index += 4;
2856 val = RREG32(reg);
2857 val = (val & and_mask) | or_mask;
2858 WREG32(reg, val);
2859 break;
2860 case 4:
2861 val = RBIOS16(index);
2862 index += 2;
2863 udelay(val);
2864 break;
2865 case 5:
2866 reg = id & 0x1fff;
2867 and_mask = RBIOS32(index);
2868 index += 4;
2869 or_mask = RBIOS32(index);
2870 index += 4;
2871 val = RREG32_PLL(reg);
2872 val = (val & and_mask) | or_mask;
2873 WREG32_PLL(reg, val);
2874 break;
2875 case 6:
2876 reg = id & 0x1fff;
2877 val = RBIOS8(index);
2878 index += 1;
2879 radeon_i2c_put_byte(tmds->i2c_bus,
2880 tmds->slave_addr,
2881 reg, val);
2882 break;
2883 default:
2884 DRM_ERROR("Unknown id %d\n", id >> 13);
2885 break;
2886 }
2887 id = RBIOS16(index);
2888 }
2889 return true;
2890 }
2891 }
2892 return false;
2893 }
2894
2895 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2896 {
2897 struct radeon_device *rdev = dev->dev_private;
2898
2899 if (offset) {
2900 while (RBIOS16(offset)) {
2901 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2902 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2903 uint32_t val, and_mask, or_mask;
2904 uint32_t tmp;
2905
2906 offset += 2;
2907 switch (cmd) {
2908 case 0:
2909 val = RBIOS32(offset);
2910 offset += 4;
2911 WREG32(addr, val);
2912 break;
2913 case 1:
2914 val = RBIOS32(offset);
2915 offset += 4;
2916 WREG32(addr, val);
2917 break;
2918 case 2:
2919 and_mask = RBIOS32(offset);
2920 offset += 4;
2921 or_mask = RBIOS32(offset);
2922 offset += 4;
2923 tmp = RREG32(addr);
2924 tmp &= and_mask;
2925 tmp |= or_mask;
2926 WREG32(addr, tmp);
2927 break;
2928 case 3:
2929 and_mask = RBIOS32(offset);
2930 offset += 4;
2931 or_mask = RBIOS32(offset);
2932 offset += 4;
2933 tmp = RREG32(addr);
2934 tmp &= and_mask;
2935 tmp |= or_mask;
2936 WREG32(addr, tmp);
2937 break;
2938 case 4:
2939 val = RBIOS16(offset);
2940 offset += 2;
2941 udelay(val);
2942 break;
2943 case 5:
2944 val = RBIOS16(offset);
2945 offset += 2;
2946 switch (addr) {
2947 case 8:
2948 while (val--) {
2949 if (!
2950 (RREG32_PLL
2951 (RADEON_CLK_PWRMGT_CNTL) &
2952 RADEON_MC_BUSY))
2953 break;
2954 }
2955 break;
2956 case 9:
2957 while (val--) {
2958 if ((RREG32(RADEON_MC_STATUS) &
2959 RADEON_MC_IDLE))
2960 break;
2961 }
2962 break;
2963 default:
2964 break;
2965 }
2966 break;
2967 default:
2968 break;
2969 }
2970 }
2971 }
2972 }
2973
2974 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2975 {
2976 struct radeon_device *rdev = dev->dev_private;
2977
2978 if (offset) {
2979 while (RBIOS8(offset)) {
2980 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2981 uint8_t addr = (RBIOS8(offset) & 0x3f);
2982 uint32_t val, shift, tmp;
2983 uint32_t and_mask, or_mask;
2984
2985 offset++;
2986 switch (cmd) {
2987 case 0:
2988 val = RBIOS32(offset);
2989 offset += 4;
2990 WREG32_PLL(addr, val);
2991 break;
2992 case 1:
2993 shift = RBIOS8(offset) * 8;
2994 offset++;
2995 and_mask = RBIOS8(offset) << shift;
2996 and_mask |= ~(0xff << shift);
2997 offset++;
2998 or_mask = RBIOS8(offset) << shift;
2999 offset++;
3000 tmp = RREG32_PLL(addr);
3001 tmp &= and_mask;
3002 tmp |= or_mask;
3003 WREG32_PLL(addr, tmp);
3004 break;
3005 case 2:
3006 case 3:
3007 tmp = 1000;
3008 switch (addr) {
3009 case 1:
3010 udelay(150);
3011 break;
3012 case 2:
3013 udelay(1000);
3014 break;
3015 case 3:
3016 while (tmp--) {
3017 if (!
3018 (RREG32_PLL
3019 (RADEON_CLK_PWRMGT_CNTL) &
3020 RADEON_MC_BUSY))
3021 break;
3022 }
3023 break;
3024 case 4:
3025 while (tmp--) {
3026 if (RREG32_PLL
3027 (RADEON_CLK_PWRMGT_CNTL) &
3028 RADEON_DLL_READY)
3029 break;
3030 }
3031 break;
3032 case 5:
3033 tmp =
3034 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3035 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3036 #if 0
3037 uint32_t mclk_cntl =
3038 RREG32_PLL
3039 (RADEON_MCLK_CNTL);
3040 mclk_cntl &= 0xffff0000;
3041 /*mclk_cntl |= 0x00001111;*//* ??? */
3042 WREG32_PLL(RADEON_MCLK_CNTL,
3043 mclk_cntl);
3044 udelay(10000);
3045 #endif
3046 WREG32_PLL
3047 (RADEON_CLK_PWRMGT_CNTL,
3048 tmp &
3049 ~RADEON_CG_NO1_DEBUG_0);
3050 udelay(10000);
3051 }
3052 break;
3053 default:
3054 break;
3055 }
3056 break;
3057 default:
3058 break;
3059 }
3060 }
3061 }
3062 }
3063
3064 static void combios_parse_ram_reset_table(struct drm_device *dev,
3065 uint16_t offset)
3066 {
3067 struct radeon_device *rdev = dev->dev_private;
3068 uint32_t tmp;
3069
3070 if (offset) {
3071 uint8_t val = RBIOS8(offset);
3072 while (val != 0xff) {
3073 offset++;
3074
3075 if (val == 0x0f) {
3076 uint32_t channel_complete_mask;
3077
3078 if (ASIC_IS_R300(rdev))
3079 channel_complete_mask =
3080 R300_MEM_PWRUP_COMPLETE;
3081 else
3082 channel_complete_mask =
3083 RADEON_MEM_PWRUP_COMPLETE;
3084 tmp = 20000;
3085 while (tmp--) {
3086 if ((RREG32(RADEON_MEM_STR_CNTL) &
3087 channel_complete_mask) ==
3088 channel_complete_mask)
3089 break;
3090 }
3091 } else {
3092 uint32_t or_mask = RBIOS16(offset);
3093 offset += 2;
3094
3095 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3096 tmp &= RADEON_SDRAM_MODE_MASK;
3097 tmp |= or_mask;
3098 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3099
3100 or_mask = val << 24;
3101 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3102 tmp &= RADEON_B3MEM_RESET_MASK;
3103 tmp |= or_mask;
3104 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3105 }
3106 val = RBIOS8(offset);
3107 }
3108 }
3109 }
3110
3111 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3112 int mem_addr_mapping)
3113 {
3114 struct radeon_device *rdev = dev->dev_private;
3115 uint32_t mem_cntl;
3116 uint32_t mem_size;
3117 uint32_t addr = 0;
3118
3119 mem_cntl = RREG32(RADEON_MEM_CNTL);
3120 if (mem_cntl & RV100_HALF_MODE)
3121 ram /= 2;
3122 mem_size = ram;
3123 mem_cntl &= ~(0xff << 8);
3124 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3125 WREG32(RADEON_MEM_CNTL, mem_cntl);
3126 RREG32(RADEON_MEM_CNTL);
3127
3128 /* sdram reset ? */
3129
3130 /* something like this???? */
3131 while (ram--) {
3132 addr = ram * 1024 * 1024;
3133 /* write to each page */
3134 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3135 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3136 /* read back and verify */
3137 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3138 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3139 return 0;
3140 }
3141
3142 return mem_size;
3143 }
3144
3145 static void combios_write_ram_size(struct drm_device *dev)
3146 {
3147 struct radeon_device *rdev = dev->dev_private;
3148 uint8_t rev;
3149 uint16_t offset;
3150 uint32_t mem_size = 0;
3151 uint32_t mem_cntl = 0;
3152
3153 /* should do something smarter here I guess... */
3154 if (rdev->flags & RADEON_IS_IGP)
3155 return;
3156
3157 /* first check detected mem table */
3158 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3159 if (offset) {
3160 rev = RBIOS8(offset);
3161 if (rev < 3) {
3162 mem_cntl = RBIOS32(offset + 1);
3163 mem_size = RBIOS16(offset + 5);
3164 if ((rdev->family < CHIP_R200) &&
3165 !ASIC_IS_RN50(rdev))
3166 WREG32(RADEON_MEM_CNTL, mem_cntl);
3167 }
3168 }
3169
3170 if (!mem_size) {
3171 offset =
3172 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3173 if (offset) {
3174 rev = RBIOS8(offset - 1);
3175 if (rev < 1) {
3176 if ((rdev->family < CHIP_R200)
3177 && !ASIC_IS_RN50(rdev)) {
3178 int ram = 0;
3179 int mem_addr_mapping = 0;
3180
3181 while (RBIOS8(offset)) {
3182 ram = RBIOS8(offset);
3183 mem_addr_mapping =
3184 RBIOS8(offset + 1);
3185 if (mem_addr_mapping != 0x25)
3186 ram *= 2;
3187 mem_size =
3188 combios_detect_ram(dev, ram,
3189 mem_addr_mapping);
3190 if (mem_size)
3191 break;
3192 offset += 2;
3193 }
3194 } else
3195 mem_size = RBIOS8(offset);
3196 } else {
3197 mem_size = RBIOS8(offset);
3198 mem_size *= 2; /* convert to MB */
3199 }
3200 }
3201 }
3202
3203 mem_size *= (1024 * 1024); /* convert to bytes */
3204 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3205 }
3206
3207 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3208 {
3209 uint16_t dyn_clk_info =
3210 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3211
3212 if (dyn_clk_info)
3213 combios_parse_pll_table(dev, dyn_clk_info);
3214 }
3215
3216 void radeon_combios_asic_init(struct drm_device *dev)
3217 {
3218 struct radeon_device *rdev = dev->dev_private;
3219 uint16_t table;
3220
3221 /* port hardcoded mac stuff from radeonfb */
3222 if (rdev->bios == NULL)
3223 return;
3224
3225 /* ASIC INIT 1 */
3226 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3227 if (table)
3228 combios_parse_mmio_table(dev, table);
3229
3230 /* PLL INIT */
3231 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3232 if (table)
3233 combios_parse_pll_table(dev, table);
3234
3235 /* ASIC INIT 2 */
3236 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3237 if (table)
3238 combios_parse_mmio_table(dev, table);
3239
3240 if (!(rdev->flags & RADEON_IS_IGP)) {
3241 /* ASIC INIT 4 */
3242 table =
3243 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3244 if (table)
3245 combios_parse_mmio_table(dev, table);
3246
3247 /* RAM RESET */
3248 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3249 if (table)
3250 combios_parse_ram_reset_table(dev, table);
3251
3252 /* ASIC INIT 3 */
3253 table =
3254 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3255 if (table)
3256 combios_parse_mmio_table(dev, table);
3257
3258 /* write CONFIG_MEMSIZE */
3259 combios_write_ram_size(dev);
3260 }
3261
3262 /* quirk for rs4xx HP nx6125 laptop to make it resume
3263 * - it hangs on resume inside the dynclk 1 table.
3264 */
3265 if (rdev->family == CHIP_RS480 &&
3266 rdev->pdev->subsystem_vendor == 0x103c &&
3267 rdev->pdev->subsystem_device == 0x308b)
3268 return;
3269
3270 /* quirk for rs4xx HP dv5000 laptop to make it resume
3271 * - it hangs on resume inside the dynclk 1 table.
3272 */
3273 if (rdev->family == CHIP_RS480 &&
3274 rdev->pdev->subsystem_vendor == 0x103c &&
3275 rdev->pdev->subsystem_device == 0x30a4)
3276 return;
3277
3278 /* DYN CLK 1 */
3279 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3280 if (table)
3281 combios_parse_pll_table(dev, table);
3282
3283 }
3284
3285 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3286 {
3287 struct radeon_device *rdev = dev->dev_private;
3288 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3289
3290 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3291 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3292 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3293
3294 /* let the bios control the backlight */
3295 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3296
3297 /* tell the bios not to handle mode switching */
3298 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3299 RADEON_ACC_MODE_CHANGE);
3300
3301 /* tell the bios a driver is loaded */
3302 bios_7_scratch |= RADEON_DRV_LOADED;
3303
3304 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3305 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3306 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3307 }
3308
3309 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3310 {
3311 struct drm_device *dev = encoder->dev;
3312 struct radeon_device *rdev = dev->dev_private;
3313 uint32_t bios_6_scratch;
3314
3315 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3316
3317 if (lock)
3318 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3319 else
3320 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3321
3322 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3323 }
3324
3325 void
3326 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3327 struct drm_encoder *encoder,
3328 bool connected)
3329 {
3330 struct drm_device *dev = connector->dev;
3331 struct radeon_device *rdev = dev->dev_private;
3332 struct radeon_connector *radeon_connector =
3333 to_radeon_connector(connector);
3334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3335 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3336 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3337
3338 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3339 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3340 if (connected) {
3341 DRM_DEBUG_KMS("TV1 connected\n");
3342 /* fix me */
3343 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3344 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3345 bios_5_scratch |= RADEON_TV1_ON;
3346 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3347 } else {
3348 DRM_DEBUG_KMS("TV1 disconnected\n");
3349 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3350 bios_5_scratch &= ~RADEON_TV1_ON;
3351 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3352 }
3353 }
3354 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3355 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3356 if (connected) {
3357 DRM_DEBUG_KMS("LCD1 connected\n");
3358 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3359 bios_5_scratch |= RADEON_LCD1_ON;
3360 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3361 } else {
3362 DRM_DEBUG_KMS("LCD1 disconnected\n");
3363 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3364 bios_5_scratch &= ~RADEON_LCD1_ON;
3365 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3366 }
3367 }
3368 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3369 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3370 if (connected) {
3371 DRM_DEBUG_KMS("CRT1 connected\n");
3372 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3373 bios_5_scratch |= RADEON_CRT1_ON;
3374 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3375 } else {
3376 DRM_DEBUG_KMS("CRT1 disconnected\n");
3377 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3378 bios_5_scratch &= ~RADEON_CRT1_ON;
3379 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3380 }
3381 }
3382 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3383 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3384 if (connected) {
3385 DRM_DEBUG_KMS("CRT2 connected\n");
3386 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3387 bios_5_scratch |= RADEON_CRT2_ON;
3388 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3389 } else {
3390 DRM_DEBUG_KMS("CRT2 disconnected\n");
3391 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3392 bios_5_scratch &= ~RADEON_CRT2_ON;
3393 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3394 }
3395 }
3396 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3397 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3398 if (connected) {
3399 DRM_DEBUG_KMS("DFP1 connected\n");
3400 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3401 bios_5_scratch |= RADEON_DFP1_ON;
3402 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3403 } else {
3404 DRM_DEBUG_KMS("DFP1 disconnected\n");
3405 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3406 bios_5_scratch &= ~RADEON_DFP1_ON;
3407 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3408 }
3409 }
3410 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3411 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3412 if (connected) {
3413 DRM_DEBUG_KMS("DFP2 connected\n");
3414 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3415 bios_5_scratch |= RADEON_DFP2_ON;
3416 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3417 } else {
3418 DRM_DEBUG_KMS("DFP2 disconnected\n");
3419 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3420 bios_5_scratch &= ~RADEON_DFP2_ON;
3421 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3422 }
3423 }
3424 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3425 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3426 }
3427
3428 void
3429 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3430 {
3431 struct drm_device *dev = encoder->dev;
3432 struct radeon_device *rdev = dev->dev_private;
3433 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3434 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3435
3436 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3437 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3438 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3439 }
3440 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3441 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3442 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3443 }
3444 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3445 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3446 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3447 }
3448 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3449 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3450 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3451 }
3452 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3453 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3454 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3455 }
3456 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3457 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3458 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3459 }
3460 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3461 }
3462
3463 void
3464 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3465 {
3466 struct drm_device *dev = encoder->dev;
3467 struct radeon_device *rdev = dev->dev_private;
3468 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3469 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3470
3471 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3472 if (on)
3473 bios_6_scratch |= RADEON_TV_DPMS_ON;
3474 else
3475 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3476 }
3477 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3478 if (on)
3479 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3480 else
3481 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3482 }
3483 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3484 if (on)
3485 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3486 else
3487 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3488 }
3489 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3490 if (on)
3491 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3492 else
3493 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3494 }
3495 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3496 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree