arch/x86/kernel/irqinit_64.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel_stat.h>
  12 #include <linux/sysdev.h>
  13 #include <linux/bitops.h>
  14 #include <linux/acpi.h>
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17
  18 #include <asm/atomic.h>
  19 #include <asm/system.h>
  20 #include <asm/timer.h>
  21 #include <asm/hw_irq.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/desc.h>
  24 #include <asm/apic.h>
  25 #include <asm/setup.h>
  26 #include <asm/i8259.h>
  27 #include <asm/traps.h>
  28
  29 /*
  30  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  31  * (these are usually mapped to vectors 0x30-0x3f)
  32  */
  33
  34 /*
  35  * The IO-APIC gives us many more interrupt sources. Most of these
  36  * are unused but an SMP system is supposed to have enough memory ...
  37  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  38  * across the spectrum, so we really want to be prepared to get all
  39  * of these. Plus, more powerful systems might have more than 64
  40  * IO-APIC registers.
  41  *
  42  * (these are usually mapped into the 0x30-0xff vector range)
  43  */
  44
  45 #ifdef CONFIG_X86_32
  46 /*
  47  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  48  * as the irq is unreliable, and exception 16 works correctly
  49  * (ie as explained in the intel literature). On a 386, you
  50  * can't use exception 16 due to bad IBM design, so we have to
  51  * rely on the less exact irq13.
  52  *
  53  * Careful.. Not only is IRQ13 unreliable, but it is also
  54  * leads to races. IBM designers who came up with it should
  55  * be shot.
  56  */
  57
  58 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  59 {
  60         outb(0, 0xF0);
  61         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  62                 return IRQ_NONE;
  63         math_error((void __user *)get_irq_regs()->ip);
  64         return IRQ_HANDLED;
  65 }
  66
  67 /*
  68  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  69  * so allow interrupt sharing.
  70  */
  71 static struct irqaction fpu_irq = {
  72         .handler = math_error_irq,
  73         .name = "fpu",
  74 };
  75 #endif
  76
  77 /*
  78  * IRQ2 is cascade interrupt to second interrupt controller
  79  */
  80 static struct irqaction irq2 = {
  81         .handler = no_action,
  82         .name = "cascade",
  83 };
  84
  85 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  86         [0 ... IRQ0_VECTOR - 1] = -1,
  87         [IRQ0_VECTOR] = 0,
  88         [IRQ1_VECTOR] = 1,
  89         [IRQ2_VECTOR] = 2,
  90         [IRQ3_VECTOR] = 3,
  91         [IRQ4_VECTOR] = 4,
  92         [IRQ5_VECTOR] = 5,
  93         [IRQ6_VECTOR] = 6,
  94         [IRQ7_VECTOR] = 7,
  95         [IRQ8_VECTOR] = 8,
  96         [IRQ9_VECTOR] = 9,
  97         [IRQ10_VECTOR] = 10,
  98         [IRQ11_VECTOR] = 11,
  99         [IRQ12_VECTOR] = 12,
 100         [IRQ13_VECTOR] = 13,
 101         [IRQ14_VECTOR] = 14,
 102         [IRQ15_VECTOR] = 15,
 103         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 104 };
 105
 106 int vector_used_by_percpu_irq(unsigned int vector)
 107 {
 108         int cpu;
 109
 110         for_each_online_cpu(cpu) {
 111                 if (per_cpu(vector_irq, cpu)[vector] != -1)
 112                         return 1;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static void __init init_ISA_irqs(void)
 119 {
 120         int i;
 121
 122 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 123         init_bsp_APIC();
 124 #endif
 125         init_8259A(0);
 126
 127         /*
 128          * 16 old-style INTA-cycle interrupts:
 129          */
 130         for (i = 0; i < NR_IRQS_LEGACY; i++) {
 131                 struct irq_desc *desc = irq_to_desc(i);
 132
 133                 desc->status = IRQ_DISABLED;
 134                 desc->action = NULL;
 135                 desc->depth = 1;
 136
 137                 set_irq_chip_and_handler_name(i, &i8259A_chip,
 138                                               handle_level_irq, "XT");
 139         }
 140 }
 141
 142 /* Overridden in paravirt.c */
 143 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 144
 145 static void __init smp_intr_init(void)
 146 {
 147 #ifdef CONFIG_SMP
 148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 149         /*
 150          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 151          * IPI, driven by wakeup.
 152          */
 153         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 154
 155         /* IPIs for invalidation */
 156         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 157         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 158         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 159         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 160         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 161         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 162         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 163         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 164
 165         /* IPI for generic function call */
 166         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 167
 168         /* IPI for generic single function call */
 169         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 170                         call_function_single_interrupt);
 171
 172         /* Low priority IPI to cleanup after moving an irq */
 173         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 174         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 175 #endif
 176 #endif /* CONFIG_SMP */
 177 }
 178
 179 static void __init apic_intr_init(void)
 180 {
 181         smp_intr_init();
 182
 183 #ifdef CONFIG_X86_64
 184         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 185         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 186 #endif
 187
 188 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 189         /* self generated IPI for local APIC timer */
 190         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 191
 192         /* generic IPI for platform specific use */
 193         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 194
 195         /* IPI vectors for APIC spurious and error interrupts */
 196         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 197         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 198 #endif
 199
 200 #ifdef CONFIG_X86_32
 201 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
 202         /* thermal monitor LVT interrupt */
 203         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 204 #endif
 205 #endif
 206 }
 207
 208 #ifdef CONFIG_X86_32
 209 /**
 210  * x86_quirk_pre_intr_init - initialisation prior to setting up interrupt vectors
 211  *
 212  * Description:
 213  *      Perform any necessary interrupt initialisation prior to setting up
 214  *      the "ordinary" interrupt call gates.  For legacy reasons, the ISA
 215  *      interrupts should be initialised here if the machine emulates a PC
 216  *      in any way.
 217  **/
 218 static void __init x86_quirk_pre_intr_init(void)
 219 {
 220         if (x86_quirks->arch_pre_intr_init) {
 221                 if (x86_quirks->arch_pre_intr_init())
 222                         return;
 223         }
 224         init_ISA_irqs();
 225 }
 226 #endif
 227
 228 void __init native_init_IRQ(void)
 229 {
 230         int i;
 231
 232 #ifdef CONFIG_X86_32
 233         /* Execute any quirks before the call gates are initialised: */
 234         x86_quirk_pre_intr_init();
 235 #else
 236         init_ISA_irqs();
 237 #endif
 238
 239         /*
 240          * Cover the whole vector space, no vector can escape
 241          * us. (some of these will be overridden and become
 242          * 'special' SMP interrupts)
 243          */
 244         for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 245 #ifdef CONFIG_X86_32
 246                 /* SYSCALL_VECTOR was reserved in trap_init. */
 247                 if (i != SYSCALL_VECTOR)
 248                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 249 #else
 250                 /* IA32_SYSCALL_VECTOR was reserved in trap_init. */
 251                 if (i != IA32_SYSCALL_VECTOR)
 252                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 253 #endif
 254         }
 255
 256         apic_intr_init();
 257
 258         if (!acpi_ioapic)
 259                 setup_irq(2, &irq2);
 260
 261 #ifdef CONFIG_X86_32
 262         /*
 263          * Call quirks after call gates are initialised (usually add in
 264          * the architecture specific gates):
 265          */
 266         x86_quirk_intr_init();
 267
 268         /*
 269          * External FPU? Set up irq13 if so, for
 270          * original braindamaged IBM FERR coupling.
 271          */
 272         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 273                 setup_irq(FPU_IRQ, &fpu_irq);
 274
 275         irq_ctx_init(smp_processor_id());
 276 #endif
 277 }