arch/arm/mach-msm/irq.c

   1 /* linux/arch/arm/mach-msm/irq.c
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ptrace.h>
  21 #include <linux/timer.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24
  25 #include <mach/hardware.h>
  26
  27 #include <mach/msm_iomap.h>
  28
  29 #define VIC_REG(off) (MSM_VIC_BASE + (off))
  30
  31 #define VIC_INT_SELECT0     VIC_REG(0x0000)  /* 1: FIQ, 0: IRQ */
  32 #define VIC_INT_SELECT1     VIC_REG(0x0004)  /* 1: FIQ, 0: IRQ */
  33 #define VIC_INT_EN0         VIC_REG(0x0010)
  34 #define VIC_INT_EN1         VIC_REG(0x0014)
  35 #define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
  36 #define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
  37 #define VIC_INT_ENSET0      VIC_REG(0x0030)
  38 #define VIC_INT_ENSET1      VIC_REG(0x0034)
  39 #define VIC_INT_TYPE0       VIC_REG(0x0040)  /* 1: EDGE, 0: LEVEL  */
  40 #define VIC_INT_TYPE1       VIC_REG(0x0044)  /* 1: EDGE, 0: LEVEL  */
  41 #define VIC_INT_POLARITY0   VIC_REG(0x0050)  /* 1: NEG, 0: POS */
  42 #define VIC_INT_POLARITY1   VIC_REG(0x0054)  /* 1: NEG, 0: POS */
  43 #define VIC_NO_PEND_VAL     VIC_REG(0x0060)
  44 #define VIC_INT_MASTEREN    VIC_REG(0x0064)  /* 1: IRQ, 2: FIQ     */
  45 #define VIC_PROTECTION      VIC_REG(0x006C)  /* 1: ENABLE          */
  46 #define VIC_CONFIG          VIC_REG(0x0068)  /* 1: USE ARM1136 VIC */
  47 #define VIC_IRQ_STATUS0     VIC_REG(0x0080)
  48 #define VIC_IRQ_STATUS1     VIC_REG(0x0084)
  49 #define VIC_FIQ_STATUS0     VIC_REG(0x0090)
  50 #define VIC_FIQ_STATUS1     VIC_REG(0x0094)
  51 #define VIC_RAW_STATUS0     VIC_REG(0x00A0)
  52 #define VIC_RAW_STATUS1     VIC_REG(0x00A4)
  53 #define VIC_INT_CLEAR0      VIC_REG(0x00B0)
  54 #define VIC_INT_CLEAR1      VIC_REG(0x00B4)
  55 #define VIC_SOFTINT0        VIC_REG(0x00C0)
  56 #define VIC_SOFTINT1        VIC_REG(0x00C4)
  57 #define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)  /* pending int # */
  58 #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)  /* pending vector addr */
  59 #define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)
  60 #define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E0)
  61 #define VIC_IRQ_IN_STACK    VIC_REG(0x00E4)
  62 #define VIC_TEST_BUS_SEL    VIC_REG(0x00E8)
  63
  64 #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
  65 #define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))
  66
  67 static void msm_irq_ack(unsigned int irq)
  68 {
  69         void __iomem *reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
  70         irq = 1 << (irq & 31);
  71         writel(irq, reg);
  72 }
  73
  74 static void msm_irq_mask(unsigned int irq)
  75 {
  76         void __iomem *reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
  77         writel(1 << (irq & 31), reg);
  78 }
  79
  80 static void msm_irq_unmask(unsigned int irq)
  81 {
  82         void __iomem *reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
  83         writel(1 << (irq & 31), reg);
  84 }
  85
  86 static int msm_irq_set_wake(unsigned int irq, unsigned int on)
  87 {
  88         return -EINVAL;
  89 }
  90
  91 static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
  92 {
  93         void __iomem *treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
  94         void __iomem *preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
  95         int b = 1 << (irq & 31);
  96
  97         if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
  98                 writel(readl(preg) | b, preg);
  99         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
 100                 writel(readl(preg) & (~b), preg);
 101
 102         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 103                 writel(readl(treg) | b, treg);
 104                 set_irq_handler(irq, handle_edge_irq);
 105         }
 106         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
 107                 writel(readl(treg) & (~b), treg);
 108                 set_irq_handler(irq, handle_level_irq);
 109         }
 110         return 0;
 111 }
 112
 113 static struct irq_chip msm_irq_chip = {
 114         .name      = "msm",
 115         .ack       = msm_irq_ack,
 116         .mask      = msm_irq_mask,
 117         .unmask    = msm_irq_unmask,
 118         .set_wake  = msm_irq_set_wake,
 119         .set_type  = msm_irq_set_type,
 120 };
 121
 122 void __init msm_init_irq(void)
 123 {
 124         unsigned n;
 125
 126         /* select level interrupts */
 127         writel(0, VIC_INT_TYPE0);
 128         writel(0, VIC_INT_TYPE1);
 129
 130         /* select highlevel interrupts */
 131         writel(0, VIC_INT_POLARITY0);
 132         writel(0, VIC_INT_POLARITY1);
 133
 134         /* select IRQ for all INTs */
 135         writel(0, VIC_INT_SELECT0);
 136         writel(0, VIC_INT_SELECT1);
 137
 138         /* disable all INTs */
 139         writel(0, VIC_INT_EN0);
 140         writel(0, VIC_INT_EN1);
 141
 142         /* don't use 1136 vic */
 143         writel(0, VIC_CONFIG);
 144
 145         /* enable interrupt controller */
 146         writel(1, VIC_INT_MASTEREN);
 147
 148         for (n = 0; n < NR_MSM_IRQS; n++) {
 149                 set_irq_chip(n, &msm_irq_chip);
 150                 set_irq_handler(n, handle_level_irq);
 151                 set_irq_flags(n, IRQF_VALID);
 152         }
 153 }