?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB: ov7670: remove obsolete enum/try/s_fmt ops
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / video / ov7670.c
blobc141d2e604e3026588d4f72f48842c4fc2a2a170
1 /*
2 * A V4L2 driver for OmniVision OV7670 cameras.
3 *
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
7 *
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
9 *
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
12 */
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-chip-ident.h>
21 #include <media/v4l2-mediabus.h>
22 #include <media/v4l2-i2c-drv.h>
23
24
25 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
26 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
27 MODULE_LICENSE("GPL");
28
29 static int debug;
30 module_param(debug, bool, 0644);
31 MODULE_PARM_DESC(debug, "Debug level (0-1)");
32
33 /*
34 * Basic window sizes. These probably belong somewhere more globally
35 * useful.
36 */
37 #define VGA_WIDTH 640
38 #define VGA_HEIGHT 480
39 #define QVGA_WIDTH 320
40 #define QVGA_HEIGHT 240
41 #define CIF_WIDTH 352
42 #define CIF_HEIGHT 288
43 #define QCIF_WIDTH 176
44 #define QCIF_HEIGHT 144
45
46 /*
47 * Our nominal (default) frame rate.
48 */
49 #define OV7670_FRAME_RATE 30
50
51 /*
52 * The 7670 sits on i2c with ID 0x42
53 */
54 #define OV7670_I2C_ADDR 0x42
55
56 /* Registers */
57 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
58 #define REG_BLUE 0x01 /* blue gain */
59 #define REG_RED 0x02 /* red gain */
60 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
61 #define REG_COM1 0x04 /* Control 1 */
62 #define COM1_CCIR656 0x40 /* CCIR656 enable */
63 #define REG_BAVE 0x05 /* U/B Average level */
64 #define REG_GbAVE 0x06 /* Y/Gb Average level */
65 #define REG_AECHH 0x07 /* AEC MS 5 bits */
66 #define REG_RAVE 0x08 /* V/R Average level */
67 #define REG_COM2 0x09 /* Control 2 */
68 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
69 #define REG_PID 0x0a /* Product ID MSB */
70 #define REG_VER 0x0b /* Product ID LSB */
71 #define REG_COM3 0x0c /* Control 3 */
72 #define COM3_SWAP 0x40 /* Byte swap */
73 #define COM3_SCALEEN 0x08 /* Enable scaling */
74 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
75 #define REG_COM4 0x0d /* Control 4 */
76 #define REG_COM5 0x0e /* All "reserved" */
77 #define REG_COM6 0x0f /* Control 6 */
78 #define REG_AECH 0x10 /* More bits of AEC value */
79 #define REG_CLKRC 0x11 /* Clocl control */
80 #define CLK_EXT 0x40 /* Use external clock directly */
81 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
82 #define REG_COM7 0x12 /* Control 7 */
83 #define COM7_RESET 0x80 /* Register reset */
84 #define COM7_FMT_MASK 0x38
85 #define COM7_FMT_VGA 0x00
86 #define COM7_FMT_CIF 0x20 /* CIF format */
87 #define COM7_FMT_QVGA 0x10 /* QVGA format */
88 #define COM7_FMT_QCIF 0x08 /* QCIF format */
89 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
90 #define COM7_YUV 0x00 /* YUV */
91 #define COM7_BAYER 0x01 /* Bayer format */
92 #define COM7_PBAYER 0x05 /* "Processed bayer" */
93 #define REG_COM8 0x13 /* Control 8 */
94 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
95 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
96 #define COM8_BFILT 0x20 /* Band filter enable */
97 #define COM8_AGC 0x04 /* Auto gain enable */
98 #define COM8_AWB 0x02 /* White balance enable */
99 #define COM8_AEC 0x01 /* Auto exposure enable */
100 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
101 #define REG_COM10 0x15 /* Control 10 */
102 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
103 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
104 #define COM10_HREF_REV 0x08 /* Reverse HREF */
105 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
106 #define COM10_VS_NEG 0x02 /* VSYNC negative */
107 #define COM10_HS_NEG 0x01 /* HSYNC negative */
108 #define REG_HSTART 0x17 /* Horiz start high bits */
109 #define REG_HSTOP 0x18 /* Horiz stop high bits */
110 #define REG_VSTART 0x19 /* Vert start high bits */
111 #define REG_VSTOP 0x1a /* Vert stop high bits */
112 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
113 #define REG_MIDH 0x1c /* Manuf. ID high */
114 #define REG_MIDL 0x1d /* Manuf. ID low */
115 #define REG_MVFP 0x1e /* Mirror / vflip */
116 #define MVFP_MIRROR 0x20 /* Mirror image */
117 #define MVFP_FLIP 0x10 /* Vertical flip */
118
119 #define REG_AEW 0x24 /* AGC upper limit */
120 #define REG_AEB 0x25 /* AGC lower limit */
121 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
122 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
123 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
124 #define REG_HREF 0x32 /* HREF pieces */
125 #define REG_TSLB 0x3a /* lots of stuff */
126 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
127 #define REG_COM11 0x3b /* Control 11 */
128 #define COM11_NIGHT 0x80 /* NIght mode enable */
129 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
130 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
131 #define COM11_50HZ 0x08 /* Manual 50Hz select */
132 #define COM11_EXP 0x02
133 #define REG_COM12 0x3c /* Control 12 */
134 #define COM12_HREF 0x80 /* HREF always */
135 #define REG_COM13 0x3d /* Control 13 */
136 #define COM13_GAMMA 0x80 /* Gamma enable */
137 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
138 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
139 #define REG_COM14 0x3e /* Control 14 */
140 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
141 #define REG_EDGE 0x3f /* Edge enhancement factor */
142 #define REG_COM15 0x40 /* Control 15 */
143 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
144 #define COM15_R01FE 0x80 /* 01 to FE */
145 #define COM15_R00FF 0xc0 /* 00 to FF */
146 #define COM15_RGB565 0x10 /* RGB565 output */
147 #define COM15_RGB555 0x30 /* RGB555 output */
148 #define REG_COM16 0x41 /* Control 16 */
149 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
150 #define REG_COM17 0x42 /* Control 17 */
151 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
152 #define COM17_CBAR 0x08 /* DSP Color bar */
153
154 /*
155 * This matrix defines how the colors are generated, must be
156 * tweaked to adjust hue and saturation.
157 *
158 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
159 *
160 * They are nine-bit signed quantities, with the sign bit
161 * stored in 0x58. Sign for v-red is bit 0, and up from there.
162 */
163 #define REG_CMATRIX_BASE 0x4f
164 #define CMATRIX_LEN 6
165 #define REG_CMATRIX_SIGN 0x58
166
167
168 #define REG_BRIGHT 0x55 /* Brightness */
169 #define REG_CONTRAS 0x56 /* Contrast control */
170
171 #define REG_GFIX 0x69 /* Fix gain control */
172
173 #define REG_REG76 0x76 /* OV's name */
174 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
175 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
176
177 #define REG_RGB444 0x8c /* RGB 444 control */
178 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
179 #define R444_RGBX 0x01 /* Empty nibble at end */
180
181 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
182 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
183
184 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
185 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
186 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
187 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
188 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
189 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
190 #define REG_BD60MAX 0xab /* 60hz banding step limit */
191
192
193 /*
194 * Information we maintain about a known sensor.
195 */
196 struct ov7670_format_struct; /* coming later */
197 struct ov7670_info {
198 struct v4l2_subdev sd;
199 struct ov7670_format_struct *fmt; /* Current format */
200 unsigned char sat; /* Saturation value */
201 int hue; /* Hue value */
202 u8 clkrc; /* Clock divider value */
203 };
204
205 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
206 {
207 return container_of(sd, struct ov7670_info, sd);
208 }
209
210
211
212 /*
213 * The default register settings, as obtained from OmniVision. There
214 * is really no making sense of most of these - lots of "reserved" values
215 * and such.
216 *
217 * These settings give VGA YUYV.
218 */
219
220 struct regval_list {
221 unsigned char reg_num;
222 unsigned char value;
223 };
224
225 static struct regval_list ov7670_default_regs[] = {
226 { REG_COM7, COM7_RESET },
227 /*
228 * Clock scale: 3 = 15fps
229 * 2 = 20fps
230 * 1 = 30fps
231 */
232 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
233 { REG_TSLB, 0x04 }, /* OV */
234 { REG_COM7, 0 }, /* VGA */
235 /*
236 * Set the hardware window. These values from OV don't entirely
237 * make sense - hstop is less than hstart. But they work...
238 */
239 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
240 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
241 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
242
243 { REG_COM3, 0 }, { REG_COM14, 0 },
244 /* Mystery scaling numbers */
245 { 0x70, 0x3a }, { 0x71, 0x35 },
246 { 0x72, 0x11 }, { 0x73, 0xf0 },
247 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
248
249 /* Gamma curve values */
250 { 0x7a, 0x20 }, { 0x7b, 0x10 },
251 { 0x7c, 0x1e }, { 0x7d, 0x35 },
252 { 0x7e, 0x5a }, { 0x7f, 0x69 },
253 { 0x80, 0x76 }, { 0x81, 0x80 },
254 { 0x82, 0x88 }, { 0x83, 0x8f },
255 { 0x84, 0x96 }, { 0x85, 0xa3 },
256 { 0x86, 0xaf }, { 0x87, 0xc4 },
257 { 0x88, 0xd7 }, { 0x89, 0xe8 },
258
259 /* AGC and AEC parameters. Note we start by disabling those features,
260 then turn them only after tweaking the values. */
261 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
262 { REG_GAIN, 0 }, { REG_AECH, 0 },
263 { REG_COM4, 0x40 }, /* magic reserved bit */
264 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
265 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
266 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
267 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
268 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
269 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
270 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
271 { REG_HAECC7, 0x94 },
272 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
273
274 /* Almost all of these are magic "reserved" values. */
275 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
276 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
277 { 0x21, 0x02 }, { 0x22, 0x91 },
278 { 0x29, 0x07 }, { 0x33, 0x0b },
279 { 0x35, 0x0b }, { 0x37, 0x1d },
280 { 0x38, 0x71 }, { 0x39, 0x2a },
281 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
282 { 0x4e, 0x20 }, { REG_GFIX, 0 },
283 { 0x6b, 0x4a }, { 0x74, 0x10 },
284 { 0x8d, 0x4f }, { 0x8e, 0 },
285 { 0x8f, 0 }, { 0x90, 0 },
286 { 0x91, 0 }, { 0x96, 0 },
287 { 0x9a, 0 }, { 0xb0, 0x84 },
288 { 0xb1, 0x0c }, { 0xb2, 0x0e },
289 { 0xb3, 0x82 }, { 0xb8, 0x0a },
290
291 /* More reserved magic, some of which tweaks white balance */
292 { 0x43, 0x0a }, { 0x44, 0xf0 },
293 { 0x45, 0x34 }, { 0x46, 0x58 },
294 { 0x47, 0x28 }, { 0x48, 0x3a },
295 { 0x59, 0x88 }, { 0x5a, 0x88 },
296 { 0x5b, 0x44 }, { 0x5c, 0x67 },
297 { 0x5d, 0x49 }, { 0x5e, 0x0e },
298 { 0x6c, 0x0a }, { 0x6d, 0x55 },
299 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
300 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
301 { REG_RED, 0x60 },
302 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
303
304 /* Matrix coefficients */
305 { 0x4f, 0x80 }, { 0x50, 0x80 },
306 { 0x51, 0 }, { 0x52, 0x22 },
307 { 0x53, 0x5e }, { 0x54, 0x80 },
308 { 0x58, 0x9e },
309
310 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
311 { 0x75, 0x05 }, { 0x76, 0xe1 },
312 { 0x4c, 0 }, { 0x77, 0x01 },
313 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
314 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
315 { 0x56, 0x40 },
316
317 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
318 { 0xa4, 0x88 }, { 0x96, 0 },
319 { 0x97, 0x30 }, { 0x98, 0x20 },
320 { 0x99, 0x30 }, { 0x9a, 0x84 },
321 { 0x9b, 0x29 }, { 0x9c, 0x03 },
322 { 0x9d, 0x4c }, { 0x9e, 0x3f },
323 { 0x78, 0x04 },
324
325 /* Extra-weird stuff. Some sort of multiplexor register */
326 { 0x79, 0x01 }, { 0xc8, 0xf0 },
327 { 0x79, 0x0f }, { 0xc8, 0x00 },
328 { 0x79, 0x10 }, { 0xc8, 0x7e },
329 { 0x79, 0x0a }, { 0xc8, 0x80 },
330 { 0x79, 0x0b }, { 0xc8, 0x01 },
331 { 0x79, 0x0c }, { 0xc8, 0x0f },
332 { 0x79, 0x0d }, { 0xc8, 0x20 },
333 { 0x79, 0x09 }, { 0xc8, 0x80 },
334 { 0x79, 0x02 }, { 0xc8, 0xc0 },
335 { 0x79, 0x03 }, { 0xc8, 0x40 },
336 { 0x79, 0x05 }, { 0xc8, 0x30 },
337 { 0x79, 0x26 },
338
339 { 0xff, 0xff }, /* END MARKER */
340 };
341
342
343 /*
344 * Here we'll try to encapsulate the changes for just the output
345 * video format.
346 *
347 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
348 *
349 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
350 */
351
352
353 static struct regval_list ov7670_fmt_yuv422[] = {
354 { REG_COM7, 0x0 }, /* Selects YUV mode */
355 { REG_RGB444, 0 }, /* No RGB444 please */
356 { REG_COM1, 0 }, /* CCIR601 */
357 { REG_COM15, COM15_R00FF },
358 { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */
359 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
360 { 0x50, 0x80 }, /* "matrix coefficient 2" */
361 { 0x51, 0 }, /* vb */
362 { 0x52, 0x22 }, /* "matrix coefficient 4" */
363 { 0x53, 0x5e }, /* "matrix coefficient 5" */
364 { 0x54, 0x80 }, /* "matrix coefficient 6" */
365 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
366 { 0xff, 0xff },
367 };
368
369 static struct regval_list ov7670_fmt_rgb565[] = {
370 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
371 { REG_RGB444, 0 }, /* No RGB444 please */
372 { REG_COM1, 0x0 }, /* CCIR601 */
373 { REG_COM15, COM15_RGB565 },
374 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
375 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
376 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
377 { 0x51, 0 }, /* vb */
378 { 0x52, 0x3d }, /* "matrix coefficient 4" */
379 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
380 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
381 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
382 { 0xff, 0xff },
383 };
384
385 static struct regval_list ov7670_fmt_rgb444[] = {
386 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
387 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
388 { REG_COM1, 0x0 }, /* CCIR601 */
389 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
390 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
391 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
392 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
393 { 0x51, 0 }, /* vb */
394 { 0x52, 0x3d }, /* "matrix coefficient 4" */
395 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
396 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
397 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
398 { 0xff, 0xff },
399 };
400
401 static struct regval_list ov7670_fmt_raw[] = {
402 { REG_COM7, COM7_BAYER },
403 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
404 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
405 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
406 { 0xff, 0xff },
407 };
408
409
410
411 /*
412 * Low-level register I/O.
413 *
414 * Note that there are two versions of these. On the XO 1, the
415 * i2c controller only does SMBUS, so that's what we use. The
416 * ov7670 is not really an SMBUS device, though, so the communication
417 * is not always entirely reliable.
418 */
419 #ifdef CONFIG_OLPC_XO_1
420 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
421 unsigned char *value)
422 {
423 struct i2c_client *client = v4l2_get_subdevdata(sd);
424 int ret;
425
426 ret = i2c_smbus_read_byte_data(client, reg);
427 if (ret >= 0) {
428 *value = (unsigned char)ret;
429 ret = 0;
430 }
431 return ret;
432 }
433
434
435 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
436 unsigned char value)
437 {
438 struct i2c_client *client = v4l2_get_subdevdata(sd);
439 int ret = i2c_smbus_write_byte_data(client, reg, value);
440
441 if (reg == REG_COM7 && (value & COM7_RESET))
442 msleep(5); /* Wait for reset to run */
443 return ret;
444 }
445
446 #else /* ! CONFIG_OLPC_XO_1 */
447 /*
448 * On most platforms, we'd rather do straight i2c I/O.
449 */
450 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
451 unsigned char *value)
452 {
453 struct i2c_client *client = v4l2_get_subdevdata(sd);
454 u8 data = reg;
455 struct i2c_msg msg;
456 int ret;
457
458 /*
459 * Send out the register address...
460 */
461 msg.addr = client->addr;
462 msg.flags = 0;
463 msg.len = 1;
464 msg.buf = &data;
465 ret = i2c_transfer(client->adapter, &msg, 1);
466 if (ret < 0) {
467 printk(KERN_ERR "Error %d on register write\n", ret);
468 return ret;
469 }
470 /*
471 * ...then read back the result.
472 */
473 msg.flags = I2C_M_RD;
474 ret = i2c_transfer(client->adapter, &msg, 1);
475 if (ret >= 0) {
476 *value = data;
477 ret = 0;
478 }
479 return ret;
480 }
481
482
483 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
484 unsigned char value)
485 {
486 struct i2c_client *client = v4l2_get_subdevdata(sd);
487 struct i2c_msg msg;
488 unsigned char data[2] = { reg, value };
489 int ret;
490
491 msg.addr = client->addr;
492 msg.flags = 0;
493 msg.len = 2;
494 msg.buf = data;
495 ret = i2c_transfer(client->adapter, &msg, 1);
496 if (ret > 0)
497 ret = 0;
498 if (reg == REG_COM7 && (value & COM7_RESET))
499 msleep(5); /* Wait for reset to run */
500 return ret;
501 }
502 #endif /* CONFIG_OLPC_XO_1 */
503
504
505 /*
506 * Write a list of register settings; ff/ff stops the process.
507 */
508 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
509 {
510 while (vals->reg_num != 0xff || vals->value != 0xff) {
511 int ret = ov7670_write(sd, vals->reg_num, vals->value);
512 if (ret < 0)
513 return ret;
514 vals++;
515 }
516 return 0;
517 }
518
519
520 /*
521 * Stuff that knows about the sensor.
522 */
523 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
524 {
525 ov7670_write(sd, REG_COM7, COM7_RESET);
526 msleep(1);
527 return 0;
528 }
529
530
531 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
532 {
533 return ov7670_write_array(sd, ov7670_default_regs);
534 }
535
536
537
538 static int ov7670_detect(struct v4l2_subdev *sd)
539 {
540 unsigned char v;
541 int ret;
542
543 ret = ov7670_init(sd, 0);
544 if (ret < 0)
545 return ret;
546 ret = ov7670_read(sd, REG_MIDH, &v);
547 if (ret < 0)
548 return ret;
549 if (v != 0x7f) /* OV manuf. id. */
550 return -ENODEV;
551 ret = ov7670_read(sd, REG_MIDL, &v);
552 if (ret < 0)
553 return ret;
554 if (v != 0xa2)
555 return -ENODEV;
556 /*
557 * OK, we know we have an OmniVision chip...but which one?
558 */
559 ret = ov7670_read(sd, REG_PID, &v);
560 if (ret < 0)
561 return ret;
562 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
563 return -ENODEV;
564 ret = ov7670_read(sd, REG_VER, &v);
565 if (ret < 0)
566 return ret;
567 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
568 return -ENODEV;
569 return 0;
570 }
571
572
573 /*
574 * Store information about the video data format. The color matrix
575 * is deeply tied into the format, so keep the relevant values here.
576 * The magic matrix numbers come from OmniVision.
577 */
578 static struct ov7670_format_struct {
579 enum v4l2_mbus_pixelcode mbus_code;
580 enum v4l2_colorspace colorspace;
581 struct regval_list *regs;
582 int cmatrix[CMATRIX_LEN];
583 } ov7670_formats[] = {
584 {
585 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
586 .colorspace = V4L2_COLORSPACE_JPEG,
587 .regs = ov7670_fmt_yuv422,
588 .cmatrix = { 128, -128, 0, -34, -94, 128 },
589 },
590 {
591 .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE,
592 .colorspace = V4L2_COLORSPACE_SRGB,
593 .regs = ov7670_fmt_rgb444,
594 .cmatrix = { 179, -179, 0, -61, -176, 228 },
595 },
596 {
597 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE,
598 .colorspace = V4L2_COLORSPACE_SRGB,
599 .regs = ov7670_fmt_rgb565,
600 .cmatrix = { 179, -179, 0, -61, -176, 228 },
601 },
602 {
603 .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8,
604 .colorspace = V4L2_COLORSPACE_SRGB,
605 .regs = ov7670_fmt_raw,
606 .cmatrix = { 0, 0, 0, 0, 0, 0 },
607 },
608 };
609 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
610
611
612 /*
613 * Then there is the issue of window sizes. Try to capture the info here.
614 */
615
616 /*
617 * QCIF mode is done (by OV) in a very strange way - it actually looks like
618 * VGA with weird scaling options - they do *not* use the canned QCIF mode
619 * which is allegedly provided by the sensor. So here's the weird register
620 * settings.
621 */
622 static struct regval_list ov7670_qcif_regs[] = {
623 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
624 { REG_COM3, COM3_DCWEN },
625 { REG_COM14, COM14_DCWEN | 0x01},
626 { 0x73, 0xf1 },
627 { 0xa2, 0x52 },
628 { 0x7b, 0x1c },
629 { 0x7c, 0x28 },
630 { 0x7d, 0x3c },
631 { 0x7f, 0x69 },
632 { REG_COM9, 0x38 },
633 { 0xa1, 0x0b },
634 { 0x74, 0x19 },
635 { 0x9a, 0x80 },
636 { 0x43, 0x14 },
637 { REG_COM13, 0xc0 },
638 { 0xff, 0xff },
639 };
640
641 static struct ov7670_win_size {
642 int width;
643 int height;
644 unsigned char com7_bit;
645 int hstart; /* Start/stop values for the camera. Note */
646 int hstop; /* that they do not always make complete */
647 int vstart; /* sense to humans, but evidently the sensor */
648 int vstop; /* will do the right thing... */
649 struct regval_list *regs; /* Regs to tweak */
650 /* h/vref stuff */
651 } ov7670_win_sizes[] = {
652 /* VGA */
653 {
654 .width = VGA_WIDTH,
655 .height = VGA_HEIGHT,
656 .com7_bit = COM7_FMT_VGA,
657 .hstart = 158, /* These values from */
658 .hstop = 14, /* Omnivision */
659 .vstart = 10,
660 .vstop = 490,
661 .regs = NULL,
662 },
663 /* CIF */
664 {
665 .width = CIF_WIDTH,
666 .height = CIF_HEIGHT,
667 .com7_bit = COM7_FMT_CIF,
668 .hstart = 170, /* Empirically determined */
669 .hstop = 90,
670 .vstart = 14,
671 .vstop = 494,
672 .regs = NULL,
673 },
674 /* QVGA */
675 {
676 .width = QVGA_WIDTH,
677 .height = QVGA_HEIGHT,
678 .com7_bit = COM7_FMT_QVGA,
679 .hstart = 164, /* Empirically determined */
680 .hstop = 20,
681 .vstart = 14,
682 .vstop = 494,
683 .regs = NULL,
684 },
685 /* QCIF */
686 {
687 .width = QCIF_WIDTH,
688 .height = QCIF_HEIGHT,
689 .com7_bit = COM7_FMT_VGA, /* see comment above */
690 .hstart = 456, /* Empirically determined */
691 .hstop = 24,
692 .vstart = 14,
693 .vstop = 494,
694 .regs = ov7670_qcif_regs,
695 },
696 };
697
698 #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes))
699
700
701 /*
702 * Store a set of start/stop values into the camera.
703 */
704 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
705 int vstart, int vstop)
706 {
707 int ret;
708 unsigned char v;
709 /*
710 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
711 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
712 * a mystery "edge offset" value in the top two bits of href.
713 */
714 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
715 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
716 ret += ov7670_read(sd, REG_HREF, &v);
717 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
718 msleep(10);
719 ret += ov7670_write(sd, REG_HREF, v);
720 /*
721 * Vertical: similar arrangement, but only 10 bits.
722 */
723 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
724 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
725 ret += ov7670_read(sd, REG_VREF, &v);
726 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
727 msleep(10);
728 ret += ov7670_write(sd, REG_VREF, v);
729 return ret;
730 }
731
732
733 static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
734 enum v4l2_mbus_pixelcode *code)
735 {
736 if (index >= N_OV7670_FMTS)
737 return -EINVAL;
738
739 *code = ov7670_formats[index].mbus_code;
740 return 0;
741 }
742
743 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
744 struct v4l2_mbus_framefmt *fmt,
745 struct ov7670_format_struct **ret_fmt,
746 struct ov7670_win_size **ret_wsize)
747 {
748 int index;
749 struct ov7670_win_size *wsize;
750
751 for (index = 0; index < N_OV7670_FMTS; index++)
752 if (ov7670_formats[index].mbus_code == fmt->code)
753 break;
754 if (index >= N_OV7670_FMTS) {
755 /* default to first format */
756 index = 0;
757 fmt->code = ov7670_formats[0].mbus_code;
758 }
759 if (ret_fmt != NULL)
760 *ret_fmt = ov7670_formats + index;
761 /*
762 * Fields: the OV devices claim to be progressive.
763 */
764 fmt->field = V4L2_FIELD_NONE;
765 /*
766 * Round requested image size down to the nearest
767 * we support, but not below the smallest.
768 */
769 for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES;
770 wsize++)
771 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
772 break;
773 if (wsize >= ov7670_win_sizes + N_WIN_SIZES)
774 wsize--; /* Take the smallest one */
775 if (ret_wsize != NULL)
776 *ret_wsize = wsize;
777 /*
778 * Note the size we'll actually handle.
779 */
780 fmt->width = wsize->width;
781 fmt->height = wsize->height;
782 fmt->colorspace = ov7670_formats[index].colorspace;
783 return 0;
784 }
785
786 static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd,
787 struct v4l2_mbus_framefmt *fmt)
788 {
789 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL);
790 }
791
792 /*
793 * Set a format.
794 */
795 static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd,
796 struct v4l2_mbus_framefmt *fmt)
797 {
798 struct ov7670_format_struct *ovfmt;
799 struct ov7670_win_size *wsize;
800 struct ov7670_info *info = to_state(sd);
801 unsigned char com7;
802 int ret;
803
804 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize);
805
806 if (ret)
807 return ret;
808 /*
809 * COM7 is a pain in the ass, it doesn't like to be read then
810 * quickly written afterward. But we have everything we need
811 * to set it absolutely here, as long as the format-specific
812 * register sets list it first.
813 */
814 com7 = ovfmt->regs[0].value;
815 com7 |= wsize->com7_bit;
816 ov7670_write(sd, REG_COM7, com7);
817 /*
818 * Now write the rest of the array. Also store start/stops
819 */
820 ov7670_write_array(sd, ovfmt->regs + 1);
821 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
822 wsize->vstop);
823 ret = 0;
824 if (wsize->regs)
825 ret = ov7670_write_array(sd, wsize->regs);
826 info->fmt = ovfmt;
827
828 /*
829 * If we're running RGB565, we must rewrite clkrc after setting
830 * the other parameters or the image looks poor. If we're *not*
831 * doing RGB565, we must not rewrite clkrc or the image looks
832 * *really* poor.
833 *
834 * (Update) Now that we retain clkrc state, we should be able
835 * to write it unconditionally, and that will make the frame
836 * rate persistent too.
837 */
838 if (ret == 0)
839 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
840 return 0;
841 }
842
843 /*
844 * Implement G/S_PARM. There is a "high quality" mode we could try
845 * to do someday; for now, we just do the frame rate tweak.
846 */
847 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
848 {
849 struct v4l2_captureparm *cp = &parms->parm.capture;
850 struct ov7670_info *info = to_state(sd);
851
852 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
853 return -EINVAL;
854
855 memset(cp, 0, sizeof(struct v4l2_captureparm));
856 cp->capability = V4L2_CAP_TIMEPERFRAME;
857 cp->timeperframe.numerator = 1;
858 cp->timeperframe.denominator = OV7670_FRAME_RATE;
859 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
860 cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE);
861 return 0;
862 }
863
864 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
865 {
866 struct v4l2_captureparm *cp = &parms->parm.capture;
867 struct v4l2_fract *tpf = &cp->timeperframe;
868 struct ov7670_info *info = to_state(sd);
869 int div;
870
871 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
872 return -EINVAL;
873 if (cp->extendedmode != 0)
874 return -EINVAL;
875
876 if (tpf->numerator == 0 || tpf->denominator == 0)
877 div = 1; /* Reset to full rate */
878 else
879 div = (tpf->numerator*OV7670_FRAME_RATE)/tpf->denominator;
880 if (div == 0)
881 div = 1;
882 else if (div > CLK_SCALE)
883 div = CLK_SCALE;
884 info->clkrc = (info->clkrc & 0x80) | div;
885 tpf->numerator = 1;
886 tpf->denominator = OV7670_FRAME_RATE/div;
887 return ov7670_write(sd, REG_CLKRC, info->clkrc);
888 }
889
890
891
892 /*
893 * Code for dealing with controls.
894 */
895
896
897
898
899
900 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
901 int matrix[CMATRIX_LEN])
902 {
903 int i, ret;
904 unsigned char signbits = 0;
905
906 /*
907 * Weird crap seems to exist in the upper part of
908 * the sign bits register, so let's preserve it.
909 */
910 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
911 signbits &= 0xc0;
912
913 for (i = 0; i < CMATRIX_LEN; i++) {
914 unsigned char raw;
915
916 if (matrix[i] < 0) {
917 signbits |= (1 << i);
918 if (matrix[i] < -255)
919 raw = 0xff;
920 else
921 raw = (-1 * matrix[i]) & 0xff;
922 }
923 else {
924 if (matrix[i] > 255)
925 raw = 0xff;
926 else
927 raw = matrix[i] & 0xff;
928 }
929 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
930 }
931 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
932 return ret;
933 }
934
935
936 /*
937 * Hue also requires messing with the color matrix. It also requires
938 * trig functions, which tend not to be well supported in the kernel.
939 * So here is a simple table of sine values, 0-90 degrees, in steps
940 * of five degrees. Values are multiplied by 1000.
941 *
942 * The following naive approximate trig functions require an argument
943 * carefully limited to -180 <= theta <= 180.
944 */
945 #define SIN_STEP 5
946 static const int ov7670_sin_table[] = {
947 0, 87, 173, 258, 342, 422,
948 499, 573, 642, 707, 766, 819,
949 866, 906, 939, 965, 984, 996,
950 1000
951 };
952
953 static int ov7670_sine(int theta)
954 {
955 int chs = 1;
956 int sine;
957
958 if (theta < 0) {
959 theta = -theta;
960 chs = -1;
961 }
962 if (theta <= 90)
963 sine = ov7670_sin_table[theta/SIN_STEP];
964 else {
965 theta -= 90;
966 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
967 }
968 return sine*chs;
969 }
970
971 static int ov7670_cosine(int theta)
972 {
973 theta = 90 - theta;
974 if (theta > 180)
975 theta -= 360;
976 else if (theta < -180)
977 theta += 360;
978 return ov7670_sine(theta);
979 }
980
981
982
983
984 static void ov7670_calc_cmatrix(struct ov7670_info *info,
985 int matrix[CMATRIX_LEN])
986 {
987 int i;
988 /*
989 * Apply the current saturation setting first.
990 */
991 for (i = 0; i < CMATRIX_LEN; i++)
992 matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7;
993 /*
994 * Then, if need be, rotate the hue value.
995 */
996 if (info->hue != 0) {
997 int sinth, costh, tmpmatrix[CMATRIX_LEN];
998
999 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1000 sinth = ov7670_sine(info->hue);
1001 costh = ov7670_cosine(info->hue);
1002
1003 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1004 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1005 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1006 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1007 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1008 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1009 }
1010 }
1011
1012
1013
1014 static int ov7670_s_sat(struct v4l2_subdev *sd, int value)
1015 {
1016 struct ov7670_info *info = to_state(sd);
1017 int matrix[CMATRIX_LEN];
1018 int ret;
1019
1020 info->sat = value;
1021 ov7670_calc_cmatrix(info, matrix);
1022 ret = ov7670_store_cmatrix(sd, matrix);
1023 return ret;
1024 }
1025
1026 static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value)
1027 {
1028 struct ov7670_info *info = to_state(sd);
1029
1030 *value = info->sat;
1031 return 0;
1032 }
1033
1034 static int ov7670_s_hue(struct v4l2_subdev *sd, int value)
1035 {
1036 struct ov7670_info *info = to_state(sd);
1037 int matrix[CMATRIX_LEN];
1038 int ret;
1039
1040 if (value < -180 || value > 180)
1041 return -EINVAL;
1042 info->hue = value;
1043 ov7670_calc_cmatrix(info, matrix);
1044 ret = ov7670_store_cmatrix(sd, matrix);
1045 return ret;
1046 }
1047
1048
1049 static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value)
1050 {
1051 struct ov7670_info *info = to_state(sd);
1052
1053 *value = info->hue;
1054 return 0;
1055 }
1056
1057
1058 /*
1059 * Some weird registers seem to store values in a sign/magnitude format!
1060 */
1061 static unsigned char ov7670_sm_to_abs(unsigned char v)
1062 {
1063 if ((v & 0x80) == 0)
1064 return v + 128;
1065 return 128 - (v & 0x7f);
1066 }
1067
1068
1069 static unsigned char ov7670_abs_to_sm(unsigned char v)
1070 {
1071 if (v > 127)
1072 return v & 0x7f;
1073 return (128 - v) | 0x80;
1074 }
1075
1076 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1077 {
1078 unsigned char com8 = 0, v;
1079 int ret;
1080
1081 ov7670_read(sd, REG_COM8, &com8);
1082 com8 &= ~COM8_AEC;
1083 ov7670_write(sd, REG_COM8, com8);
1084 v = ov7670_abs_to_sm(value);
1085 ret = ov7670_write(sd, REG_BRIGHT, v);
1086 return ret;
1087 }
1088
1089 static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value)
1090 {
1091 unsigned char v = 0;
1092 int ret = ov7670_read(sd, REG_BRIGHT, &v);
1093
1094 *value = ov7670_sm_to_abs(v);
1095 return ret;
1096 }
1097
1098 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1099 {
1100 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1101 }
1102
1103 static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value)
1104 {
1105 unsigned char v = 0;
1106 int ret = ov7670_read(sd, REG_CONTRAS, &v);
1107
1108 *value = v;
1109 return ret;
1110 }
1111
1112 static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value)
1113 {
1114 int ret;
1115 unsigned char v = 0;
1116
1117 ret = ov7670_read(sd, REG_MVFP, &v);
1118 *value = (v & MVFP_MIRROR) == MVFP_MIRROR;
1119 return ret;
1120 }
1121
1122
1123 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1124 {
1125 unsigned char v = 0;
1126 int ret;
1127
1128 ret = ov7670_read(sd, REG_MVFP, &v);
1129 if (value)
1130 v |= MVFP_MIRROR;
1131 else
1132 v &= ~MVFP_MIRROR;
1133 msleep(10); /* FIXME */
1134 ret += ov7670_write(sd, REG_MVFP, v);
1135 return ret;
1136 }
1137
1138
1139
1140 static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value)
1141 {
1142 int ret;
1143 unsigned char v = 0;
1144
1145 ret = ov7670_read(sd, REG_MVFP, &v);
1146 *value = (v & MVFP_FLIP) == MVFP_FLIP;
1147 return ret;
1148 }
1149
1150
1151 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1152 {
1153 unsigned char v = 0;
1154 int ret;
1155
1156 ret = ov7670_read(sd, REG_MVFP, &v);
1157 if (value)
1158 v |= MVFP_FLIP;
1159 else
1160 v &= ~MVFP_FLIP;
1161 msleep(10); /* FIXME */
1162 ret += ov7670_write(sd, REG_MVFP, v);
1163 return ret;
1164 }
1165
1166 /*
1167 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1168 * the data sheet, the VREF parts should be the most significant, but
1169 * experience shows otherwise. There seems to be little value in
1170 * messing with the VREF bits, so we leave them alone.
1171 */
1172 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1173 {
1174 int ret;
1175 unsigned char gain;
1176
1177 ret = ov7670_read(sd, REG_GAIN, &gain);
1178 *value = gain;
1179 return ret;
1180 }
1181
1182 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1183 {
1184 int ret;
1185 unsigned char com8;
1186
1187 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1188 /* Have to turn off AGC as well */
1189 if (ret == 0) {
1190 ret = ov7670_read(sd, REG_COM8, &com8);
1191 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1192 }
1193 return ret;
1194 }
1195
1196 /*
1197 * Tweak autogain.
1198 */
1199 static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value)
1200 {
1201 int ret;
1202 unsigned char com8;
1203
1204 ret = ov7670_read(sd, REG_COM8, &com8);
1205 *value = (com8 & COM8_AGC) != 0;
1206 return ret;
1207 }
1208
1209 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1210 {
1211 int ret;
1212 unsigned char com8;
1213
1214 ret = ov7670_read(sd, REG_COM8, &com8);
1215 if (ret == 0) {
1216 if (value)
1217 com8 |= COM8_AGC;
1218 else
1219 com8 &= ~COM8_AGC;
1220 ret = ov7670_write(sd, REG_COM8, com8);
1221 }
1222 return ret;
1223 }
1224
1225 /*
1226 * Exposure is spread all over the place: top 6 bits in AECHH, middle
1227 * 8 in AECH, and two stashed in COM1 just for the hell of it.
1228 */
1229 static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value)
1230 {
1231 int ret;
1232 unsigned char com1, aech, aechh;
1233
1234 ret = ov7670_read(sd, REG_COM1, &com1) +
1235 ov7670_read(sd, REG_AECH, &aech) +
1236 ov7670_read(sd, REG_AECHH, &aechh);
1237 *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03);
1238 return ret;
1239 }
1240
1241 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1242 {
1243 int ret;
1244 unsigned char com1, com8, aech, aechh;
1245
1246 ret = ov7670_read(sd, REG_COM1, &com1) +
1247 ov7670_read(sd, REG_COM8, &com8);
1248 ov7670_read(sd, REG_AECHH, &aechh);
1249 if (ret)
1250 return ret;
1251
1252 com1 = (com1 & 0xfc) | (value & 0x03);
1253 aech = (value >> 2) & 0xff;
1254 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1255 ret = ov7670_write(sd, REG_COM1, com1) +
1256 ov7670_write(sd, REG_AECH, aech) +
1257 ov7670_write(sd, REG_AECHH, aechh);
1258 /* Have to turn off AEC as well */
1259 if (ret == 0)
1260 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1261 return ret;
1262 }
1263
1264 /*
1265 * Tweak autoexposure.
1266 */
1267 static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value)
1268 {
1269 int ret;
1270 unsigned char com8;
1271 enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value;
1272
1273 ret = ov7670_read(sd, REG_COM8, &com8);
1274 if (com8 & COM8_AEC)
1275 *atype = V4L2_EXPOSURE_AUTO;
1276 else
1277 *atype = V4L2_EXPOSURE_MANUAL;
1278 return ret;
1279 }
1280
1281 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1282 enum v4l2_exposure_auto_type value)
1283 {
1284 int ret;
1285 unsigned char com8;
1286
1287 ret = ov7670_read(sd, REG_COM8, &com8);
1288 if (ret == 0) {
1289 if (value == V4L2_EXPOSURE_AUTO)
1290 com8 |= COM8_AEC;
1291 else
1292 com8 &= ~COM8_AEC;
1293 ret = ov7670_write(sd, REG_COM8, com8);
1294 }
1295 return ret;
1296 }
1297
1298
1299
1300 static int ov7670_queryctrl(struct v4l2_subdev *sd,
1301 struct v4l2_queryctrl *qc)
1302 {
1303 /* Fill in min, max, step and default value for these controls. */
1304 switch (qc->id) {
1305 case V4L2_CID_BRIGHTNESS:
1306 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
1307 case V4L2_CID_CONTRAST:
1308 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
1309 case V4L2_CID_VFLIP:
1310 case V4L2_CID_HFLIP:
1311 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1312 case V4L2_CID_SATURATION:
1313 return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128);
1314 case V4L2_CID_HUE:
1315 return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0);
1316 case V4L2_CID_GAIN:
1317 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
1318 case V4L2_CID_AUTOGAIN:
1319 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1);
1320 case V4L2_CID_EXPOSURE:
1321 return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500);
1322 case V4L2_CID_EXPOSURE_AUTO:
1323 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1324 }
1325 return -EINVAL;
1326 }
1327
1328 static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1329 {
1330 switch (ctrl->id) {
1331 case V4L2_CID_BRIGHTNESS:
1332 return ov7670_g_brightness(sd, &ctrl->value);
1333 case V4L2_CID_CONTRAST:
1334 return ov7670_g_contrast(sd, &ctrl->value);
1335 case V4L2_CID_SATURATION:
1336 return ov7670_g_sat(sd, &ctrl->value);
1337 case V4L2_CID_HUE:
1338 return ov7670_g_hue(sd, &ctrl->value);
1339 case V4L2_CID_VFLIP:
1340 return ov7670_g_vflip(sd, &ctrl->value);
1341 case V4L2_CID_HFLIP:
1342 return ov7670_g_hflip(sd, &ctrl->value);
1343 case V4L2_CID_GAIN:
1344 return ov7670_g_gain(sd, &ctrl->value);
1345 case V4L2_CID_AUTOGAIN:
1346 return ov7670_g_autogain(sd, &ctrl->value);
1347 case V4L2_CID_EXPOSURE:
1348 return ov7670_g_exp(sd, &ctrl->value);
1349 case V4L2_CID_EXPOSURE_AUTO:
1350 return ov7670_g_autoexp(sd, &ctrl->value);
1351 }
1352 return -EINVAL;
1353 }
1354
1355 static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1356 {
1357 switch (ctrl->id) {
1358 case V4L2_CID_BRIGHTNESS:
1359 return ov7670_s_brightness(sd, ctrl->value);
1360 case V4L2_CID_CONTRAST:
1361 return ov7670_s_contrast(sd, ctrl->value);
1362 case V4L2_CID_SATURATION:
1363 return ov7670_s_sat(sd, ctrl->value);
1364 case V4L2_CID_HUE:
1365 return ov7670_s_hue(sd, ctrl->value);
1366 case V4L2_CID_VFLIP:
1367 return ov7670_s_vflip(sd, ctrl->value);
1368 case V4L2_CID_HFLIP:
1369 return ov7670_s_hflip(sd, ctrl->value);
1370 case V4L2_CID_GAIN:
1371 return ov7670_s_gain(sd, ctrl->value);
1372 case V4L2_CID_AUTOGAIN:
1373 return ov7670_s_autogain(sd, ctrl->value);
1374 case V4L2_CID_EXPOSURE:
1375 return ov7670_s_exp(sd, ctrl->value);
1376 case V4L2_CID_EXPOSURE_AUTO:
1377 return ov7670_s_autoexp(sd,
1378 (enum v4l2_exposure_auto_type) ctrl->value);
1379 }
1380 return -EINVAL;
1381 }
1382
1383 static int ov7670_g_chip_ident(struct v4l2_subdev *sd,
1384 struct v4l2_dbg_chip_ident *chip)
1385 {
1386 struct i2c_client *client = v4l2_get_subdevdata(sd);
1387
1388 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0);
1389 }
1390
1391 #ifdef CONFIG_VIDEO_ADV_DEBUG
1392 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1393 {
1394 struct i2c_client *client = v4l2_get_subdevdata(sd);
1395 unsigned char val = 0;
1396 int ret;
1397
1398 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1399 return -EINVAL;
1400 if (!capable(CAP_SYS_ADMIN))
1401 return -EPERM;
1402 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1403 reg->val = val;
1404 reg->size = 1;
1405 return ret;
1406 }
1407
1408 static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1409 {
1410 struct i2c_client *client = v4l2_get_subdevdata(sd);
1411
1412 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1413 return -EINVAL;
1414 if (!capable(CAP_SYS_ADMIN))
1415 return -EPERM;
1416 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1417 return 0;
1418 }
1419 #endif
1420
1421 /* ----------------------------------------------------------------------- */
1422
1423 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1424 .g_chip_ident = ov7670_g_chip_ident,
1425 .g_ctrl = ov7670_g_ctrl,
1426 .s_ctrl = ov7670_s_ctrl,
1427 .queryctrl = ov7670_queryctrl,
1428 .reset = ov7670_reset,
1429 .init = ov7670_init,
1430 #ifdef CONFIG_VIDEO_ADV_DEBUG
1431 .g_register = ov7670_g_register,
1432 .s_register = ov7670_s_register,
1433 #endif
1434 };
1435
1436 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1437 .enum_mbus_fmt = ov7670_enum_mbus_fmt,
1438 .try_mbus_fmt = ov7670_try_mbus_fmt,
1439 .s_mbus_fmt = ov7670_s_mbus_fmt,
1440 .s_parm = ov7670_s_parm,
1441 .g_parm = ov7670_g_parm,
1442 };
1443
1444 static const struct v4l2_subdev_ops ov7670_ops = {
1445 .core = &ov7670_core_ops,
1446 .video = &ov7670_video_ops,
1447 };
1448
1449 /* ----------------------------------------------------------------------- */
1450
1451 static int ov7670_probe(struct i2c_client *client,
1452 const struct i2c_device_id *id)
1453 {
1454 struct v4l2_subdev *sd;
1455 struct ov7670_info *info;
1456 int ret;
1457
1458 info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL);
1459 if (info == NULL)
1460 return -ENOMEM;
1461 sd = &info->sd;
1462 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1463
1464 /* Make sure it's an ov7670 */
1465 ret = ov7670_detect(sd);
1466 if (ret) {
1467 v4l_dbg(1, debug, client,
1468 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1469 client->addr << 1, client->adapter->name);
1470 kfree(info);
1471 return ret;
1472 }
1473 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1474 client->addr << 1, client->adapter->name);
1475
1476 info->fmt = &ov7670_formats[0];
1477 info->sat = 128; /* Review this */
1478 info->clkrc = 1; /* 30fps */
1479
1480 return 0;
1481 }
1482
1483
1484 static int ov7670_remove(struct i2c_client *client)
1485 {
1486 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1487
1488 v4l2_device_unregister_subdev(sd);
1489 kfree(to_state(sd));
1490 return 0;
1491 }
1492
1493 static const struct i2c_device_id ov7670_id[] = {
1494 { "ov7670", 0 },
1495 { }
1496 };
1497 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1498
1499 static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1500 .name = "ov7670",
1501 .probe = ov7670_probe,
1502 .remove = ov7670_remove,
1503 .id_table = ov7670_id,
1504 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree