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[PATCH] bcm43xx:Eliminate some 'G Mode Enable' magic numbers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
blob5e96bca6730a470df027e7f10a62899f1c331cf5
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
43
44 #include "bcm43xx.h"
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55 #include "bcm43xx_sysfs.h"
56
57
58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59 MODULE_AUTHOR("Martin Langer");
60 MODULE_AUTHOR("Stefano Brivio");
61 MODULE_AUTHOR("Michael Buesch");
62 MODULE_LICENSE("GPL");
63
64 #ifdef CONFIG_BCM947XX
65 extern char *nvram_get(char *name);
66 #endif
67
68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
69 static int modparam_pio;
70 module_param_named(pio, modparam_pio, int, 0444);
71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72 #elif defined(CONFIG_BCM43XX_DMA)
73 # define modparam_pio 0
74 #elif defined(CONFIG_BCM43XX_PIO)
75 # define modparam_pio 1
76 #endif
77
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
81
82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83 module_param_named(short_retry, modparam_short_retry, int, 0444);
84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
85
86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87 module_param_named(long_retry, modparam_long_retry, int, 0444);
88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
89
90 static int modparam_locale = -1;
91 module_param_named(locale, modparam_locale, int, 0444);
92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
93
94 static int modparam_noleds;
95 module_param_named(noleds, modparam_noleds, int, 0444);
96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
97
98 static char modparam_fwpostfix[64];
99 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
100 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for using multiple firmware image versions.");
101
102
103 /* If you want to debug with just a single device, enable this,
104 * where the string is the pci device ID (as given by the kernel's
105 * pci_name function) of the device to be used.
106 */
107 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
108
109 /* If you want to enable printing of each MMIO access, enable this. */
110 //#define DEBUG_ENABLE_MMIO_PRINT
111
112 /* If you want to enable printing of MMIO access within
113 * ucode/pcm upload, initvals write, enable this.
114 */
115 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
116
117 /* If you want to enable printing of PCI Config Space access, enable this */
118 //#define DEBUG_ENABLE_PCILOG
119
120
121 /* Detailed list maintained at:
122 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
123 */
124 static struct pci_device_id bcm43xx_pci_tbl[] = {
125 /* Broadcom 4303 802.11b */
126 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 /* Broadcom 4307 802.11b */
128 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 /* Broadcom 4311 802.11(a)/b/g */
130 { PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4312 802.11a/b/g */
132 { PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4306 802.11b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 4306 802.11a */
140 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 /* Broadcom 4309 802.11a/b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 /* Broadcom 43XG 802.11b/g */
144 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 #ifdef CONFIG_BCM947XX
146 /* SB bus on BCM947xx */
147 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 #endif
149 { 0 },
150 };
151 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
152
153 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
154 {
155 u32 status;
156
157 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
158 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
159 val = swab32(val);
160
161 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
162 mmiowb();
163 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
164 }
165
166 static inline
167 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
168 u16 routing, u16 offset)
169 {
170 u32 control;
171
172 /* "offset" is the WORD offset. */
173
174 control = routing;
175 control <<= 16;
176 control |= offset;
177 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
178 }
179
180 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
181 u16 routing, u16 offset)
182 {
183 u32 ret;
184
185 if (routing == BCM43xx_SHM_SHARED) {
186 if (offset & 0x0003) {
187 /* Unaligned access */
188 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
189 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
190 ret <<= 16;
191 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
192 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
193
194 return ret;
195 }
196 offset >>= 2;
197 }
198 bcm43xx_shm_control_word(bcm, routing, offset);
199 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
200
201 return ret;
202 }
203
204 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
205 u16 routing, u16 offset)
206 {
207 u16 ret;
208
209 if (routing == BCM43xx_SHM_SHARED) {
210 if (offset & 0x0003) {
211 /* Unaligned access */
212 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
213 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
214
215 return ret;
216 }
217 offset >>= 2;
218 }
219 bcm43xx_shm_control_word(bcm, routing, offset);
220 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
221
222 return ret;
223 }
224
225 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
226 u16 routing, u16 offset,
227 u32 value)
228 {
229 if (routing == BCM43xx_SHM_SHARED) {
230 if (offset & 0x0003) {
231 /* Unaligned access */
232 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
233 mmiowb();
234 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
235 (value >> 16) & 0xffff);
236 mmiowb();
237 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
238 mmiowb();
239 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
240 value & 0xffff);
241 return;
242 }
243 offset >>= 2;
244 }
245 bcm43xx_shm_control_word(bcm, routing, offset);
246 mmiowb();
247 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
248 }
249
250 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
251 u16 routing, u16 offset,
252 u16 value)
253 {
254 if (routing == BCM43xx_SHM_SHARED) {
255 if (offset & 0x0003) {
256 /* Unaligned access */
257 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
258 mmiowb();
259 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
260 value);
261 return;
262 }
263 offset >>= 2;
264 }
265 bcm43xx_shm_control_word(bcm, routing, offset);
266 mmiowb();
267 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
268 }
269
270 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
271 {
272 /* We need to be careful. As we read the TSF from multiple
273 * registers, we should take care of register overflows.
274 * In theory, the whole tsf read process should be atomic.
275 * We try to be atomic here, by restaring the read process,
276 * if any of the high registers changed (overflew).
277 */
278 if (bcm->current_core->rev >= 3) {
279 u32 low, high, high2;
280
281 do {
282 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
283 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
284 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
285 } while (unlikely(high != high2));
286
287 *tsf = high;
288 *tsf <<= 32;
289 *tsf |= low;
290 } else {
291 u64 tmp;
292 u16 v0, v1, v2, v3;
293 u16 test1, test2, test3;
294
295 do {
296 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
297 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
298 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
299 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
300
301 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
302 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
303 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
304 } while (v3 != test3 || v2 != test2 || v1 != test1);
305
306 *tsf = v3;
307 *tsf <<= 48;
308 tmp = v2;
309 tmp <<= 32;
310 *tsf |= tmp;
311 tmp = v1;
312 tmp <<= 16;
313 *tsf |= tmp;
314 *tsf |= v0;
315 }
316 }
317
318 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
319 {
320 u32 status;
321
322 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
323 status |= BCM43xx_SBF_TIME_UPDATE;
324 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
325 mmiowb();
326
327 /* Be careful with the in-progress timer.
328 * First zero out the low register, so we have a full
329 * register-overflow duration to complete the operation.
330 */
331 if (bcm->current_core->rev >= 3) {
332 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
333 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
334
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
336 mmiowb();
337 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
338 mmiowb();
339 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
340 } else {
341 u16 v0 = (tsf & 0x000000000000FFFFULL);
342 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
343 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
344 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
345
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
347 mmiowb();
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
349 mmiowb();
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
351 mmiowb();
352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
353 mmiowb();
354 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
355 }
356
357 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
358 status &= ~BCM43xx_SBF_TIME_UPDATE;
359 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
360 }
361
362 static
363 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
364 u16 offset,
365 const u8 *mac)
366 {
367 u16 data;
368
369 offset |= 0x0020;
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
371
372 data = mac[0];
373 data |= mac[1] << 8;
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
375 data = mac[2];
376 data |= mac[3] << 8;
377 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
378 data = mac[4];
379 data |= mac[5] << 8;
380 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
381 }
382
383 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
384 u16 offset)
385 {
386 const u8 zero_addr[ETH_ALEN] = { 0 };
387
388 bcm43xx_macfilter_set(bcm, offset, zero_addr);
389 }
390
391 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
392 {
393 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
394 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
395 u8 mac_bssid[ETH_ALEN * 2];
396 int i;
397
398 memcpy(mac_bssid, mac, ETH_ALEN);
399 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
400
401 /* Write our MAC address and BSSID to template ram */
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
404 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
405 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
406 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
407 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
408 }
409
410 //FIXME: Well, we should probably call them from somewhere.
411 #if 0
412 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
413 {
414 /* slot_time is in usec. */
415 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
416 return;
417 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
418 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
419 }
420
421 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
422 {
423 bcm43xx_set_slot_time(bcm, 9);
424 }
425
426 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
427 {
428 bcm43xx_set_slot_time(bcm, 20);
429 }
430 #endif
431
432 /* FIXME: To get the MAC-filter working, we need to implement the
433 * following functions (and rename them :)
434 */
435 #if 0
436 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
437 {
438 bcm43xx_mac_suspend(bcm);
439 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
440
441 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
442 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
443 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
444 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
445 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
446 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
447
448 if (bcm->current_core->rev < 3) {
449 bcm43xx_write16(bcm, 0x0610, 0x8000);
450 bcm43xx_write16(bcm, 0x060E, 0x0000);
451 } else
452 bcm43xx_write32(bcm, 0x0188, 0x80000000);
453
454 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
455
456 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
457 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
458 bcm43xx_short_slot_timing_enable(bcm);
459
460 bcm43xx_mac_enable(bcm);
461 }
462
463 static void bcm43xx_associate(struct bcm43xx_private *bcm,
464 const u8 *mac)
465 {
466 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
467
468 bcm43xx_mac_suspend(bcm);
469 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
470 bcm43xx_write_mac_bssid_templates(bcm);
471 bcm43xx_mac_enable(bcm);
472 }
473 #endif
474
475 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
476 * Returns the _previously_ enabled IRQ mask.
477 */
478 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
479 {
480 u32 old_mask;
481
482 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
483 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
484
485 return old_mask;
486 }
487
488 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
489 * Returns the _previously_ enabled IRQ mask.
490 */
491 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
492 {
493 u32 old_mask;
494
495 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
496 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
497
498 return old_mask;
499 }
500
501 /* Synchronize IRQ top- and bottom-half.
502 * IRQs must be masked before calling this.
503 * This must not be called with the irq_lock held.
504 */
505 static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
506 {
507 synchronize_irq(bcm->irq);
508 tasklet_disable(&bcm->isr_tasklet);
509 }
510
511 /* Make sure we don't receive more data from the device. */
512 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
513 {
514 unsigned long flags;
515
516 spin_lock_irqsave(&bcm->irq_lock, flags);
517 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
518 spin_unlock_irqrestore(&bcm->irq_lock, flags);
519 return -EBUSY;
520 }
521 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
522 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
523 spin_unlock_irqrestore(&bcm->irq_lock, flags);
524 bcm43xx_synchronize_irq(bcm);
525
526 return 0;
527 }
528
529 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
530 {
531 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
532 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
533 u32 radio_id;
534 u16 manufact;
535 u16 version;
536 u8 revision;
537
538 if (bcm->chip_id == 0x4317) {
539 if (bcm->chip_rev == 0x00)
540 radio_id = 0x3205017F;
541 else if (bcm->chip_rev == 0x01)
542 radio_id = 0x4205017F;
543 else
544 radio_id = 0x5205017F;
545 } else {
546 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
547 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
548 radio_id <<= 16;
549 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
550 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
551 }
552
553 manufact = (radio_id & 0x00000FFF);
554 version = (radio_id & 0x0FFFF000) >> 12;
555 revision = (radio_id & 0xF0000000) >> 28;
556
557 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
558 radio_id, manufact, version, revision);
559
560 switch (phy->type) {
561 case BCM43xx_PHYTYPE_A:
562 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
563 goto err_unsupported_radio;
564 break;
565 case BCM43xx_PHYTYPE_B:
566 if ((version & 0xFFF0) != 0x2050)
567 goto err_unsupported_radio;
568 break;
569 case BCM43xx_PHYTYPE_G:
570 if (version != 0x2050)
571 goto err_unsupported_radio;
572 break;
573 }
574
575 radio->manufact = manufact;
576 radio->version = version;
577 radio->revision = revision;
578
579 if (phy->type == BCM43xx_PHYTYPE_A)
580 radio->txpower_desired = bcm->sprom.maxpower_aphy;
581 else
582 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
583
584 return 0;
585
586 err_unsupported_radio:
587 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
588 return -ENODEV;
589 }
590
591 static const char * bcm43xx_locale_iso(u8 locale)
592 {
593 /* ISO 3166-1 country codes.
594 * Note that there aren't ISO 3166-1 codes for
595 * all or locales. (Not all locales are countries)
596 */
597 switch (locale) {
598 case BCM43xx_LOCALE_WORLD:
599 case BCM43xx_LOCALE_ALL:
600 return "XX";
601 case BCM43xx_LOCALE_THAILAND:
602 return "TH";
603 case BCM43xx_LOCALE_ISRAEL:
604 return "IL";
605 case BCM43xx_LOCALE_JORDAN:
606 return "JO";
607 case BCM43xx_LOCALE_CHINA:
608 return "CN";
609 case BCM43xx_LOCALE_JAPAN:
610 case BCM43xx_LOCALE_JAPAN_HIGH:
611 return "JP";
612 case BCM43xx_LOCALE_USA_CANADA_ANZ:
613 case BCM43xx_LOCALE_USA_LOW:
614 return "US";
615 case BCM43xx_LOCALE_EUROPE:
616 return "EU";
617 case BCM43xx_LOCALE_NONE:
618 return " ";
619 }
620 assert(0);
621 return " ";
622 }
623
624 static const char * bcm43xx_locale_string(u8 locale)
625 {
626 switch (locale) {
627 case BCM43xx_LOCALE_WORLD:
628 return "World";
629 case BCM43xx_LOCALE_THAILAND:
630 return "Thailand";
631 case BCM43xx_LOCALE_ISRAEL:
632 return "Israel";
633 case BCM43xx_LOCALE_JORDAN:
634 return "Jordan";
635 case BCM43xx_LOCALE_CHINA:
636 return "China";
637 case BCM43xx_LOCALE_JAPAN:
638 return "Japan";
639 case BCM43xx_LOCALE_USA_CANADA_ANZ:
640 return "USA/Canada/ANZ";
641 case BCM43xx_LOCALE_EUROPE:
642 return "Europe";
643 case BCM43xx_LOCALE_USA_LOW:
644 return "USAlow";
645 case BCM43xx_LOCALE_JAPAN_HIGH:
646 return "JapanHigh";
647 case BCM43xx_LOCALE_ALL:
648 return "All";
649 case BCM43xx_LOCALE_NONE:
650 return "None";
651 }
652 assert(0);
653 return "";
654 }
655
656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
657 {
658 static const u8 t[] = {
659 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
660 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
661 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
662 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
663 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
664 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
665 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
666 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
667 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
668 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
669 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
670 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
671 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
672 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
673 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
674 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
675 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
676 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
677 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
678 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
679 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
680 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
681 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
682 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
683 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
684 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
685 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
686 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
687 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
688 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
689 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
690 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
691 };
692 return t[crc ^ data];
693 }
694
695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
696 {
697 int word;
698 u8 crc = 0xFF;
699
700 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
701 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
702 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
703 }
704 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
705 crc ^= 0xFF;
706
707 return crc;
708 }
709
710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
711 {
712 int i;
713 u8 crc, expected_crc;
714
715 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
716 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
717 /* CRC-8 check. */
718 crc = bcm43xx_sprom_crc(sprom);
719 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
720 if (crc != expected_crc) {
721 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
722 "(0x%02X, expected: 0x%02X)\n",
723 crc, expected_crc);
724 return -EINVAL;
725 }
726
727 return 0;
728 }
729
730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
731 {
732 int i, err;
733 u8 crc, expected_crc;
734 u32 spromctl;
735
736 /* CRC-8 validation of the input data. */
737 crc = bcm43xx_sprom_crc(sprom);
738 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
739 if (crc != expected_crc) {
740 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
741 return -EINVAL;
742 }
743
744 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
745 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
746 if (err)
747 goto err_ctlreg;
748 spromctl |= 0x10; /* SPROM WRITE enable. */
749 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
750 if (err)
751 goto err_ctlreg;
752 /* We must burn lots of CPU cycles here, but that does not
753 * really matter as one does not write the SPROM every other minute...
754 */
755 printk(KERN_INFO PFX "[ 0%%");
756 mdelay(500);
757 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
758 if (i == 16)
759 printk("25%%");
760 else if (i == 32)
761 printk("50%%");
762 else if (i == 48)
763 printk("75%%");
764 else if (i % 2)
765 printk(".");
766 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
767 mmiowb();
768 mdelay(20);
769 }
770 spromctl &= ~0x10; /* SPROM WRITE enable. */
771 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
772 if (err)
773 goto err_ctlreg;
774 mdelay(500);
775 printk("100%% ]\n");
776 printk(KERN_INFO PFX "SPROM written.\n");
777 bcm43xx_controller_restart(bcm, "SPROM update");
778
779 return 0;
780 err_ctlreg:
781 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
782 return -ENODEV;
783 }
784
785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
786 {
787 u16 value;
788 u16 *sprom;
789 #ifdef CONFIG_BCM947XX
790 char *c;
791 #endif
792
793 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
794 GFP_KERNEL);
795 if (!sprom) {
796 printk(KERN_ERR PFX "sprom_extract OOM\n");
797 return -ENOMEM;
798 }
799 #ifdef CONFIG_BCM947XX
800 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
801 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
802
803 if ((c = nvram_get("il0macaddr")) != NULL)
804 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
805
806 if ((c = nvram_get("et1macaddr")) != NULL)
807 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
808
809 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
810 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
811 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
812
813 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
814 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
815 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
816
817 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
818 #else
819 bcm43xx_sprom_read(bcm, sprom);
820 #endif
821
822 /* boardflags2 */
823 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
824 bcm->sprom.boardflags2 = value;
825
826 /* il0macaddr */
827 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
828 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
830 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
832 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
833
834 /* et0macaddr */
835 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
836 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
838 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
840 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
841
842 /* et1macaddr */
843 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
844 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
845 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
846 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
847 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
848 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
849
850 /* ethernet phy settings */
851 value = sprom[BCM43xx_SPROM_ETHPHY];
852 bcm->sprom.et0phyaddr = (value & 0x001F);
853 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
854
855 /* boardrev, antennas, locale */
856 value = sprom[BCM43xx_SPROM_BOARDREV];
857 bcm->sprom.boardrev = (value & 0x00FF);
858 bcm->sprom.locale = (value & 0x0F00) >> 8;
859 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
860 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
861 if (modparam_locale != -1) {
862 if (modparam_locale >= 0 && modparam_locale <= 11) {
863 bcm->sprom.locale = modparam_locale;
864 printk(KERN_WARNING PFX "Operating with modified "
865 "LocaleCode %u (%s)\n",
866 bcm->sprom.locale,
867 bcm43xx_locale_string(bcm->sprom.locale));
868 } else {
869 printk(KERN_WARNING PFX "Module parameter \"locale\" "
870 "invalid value. (0 - 11)\n");
871 }
872 }
873
874 /* pa0b* */
875 value = sprom[BCM43xx_SPROM_PA0B0];
876 bcm->sprom.pa0b0 = value;
877 value = sprom[BCM43xx_SPROM_PA0B1];
878 bcm->sprom.pa0b1 = value;
879 value = sprom[BCM43xx_SPROM_PA0B2];
880 bcm->sprom.pa0b2 = value;
881
882 /* wl0gpio* */
883 value = sprom[BCM43xx_SPROM_WL0GPIO0];
884 if (value == 0x0000)
885 value = 0xFFFF;
886 bcm->sprom.wl0gpio0 = value & 0x00FF;
887 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
888 value = sprom[BCM43xx_SPROM_WL0GPIO2];
889 if (value == 0x0000)
890 value = 0xFFFF;
891 bcm->sprom.wl0gpio2 = value & 0x00FF;
892 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
893
894 /* maxpower */
895 value = sprom[BCM43xx_SPROM_MAXPWR];
896 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
897 bcm->sprom.maxpower_bgphy = value & 0x00FF;
898
899 /* pa1b* */
900 value = sprom[BCM43xx_SPROM_PA1B0];
901 bcm->sprom.pa1b0 = value;
902 value = sprom[BCM43xx_SPROM_PA1B1];
903 bcm->sprom.pa1b1 = value;
904 value = sprom[BCM43xx_SPROM_PA1B2];
905 bcm->sprom.pa1b2 = value;
906
907 /* idle tssi target */
908 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
909 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
910 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
911
912 /* boardflags */
913 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
914 if (value == 0xFFFF)
915 value = 0x0000;
916 bcm->sprom.boardflags = value;
917 /* boardflags workarounds */
918 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
919 bcm->chip_id == 0x4301 &&
920 bcm->board_revision == 0x74)
921 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
922 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
923 bcm->board_type == 0x4E &&
924 bcm->board_revision > 0x40)
925 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
926
927 /* antenna gain */
928 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
929 if (value == 0x0000 || value == 0xFFFF)
930 value = 0x0202;
931 /* convert values to Q5.2 */
932 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
933 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
934
935 kfree(sprom);
936
937 return 0;
938 }
939
940 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
941 {
942 struct ieee80211_geo *geo;
943 struct ieee80211_channel *chan;
944 int have_a = 0, have_bg = 0;
945 int i;
946 u8 channel;
947 struct bcm43xx_phyinfo *phy;
948 const char *iso_country;
949 u8 max_bg_channel;
950
951 geo = kzalloc(sizeof(*geo), GFP_KERNEL);
952 if (!geo)
953 return -ENOMEM;
954
955 for (i = 0; i < bcm->nr_80211_available; i++) {
956 phy = &(bcm->core_80211_ext[i].phy);
957 switch (phy->type) {
958 case BCM43xx_PHYTYPE_B:
959 case BCM43xx_PHYTYPE_G:
960 have_bg = 1;
961 break;
962 case BCM43xx_PHYTYPE_A:
963 have_a = 1;
964 break;
965 default:
966 assert(0);
967 }
968 }
969 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
970
971 /* set the maximum channel based on locale set in sprom or witle locale option */
972 switch (bcm->sprom.locale) {
973 case BCM43xx_LOCALE_THAILAND:
974 case BCM43xx_LOCALE_ISRAEL:
975 case BCM43xx_LOCALE_JORDAN:
976 case BCM43xx_LOCALE_USA_CANADA_ANZ:
977 case BCM43xx_LOCALE_USA_LOW:
978 max_bg_channel = 11;
979 break;
980 case BCM43xx_LOCALE_JAPAN:
981 case BCM43xx_LOCALE_JAPAN_HIGH:
982 max_bg_channel = 14;
983 break;
984 default:
985 max_bg_channel = 13;
986 }
987
988 if (have_a) {
989 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
990 channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
991 chan = &geo->a[i++];
992 chan->freq = bcm43xx_channel_to_freq_a(channel);
993 chan->channel = channel;
994 }
995 geo->a_channels = i;
996 }
997 if (have_bg) {
998 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
999 channel <= max_bg_channel; channel++) {
1000 chan = &geo->bg[i++];
1001 chan->freq = bcm43xx_channel_to_freq_bg(channel);
1002 chan->channel = channel;
1003 }
1004 geo->bg_channels = i;
1005 }
1006 memcpy(geo->name, iso_country, 2);
1007 if (0 /*TODO: Outdoor use only */)
1008 geo->name[2] = 'O';
1009 else if (0 /*TODO: Indoor use only */)
1010 geo->name[2] = 'I';
1011 else
1012 geo->name[2] = ' ';
1013 geo->name[3] = '\0';
1014
1015 ieee80211_set_geo(bcm->ieee, geo);
1016 kfree(geo);
1017
1018 return 0;
1019 }
1020
1021 /* DummyTransmission function, as documented on
1022 * http://bcm-specs.sipsolutions.net/DummyTransmission
1023 */
1024 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1025 {
1026 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1027 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1028 unsigned int i, max_loop;
1029 u16 value = 0;
1030 u32 buffer[5] = {
1031 0x00000000,
1032 0x0000D400,
1033 0x00000000,
1034 0x00000001,
1035 0x00000000,
1036 };
1037
1038 switch (phy->type) {
1039 case BCM43xx_PHYTYPE_A:
1040 max_loop = 0x1E;
1041 buffer[0] = 0xCC010200;
1042 break;
1043 case BCM43xx_PHYTYPE_B:
1044 case BCM43xx_PHYTYPE_G:
1045 max_loop = 0xFA;
1046 buffer[0] = 0x6E840B00;
1047 break;
1048 default:
1049 assert(0);
1050 return;
1051 }
1052
1053 for (i = 0; i < 5; i++)
1054 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1055
1056 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1057
1058 bcm43xx_write16(bcm, 0x0568, 0x0000);
1059 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1060 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1061 bcm43xx_write16(bcm, 0x0508, 0x0000);
1062 bcm43xx_write16(bcm, 0x050A, 0x0000);
1063 bcm43xx_write16(bcm, 0x054C, 0x0000);
1064 bcm43xx_write16(bcm, 0x056A, 0x0014);
1065 bcm43xx_write16(bcm, 0x0568, 0x0826);
1066 bcm43xx_write16(bcm, 0x0500, 0x0000);
1067 bcm43xx_write16(bcm, 0x0502, 0x0030);
1068
1069 if (radio->version == 0x2050 && radio->revision <= 0x5)
1070 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1071 for (i = 0x00; i < max_loop; i++) {
1072 value = bcm43xx_read16(bcm, 0x050E);
1073 if (value & 0x0080)
1074 break;
1075 udelay(10);
1076 }
1077 for (i = 0x00; i < 0x0A; i++) {
1078 value = bcm43xx_read16(bcm, 0x050E);
1079 if (value & 0x0400)
1080 break;
1081 udelay(10);
1082 }
1083 for (i = 0x00; i < 0x0A; i++) {
1084 value = bcm43xx_read16(bcm, 0x0690);
1085 if (!(value & 0x0100))
1086 break;
1087 udelay(10);
1088 }
1089 if (radio->version == 0x2050 && radio->revision <= 0x5)
1090 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1091 }
1092
1093 static void key_write(struct bcm43xx_private *bcm,
1094 u8 index, u8 algorithm, const u16 *key)
1095 {
1096 unsigned int i, basic_wep = 0;
1097 u32 offset;
1098 u16 value;
1099
1100 /* Write associated key information */
1101 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1102 ((index << 4) | (algorithm & 0x0F)));
1103
1104 /* The first 4 WEP keys need extra love */
1105 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1106 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1107 basic_wep = 1;
1108
1109 /* Write key payload, 8 little endian words */
1110 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1111 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1112 value = cpu_to_le16(key[i]);
1113 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1114 offset + (i * 2), value);
1115
1116 if (!basic_wep)
1117 continue;
1118
1119 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1120 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1121 value);
1122 }
1123 }
1124
1125 static void keymac_write(struct bcm43xx_private *bcm,
1126 u8 index, const u32 *addr)
1127 {
1128 /* for keys 0-3 there is no associated mac address */
1129 if (index < 4)
1130 return;
1131
1132 index -= 4;
1133 if (bcm->current_core->rev >= 5) {
1134 bcm43xx_shm_write32(bcm,
1135 BCM43xx_SHM_HWMAC,
1136 index * 2,
1137 cpu_to_be32(*addr));
1138 bcm43xx_shm_write16(bcm,
1139 BCM43xx_SHM_HWMAC,
1140 (index * 2) + 1,
1141 cpu_to_be16(*((u16 *)(addr + 1))));
1142 } else {
1143 if (index < 8) {
1144 TODO(); /* Put them in the macaddress filter */
1145 } else {
1146 TODO();
1147 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1148 Keep in mind to update the count of keymacs in 0x003E as well! */
1149 }
1150 }
1151 }
1152
1153 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1154 u8 index, u8 algorithm,
1155 const u8 *_key, int key_len,
1156 const u8 *mac_addr)
1157 {
1158 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1159
1160 if (index >= ARRAY_SIZE(bcm->key))
1161 return -EINVAL;
1162 if (key_len > ARRAY_SIZE(key))
1163 return -EINVAL;
1164 if (algorithm < 1 || algorithm > 5)
1165 return -EINVAL;
1166
1167 memcpy(key, _key, key_len);
1168 key_write(bcm, index, algorithm, (const u16 *)key);
1169 keymac_write(bcm, index, (const u32 *)mac_addr);
1170
1171 bcm->key[index].algorithm = algorithm;
1172
1173 return 0;
1174 }
1175
1176 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1177 {
1178 static const u32 zero_mac[2] = { 0 };
1179 unsigned int i,j, nr_keys = 54;
1180 u16 offset;
1181
1182 if (bcm->current_core->rev < 5)
1183 nr_keys = 16;
1184 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1185
1186 for (i = 0; i < nr_keys; i++) {
1187 bcm->key[i].enabled = 0;
1188 /* returns for i < 4 immediately */
1189 keymac_write(bcm, i, zero_mac);
1190 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1191 0x100 + (i * 2), 0x0000);
1192 for (j = 0; j < 8; j++) {
1193 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1194 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1195 offset, 0x0000);
1196 }
1197 }
1198 dprintk(KERN_INFO PFX "Keys cleared\n");
1199 }
1200
1201 /* Lowlevel core-switch function. This is only to be used in
1202 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1203 */
1204 static int _switch_core(struct bcm43xx_private *bcm, int core)
1205 {
1206 int err;
1207 int attempts = 0;
1208 u32 current_core;
1209
1210 assert(core >= 0);
1211 while (1) {
1212 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1213 (core * 0x1000) + 0x18000000);
1214 if (unlikely(err))
1215 goto error;
1216 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1217 &current_core);
1218 if (unlikely(err))
1219 goto error;
1220 current_core = (current_core - 0x18000000) / 0x1000;
1221 if (current_core == core)
1222 break;
1223
1224 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1225 goto error;
1226 udelay(10);
1227 }
1228 #ifdef CONFIG_BCM947XX
1229 if (bcm->pci_dev->bus->number == 0)
1230 bcm->current_core_offset = 0x1000 * core;
1231 else
1232 bcm->current_core_offset = 0;
1233 #endif
1234
1235 return 0;
1236 error:
1237 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1238 return -ENODEV;
1239 }
1240
1241 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1242 {
1243 int err;
1244
1245 if (unlikely(!new_core))
1246 return 0;
1247 if (!new_core->available)
1248 return -ENODEV;
1249 if (bcm->current_core == new_core)
1250 return 0;
1251 err = _switch_core(bcm, new_core->index);
1252 if (unlikely(err))
1253 goto out;
1254
1255 bcm->current_core = new_core;
1256 out:
1257 return err;
1258 }
1259
1260 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1261 {
1262 u32 value;
1263
1264 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1265 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1266 | BCM43xx_SBTMSTATELOW_REJECT;
1267
1268 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1269 }
1270
1271 /* disable current core */
1272 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1273 {
1274 u32 sbtmstatelow;
1275 u32 sbtmstatehigh;
1276 int i;
1277
1278 /* fetch sbtmstatelow from core information registers */
1279 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1280
1281 /* core is already in reset */
1282 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1283 goto out;
1284
1285 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1286 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1287 BCM43xx_SBTMSTATELOW_REJECT;
1288 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1289
1290 for (i = 0; i < 1000; i++) {
1291 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1292 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1293 i = -1;
1294 break;
1295 }
1296 udelay(10);
1297 }
1298 if (i != -1) {
1299 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1300 return -EBUSY;
1301 }
1302
1303 for (i = 0; i < 1000; i++) {
1304 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1305 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1306 i = -1;
1307 break;
1308 }
1309 udelay(10);
1310 }
1311 if (i != -1) {
1312 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1313 return -EBUSY;
1314 }
1315
1316 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1317 BCM43xx_SBTMSTATELOW_REJECT |
1318 BCM43xx_SBTMSTATELOW_RESET |
1319 BCM43xx_SBTMSTATELOW_CLOCK |
1320 core_flags;
1321 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1322 udelay(10);
1323 }
1324
1325 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1326 BCM43xx_SBTMSTATELOW_REJECT |
1327 core_flags;
1328 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1329
1330 out:
1331 bcm->current_core->enabled = 0;
1332
1333 return 0;
1334 }
1335
1336 /* enable (reset) current core */
1337 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1338 {
1339 u32 sbtmstatelow;
1340 u32 sbtmstatehigh;
1341 u32 sbimstate;
1342 int err;
1343
1344 err = bcm43xx_core_disable(bcm, core_flags);
1345 if (err)
1346 goto out;
1347
1348 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1349 BCM43xx_SBTMSTATELOW_RESET |
1350 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1351 core_flags;
1352 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1353 udelay(1);
1354
1355 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1356 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1357 sbtmstatehigh = 0x00000000;
1358 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1359 }
1360
1361 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1362 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1363 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1364 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1365 }
1366
1367 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1368 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1369 core_flags;
1370 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1371 udelay(1);
1372
1373 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1374 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1375 udelay(1);
1376
1377 bcm->current_core->enabled = 1;
1378 assert(err == 0);
1379 out:
1380 return err;
1381 }
1382
1383 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1384 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1385 {
1386 u32 flags = 0x00040000;
1387
1388 if ((bcm43xx_core_enabled(bcm)) &&
1389 !bcm43xx_using_pio(bcm)) {
1390 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1391 #if 0
1392 #ifndef CONFIG_BCM947XX
1393 /* reset all used DMA controllers. */
1394 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1395 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1396 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1397 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1398 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1399 if (bcm->current_core->rev < 5)
1400 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1401 #endif
1402 #endif
1403 }
1404 if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
1405 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1406 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1407 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1408 } else {
1409 if (connect_phy)
1410 flags |= BCM43xx_SBTMSTATELOW_G_MODE_ENABLE;
1411 bcm43xx_phy_connect(bcm, connect_phy);
1412 bcm43xx_core_enable(bcm, flags);
1413 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1414 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1415 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1416 | BCM43xx_SBF_400);
1417 }
1418 }
1419
1420 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1421 {
1422 bcm43xx_radio_turn_off(bcm);
1423 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1424 bcm43xx_core_disable(bcm, 0);
1425 }
1426
1427 /* Mark the current 80211 core inactive. */
1428 static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
1429 {
1430 u32 sbtmstatelow;
1431
1432 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1433 bcm43xx_radio_turn_off(bcm);
1434 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1435 sbtmstatelow &= 0xDFF5FFFF;
1436 sbtmstatelow |= 0x000A0000;
1437 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1438 udelay(1);
1439 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1440 sbtmstatelow &= 0xFFF5FFFF;
1441 sbtmstatelow |= 0x00080000;
1442 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1443 udelay(1);
1444 }
1445
1446 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1447 {
1448 u32 v0, v1;
1449 u16 tmp;
1450 struct bcm43xx_xmitstatus stat;
1451
1452 while (1) {
1453 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1454 if (!v0)
1455 break;
1456 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1457
1458 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1459 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1460 stat.flags = tmp & 0xFF;
1461 stat.cnt1 = (tmp & 0x0F00) >> 8;
1462 stat.cnt2 = (tmp & 0xF000) >> 12;
1463 stat.seq = (u16)(v1 & 0xFFFF);
1464 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1465
1466 bcm43xx_debugfs_log_txstat(bcm, &stat);
1467
1468 if (stat.flags & BCM43xx_TXSTAT_FLAG_AMPDU)
1469 continue;
1470 if (stat.flags & BCM43xx_TXSTAT_FLAG_INTER)
1471 continue;
1472
1473 if (bcm43xx_using_pio(bcm))
1474 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1475 else
1476 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1477 }
1478 }
1479
1480 static void drain_txstatus_queue(struct bcm43xx_private *bcm)
1481 {
1482 u32 dummy;
1483
1484 if (bcm->current_core->rev < 5)
1485 return;
1486 /* Read all entries from the microcode TXstatus FIFO
1487 * and throw them away.
1488 */
1489 while (1) {
1490 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1491 if (!dummy)
1492 break;
1493 dummy = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1494 }
1495 }
1496
1497 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1498 {
1499 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1500 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1501 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1502 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1503 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1504 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1505 }
1506
1507 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1508 {
1509 /* Top half of Link Quality calculation. */
1510
1511 if (bcm->noisecalc.calculation_running)
1512 return;
1513 bcm->noisecalc.core_at_start = bcm->current_core;
1514 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1515 bcm->noisecalc.calculation_running = 1;
1516 bcm->noisecalc.nr_samples = 0;
1517
1518 bcm43xx_generate_noise_sample(bcm);
1519 }
1520
1521 static void handle_irq_noise(struct bcm43xx_private *bcm)
1522 {
1523 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1524 u16 tmp;
1525 u8 noise[4];
1526 u8 i, j;
1527 s32 average;
1528
1529 /* Bottom half of Link Quality calculation. */
1530
1531 assert(bcm->noisecalc.calculation_running);
1532 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1533 bcm->noisecalc.channel_at_start != radio->channel)
1534 goto drop_calculation;
1535 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1536 noise[0] = (tmp & 0x00FF);
1537 noise[1] = (tmp & 0xFF00) >> 8;
1538 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1539 noise[2] = (tmp & 0x00FF);
1540 noise[3] = (tmp & 0xFF00) >> 8;
1541 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1542 noise[2] == 0x7F || noise[3] == 0x7F)
1543 goto generate_new;
1544
1545 /* Get the noise samples. */
1546 assert(bcm->noisecalc.nr_samples < 8);
1547 i = bcm->noisecalc.nr_samples;
1548 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1549 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1550 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1551 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1552 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1553 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1554 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1555 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1556 bcm->noisecalc.nr_samples++;
1557 if (bcm->noisecalc.nr_samples == 8) {
1558 /* Calculate the Link Quality by the noise samples. */
1559 average = 0;
1560 for (i = 0; i < 8; i++) {
1561 for (j = 0; j < 4; j++)
1562 average += bcm->noisecalc.samples[i][j];
1563 }
1564 average /= (8 * 4);
1565 average *= 125;
1566 average += 64;
1567 average /= 128;
1568
1569 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1570 tmp = (tmp / 128) & 0x1F;
1571 if (tmp >= 8)
1572 average += 2;
1573 else
1574 average -= 25;
1575 if (tmp == 8)
1576 average -= 72;
1577 else
1578 average -= 48;
1579
1580 bcm->stats.noise = average;
1581 drop_calculation:
1582 bcm->noisecalc.calculation_running = 0;
1583 return;
1584 }
1585 generate_new:
1586 bcm43xx_generate_noise_sample(bcm);
1587 }
1588
1589 static void handle_irq_ps(struct bcm43xx_private *bcm)
1590 {
1591 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1592 ///TODO: PS TBTT
1593 } else {
1594 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1595 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1596 }
1597 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1598 bcm->reg124_set_0x4 = 1;
1599 //FIXME else set to false?
1600 }
1601
1602 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1603 {
1604 if (!bcm->reg124_set_0x4)
1605 return;
1606 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1607 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1608 | 0x4);
1609 //FIXME: reset reg124_set_0x4 to false?
1610 }
1611
1612 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1613 {
1614 u32 tmp;
1615
1616 //TODO: AP mode.
1617
1618 while (1) {
1619 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1620 if (!(tmp & 0x00000008))
1621 break;
1622 }
1623 /* 16bit write is odd, but correct. */
1624 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1625 }
1626
1627 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1628 u16 ram_offset, u16 shm_size_offset)
1629 {
1630 u32 value;
1631 u16 size = 0;
1632
1633 /* Timestamp. */
1634 //FIXME: assumption: The chip sets the timestamp
1635 value = 0;
1636 bcm43xx_ram_write(bcm, ram_offset++, value);
1637 bcm43xx_ram_write(bcm, ram_offset++, value);
1638 size += 8;
1639
1640 /* Beacon Interval / Capability Information */
1641 value = 0x0000;//FIXME: Which interval?
1642 value |= (1 << 0) << 16; /* ESS */
1643 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1644 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1645 if (!bcm->ieee->open_wep)
1646 value |= (1 << 4) << 16; /* Privacy */
1647 bcm43xx_ram_write(bcm, ram_offset++, value);
1648 size += 4;
1649
1650 /* SSID */
1651 //TODO
1652
1653 /* FH Parameter Set */
1654 //TODO
1655
1656 /* DS Parameter Set */
1657 //TODO
1658
1659 /* CF Parameter Set */
1660 //TODO
1661
1662 /* TIM */
1663 //TODO
1664
1665 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1666 }
1667
1668 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1669 {
1670 u32 status;
1671
1672 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1673 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1674
1675 if ((status & 0x1) && (status & 0x2)) {
1676 /* ACK beacon IRQ. */
1677 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1678 BCM43xx_IRQ_BEACON);
1679 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1680 return;
1681 }
1682 if (!(status & 0x1)) {
1683 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1684 status |= 0x1;
1685 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1686 }
1687 if (!(status & 0x2)) {
1688 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1689 status |= 0x2;
1690 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1691 }
1692 }
1693
1694 /* Interrupt handler bottom-half */
1695 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1696 {
1697 u32 reason;
1698 u32 dma_reason[6];
1699 u32 merged_dma_reason = 0;
1700 int i, activity = 0;
1701 unsigned long flags;
1702
1703 #ifdef CONFIG_BCM43XX_DEBUG
1704 u32 _handled = 0x00000000;
1705 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1706 #else
1707 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1708 #endif /* CONFIG_BCM43XX_DEBUG*/
1709
1710 spin_lock_irqsave(&bcm->irq_lock, flags);
1711 reason = bcm->irq_reason;
1712 for (i = 5; i >= 0; i--) {
1713 dma_reason[i] = bcm->dma_reason[i];
1714 merged_dma_reason |= dma_reason[i];
1715 }
1716
1717 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1718 /* TX error. We get this when Template Ram is written in wrong endianess
1719 * in dummy_tx(). We also get this if something is wrong with the TX header
1720 * on DMA or PIO queues.
1721 * Maybe we get this in other error conditions, too.
1722 */
1723 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1724 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1725 }
1726 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
1727 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1728 "0x%08X, 0x%08X, 0x%08X, "
1729 "0x%08X, 0x%08X, 0x%08X\n",
1730 dma_reason[0], dma_reason[1],
1731 dma_reason[2], dma_reason[3],
1732 dma_reason[4], dma_reason[5]);
1733 bcm43xx_controller_restart(bcm, "DMA error");
1734 mmiowb();
1735 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1736 return;
1737 }
1738 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
1739 printkl(KERN_ERR PFX "DMA error: "
1740 "0x%08X, 0x%08X, 0x%08X, "
1741 "0x%08X, 0x%08X, 0x%08X\n",
1742 dma_reason[0], dma_reason[1],
1743 dma_reason[2], dma_reason[3],
1744 dma_reason[4], dma_reason[5]);
1745 }
1746
1747 if (reason & BCM43xx_IRQ_PS) {
1748 handle_irq_ps(bcm);
1749 bcmirq_handled(BCM43xx_IRQ_PS);
1750 }
1751
1752 if (reason & BCM43xx_IRQ_REG124) {
1753 handle_irq_reg124(bcm);
1754 bcmirq_handled(BCM43xx_IRQ_REG124);
1755 }
1756
1757 if (reason & BCM43xx_IRQ_BEACON) {
1758 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1759 handle_irq_beacon(bcm);
1760 bcmirq_handled(BCM43xx_IRQ_BEACON);
1761 }
1762
1763 if (reason & BCM43xx_IRQ_PMQ) {
1764 handle_irq_pmq(bcm);
1765 bcmirq_handled(BCM43xx_IRQ_PMQ);
1766 }
1767
1768 if (reason & BCM43xx_IRQ_SCAN) {
1769 /*TODO*/
1770 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1771 }
1772
1773 if (reason & BCM43xx_IRQ_NOISE) {
1774 handle_irq_noise(bcm);
1775 bcmirq_handled(BCM43xx_IRQ_NOISE);
1776 }
1777
1778 /* Check the DMA reason registers for received data. */
1779 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1780 if (bcm43xx_using_pio(bcm))
1781 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1782 else
1783 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1784 /* We intentionally don't set "activity" to 1, here. */
1785 }
1786 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1787 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1788 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1789 if (bcm43xx_using_pio(bcm))
1790 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1791 else
1792 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
1793 activity = 1;
1794 }
1795 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1796 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1797 bcmirq_handled(BCM43xx_IRQ_RX);
1798
1799 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1800 handle_irq_transmit_status(bcm);
1801 activity = 1;
1802 //TODO: In AP mode, this also causes sending of powersave responses.
1803 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1804 }
1805
1806 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1807 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1808 #ifdef CONFIG_BCM43XX_DEBUG
1809 if (unlikely(reason & ~_handled)) {
1810 printkl(KERN_WARNING PFX
1811 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1812 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1813 reason, (reason & ~_handled),
1814 dma_reason[0], dma_reason[1],
1815 dma_reason[2], dma_reason[3]);
1816 }
1817 #endif
1818 #undef bcmirq_handled
1819
1820 if (!modparam_noleds)
1821 bcm43xx_leds_update(bcm, activity);
1822 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1823 mmiowb();
1824 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1825 }
1826
1827 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1828 u16 base, int queueidx)
1829 {
1830 u16 rxctl;
1831
1832 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1833 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1834 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1835 else
1836 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1837 }
1838
1839 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1840 {
1841 if (bcm43xx_using_pio(bcm) &&
1842 (bcm->current_core->rev < 3) &&
1843 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1844 /* Apply a PIO specific workaround to the dma_reasons */
1845 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1846 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1847 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1848 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1849 }
1850
1851 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1852
1853 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
1854 bcm->dma_reason[0]);
1855 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1856 bcm->dma_reason[1]);
1857 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1858 bcm->dma_reason[2]);
1859 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1860 bcm->dma_reason[3]);
1861 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1862 bcm->dma_reason[4]);
1863 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1864 bcm->dma_reason[5]);
1865 }
1866
1867 /* Interrupt handler top-half */
1868 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
1869 {
1870 irqreturn_t ret = IRQ_HANDLED;
1871 struct bcm43xx_private *bcm = dev_id;
1872 u32 reason;
1873
1874 if (!bcm)
1875 return IRQ_NONE;
1876
1877 spin_lock(&bcm->irq_lock);
1878
1879 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1880 if (reason == 0xffffffff) {
1881 /* irq not for us (shared irq) */
1882 ret = IRQ_NONE;
1883 goto out;
1884 }
1885 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1886 if (!reason)
1887 goto out;
1888
1889 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1890 assert(bcm->current_core->id == BCM43xx_COREID_80211);
1891
1892 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1893 & 0x0001DC00;
1894 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1895 & 0x0000DC00;
1896 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1897 & 0x0000DC00;
1898 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1899 & 0x0001DC00;
1900 bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1901 & 0x0000DC00;
1902 bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1903 & 0x0000DC00;
1904
1905 bcm43xx_interrupt_ack(bcm, reason);
1906
1907 /* disable all IRQs. They are enabled again in the bottom half. */
1908 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1909 /* save the reason code and call our bottom half. */
1910 bcm->irq_reason = reason;
1911 tasklet_schedule(&bcm->isr_tasklet);
1912
1913 out:
1914 mmiowb();
1915 spin_unlock(&bcm->irq_lock);
1916
1917 return ret;
1918 }
1919
1920 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1921 {
1922 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1923
1924 if (bcm->firmware_norelease && !force)
1925 return; /* Suspending or controller reset. */
1926 release_firmware(phy->ucode);
1927 phy->ucode = NULL;
1928 release_firmware(phy->pcm);
1929 phy->pcm = NULL;
1930 release_firmware(phy->initvals0);
1931 phy->initvals0 = NULL;
1932 release_firmware(phy->initvals1);
1933 phy->initvals1 = NULL;
1934 }
1935
1936 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1937 {
1938 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1939 u8 rev = bcm->current_core->rev;
1940 int err = 0;
1941 int nr;
1942 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1943
1944 if (!phy->ucode) {
1945 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1946 (rev >= 5 ? 5 : rev),
1947 modparam_fwpostfix);
1948 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
1949 if (err) {
1950 printk(KERN_ERR PFX
1951 "Error: Microcode \"%s\" not available or load failed.\n",
1952 buf);
1953 goto error;
1954 }
1955 }
1956
1957 if (!phy->pcm) {
1958 snprintf(buf, ARRAY_SIZE(buf),
1959 "bcm43xx_pcm%d%s.fw",
1960 (rev < 5 ? 4 : 5),
1961 modparam_fwpostfix);
1962 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
1963 if (err) {
1964 printk(KERN_ERR PFX
1965 "Error: PCM \"%s\" not available or load failed.\n",
1966 buf);
1967 goto error;
1968 }
1969 }
1970
1971 if (!phy->initvals0) {
1972 if (rev == 2 || rev == 4) {
1973 switch (phy->type) {
1974 case BCM43xx_PHYTYPE_A:
1975 nr = 3;
1976 break;
1977 case BCM43xx_PHYTYPE_B:
1978 case BCM43xx_PHYTYPE_G:
1979 nr = 1;
1980 break;
1981 default:
1982 goto err_noinitval;
1983 }
1984
1985 } else if (rev >= 5) {
1986 switch (phy->type) {
1987 case BCM43xx_PHYTYPE_A:
1988 nr = 7;
1989 break;
1990 case BCM43xx_PHYTYPE_B:
1991 case BCM43xx_PHYTYPE_G:
1992 nr = 5;
1993 break;
1994 default:
1995 goto err_noinitval;
1996 }
1997 } else
1998 goto err_noinitval;
1999 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2000 nr, modparam_fwpostfix);
2001
2002 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
2003 if (err) {
2004 printk(KERN_ERR PFX
2005 "Error: InitVals \"%s\" not available or load failed.\n",
2006 buf);
2007 goto error;
2008 }
2009 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
2010 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2011 goto error;
2012 }
2013 }
2014
2015 if (!phy->initvals1) {
2016 if (rev >= 5) {
2017 u32 sbtmstatehigh;
2018
2019 switch (phy->type) {
2020 case BCM43xx_PHYTYPE_A:
2021 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2022 if (sbtmstatehigh & 0x00010000)
2023 nr = 9;
2024 else
2025 nr = 10;
2026 break;
2027 case BCM43xx_PHYTYPE_B:
2028 case BCM43xx_PHYTYPE_G:
2029 nr = 6;
2030 break;
2031 default:
2032 goto err_noinitval;
2033 }
2034 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2035 nr, modparam_fwpostfix);
2036
2037 err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
2038 if (err) {
2039 printk(KERN_ERR PFX
2040 "Error: InitVals \"%s\" not available or load failed.\n",
2041 buf);
2042 goto error;
2043 }
2044 if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
2045 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2046 goto error;
2047 }
2048 }
2049 }
2050
2051 out:
2052 return err;
2053 error:
2054 bcm43xx_release_firmware(bcm, 1);
2055 goto out;
2056 err_noinitval:
2057 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2058 err = -ENOENT;
2059 goto error;
2060 }
2061
2062 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2063 {
2064 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2065 const u32 *data;
2066 unsigned int i, len;
2067
2068 /* Upload Microcode. */
2069 data = (u32 *)(phy->ucode->data);
2070 len = phy->ucode->size / sizeof(u32);
2071 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2072 for (i = 0; i < len; i++) {
2073 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2074 be32_to_cpu(data[i]));
2075 udelay(10);
2076 }
2077
2078 /* Upload PCM data. */
2079 data = (u32 *)(phy->pcm->data);
2080 len = phy->pcm->size / sizeof(u32);
2081 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2082 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2083 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2084 for (i = 0; i < len; i++) {
2085 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2086 be32_to_cpu(data[i]));
2087 udelay(10);
2088 }
2089 }
2090
2091 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2092 const struct bcm43xx_initval *data,
2093 const unsigned int len)
2094 {
2095 u16 offset, size;
2096 u32 value;
2097 unsigned int i;
2098
2099 for (i = 0; i < len; i++) {
2100 offset = be16_to_cpu(data[i].offset);
2101 size = be16_to_cpu(data[i].size);
2102 value = be32_to_cpu(data[i].value);
2103
2104 if (unlikely(offset >= 0x1000))
2105 goto err_format;
2106 if (size == 2) {
2107 if (unlikely(value & 0xFFFF0000))
2108 goto err_format;
2109 bcm43xx_write16(bcm, offset, (u16)value);
2110 } else if (size == 4) {
2111 bcm43xx_write32(bcm, offset, value);
2112 } else
2113 goto err_format;
2114 }
2115
2116 return 0;
2117
2118 err_format:
2119 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2120 "Please fix your bcm43xx firmware files.\n");
2121 return -EPROTO;
2122 }
2123
2124 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2125 {
2126 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2127 int err;
2128
2129 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2130 phy->initvals0->size / sizeof(struct bcm43xx_initval));
2131 if (err)
2132 goto out;
2133 if (phy->initvals1) {
2134 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2135 phy->initvals1->size / sizeof(struct bcm43xx_initval));
2136 if (err)
2137 goto out;
2138 }
2139 out:
2140 return err;
2141 }
2142
2143 #ifdef CONFIG_BCM947XX
2144 static struct pci_device_id bcm43xx_47xx_ids[] = {
2145 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2146 { 0 }
2147 };
2148 #endif
2149
2150 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2151 {
2152 int err;
2153
2154 bcm->irq = bcm->pci_dev->irq;
2155 #ifdef CONFIG_BCM947XX
2156 if (bcm->pci_dev->bus->number == 0) {
2157 struct pci_dev *d;
2158 struct pci_device_id *id;
2159 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2160 d = pci_get_device(id->vendor, id->device, NULL);
2161 if (d != NULL) {
2162 bcm->irq = d->irq;
2163 pci_dev_put(d);
2164 break;
2165 }
2166 }
2167 }
2168 #endif
2169 err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2170 IRQF_SHARED, KBUILD_MODNAME, bcm);
2171 if (err)
2172 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2173
2174 return err;
2175 }
2176
2177 /* Switch to the core used to write the GPIO register.
2178 * This is either the ChipCommon, or the PCI core.
2179 */
2180 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2181 {
2182 int err;
2183
2184 /* Where to find the GPIO register depends on the chipset.
2185 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2186 * control register. Otherwise the register at offset 0x6c in the
2187 * PCI core is the GPIO control register.
2188 */
2189 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2190 if (err == -ENODEV) {
2191 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2192 if (unlikely(err == -ENODEV)) {
2193 printk(KERN_ERR PFX "gpio error: "
2194 "Neither ChipCommon nor PCI core available!\n");
2195 }
2196 }
2197
2198 return err;
2199 }
2200
2201 /* Initialize the GPIOs
2202 * http://bcm-specs.sipsolutions.net/GPIO
2203 */
2204 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2205 {
2206 struct bcm43xx_coreinfo *old_core;
2207 int err;
2208 u32 mask, set;
2209
2210 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2211 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2212 & 0xFFFF3FFF);
2213
2214 bcm43xx_leds_switch_all(bcm, 0);
2215 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2216 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2217
2218 mask = 0x0000001F;
2219 set = 0x0000000F;
2220 if (bcm->chip_id == 0x4301) {
2221 mask |= 0x0060;
2222 set |= 0x0060;
2223 }
2224 if (0 /* FIXME: conditional unknown */) {
2225 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2226 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2227 | 0x0100);
2228 mask |= 0x0180;
2229 set |= 0x0180;
2230 }
2231 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2232 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2233 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2234 | 0x0200);
2235 mask |= 0x0200;
2236 set |= 0x0200;
2237 }
2238 if (bcm->current_core->rev >= 2)
2239 mask |= 0x0010; /* FIXME: This is redundant. */
2240
2241 old_core = bcm->current_core;
2242 err = switch_to_gpio_core(bcm);
2243 if (err)
2244 goto out;
2245 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2246 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2247 err = bcm43xx_switch_core(bcm, old_core);
2248 out:
2249 return err;
2250 }
2251
2252 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2253 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2254 {
2255 struct bcm43xx_coreinfo *old_core;
2256 int err;
2257
2258 old_core = bcm->current_core;
2259 err = switch_to_gpio_core(bcm);
2260 if (err)
2261 return err;
2262 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2263 err = bcm43xx_switch_core(bcm, old_core);
2264 assert(err == 0);
2265
2266 return 0;
2267 }
2268
2269 /* http://bcm-specs.sipsolutions.net/EnableMac */
2270 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2271 {
2272 bcm->mac_suspended--;
2273 assert(bcm->mac_suspended >= 0);
2274 if (bcm->mac_suspended == 0) {
2275 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2276 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2277 | BCM43xx_SBF_MAC_ENABLED);
2278 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2279 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2280 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2281 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2282 }
2283 }
2284
2285 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2286 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2287 {
2288 int i;
2289 u32 tmp;
2290
2291 assert(bcm->mac_suspended >= 0);
2292 if (bcm->mac_suspended == 0) {
2293 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2294 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2295 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2296 & ~BCM43xx_SBF_MAC_ENABLED);
2297 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2298 for (i = 10000; i; i--) {
2299 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2300 if (tmp & BCM43xx_IRQ_READY)
2301 goto out;
2302 udelay(1);
2303 }
2304 printkl(KERN_ERR PFX "MAC suspend failed\n");
2305 }
2306 out:
2307 bcm->mac_suspended++;
2308 }
2309
2310 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2311 int iw_mode)
2312 {
2313 unsigned long flags;
2314 struct net_device *net_dev = bcm->net_dev;
2315 u32 status;
2316 u16 value;
2317
2318 spin_lock_irqsave(&bcm->ieee->lock, flags);
2319 bcm->ieee->iw_mode = iw_mode;
2320 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2321 if (iw_mode == IW_MODE_MONITOR)
2322 net_dev->type = ARPHRD_IEEE80211;
2323 else
2324 net_dev->type = ARPHRD_ETHER;
2325
2326 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2327 /* Reset status to infrastructured mode */
2328 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2329 status &= ~BCM43xx_SBF_MODE_PROMISC;
2330 status |= BCM43xx_SBF_MODE_NOTADHOC;
2331
2332 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2333 status |= BCM43xx_SBF_MODE_PROMISC;
2334
2335 switch (iw_mode) {
2336 case IW_MODE_MONITOR:
2337 status |= BCM43xx_SBF_MODE_MONITOR;
2338 status |= BCM43xx_SBF_MODE_PROMISC;
2339 break;
2340 case IW_MODE_ADHOC:
2341 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2342 break;
2343 case IW_MODE_MASTER:
2344 status |= BCM43xx_SBF_MODE_AP;
2345 break;
2346 case IW_MODE_SECOND:
2347 case IW_MODE_REPEAT:
2348 TODO(); /* TODO */
2349 break;
2350 case IW_MODE_INFRA:
2351 /* nothing to be done here... */
2352 break;
2353 default:
2354 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2355 }
2356 if (net_dev->flags & IFF_PROMISC)
2357 status |= BCM43xx_SBF_MODE_PROMISC;
2358 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2359
2360 value = 0x0002;
2361 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2362 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2363 value = 0x0064;
2364 else
2365 value = 0x0032;
2366 }
2367 bcm43xx_write16(bcm, 0x0612, value);
2368 }
2369
2370 /* This is the opposite of bcm43xx_chip_init() */
2371 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2372 {
2373 bcm43xx_radio_turn_off(bcm);
2374 if (!modparam_noleds)
2375 bcm43xx_leds_exit(bcm);
2376 bcm43xx_gpio_cleanup(bcm);
2377 bcm43xx_release_firmware(bcm, 0);
2378 }
2379
2380 /* Initialize the chip
2381 * http://bcm-specs.sipsolutions.net/ChipInit
2382 */
2383 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2384 {
2385 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2386 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2387 int err;
2388 int i, tmp;
2389 u32 value32;
2390 u16 value16;
2391
2392 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2393 BCM43xx_SBF_CORE_READY
2394 | BCM43xx_SBF_400);
2395
2396 err = bcm43xx_request_firmware(bcm);
2397 if (err)
2398 goto out;
2399 bcm43xx_upload_microcode(bcm);
2400
2401 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2402 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2403 i = 0;
2404 while (1) {
2405 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2406 if (value32 == BCM43xx_IRQ_READY)
2407 break;
2408 i++;
2409 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2410 printk(KERN_ERR PFX "IRQ_READY timeout\n");
2411 err = -ENODEV;
2412 goto err_release_fw;
2413 }
2414 udelay(10);
2415 }
2416 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2417
2418 value16 = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2419 BCM43xx_UCODE_REVISION);
2420
2421 dprintk(KERN_INFO PFX "Microcode rev 0x%x, pl 0x%x "
2422 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", value16,
2423 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2424 BCM43xx_UCODE_PATCHLEVEL),
2425 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2426 BCM43xx_UCODE_DATE) >> 12) & 0xf,
2427 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2428 BCM43xx_UCODE_DATE) >> 8) & 0xf,
2429 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2430 BCM43xx_UCODE_DATE) & 0xff,
2431 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2432 BCM43xx_UCODE_TIME) >> 11) & 0x1f,
2433 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2434 BCM43xx_UCODE_TIME) >> 5) & 0x3f,
2435 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2436 BCM43xx_UCODE_TIME) & 0x1f);
2437
2438 if ( value16 > 0x128 ) {
2439 printk(KERN_ERR PFX
2440 "Firmware: no support for microcode extracted "
2441 "from version 4.x binary drivers.\n");
2442 err = -EOPNOTSUPP;
2443 goto err_release_fw;
2444 }
2445
2446 err = bcm43xx_gpio_init(bcm);
2447 if (err)
2448 goto err_release_fw;
2449
2450 err = bcm43xx_upload_initvals(bcm);
2451 if (err)
2452 goto err_gpio_cleanup;
2453 bcm43xx_radio_turn_on(bcm);
2454 bcm->radio_hw_enable = bcm43xx_is_hw_radio_enabled(bcm);
2455 dprintk(KERN_INFO PFX "Radio %s by hardware\n",
2456 (bcm->radio_hw_enable == 0) ? "disabled" : "enabled");
2457
2458 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2459 err = bcm43xx_phy_init(bcm);
2460 if (err)
2461 goto err_radio_off;
2462
2463 /* Select initial Interference Mitigation. */
2464 tmp = radio->interfmode;
2465 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2466 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2467
2468 bcm43xx_phy_set_antenna_diversity(bcm);
2469 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2470 if (phy->type == BCM43xx_PHYTYPE_B) {
2471 value16 = bcm43xx_read16(bcm, 0x005E);
2472 value16 |= 0x0004;
2473 bcm43xx_write16(bcm, 0x005E, value16);
2474 }
2475 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2476 if (bcm->current_core->rev < 5)
2477 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2478
2479 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2480 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2481 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2482 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2483 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2484 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2485
2486 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2487 value32 |= 0x100000;
2488 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2489
2490 if (bcm43xx_using_pio(bcm)) {
2491 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2492 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2493 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2494 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2495 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2496 }
2497
2498 /* Probe Response Timeout value */
2499 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2500 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2501
2502 /* Initially set the wireless operation mode. */
2503 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2504
2505 if (bcm->current_core->rev < 3) {
2506 bcm43xx_write16(bcm, 0x060E, 0x0000);
2507 bcm43xx_write16(bcm, 0x0610, 0x8000);
2508 bcm43xx_write16(bcm, 0x0604, 0x0000);
2509 bcm43xx_write16(bcm, 0x0606, 0x0200);
2510 } else {
2511 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2512 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2513 }
2514 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2515 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2516 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2517 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2518 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2519 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2520 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2521
2522 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2523 value32 |= 0x00100000;
2524 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2525
2526 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2527
2528 assert(err == 0);
2529 dprintk(KERN_INFO PFX "Chip initialized\n");
2530 out:
2531 return err;
2532
2533 err_radio_off:
2534 bcm43xx_radio_turn_off(bcm);
2535 err_gpio_cleanup:
2536 bcm43xx_gpio_cleanup(bcm);
2537 err_release_fw:
2538 bcm43xx_release_firmware(bcm, 1);
2539 goto out;
2540 }
2541
2542 /* Validate chip access
2543 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2544 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2545 {
2546 u32 value;
2547 u32 shm_backup;
2548
2549 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2550 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2551 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2552 goto error;
2553 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2554 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2555 goto error;
2556 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2557
2558 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2559 if ((value | 0x80000000) != 0x80000400)
2560 goto error;
2561
2562 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2563 if (value != 0x00000000)
2564 goto error;
2565
2566 return 0;
2567 error:
2568 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2569 return -ENODEV;
2570 }
2571
2572 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2573 {
2574 /* Initialize a "phyinfo" structure. The structure is already
2575 * zeroed out.
2576 * This is called on insmod time to initialize members.
2577 */
2578 phy->savedpctlreg = 0xFFFF;
2579 spin_lock_init(&phy->lock);
2580 }
2581
2582 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2583 {
2584 /* Initialize a "radioinfo" structure. The structure is already
2585 * zeroed out.
2586 * This is called on insmod time to initialize members.
2587 */
2588 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2589 radio->channel = 0xFF;
2590 radio->initial_channel = 0xFF;
2591 }
2592
2593 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2594 {
2595 int err, i;
2596 int current_core;
2597 u32 core_vendor, core_id, core_rev;
2598 u32 sb_id_hi, chip_id_32 = 0;
2599 u16 pci_device, chip_id_16;
2600 u8 core_count;
2601
2602 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2603 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2604 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2605 * BCM43xx_MAX_80211_CORES);
2606 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2607 * BCM43xx_MAX_80211_CORES);
2608 bcm->nr_80211_available = 0;
2609 bcm->current_core = NULL;
2610 bcm->active_80211_core = NULL;
2611
2612 /* map core 0 */
2613 err = _switch_core(bcm, 0);
2614 if (err)
2615 goto out;
2616
2617 /* fetch sb_id_hi from core information registers */
2618 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2619
2620 core_id = (sb_id_hi & 0x8FF0) >> 4;
2621 core_rev = (sb_id_hi & 0x7000) >> 8;
2622 core_rev |= (sb_id_hi & 0xF);
2623 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2624
2625 /* if present, chipcommon is always core 0; read the chipid from it */
2626 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2627 chip_id_32 = bcm43xx_read32(bcm, 0);
2628 chip_id_16 = chip_id_32 & 0xFFFF;
2629 bcm->core_chipcommon.available = 1;
2630 bcm->core_chipcommon.id = core_id;
2631 bcm->core_chipcommon.rev = core_rev;
2632 bcm->core_chipcommon.index = 0;
2633 /* While we are at it, also read the capabilities. */
2634 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2635 } else {
2636 /* without a chipCommon, use a hard coded table. */
2637 pci_device = bcm->pci_dev->device;
2638 if (pci_device == 0x4301)
2639 chip_id_16 = 0x4301;
2640 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2641 chip_id_16 = 0x4307;
2642 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2643 chip_id_16 = 0x4402;
2644 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2645 chip_id_16 = 0x4610;
2646 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2647 chip_id_16 = 0x4710;
2648 #ifdef CONFIG_BCM947XX
2649 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2650 chip_id_16 = 0x4309;
2651 #endif
2652 else {
2653 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2654 return -ENODEV;
2655 }
2656 }
2657
2658 /* ChipCommon with Core Rev >=4 encodes number of cores,
2659 * otherwise consult hardcoded table */
2660 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2661 core_count = (chip_id_32 & 0x0F000000) >> 24;
2662 } else {
2663 switch (chip_id_16) {
2664 case 0x4610:
2665 case 0x4704:
2666 case 0x4710:
2667 core_count = 9;
2668 break;
2669 case 0x4310:
2670 core_count = 8;
2671 break;
2672 case 0x5365:
2673 core_count = 7;
2674 break;
2675 case 0x4306:
2676 core_count = 6;
2677 break;
2678 case 0x4301:
2679 case 0x4307:
2680 core_count = 5;
2681 break;
2682 case 0x4402:
2683 core_count = 3;
2684 break;
2685 default:
2686 /* SOL if we get here */
2687 assert(0);
2688 core_count = 1;
2689 }
2690 }
2691
2692 bcm->chip_id = chip_id_16;
2693 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2694 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2695
2696 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2697 bcm->chip_id, bcm->chip_rev);
2698 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2699 if (bcm->core_chipcommon.available) {
2700 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2701 core_id, core_rev, core_vendor);
2702 current_core = 1;
2703 } else
2704 current_core = 0;
2705 for ( ; current_core < core_count; current_core++) {
2706 struct bcm43xx_coreinfo *core;
2707 struct bcm43xx_coreinfo_80211 *ext_80211;
2708
2709 err = _switch_core(bcm, current_core);
2710 if (err)
2711 goto out;
2712 /* Gather information */
2713 /* fetch sb_id_hi from core information registers */
2714 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2715
2716 /* extract core_id, core_rev, core_vendor */
2717 core_id = (sb_id_hi & 0x8FF0) >> 4;
2718 core_rev = ((sb_id_hi & 0xF) | ((sb_id_hi & 0x7000) >> 8));
2719 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2720
2721 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2722 current_core, core_id, core_rev, core_vendor);
2723
2724 core = NULL;
2725 switch (core_id) {
2726 case BCM43xx_COREID_PCI:
2727 case BCM43xx_COREID_PCIE:
2728 core = &bcm->core_pci;
2729 if (core->available) {
2730 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2731 continue;
2732 }
2733 break;
2734 case BCM43xx_COREID_80211:
2735 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2736 core = &(bcm->core_80211[i]);
2737 ext_80211 = &(bcm->core_80211_ext[i]);
2738 if (!core->available)
2739 break;
2740 core = NULL;
2741 }
2742 if (!core) {
2743 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2744 BCM43xx_MAX_80211_CORES);
2745 continue;
2746 }
2747 if (i != 0) {
2748 /* More than one 80211 core is only supported
2749 * by special chips.
2750 * There are chips with two 80211 cores, but with
2751 * dangling pins on the second core. Be careful
2752 * and ignore these cores here.
2753 */
2754 if (1 /*bcm->pci_dev->device != 0x4324*/ ) {
2755 /* TODO: A PHY */
2756 dprintk(KERN_INFO PFX "Ignoring additional 802.11a core.\n");
2757 continue;
2758 }
2759 }
2760 switch (core_rev) {
2761 case 2:
2762 case 4:
2763 case 5:
2764 case 6:
2765 case 7:
2766 case 9:
2767 case 10:
2768 break;
2769 default:
2770 printk(KERN_WARNING PFX
2771 "Unsupported 80211 core revision %u\n",
2772 core_rev);
2773 }
2774 bcm->nr_80211_available++;
2775 core->priv = ext_80211;
2776 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2777 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2778 break;
2779 case BCM43xx_COREID_CHIPCOMMON:
2780 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2781 break;
2782 }
2783 if (core) {
2784 core->available = 1;
2785 core->id = core_id;
2786 core->rev = core_rev;
2787 core->index = current_core;
2788 }
2789 }
2790
2791 if (!bcm->core_80211[0].available) {
2792 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2793 err = -ENODEV;
2794 goto out;
2795 }
2796
2797 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2798
2799 assert(err == 0);
2800 out:
2801 return err;
2802 }
2803
2804 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2805 {
2806 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2807 u8 *bssid = bcm->ieee->bssid;
2808
2809 switch (bcm->ieee->iw_mode) {
2810 case IW_MODE_ADHOC:
2811 random_ether_addr(bssid);
2812 break;
2813 case IW_MODE_MASTER:
2814 case IW_MODE_INFRA:
2815 case IW_MODE_REPEAT:
2816 case IW_MODE_SECOND:
2817 case IW_MODE_MONITOR:
2818 memcpy(bssid, mac, ETH_ALEN);
2819 break;
2820 default:
2821 assert(0);
2822 }
2823 }
2824
2825 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2826 u16 rate,
2827 int is_ofdm)
2828 {
2829 u16 offset;
2830
2831 if (is_ofdm) {
2832 offset = 0x480;
2833 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2834 }
2835 else {
2836 offset = 0x4C0;
2837 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2838 }
2839 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2840 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2841 }
2842
2843 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2844 {
2845 switch (bcm43xx_current_phy(bcm)->type) {
2846 case BCM43xx_PHYTYPE_A:
2847 case BCM43xx_PHYTYPE_G:
2848 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2849 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2850 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2851 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2852 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2853 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2854 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2855 case BCM43xx_PHYTYPE_B:
2856 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2857 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2858 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2859 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2860 break;
2861 default:
2862 assert(0);
2863 }
2864 }
2865
2866 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2867 {
2868 bcm43xx_chip_cleanup(bcm);
2869 bcm43xx_pio_free(bcm);
2870 bcm43xx_dma_free(bcm);
2871
2872 bcm->current_core->initialized = 0;
2873 }
2874
2875 /* http://bcm-specs.sipsolutions.net/80211Init */
2876 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2877 int active_wlcore)
2878 {
2879 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2880 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2881 u32 ucodeflags;
2882 int err;
2883 u32 sbimconfiglow;
2884 u8 limit;
2885
2886 if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
2887 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2888 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2889 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2890 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2891 sbimconfiglow |= 0x32;
2892 else
2893 sbimconfiglow |= 0x53;
2894 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2895 }
2896
2897 bcm43xx_phy_calibrate(bcm);
2898 err = bcm43xx_chip_init(bcm);
2899 if (err)
2900 goto out;
2901
2902 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2903 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2904
2905 if (0 /*FIXME: which condition has to be used here? */)
2906 ucodeflags |= 0x00000010;
2907
2908 /* HW decryption needs to be set now */
2909 ucodeflags |= 0x40000000;
2910
2911 if (phy->type == BCM43xx_PHYTYPE_G) {
2912 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2913 if (phy->rev == 1)
2914 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2915 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2916 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2917 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2918 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2919 if (phy->rev >= 2 && radio->version == 0x2050)
2920 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2921 }
2922
2923 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2924 BCM43xx_UCODEFLAGS_OFFSET)) {
2925 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2926 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2927 }
2928
2929 /* Short/Long Retry Limit.
2930 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2931 * the chip-internal counter.
2932 */
2933 limit = limit_value(modparam_short_retry, 0, 0xF);
2934 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2935 limit = limit_value(modparam_long_retry, 0, 0xF);
2936 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2937
2938 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2939 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2940
2941 bcm43xx_rate_memory_init(bcm);
2942
2943 /* Minimum Contention Window */
2944 if (phy->type == BCM43xx_PHYTYPE_B)
2945 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2946 else
2947 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2948 /* Maximum Contention Window */
2949 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2950
2951 bcm43xx_gen_bssid(bcm);
2952 bcm43xx_write_mac_bssid_templates(bcm);
2953
2954 if (bcm->current_core->rev >= 5)
2955 bcm43xx_write16(bcm, 0x043C, 0x000C);
2956
2957 if (active_wlcore) {
2958 if (bcm43xx_using_pio(bcm)) {
2959 err = bcm43xx_pio_init(bcm);
2960 } else {
2961 err = bcm43xx_dma_init(bcm);
2962 if (err == -ENOSYS)
2963 err = bcm43xx_pio_init(bcm);
2964 }
2965 if (err)
2966 goto err_chip_cleanup;
2967 }
2968 bcm43xx_write16(bcm, 0x0612, 0x0050);
2969 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2970 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2971
2972 if (active_wlcore) {
2973 if (radio->initial_channel != 0xFF)
2974 bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2975 }
2976
2977 /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2978 * We enable it later.
2979 */
2980 bcm->current_core->initialized = 1;
2981 out:
2982 return err;
2983
2984 err_chip_cleanup:
2985 bcm43xx_chip_cleanup(bcm);
2986 goto out;
2987 }
2988
2989 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2990 {
2991 int err;
2992 u16 pci_status;
2993
2994 err = bcm43xx_pctl_set_crystal(bcm, 1);
2995 if (err)
2996 goto out;
2997 err = bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2998 if (err)
2999 goto out;
3000 err = bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
3001
3002 out:
3003 return err;
3004 }
3005
3006 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
3007 {
3008 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3009 bcm43xx_pctl_set_crystal(bcm, 0);
3010 }
3011
3012 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
3013 u32 address,
3014 u32 data)
3015 {
3016 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
3017 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
3018 }
3019
3020 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
3021 {
3022 int err = 0;
3023
3024 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3025
3026 if (bcm->core_chipcommon.available) {
3027 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
3028 if (err)
3029 goto out;
3030
3031 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3032
3033 /* this function is always called when a PCI core is mapped */
3034 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3035 if (err)
3036 goto out;
3037 } else
3038 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3039
3040 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3041
3042 out:
3043 return err;
3044 }
3045
3046 static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
3047 {
3048 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3049 return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
3050 }
3051
3052 static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
3053 u32 data)
3054 {
3055 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3056 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
3057 }
3058
3059 static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
3060 u16 data)
3061 {
3062 int i;
3063
3064 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
3065 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
3066 BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
3067 (reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
3068 data);
3069 udelay(10);
3070
3071 for (i = 0; i < 10; i++) {
3072 if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
3073 BCM43xx_PCIE_MDIO_TC)
3074 break;
3075 msleep(1);
3076 }
3077 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
3078 }
3079
3080 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3081 * To enable core 0, pass a core_mask of 1<<0
3082 */
3083 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3084 u32 core_mask)
3085 {
3086 u32 backplane_flag_nr;
3087 u32 value;
3088 struct bcm43xx_coreinfo *old_core;
3089 int err = 0;
3090
3091 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
3092 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
3093
3094 old_core = bcm->current_core;
3095 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3096 if (err)
3097 goto out;
3098
3099 if (bcm->current_core->rev < 6 &&
3100 bcm->current_core->id == BCM43xx_COREID_PCI) {
3101 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3102 value |= (1 << backplane_flag_nr);
3103 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3104 } else {
3105 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3106 if (err) {
3107 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3108 goto out_switch_back;
3109 }
3110 value |= core_mask << 8;
3111 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3112 if (err) {
3113 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3114 goto out_switch_back;
3115 }
3116 }
3117
3118 if (bcm->current_core->id == BCM43xx_COREID_PCI) {
3119 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3120 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3121 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3122
3123 if (bcm->current_core->rev < 5) {
3124 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3125 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3126 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3127 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3128 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3129 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3130 err = bcm43xx_pcicore_commit_settings(bcm);
3131 assert(err == 0);
3132 } else if (bcm->current_core->rev >= 11) {
3133 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3134 value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
3135 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3136 }
3137 } else {
3138 if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
3139 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
3140 value |= 0x8;
3141 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
3142 value);
3143 }
3144 if (bcm->current_core->rev == 0) {
3145 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3146 BCM43xx_SERDES_RXTIMER, 0x8128);
3147 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3148 BCM43xx_SERDES_CDR, 0x0100);
3149 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3150 BCM43xx_SERDES_CDR_BW, 0x1466);
3151 } else if (bcm->current_core->rev == 1) {
3152 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
3153 value |= 0x40;
3154 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
3155 value);
3156 }
3157 }
3158 out_switch_back:
3159 err = bcm43xx_switch_core(bcm, old_core);
3160 out:
3161 return err;
3162 }
3163
3164 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3165 {
3166 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3167
3168 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3169 return;
3170
3171 bcm43xx_mac_suspend(bcm);
3172 bcm43xx_phy_lo_g_measure(bcm);
3173 bcm43xx_mac_enable(bcm);
3174 }
3175
3176 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3177 {
3178 bcm43xx_phy_lo_mark_all_unused(bcm);
3179 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3180 bcm43xx_mac_suspend(bcm);
3181 bcm43xx_calc_nrssi_slope(bcm);
3182 bcm43xx_mac_enable(bcm);
3183 }
3184 }
3185
3186 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3187 {
3188 /* Update device statistics. */
3189 bcm43xx_calculate_link_quality(bcm);
3190 }
3191
3192 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3193 {
3194 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3195 //TODO for APHY (temperature?)
3196 }
3197
3198 static void bcm43xx_periodic_every1sec(struct bcm43xx_private *bcm)
3199 {
3200 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3201 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3202 int radio_hw_enable;
3203
3204 /* check if radio hardware enabled status changed */
3205 radio_hw_enable = bcm43xx_is_hw_radio_enabled(bcm);
3206 if (unlikely(bcm->radio_hw_enable != radio_hw_enable)) {
3207 bcm->radio_hw_enable = radio_hw_enable;
3208 dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
3209 (radio_hw_enable == 0) ? "disabled" : "enabled");
3210 bcm43xx_leds_update(bcm, 0);
3211 }
3212 if (phy->type == BCM43xx_PHYTYPE_G) {
3213 //TODO: update_aci_moving_average
3214 if (radio->aci_enable && radio->aci_wlan_automatic) {
3215 bcm43xx_mac_suspend(bcm);
3216 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3217 if (0 /*TODO: bunch of conditions*/) {
3218 bcm43xx_radio_set_interference_mitigation(bcm,
3219 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3220 }
3221 } else if (1/*TODO*/) {
3222 /*
3223 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3224 bcm43xx_radio_set_interference_mitigation(bcm,
3225 BCM43xx_RADIO_INTERFMODE_NONE);
3226 }
3227 */
3228 }
3229 bcm43xx_mac_enable(bcm);
3230 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3231 phy->rev == 1) {
3232 //TODO: implement rev1 workaround
3233 }
3234 }
3235 }
3236
3237 static void do_periodic_work(struct bcm43xx_private *bcm)
3238 {
3239 if (bcm->periodic_state % 120 == 0)
3240 bcm43xx_periodic_every120sec(bcm);
3241 if (bcm->periodic_state % 60 == 0)
3242 bcm43xx_periodic_every60sec(bcm);
3243 if (bcm->periodic_state % 30 == 0)
3244 bcm43xx_periodic_every30sec(bcm);
3245 if (bcm->periodic_state % 15 == 0)
3246 bcm43xx_periodic_every15sec(bcm);
3247 bcm43xx_periodic_every1sec(bcm);
3248
3249 schedule_delayed_work(&bcm->periodic_work, HZ);
3250 }
3251
3252 static void bcm43xx_periodic_work_handler(struct work_struct *work)
3253 {
3254 struct bcm43xx_private *bcm =
3255 container_of(work, struct bcm43xx_private, periodic_work.work);
3256 struct net_device *net_dev = bcm->net_dev;
3257 unsigned long flags;
3258 u32 savedirqs = 0;
3259 unsigned long orig_trans_start = 0;
3260
3261 mutex_lock(&bcm->mutex);
3262 if (unlikely(bcm->periodic_state % 60 == 0)) {
3263 /* Periodic work will take a long time, so we want it to
3264 * be preemtible.
3265 */
3266
3267 netif_tx_lock_bh(net_dev);
3268 /* We must fake a started transmission here, as we are going to
3269 * disable TX. If we wouldn't fake a TX, it would be possible to
3270 * trigger the netdev watchdog, if the last real TX is already
3271 * some time on the past (slightly less than 5secs)
3272 */
3273 orig_trans_start = net_dev->trans_start;
3274 net_dev->trans_start = jiffies;
3275 netif_stop_queue(net_dev);
3276 netif_tx_unlock_bh(net_dev);
3277
3278 spin_lock_irqsave(&bcm->irq_lock, flags);
3279 bcm43xx_mac_suspend(bcm);
3280 if (bcm43xx_using_pio(bcm))
3281 bcm43xx_pio_freeze_txqueues(bcm);
3282 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3283 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3284 bcm43xx_synchronize_irq(bcm);
3285 } else {
3286 /* Periodic work should take short time, so we want low
3287 * locking overhead.
3288 */
3289 spin_lock_irqsave(&bcm->irq_lock, flags);
3290 }
3291
3292 do_periodic_work(bcm);
3293
3294 if (unlikely(bcm->periodic_state % 60 == 0)) {
3295 spin_lock_irqsave(&bcm->irq_lock, flags);
3296 tasklet_enable(&bcm->isr_tasklet);
3297 bcm43xx_interrupt_enable(bcm, savedirqs);
3298 if (bcm43xx_using_pio(bcm))
3299 bcm43xx_pio_thaw_txqueues(bcm);
3300 bcm43xx_mac_enable(bcm);
3301 netif_wake_queue(bcm->net_dev);
3302 net_dev->trans_start = orig_trans_start;
3303 }
3304 mmiowb();
3305 bcm->periodic_state++;
3306 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3307 mutex_unlock(&bcm->mutex);
3308 }
3309
3310 void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3311 {
3312 cancel_rearming_delayed_work(&bcm->periodic_work);
3313 }
3314
3315 void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3316 {
3317 struct delayed_work *work = &bcm->periodic_work;
3318
3319 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
3320 INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
3321 schedule_delayed_work(work, 0);
3322 }
3323
3324 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3325 {
3326 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3327 0x0056) * 2;
3328 bcm43xx_clear_keys(bcm);
3329 }
3330
3331 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3332 {
3333 struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3334 unsigned long flags;
3335
3336 spin_lock_irqsave(&(bcm)->irq_lock, flags);
3337 *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
3338 spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
3339
3340 return (sizeof(u16));
3341 }
3342
3343 static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3344 {
3345 hwrng_unregister(&bcm->rng);
3346 }
3347
3348 static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3349 {
3350 int err;
3351
3352 snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3353 "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3354 bcm->rng.name = bcm->rng_name;
3355 bcm->rng.data_read = bcm43xx_rng_read;
3356 bcm->rng.priv = (unsigned long)bcm;
3357 err = hwrng_register(&bcm->rng);
3358 if (err)
3359 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3360
3361 return err;
3362 }
3363
3364 static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
3365 {
3366 int ret = 0;
3367 int i, err;
3368 struct bcm43xx_coreinfo *core;
3369
3370 bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3371 for (i = 0; i < bcm->nr_80211_available; i++) {
3372 core = &(bcm->core_80211[i]);
3373 assert(core->available);
3374 if (!core->initialized)
3375 continue;
3376 err = bcm43xx_switch_core(bcm, core);
3377 if (err) {
3378 dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3379 "switch_core failed (%d)\n", err);
3380 ret = err;
3381 continue;
3382 }
3383 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3384 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3385 bcm43xx_wireless_core_cleanup(bcm);
3386 if (core == bcm->active_80211_core)
3387 bcm->active_80211_core = NULL;
3388 }
3389 free_irq(bcm->irq, bcm);
3390 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3391
3392 return ret;
3393 }
3394
3395 /* This is the opposite of bcm43xx_init_board() */
3396 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3397 {
3398 bcm43xx_rng_exit(bcm);
3399 bcm43xx_sysfs_unregister(bcm);
3400 bcm43xx_periodic_tasks_delete(bcm);
3401
3402 mutex_lock(&(bcm)->mutex);
3403 bcm43xx_shutdown_all_wireless_cores(bcm);
3404 bcm43xx_pctl_set_crystal(bcm, 0);
3405 mutex_unlock(&(bcm)->mutex);
3406 }
3407
3408 static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3409 {
3410 phy->antenna_diversity = 0xFFFF;
3411 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3412 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3413
3414 /* Flags */
3415 phy->calibrated = 0;
3416 phy->is_locked = 0;
3417
3418 if (phy->_lo_pairs) {
3419 memset(phy->_lo_pairs, 0,
3420 sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3421 }
3422 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3423 }
3424
3425 static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3426 struct bcm43xx_radioinfo *radio)
3427 {
3428 int i;
3429
3430 /* Set default attenuation values. */
3431 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3432 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3433 radio->txctl1 = bcm43xx_default_txctl1(bcm);
3434 radio->txctl2 = 0xFFFF;
3435 radio->txpwr_offset = 0;
3436
3437 /* NRSSI */
3438 radio->nrssislope = 0;
3439 for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3440 radio->nrssi[i] = -1000;
3441 for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3442 radio->nrssi_lt[i] = i;
3443
3444 radio->lofcal = 0xFFFF;
3445 radio->initval = 0xFFFF;
3446
3447 radio->aci_enable = 0;
3448 radio->aci_wlan_automatic = 0;
3449 radio->aci_hw_rssi = 0;
3450 }
3451
3452 static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3453 {
3454 int i;
3455 struct bcm43xx_coreinfo *core;
3456 struct bcm43xx_coreinfo_80211 *wlext;
3457
3458 assert(!bcm->active_80211_core);
3459
3460 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3461
3462 /* Flags */
3463 bcm->was_initialized = 0;
3464 bcm->reg124_set_0x4 = 0;
3465
3466 /* Stats */
3467 memset(&bcm->stats, 0, sizeof(bcm->stats));
3468
3469 /* Wireless core data */
3470 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3471 core = &(bcm->core_80211[i]);
3472 wlext = core->priv;
3473
3474 if (!core->available)
3475 continue;
3476 assert(wlext == &(bcm->core_80211_ext[i]));
3477
3478 prepare_phydata_for_init(&wlext->phy);
3479 prepare_radiodata_for_init(bcm, &wlext->radio);
3480 }
3481
3482 /* IRQ related flags */
3483 bcm->irq_reason = 0;
3484 memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3485 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3486
3487 bcm->mac_suspended = 1;
3488
3489 /* Noise calculation context */
3490 memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3491
3492 /* Periodic work context */
3493 bcm->periodic_state = 0;
3494 }
3495
3496 static int wireless_core_up(struct bcm43xx_private *bcm,
3497 int active_wlcore)
3498 {
3499 int err;
3500
3501 if (!bcm43xx_core_enabled(bcm))
3502 bcm43xx_wireless_core_reset(bcm, 1);
3503 if (!active_wlcore)
3504 bcm43xx_wireless_core_mark_inactive(bcm);
3505 err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3506 if (err)
3507 goto out;
3508 if (!active_wlcore)
3509 bcm43xx_radio_turn_off(bcm);
3510 out:
3511 return err;
3512 }
3513
3514 /* Select and enable the "to be used" wireless core.
3515 * Locking: bcm->mutex must be aquired before calling this.
3516 * bcm->irq_lock must not be aquired.
3517 */
3518 int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3519 int phytype)
3520 {
3521 int i, err;
3522 struct bcm43xx_coreinfo *active_core = NULL;
3523 struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3524 struct bcm43xx_coreinfo *core;
3525 struct bcm43xx_coreinfo_80211 *wlext;
3526 int adjust_active_sbtmstatelow = 0;
3527
3528 might_sleep();
3529
3530 if (phytype < 0) {
3531 /* If no phytype is requested, select the first core. */
3532 assert(bcm->core_80211[0].available);
3533 wlext = bcm->core_80211[0].priv;
3534 phytype = wlext->phy.type;
3535 }
3536 /* Find the requested core. */
3537 for (i = 0; i < bcm->nr_80211_available; i++) {
3538 core = &(bcm->core_80211[i]);
3539 wlext = core->priv;
3540 if (wlext->phy.type == phytype) {
3541 active_core = core;
3542 active_wlext = wlext;
3543 break;
3544 }
3545 }
3546 if (!active_core)
3547 return -ESRCH; /* No such PHYTYPE on this board. */
3548
3549 if (bcm->active_80211_core) {
3550 /* We already selected a wl core in the past.
3551 * So first clean up everything.
3552 */
3553 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3554 ieee80211softmac_stop(bcm->net_dev);
3555 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3556 err = bcm43xx_disable_interrupts_sync(bcm);
3557 assert(!err);
3558 tasklet_enable(&bcm->isr_tasklet);
3559 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3560 if (err)
3561 goto error;
3562 /* Ok, everything down, continue to re-initialize. */
3563 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3564 }
3565
3566 /* Reset all data structures. */
3567 prepare_priv_for_init(bcm);
3568
3569 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3570 if (err)
3571 goto error;
3572
3573 /* Mark all unused cores "inactive". */
3574 for (i = 0; i < bcm->nr_80211_available; i++) {
3575 core = &(bcm->core_80211[i]);
3576 wlext = core->priv;
3577
3578 if (core == active_core)
3579 continue;
3580 err = bcm43xx_switch_core(bcm, core);
3581 if (err) {
3582 dprintk(KERN_ERR PFX "Could not switch to inactive "
3583 "802.11 core (%d)\n", err);
3584 goto error;
3585 }
3586 err = wireless_core_up(bcm, 0);
3587 if (err) {
3588 dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3589 "failed (%d)\n", err);
3590 goto error;
3591 }
3592 adjust_active_sbtmstatelow = 1;
3593 }
3594
3595 /* Now initialize the active 802.11 core. */
3596 err = bcm43xx_switch_core(bcm, active_core);
3597 if (err) {
3598 dprintk(KERN_ERR PFX "Could not switch to active "
3599 "802.11 core (%d)\n", err);
3600 goto error;
3601 }
3602 if (adjust_active_sbtmstatelow &&
3603 active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3604 u32 sbtmstatelow;
3605
3606 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3607 sbtmstatelow |= BCM43xx_SBTMSTATELOW_G_MODE_ENABLE;
3608 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3609 }
3610 err = wireless_core_up(bcm, 1);
3611 if (err) {
3612 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3613 "failed (%d)\n", err);
3614 goto error;
3615 }
3616 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3617 if (err)
3618 goto error;
3619 bcm->active_80211_core = active_core;
3620
3621 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3622 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3623 bcm43xx_security_init(bcm);
3624 drain_txstatus_queue(bcm);
3625 ieee80211softmac_start(bcm->net_dev);
3626
3627 /* Let's go! Be careful after enabling the IRQs.
3628 * Don't switch cores, for example.
3629 */
3630 bcm43xx_mac_enable(bcm);
3631 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3632 err = bcm43xx_initialize_irq(bcm);
3633 if (err)
3634 goto error;
3635 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3636
3637 dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3638 active_wlext->phy.type);
3639
3640 return 0;
3641
3642 error:
3643 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3644 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3645 return err;
3646 }
3647
3648 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3649 {
3650 int err;
3651
3652 mutex_lock(&(bcm)->mutex);
3653
3654 tasklet_enable(&bcm->isr_tasklet);
3655 err = bcm43xx_pctl_set_crystal(bcm, 1);
3656 if (err)
3657 goto err_tasklet;
3658 err = bcm43xx_pctl_init(bcm);
3659 if (err)
3660 goto err_crystal_off;
3661 err = bcm43xx_select_wireless_core(bcm, -1);
3662 if (err)
3663 goto err_crystal_off;
3664 err = bcm43xx_sysfs_register(bcm);
3665 if (err)
3666 goto err_wlshutdown;
3667 err = bcm43xx_rng_init(bcm);
3668 if (err)
3669 goto err_sysfs_unreg;
3670 bcm43xx_periodic_tasks_setup(bcm);
3671
3672 /*FIXME: This should be handled by softmac instead. */
3673 schedule_delayed_work(&bcm->softmac->associnfo.work, 0);
3674
3675 out:
3676 mutex_unlock(&(bcm)->mutex);
3677
3678 return err;
3679
3680 err_sysfs_unreg:
3681 bcm43xx_sysfs_unregister(bcm);
3682 err_wlshutdown:
3683 bcm43xx_shutdown_all_wireless_cores(bcm);
3684 err_crystal_off:
3685 bcm43xx_pctl_set_crystal(bcm, 0);
3686 err_tasklet:
3687 tasklet_disable(&bcm->isr_tasklet);
3688 goto out;
3689 }
3690
3691 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3692 {
3693 struct pci_dev *pci_dev = bcm->pci_dev;
3694 int i;
3695
3696 bcm43xx_chipset_detach(bcm);
3697 /* Do _not_ access the chip, after it is detached. */
3698 pci_iounmap(pci_dev, bcm->mmio_addr);
3699 pci_release_regions(pci_dev);
3700 pci_disable_device(pci_dev);
3701
3702 /* Free allocated structures/fields */
3703 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3704 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3705 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3706 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3707 }
3708 }
3709
3710 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3711 {
3712 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3713 u16 value;
3714 u8 phy_analog;
3715 u8 phy_type;
3716 u8 phy_rev;
3717 int phy_rev_ok = 1;
3718 void *p;
3719
3720 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3721
3722 phy_analog = (value & 0xF000) >> 12;
3723 phy_type = (value & 0x0F00) >> 8;
3724 phy_rev = (value & 0x000F);
3725
3726 dprintk(KERN_INFO PFX "Detected PHY: Analog: %x, Type %x, Revision %x\n",
3727 phy_analog, phy_type, phy_rev);
3728
3729 switch (phy_type) {
3730 case BCM43xx_PHYTYPE_A:
3731 if (phy_rev >= 4)
3732 phy_rev_ok = 0;
3733 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3734 * if we switch 80211 cores after init is done.
3735 * As we do not implement on the fly switching between
3736 * wireless cores, I will leave this as a future task.
3737 */
3738 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3739 bcm->ieee->mode = IEEE_A;
3740 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3741 IEEE80211_24GHZ_BAND;
3742 break;
3743 case BCM43xx_PHYTYPE_B:
3744 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3745 phy_rev_ok = 0;
3746 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3747 bcm->ieee->mode = IEEE_B;
3748 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3749 break;
3750 case BCM43xx_PHYTYPE_G:
3751 if (phy_rev > 8)
3752 phy_rev_ok = 0;
3753 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3754 IEEE80211_CCK_MODULATION;
3755 bcm->ieee->mode = IEEE_G;
3756 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3757 break;
3758 default:
3759 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3760 phy_type);
3761 return -ENODEV;
3762 };
3763 bcm->ieee->perfect_rssi = RX_RSSI_MAX;
3764 bcm->ieee->worst_rssi = 0;
3765 if (!phy_rev_ok) {
3766 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3767 phy_rev);
3768 }
3769
3770 phy->analog = phy_analog;
3771 phy->type = phy_type;
3772 phy->rev = phy_rev;
3773 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3774 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3775 GFP_KERNEL);
3776 if (!p)
3777 return -ENOMEM;
3778 phy->_lo_pairs = p;
3779 }
3780
3781 return 0;
3782 }
3783
3784 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3785 {
3786 struct pci_dev *pci_dev = bcm->pci_dev;
3787 struct net_device *net_dev = bcm->net_dev;
3788 int err;
3789 int i;
3790 u32 coremask;
3791
3792 err = pci_enable_device(pci_dev);
3793 if (err) {
3794 printk(KERN_ERR PFX "pci_enable_device() failed\n");
3795 goto out;
3796 }
3797 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3798 if (err) {
3799 printk(KERN_ERR PFX "pci_request_regions() failed\n");
3800 goto err_pci_disable;
3801 }
3802 /* enable PCI bus-mastering */
3803 pci_set_master(pci_dev);
3804 bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
3805 if (!bcm->mmio_addr) {
3806 printk(KERN_ERR PFX "pci_iomap() failed\n");
3807 err = -EIO;
3808 goto err_pci_release;
3809 }
3810 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3811
3812 err = bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3813 &bcm->board_vendor);
3814 if (err)
3815 goto err_iounmap;
3816 err = bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3817 &bcm->board_type);
3818 if (err)
3819 goto err_iounmap;
3820 err = bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3821 &bcm->board_revision);
3822 if (err)
3823 goto err_iounmap;
3824
3825 err = bcm43xx_chipset_attach(bcm);
3826 if (err)
3827 goto err_iounmap;
3828 err = bcm43xx_pctl_init(bcm);
3829 if (err)
3830 goto err_chipset_detach;
3831 err = bcm43xx_probe_cores(bcm);
3832 if (err)
3833 goto err_chipset_detach;
3834
3835 /* Attach all IO cores to the backplane. */
3836 coremask = 0;
3837 for (i = 0; i < bcm->nr_80211_available; i++)
3838 coremask |= (1 << bcm->core_80211[i].index);
3839 //FIXME: Also attach some non80211 cores?
3840 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3841 if (err) {
3842 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3843 goto err_chipset_detach;
3844 }
3845
3846 err = bcm43xx_sprom_extract(bcm);
3847 if (err)
3848 goto err_chipset_detach;
3849 err = bcm43xx_leds_init(bcm);
3850 if (err)
3851 goto err_chipset_detach;
3852
3853 for (i = 0; i < bcm->nr_80211_available; i++) {
3854 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3855 assert(err != -ENODEV);
3856 if (err)
3857 goto err_80211_unwind;
3858
3859 /* Enable the selected wireless core.
3860 * Connect PHY only on the first core.
3861 */
3862 bcm43xx_wireless_core_reset(bcm, (i == 0));
3863
3864 err = bcm43xx_read_phyinfo(bcm);
3865 if (err && (i == 0))
3866 goto err_80211_unwind;
3867
3868 err = bcm43xx_read_radioinfo(bcm);
3869 if (err && (i == 0))
3870 goto err_80211_unwind;
3871
3872 err = bcm43xx_validate_chip(bcm);
3873 if (err && (i == 0))
3874 goto err_80211_unwind;
3875
3876 bcm43xx_radio_turn_off(bcm);
3877 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3878 if (err)
3879 goto err_80211_unwind;
3880 bcm43xx_wireless_core_disable(bcm);
3881 }
3882 err = bcm43xx_geo_init(bcm);
3883 if (err)
3884 goto err_80211_unwind;
3885 bcm43xx_pctl_set_crystal(bcm, 0);
3886
3887 /* Set the MAC address in the networking subsystem */
3888 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3889 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3890 else
3891 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3892
3893 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3894 "Broadcom %04X", bcm->chip_id);
3895
3896 assert(err == 0);
3897 out:
3898 return err;
3899
3900 err_80211_unwind:
3901 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3902 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3903 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3904 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3905 }
3906 err_chipset_detach:
3907 bcm43xx_chipset_detach(bcm);
3908 err_iounmap:
3909 pci_iounmap(pci_dev, bcm->mmio_addr);
3910 err_pci_release:
3911 pci_release_regions(pci_dev);
3912 err_pci_disable:
3913 pci_disable_device(pci_dev);
3914 printk(KERN_ERR PFX "Unable to attach board\n");
3915 goto out;
3916 }
3917
3918 /* Do the Hardware IO operations to send the txb */
3919 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3920 struct ieee80211_txb *txb)
3921 {
3922 int err = -ENODEV;
3923
3924 if (bcm43xx_using_pio(bcm))
3925 err = bcm43xx_pio_tx(bcm, txb);
3926 else
3927 err = bcm43xx_dma_tx(bcm, txb);
3928 bcm->net_dev->trans_start = jiffies;
3929
3930 return err;
3931 }
3932
3933 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3934 u8 channel)
3935 {
3936 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3937 struct bcm43xx_radioinfo *radio;
3938 unsigned long flags;
3939
3940 mutex_lock(&bcm->mutex);
3941 spin_lock_irqsave(&bcm->irq_lock, flags);
3942 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
3943 bcm43xx_mac_suspend(bcm);
3944 bcm43xx_radio_selectchannel(bcm, channel, 0);
3945 bcm43xx_mac_enable(bcm);
3946 } else {
3947 radio = bcm43xx_current_radio(bcm);
3948 radio->initial_channel = channel;
3949 }
3950 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3951 mutex_unlock(&bcm->mutex);
3952 }
3953
3954 /* set_security() callback in struct ieee80211_device */
3955 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3956 struct ieee80211_security *sec)
3957 {
3958 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3959 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3960 unsigned long flags;
3961 int keyidx;
3962
3963 dprintk(KERN_INFO PFX "set security called");
3964
3965 mutex_lock(&bcm->mutex);
3966 spin_lock_irqsave(&bcm->irq_lock, flags);
3967
3968 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3969 if (sec->flags & (1<<keyidx)) {
3970 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3971 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3972 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3973 }
3974
3975 if (sec->flags & SEC_ACTIVE_KEY) {
3976 secinfo->active_key = sec->active_key;
3977 dprintk(", .active_key = %d", sec->active_key);
3978 }
3979 if (sec->flags & SEC_UNICAST_GROUP) {
3980 secinfo->unicast_uses_group = sec->unicast_uses_group;
3981 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
3982 }
3983 if (sec->flags & SEC_LEVEL) {
3984 secinfo->level = sec->level;
3985 dprintk(", .level = %d", sec->level);
3986 }
3987 if (sec->flags & SEC_ENABLED) {
3988 secinfo->enabled = sec->enabled;
3989 dprintk(", .enabled = %d", sec->enabled);
3990 }
3991 if (sec->flags & SEC_ENCRYPT) {
3992 secinfo->encrypt = sec->encrypt;
3993 dprintk(", .encrypt = %d", sec->encrypt);
3994 }
3995 if (sec->flags & SEC_AUTH_MODE) {
3996 secinfo->auth_mode = sec->auth_mode;
3997 dprintk(", .auth_mode = %d", sec->auth_mode);
3998 }
3999 dprintk("\n");
4000 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
4001 !bcm->ieee->host_encrypt) {
4002 if (secinfo->enabled) {
4003 /* upload WEP keys to hardware */
4004 char null_address[6] = { 0 };
4005 u8 algorithm = 0;
4006 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
4007 if (!(sec->flags & (1<<keyidx)))
4008 continue;
4009 switch (sec->encode_alg[keyidx]) {
4010 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
4011 case SEC_ALG_WEP:
4012 algorithm = BCM43xx_SEC_ALGO_WEP;
4013 if (secinfo->key_sizes[keyidx] == 13)
4014 algorithm = BCM43xx_SEC_ALGO_WEP104;
4015 break;
4016 case SEC_ALG_TKIP:
4017 FIXME();
4018 algorithm = BCM43xx_SEC_ALGO_TKIP;
4019 break;
4020 case SEC_ALG_CCMP:
4021 FIXME();
4022 algorithm = BCM43xx_SEC_ALGO_AES;
4023 break;
4024 default:
4025 assert(0);
4026 break;
4027 }
4028 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
4029 bcm->key[keyidx].enabled = 1;
4030 bcm->key[keyidx].algorithm = algorithm;
4031 }
4032 } else
4033 bcm43xx_clear_keys(bcm);
4034 }
4035 spin_unlock_irqrestore(&bcm->irq_lock, flags);
4036 mutex_unlock(&bcm->mutex);
4037 }
4038
4039 /* hard_start_xmit() callback in struct ieee80211_device */
4040 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
4041 struct net_device *net_dev,
4042 int pri)
4043 {
4044 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4045 int err = -ENODEV;
4046 unsigned long flags;
4047
4048 spin_lock_irqsave(&bcm->irq_lock, flags);
4049 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
4050 err = bcm43xx_tx(bcm, txb);
4051 spin_unlock_irqrestore(&bcm->irq_lock, flags);
4052
4053 if (unlikely(err))
4054 return NETDEV_TX_BUSY;
4055 return NETDEV_TX_OK;
4056 }
4057
4058 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
4059 {
4060 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4061 unsigned long flags;
4062
4063 spin_lock_irqsave(&bcm->irq_lock, flags);
4064 bcm43xx_controller_restart(bcm, "TX timeout");
4065 spin_unlock_irqrestore(&bcm->irq_lock, flags);
4066 }
4067
4068 #ifdef CONFIG_NET_POLL_CONTROLLER
4069 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
4070 {
4071 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4072 unsigned long flags;
4073
4074 local_irq_save(flags);
4075 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
4076 bcm43xx_interrupt_handler(bcm->irq, bcm);
4077 local_irq_restore(flags);
4078 }
4079 #endif /* CONFIG_NET_POLL_CONTROLLER */
4080
4081 static int bcm43xx_net_open(struct net_device *net_dev)
4082 {
4083 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4084
4085 return bcm43xx_init_board(bcm);
4086 }
4087
4088 static int bcm43xx_net_stop(struct net_device *net_dev)
4089 {
4090 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4091 int err;
4092
4093 ieee80211softmac_stop(net_dev);
4094 err = bcm43xx_disable_interrupts_sync(bcm);
4095 assert(!err);
4096 bcm43xx_free_board(bcm);
4097 flush_scheduled_work();
4098
4099 return 0;
4100 }
4101
4102 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
4103 struct net_device *net_dev,
4104 struct pci_dev *pci_dev)
4105 {
4106 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
4107 bcm->ieee = netdev_priv(net_dev);
4108 bcm->softmac = ieee80211_priv(net_dev);
4109 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
4110
4111 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
4112 bcm->mac_suspended = 1;
4113 bcm->pci_dev = pci_dev;
4114 bcm->net_dev = net_dev;
4115 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
4116 spin_lock_init(&bcm->irq_lock);
4117 spin_lock_init(&bcm->leds_lock);
4118 mutex_init(&bcm->mutex);
4119 tasklet_init(&bcm->isr_tasklet,
4120 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
4121 (unsigned long)bcm);
4122 tasklet_disable_nosync(&bcm->isr_tasklet);
4123 if (modparam_pio)
4124 bcm->__using_pio = 1;
4125 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4126
4127 /* default to sw encryption for now */
4128 bcm->ieee->host_build_iv = 0;
4129 bcm->ieee->host_encrypt = 1;
4130 bcm->ieee->host_decrypt = 1;
4131
4132 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4133 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4134 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4135 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
4136
4137 return 0;
4138 }
4139
4140 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4141 const struct pci_device_id *ent)
4142 {
4143 struct net_device *net_dev;
4144 struct bcm43xx_private *bcm;
4145 int err;
4146
4147 #ifdef CONFIG_BCM947XX
4148 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4149 return -ENODEV;
4150 #endif
4151
4152 #ifdef DEBUG_SINGLE_DEVICE_ONLY
4153 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4154 return -ENODEV;
4155 #endif
4156
4157 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4158 if (!net_dev) {
4159 printk(KERN_ERR PFX
4160 "could not allocate ieee80211 device %s\n",
4161 pci_name(pdev));
4162 err = -ENOMEM;
4163 goto out;
4164 }
4165 /* initialize the net_device struct */
4166 SET_MODULE_OWNER(net_dev);
4167 SET_NETDEV_DEV(net_dev, &pdev->dev);
4168
4169 net_dev->open = bcm43xx_net_open;
4170 net_dev->stop = bcm43xx_net_stop;
4171 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4172 #ifdef CONFIG_NET_POLL_CONTROLLER
4173 net_dev->poll_controller = bcm43xx_net_poll_controller;
4174 #endif
4175 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4176 net_dev->irq = pdev->irq;
4177 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
4178
4179 /* initialize the bcm43xx_private struct */
4180 bcm = bcm43xx_priv(net_dev);
4181 memset(bcm, 0, sizeof(*bcm));
4182 err = bcm43xx_init_private(bcm, net_dev, pdev);
4183 if (err)
4184 goto err_free_netdev;
4185
4186 pci_set_drvdata(pdev, net_dev);
4187
4188 err = bcm43xx_attach_board(bcm);
4189 if (err)
4190 goto err_free_netdev;
4191
4192 err = register_netdev(net_dev);
4193 if (err) {
4194 printk(KERN_ERR PFX "Cannot register net device, "
4195 "aborting.\n");
4196 err = -ENOMEM;
4197 goto err_detach_board;
4198 }
4199
4200 bcm43xx_debugfs_add_device(bcm);
4201
4202 assert(err == 0);
4203 out:
4204 return err;
4205
4206 err_detach_board:
4207 bcm43xx_detach_board(bcm);
4208 err_free_netdev:
4209 free_ieee80211softmac(net_dev);
4210 goto out;
4211 }
4212
4213 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4214 {
4215 struct net_device *net_dev = pci_get_drvdata(pdev);
4216 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4217
4218 bcm43xx_debugfs_remove_device(bcm);
4219 unregister_netdev(net_dev);
4220 bcm43xx_detach_board(bcm);
4221 free_ieee80211softmac(net_dev);
4222 }
4223
4224 /* Hard-reset the chip. Do not call this directly.
4225 * Use bcm43xx_controller_restart()
4226 */
4227 static void bcm43xx_chip_reset(struct work_struct *work)
4228 {
4229 struct bcm43xx_private *bcm =
4230 container_of(work, struct bcm43xx_private, restart_work);
4231 struct bcm43xx_phyinfo *phy;
4232 int err = -ENODEV;
4233
4234 mutex_lock(&(bcm)->mutex);
4235 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4236 bcm43xx_periodic_tasks_delete(bcm);
4237 phy = bcm43xx_current_phy(bcm);
4238 err = bcm43xx_select_wireless_core(bcm, phy->type);
4239 if (!err)
4240 bcm43xx_periodic_tasks_setup(bcm);
4241 }
4242 mutex_unlock(&(bcm)->mutex);
4243
4244 printk(KERN_ERR PFX "Controller restart%s\n",
4245 (err == 0) ? "ed" : " failed");
4246 }
4247
4248 /* Hard-reset the chip.
4249 * This can be called from interrupt or process context.
4250 * bcm->irq_lock must be locked.
4251 */
4252 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4253 {
4254 if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
4255 return;
4256 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
4257 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset);
4258 schedule_work(&bcm->restart_work);
4259 }
4260
4261 #ifdef CONFIG_PM
4262
4263 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4264 {
4265 struct net_device *net_dev = pci_get_drvdata(pdev);
4266 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4267 int err;
4268
4269 dprintk(KERN_INFO PFX "Suspending...\n");
4270
4271 netif_device_detach(net_dev);
4272 bcm->was_initialized = 0;
4273 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4274 bcm->was_initialized = 1;
4275 ieee80211softmac_stop(net_dev);
4276 err = bcm43xx_disable_interrupts_sync(bcm);
4277 if (unlikely(err)) {
4278 dprintk(KERN_ERR PFX "Suspend failed.\n");
4279 return -EAGAIN;
4280 }
4281 bcm->firmware_norelease = 1;
4282 bcm43xx_free_board(bcm);
4283 bcm->firmware_norelease = 0;
4284 }
4285 bcm43xx_chipset_detach(bcm);
4286
4287 pci_save_state(pdev);
4288 pci_disable_device(pdev);
4289 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4290
4291 dprintk(KERN_INFO PFX "Device suspended.\n");
4292
4293 return 0;
4294 }
4295
4296 static int bcm43xx_resume(struct pci_dev *pdev)
4297 {
4298 struct net_device *net_dev = pci_get_drvdata(pdev);
4299 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4300 int err = 0;
4301
4302 dprintk(KERN_INFO PFX "Resuming...\n");
4303
4304 pci_set_power_state(pdev, 0);
4305 err = pci_enable_device(pdev);
4306 if (err) {
4307 printk(KERN_ERR PFX "Failure with pci_enable_device!\n");
4308 return err;
4309 }
4310 pci_restore_state(pdev);
4311
4312 bcm43xx_chipset_attach(bcm);
4313 if (bcm->was_initialized)
4314 err = bcm43xx_init_board(bcm);
4315 if (err) {
4316 printk(KERN_ERR PFX "Resume failed!\n");
4317 return err;
4318 }
4319 netif_device_attach(net_dev);
4320
4321 dprintk(KERN_INFO PFX "Device resumed.\n");
4322
4323 return 0;
4324 }
4325
4326 #endif /* CONFIG_PM */
4327
4328 static struct pci_driver bcm43xx_pci_driver = {
4329 .name = KBUILD_MODNAME,
4330 .id_table = bcm43xx_pci_tbl,
4331 .probe = bcm43xx_init_one,
4332 .remove = __devexit_p(bcm43xx_remove_one),
4333 #ifdef CONFIG_PM
4334 .suspend = bcm43xx_suspend,
4335 .resume = bcm43xx_resume,
4336 #endif /* CONFIG_PM */
4337 };
4338
4339 static int __init bcm43xx_init(void)
4340 {
4341 printk(KERN_INFO KBUILD_MODNAME " driver\n");
4342 bcm43xx_debugfs_init();
4343 return pci_register_driver(&bcm43xx_pci_driver);
4344 }
4345
4346 static void __exit bcm43xx_exit(void)
4347 {
4348 pci_unregister_driver(&bcm43xx_pci_driver);
4349 bcm43xx_debugfs_exit();
4350 }
4351
4352 module_init(bcm43xx_init)
4353 module_exit(bcm43xx_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree