1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
28 #include "psb_intel_reg.h"
29 #include "psb_powermgmt.h"
37 psb_pipestat(int pipe
)
49 mid_pipe_event(int pipe
)
52 return _PSB_PIPEA_EVENT_FLAG
;
54 return _MDFLD_PIPEB_EVENT_FLAG
;
56 return _MDFLD_PIPEC_EVENT_FLAG
;
61 mid_pipe_vsync(int pipe
)
64 return _PSB_VSYNC_PIPEA_FLAG
;
66 return _PSB_VSYNC_PIPEB_FLAG
;
68 return _MDFLD_PIPEC_VBLANK_FLAG
;
73 mid_pipeconf(int pipe
)
85 psb_enable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
87 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
88 u32 reg
= psb_pipestat(pipe
);
89 dev_priv
->pipestat
[pipe
] |= mask
;
90 /* Enable the interrupt, clear any pending status */
91 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
92 OSPM_UHB_ONLY_IF_ON
)) {
93 u32 writeVal
= PSB_RVDC32(reg
);
94 writeVal
|= (mask
| (mask
>> 16));
95 PSB_WVDC32(writeVal
, reg
);
96 (void) PSB_RVDC32(reg
);
97 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
103 psb_disable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
105 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
106 u32 reg
= psb_pipestat(pipe
);
107 dev_priv
->pipestat
[pipe
] &= ~mask
;
108 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
109 OSPM_UHB_ONLY_IF_ON
)) {
110 u32 writeVal
= PSB_RVDC32(reg
);
112 PSB_WVDC32(writeVal
, reg
);
113 (void) PSB_RVDC32(reg
);
114 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
119 void mid_enable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
121 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
122 OSPM_UHB_ONLY_IF_ON
)) {
123 u32 pipe_event
= mid_pipe_event(pipe
);
124 dev_priv
->vdc_irq_mask
|= pipe_event
;
125 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
126 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
127 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
131 void mid_disable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
133 if (dev_priv
->pipestat
[pipe
] == 0) {
134 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
135 OSPM_UHB_ONLY_IF_ON
)) {
136 u32 pipe_event
= mid_pipe_event(pipe
);
137 dev_priv
->vdc_irq_mask
&= ~pipe_event
;
138 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
139 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
140 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
146 * Display controller interrupt handler for vsync/vblank.
149 static void mid_vblank_handler(struct drm_device
*dev
, uint32_t pipe
)
151 drm_handle_vblank(dev
, pipe
);
156 * Display controller interrupt handler for pipe event.
159 #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
160 static void mid_pipe_event_handler(struct drm_device
*dev
, uint32_t pipe
)
162 struct drm_psb_private
*dev_priv
=
163 (struct drm_psb_private
*) dev
->dev_private
;
165 uint32_t pipe_stat_val
= 0;
166 uint32_t pipe_stat_reg
= psb_pipestat(pipe
);
167 uint32_t pipe_enable
= dev_priv
->pipestat
[pipe
];
168 uint32_t pipe_status
= dev_priv
->pipestat
[pipe
] >> 16;
171 spin_lock(&dev_priv
->irqmask_lock
);
173 pipe_stat_val
= PSB_RVDC32(pipe_stat_reg
);
174 pipe_stat_val
&= pipe_enable
| pipe_status
;
175 pipe_stat_val
&= pipe_stat_val
>> 16;
177 spin_unlock(&dev_priv
->irqmask_lock
);
179 /* clear the 2nd level interrupt status bits */
181 * FIXME: shouldn't use while loop here. However, the interrupt
182 * status 'sticky' bits cannot be cleared by setting '1' to that
185 for (i
= 0; i
< WAIT_STATUS_CLEAR_LOOP_COUNT
; i
++) {
186 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg
), pipe_stat_reg
);
187 (void) PSB_RVDC32(pipe_stat_reg
);
189 if ((PSB_RVDC32(pipe_stat_reg
) & pipe_status
) == 0)
193 if (i
== WAIT_STATUS_CLEAR_LOOP_COUNT
)
194 DRM_ERROR("%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
195 __func__
, PSB_RVDC32(pipe_stat_reg
));
197 if (pipe_stat_val
& PIPE_VBLANK_STATUS
)
198 mid_vblank_handler(dev
, pipe
);
200 if (pipe_stat_val
& PIPE_TE_STATUS
)
201 drm_handle_vblank(dev
, pipe
);
205 * Display controller interrupt handler.
207 static void psb_vdc_interrupt(struct drm_device
*dev
, uint32_t vdc_stat
)
209 if (vdc_stat
& _PSB_PIPEA_EVENT_FLAG
)
210 mid_pipe_event_handler(dev
, 0);
213 irqreturn_t
psb_irq_handler(DRM_IRQ_ARGS
)
215 struct drm_device
*dev
= (struct drm_device
*) arg
;
216 struct drm_psb_private
*dev_priv
=
217 (struct drm_psb_private
*) dev
->dev_private
;
219 uint32_t vdc_stat
, dsp_int
= 0, sgx_int
= 0;
222 spin_lock(&dev_priv
->irqmask_lock
);
224 vdc_stat
= PSB_RVDC32(PSB_INT_IDENTITY_R
);
226 if (vdc_stat
& _MDFLD_DISP_ALL_IRQ_FLAG
) {
227 PSB_DEBUG_IRQ("Got DISP interrupt\n");
231 if (vdc_stat
& _PSB_IRQ_SGX_FLAG
) {
232 PSB_DEBUG_IRQ("Got SGX interrupt\n");
235 if (vdc_stat
& _PSB_IRQ_MSVDX_FLAG
)
236 PSB_DEBUG_IRQ("Got MSVDX interrupt\n");
238 if (vdc_stat
& _LNC_IRQ_TOPAZ_FLAG
)
239 PSB_DEBUG_IRQ("Got TOPAZ interrupt\n");
242 vdc_stat
&= dev_priv
->vdc_irq_mask
;
243 spin_unlock(&dev_priv
->irqmask_lock
);
245 if (dsp_int
&& ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND
)) {
246 psb_vdc_interrupt(dev
, vdc_stat
);
251 /* Not expected - we have it masked, shut it up */
253 s
= PSB_RSGX32(PSB_CR_EVENT_STATUS
);
254 s2
= PSB_RSGX32(PSB_CR_EVENT_STATUS2
);
255 PSB_WSGX32(s
, PSB_CR_EVENT_HOST_CLEAR
);
256 PSB_WSGX32(s2
, PSB_CR_EVENT_HOST_CLEAR2
);
257 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
258 we may as well poll even if we add that ! */
262 PSB_WVDC32(vdc_stat
, PSB_INT_IDENTITY_R
);
263 (void) PSB_RVDC32(PSB_INT_IDENTITY_R
);
264 DRM_READMEMORYBARRIER();
272 void psb_irq_preinstall(struct drm_device
*dev
)
274 psb_irq_preinstall_islands(dev
, OSPM_ALL_ISLANDS
);
278 * FIXME: should I remove display irq enable here??
280 void psb_irq_preinstall_islands(struct drm_device
*dev
, int hw_islands
)
282 struct drm_psb_private
*dev_priv
=
283 (struct drm_psb_private
*) dev
->dev_private
;
284 unsigned long irqflags
;
286 PSB_DEBUG_ENTRY("\n");
288 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
290 if (hw_islands
& OSPM_DISPLAY_ISLAND
) {
291 if (ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND
)) {
292 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
293 if (dev
->vblank_enabled
[0])
294 dev_priv
->vdc_irq_mask
|=
295 _PSB_PIPEA_EVENT_FLAG
;
296 if (dev
->vblank_enabled
[1])
297 dev_priv
->vdc_irq_mask
|=
298 _MDFLD_PIPEB_EVENT_FLAG
;
299 if (dev
->vblank_enabled
[2])
300 dev_priv
->vdc_irq_mask
|=
301 _MDFLD_PIPEC_EVENT_FLAG
;
304 /* NO I DONT WANT ANY IRQS GRRR FIXMEAC */
305 if (hw_islands
& OSPM_GRAPHICS_ISLAND
)
306 dev_priv
->vdc_irq_mask
|= _PSB_IRQ_SGX_FLAG
;
308 /*This register is safe even if display island is off*/
309 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
311 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
314 int psb_irq_postinstall(struct drm_device
*dev
)
316 return psb_irq_postinstall_islands(dev
, OSPM_ALL_ISLANDS
);
319 int psb_irq_postinstall_islands(struct drm_device
*dev
, int hw_islands
)
322 struct drm_psb_private
*dev_priv
=
323 (struct drm_psb_private
*) dev
->dev_private
;
324 unsigned long irqflags
;
326 PSB_DEBUG_ENTRY("\n");
328 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
330 /*This register is safe even if display island is off*/
331 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
333 if (hw_islands
& OSPM_DISPLAY_ISLAND
) {
334 if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
335 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
337 if (dev
->vblank_enabled
[0])
338 psb_enable_pipestat(dev_priv
, 0,
339 PIPE_VBLANK_INTERRUPT_ENABLE
);
341 psb_disable_pipestat(dev_priv
, 0,
342 PIPE_VBLANK_INTERRUPT_ENABLE
);
344 if (dev
->vblank_enabled
[1])
345 psb_enable_pipestat(dev_priv
, 1,
346 PIPE_VBLANK_INTERRUPT_ENABLE
);
348 psb_disable_pipestat(dev_priv
, 1,
349 PIPE_VBLANK_INTERRUPT_ENABLE
);
351 if (dev
->vblank_enabled
[2])
352 psb_enable_pipestat(dev_priv
, 2,
353 PIPE_VBLANK_INTERRUPT_ENABLE
);
355 psb_disable_pipestat(dev_priv
, 2,
356 PIPE_VBLANK_INTERRUPT_ENABLE
);
360 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
365 void psb_irq_uninstall(struct drm_device
*dev
)
367 psb_irq_uninstall_islands(dev
, OSPM_ALL_ISLANDS
);
370 void psb_irq_uninstall_islands(struct drm_device
*dev
, int hw_islands
)
372 struct drm_psb_private
*dev_priv
=
373 (struct drm_psb_private
*) dev
->dev_private
;
374 unsigned long irqflags
;
376 PSB_DEBUG_ENTRY("\n");
378 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
380 if (hw_islands
& OSPM_DISPLAY_ISLAND
) {
381 if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
382 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
384 if (dev
->vblank_enabled
[0])
385 psb_disable_pipestat(dev_priv
, 0,
386 PIPE_VBLANK_INTERRUPT_ENABLE
);
388 if (dev
->vblank_enabled
[1])
389 psb_disable_pipestat(dev_priv
, 1,
390 PIPE_VBLANK_INTERRUPT_ENABLE
);
392 if (dev
->vblank_enabled
[2])
393 psb_disable_pipestat(dev_priv
, 2,
394 PIPE_VBLANK_INTERRUPT_ENABLE
);
396 dev_priv
->vdc_irq_mask
&= _PSB_IRQ_SGX_FLAG
|
397 _PSB_IRQ_MSVDX_FLAG
|
400 /*TODO: remove following code*/
401 if (hw_islands
& OSPM_GRAPHICS_ISLAND
)
402 dev_priv
->vdc_irq_mask
&= ~_PSB_IRQ_SGX_FLAG
;
404 /*These two registers are safe even if display island is off*/
405 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
406 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
410 /*This register is safe even if display island is off*/
411 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R
), PSB_INT_IDENTITY_R
);
413 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
416 void psb_irq_turn_on_dpst(struct drm_device
*dev
)
418 struct drm_psb_private
*dev_priv
=
419 (struct drm_psb_private
*) dev
->dev_private
;
423 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
424 OSPM_UHB_ONLY_IF_ON
)) {
425 PSB_WVDC32(BIT31
, HISTOGRAM_LOGIC_CONTROL
);
426 hist_reg
= PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL
);
427 PSB_WVDC32(BIT31
, HISTOGRAM_INT_CONTROL
);
428 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
430 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC
);
431 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
432 PSB_WVDC32(pwm_reg
| PWM_PHASEIN_ENABLE
433 | PWM_PHASEIN_INT_ENABLE
,
435 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
437 psb_enable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
439 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
440 PSB_WVDC32(hist_reg
| HISTOGRAM_INT_CTRL_CLEAR
,
441 HISTOGRAM_INT_CONTROL
);
442 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
443 PSB_WVDC32(pwm_reg
| 0x80010100 | PWM_PHASEIN_ENABLE
,
446 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
450 int psb_irq_enable_dpst(struct drm_device
*dev
)
452 struct drm_psb_private
*dev_priv
=
453 (struct drm_psb_private
*) dev
->dev_private
;
454 unsigned long irqflags
;
456 PSB_DEBUG_ENTRY("\n");
458 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
461 mid_enable_pipe_event(dev_priv
, 0);
462 psb_irq_turn_on_dpst(dev
);
464 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
468 void psb_irq_turn_off_dpst(struct drm_device
*dev
)
470 struct drm_psb_private
*dev_priv
=
471 (struct drm_psb_private
*) dev
->dev_private
;
475 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
476 OSPM_UHB_ONLY_IF_ON
)) {
477 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL
);
478 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
480 psb_disable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
482 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
483 PSB_WVDC32(pwm_reg
& !(PWM_PHASEIN_INT_ENABLE
),
485 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
487 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
491 int psb_irq_disable_dpst(struct drm_device
*dev
)
493 struct drm_psb_private
*dev_priv
=
494 (struct drm_psb_private
*) dev
->dev_private
;
495 unsigned long irqflags
;
497 PSB_DEBUG_ENTRY("\n");
499 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
501 mid_disable_pipe_event(dev_priv
, 0);
502 psb_irq_turn_off_dpst(dev
);
504 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
510 static int psb_vblank_do_wait(struct drm_device
*dev
,
511 unsigned int *sequence
, atomic_t
*counter
)
513 unsigned int cur_vblank
;
515 DRM_WAIT_ON(ret
, dev
->vbl_queue
, 3 * DRM_HZ
,
516 (((cur_vblank
= atomic_read(counter
))
517 - *sequence
) <= (1 << 23)));
518 *sequence
= cur_vblank
;
525 * It is used to enable VBLANK interrupt
527 int psb_enable_vblank(struct drm_device
*dev
, int pipe
)
529 struct drm_psb_private
*dev_priv
=
530 (struct drm_psb_private
*) dev
->dev_private
;
531 unsigned long irqflags
;
532 uint32_t reg_val
= 0;
533 uint32_t pipeconf_reg
= mid_pipeconf(pipe
);
535 PSB_DEBUG_ENTRY("\n");
537 if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
538 OSPM_UHB_ONLY_IF_ON
)) {
539 reg_val
= REG_READ(pipeconf_reg
);
540 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
543 if (!(reg_val
& PIPEACONF_ENABLE
))
546 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
548 drm_psb_disable_vsync
= 0;
549 mid_enable_pipe_event(dev_priv
, pipe
);
550 psb_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
552 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
558 * It is used to disable VBLANK interrupt
560 void psb_disable_vblank(struct drm_device
*dev
, int pipe
)
562 struct drm_psb_private
*dev_priv
=
563 (struct drm_psb_private
*) dev
->dev_private
;
564 unsigned long irqflags
;
566 PSB_DEBUG_ENTRY("\n");
568 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
570 drm_psb_disable_vsync
= 1;
571 mid_disable_pipe_event(dev_priv
, pipe
);
572 psb_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
574 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
577 /* Called from drm generic code, passed a 'crtc', which
578 * we use as a pipe index
580 u32
psb_get_vblank_counter(struct drm_device
*dev
, int pipe
)
582 uint32_t high_frame
= PIPEAFRAMEHIGH
;
583 uint32_t low_frame
= PIPEAFRAMEPIXEL
;
584 uint32_t pipeconf_reg
= PIPEACONF
;
585 uint32_t reg_val
= 0;
586 uint32_t high1
= 0, high2
= 0, low
= 0, count
= 0;
592 high_frame
= PIPEBFRAMEHIGH
;
593 low_frame
= PIPEBFRAMEPIXEL
;
594 pipeconf_reg
= PIPEBCONF
;
597 high_frame
= PIPECFRAMEHIGH
;
598 low_frame
= PIPECFRAMEPIXEL
;
599 pipeconf_reg
= PIPECCONF
;
602 DRM_ERROR("%s, invalded pipe.\n", __func__
);
606 if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
, false))
609 reg_val
= REG_READ(pipeconf_reg
);
611 if (!(reg_val
& PIPEACONF_ENABLE
)) {
612 DRM_ERROR("trying to get vblank count for disabled pipe %d\n",
614 goto psb_get_vblank_counter_exit
;
618 * High & low register fields aren't synchronized, so make sure
619 * we get a low value that's stable across two reads of the high
623 high1
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
624 PIPE_FRAME_HIGH_SHIFT
);
625 low
= ((REG_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
626 PIPE_FRAME_LOW_SHIFT
);
627 high2
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
628 PIPE_FRAME_HIGH_SHIFT
);
629 } while (high1
!= high2
);
631 count
= (high1
<< 8) | low
;
633 psb_get_vblank_counter_exit
:
635 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);