?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/i915: drop alignment ringbuffer parameter
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
blobc9894c2bcd65812ec6935f1e79288f84c3130939
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static u32 i915_gem_get_seqno(struct drm_device *dev)
38 {
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 u32 seqno;
41
42 seqno = dev_priv->next_seqno;
43
44 /* reserve 0 for non-seqno */
45 if (++dev_priv->next_seqno == 0)
46 dev_priv->next_seqno = 1;
47
48 return seqno;
49 }
50
51 static void
52 render_ring_flush(struct drm_device *dev,
53 struct intel_ring_buffer *ring,
54 u32 invalidate_domains,
55 u32 flush_domains)
56 {
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 cmd;
59
60 #if WATCH_EXEC
61 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62 invalidate_domains, flush_domains);
63 #endif
64
65 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
66 invalidate_domains, flush_domains);
67
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69 /*
70 * read/write caches:
71 *
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */
96
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112 #if WATCH_EXEC
113 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
114 #endif
115 intel_ring_begin(dev, ring, 2);
116 intel_ring_emit(dev, ring, cmd);
117 intel_ring_emit(dev, ring, MI_NOOP);
118 intel_ring_advance(dev, ring);
119 }
120 }
121
122 static void ring_set_tail(struct drm_device *dev,
123 struct intel_ring_buffer *ring,
124 u32 value)
125 {
126 drm_i915_private_t *dev_priv = dev->dev_private;
127 I915_WRITE_TAIL(ring, ring->tail);
128 }
129
130 static unsigned int render_ring_get_active_head(struct drm_device *dev,
131 struct intel_ring_buffer *ring)
132 {
133 drm_i915_private_t *dev_priv = dev->dev_private;
134 u32 acthd_reg = INTEL_INFO(dev)->gen ? ACTHD_I965 : ACTHD;
135
136 return I915_READ(acthd_reg);
137 }
138
139 static int init_ring_common(struct drm_device *dev,
140 struct intel_ring_buffer *ring)
141 {
142 u32 head;
143 drm_i915_private_t *dev_priv = dev->dev_private;
144 struct drm_i915_gem_object *obj_priv;
145 obj_priv = to_intel_bo(ring->gem_object);
146
147 /* Stop the ring if it's running. */
148 I915_WRITE_CTL(ring, 0);
149 I915_WRITE_HEAD(ring, 0);
150 ring->set_tail(dev, ring, 0);
151
152 /* Initialize the ring. */
153 I915_WRITE_START(ring, obj_priv->gtt_offset);
154 head = I915_READ_HEAD(ring) & HEAD_ADDR;
155
156 /* G45 ring initialization fails to reset head to zero */
157 if (head != 0) {
158 DRM_ERROR("%s head not reset to zero "
159 "ctl %08x head %08x tail %08x start %08x\n",
160 ring->name,
161 I915_READ_CTL(ring),
162 I915_READ_HEAD(ring),
163 I915_READ_TAIL(ring),
164 I915_READ_START(ring));
165
166 I915_WRITE_HEAD(ring, 0);
167
168 DRM_ERROR("%s head forced to zero "
169 "ctl %08x head %08x tail %08x start %08x\n",
170 ring->name,
171 I915_READ_CTL(ring),
172 I915_READ_HEAD(ring),
173 I915_READ_TAIL(ring),
174 I915_READ_START(ring));
175 }
176
177 I915_WRITE_CTL(ring,
178 ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
179 | RING_NO_REPORT | RING_VALID);
180
181 head = I915_READ_HEAD(ring) & HEAD_ADDR;
182 /* If the head is still not zero, the ring is dead */
183 if (head != 0) {
184 DRM_ERROR("%s initialization failed "
185 "ctl %08x head %08x tail %08x start %08x\n",
186 ring->name,
187 I915_READ_CTL(ring),
188 I915_READ_HEAD(ring),
189 I915_READ_TAIL(ring),
190 I915_READ_START(ring));
191 return -EIO;
192 }
193
194 if (!drm_core_check_feature(dev, DRIVER_MODESET))
195 i915_kernel_lost_context(dev);
196 else {
197 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
198 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
199 ring->space = ring->head - (ring->tail + 8);
200 if (ring->space < 0)
201 ring->space += ring->size;
202 }
203 return 0;
204 }
205
206 static int init_render_ring(struct drm_device *dev,
207 struct intel_ring_buffer *ring)
208 {
209 drm_i915_private_t *dev_priv = dev->dev_private;
210 int ret = init_ring_common(dev, ring);
211 int mode;
212
213 if (INTEL_INFO(dev)->gen > 3) {
214 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
215 if (IS_GEN6(dev))
216 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
217 I915_WRITE(MI_MODE, mode);
218 }
219 return ret;
220 }
221
222 #define PIPE_CONTROL_FLUSH(addr) \
223 do { \
224 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
225 PIPE_CONTROL_DEPTH_STALL | 2); \
226 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
227 OUT_RING(0); \
228 OUT_RING(0); \
229 } while (0)
230
231 /**
232 * Creates a new sequence number, emitting a write of it to the status page
233 * plus an interrupt, which will trigger i915_user_interrupt_handler.
234 *
235 * Must be called with struct_lock held.
236 *
237 * Returned sequence numbers are nonzero on success.
238 */
239 static u32
240 render_ring_add_request(struct drm_device *dev,
241 struct intel_ring_buffer *ring,
242 struct drm_file *file_priv,
243 u32 flush_domains)
244 {
245 drm_i915_private_t *dev_priv = dev->dev_private;
246 u32 seqno;
247
248 seqno = i915_gem_get_seqno(dev);
249
250 if (IS_GEN6(dev)) {
251 BEGIN_LP_RING(6);
252 OUT_RING(GFX_OP_PIPE_CONTROL | 3);
253 OUT_RING(PIPE_CONTROL_QW_WRITE |
254 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
255 PIPE_CONTROL_NOTIFY);
256 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
257 OUT_RING(seqno);
258 OUT_RING(0);
259 OUT_RING(0);
260 ADVANCE_LP_RING();
261 } else if (HAS_PIPE_CONTROL(dev)) {
262 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
263
264 /*
265 * Workaround qword write incoherence by flushing the
266 * PIPE_NOTIFY buffers out to memory before requesting
267 * an interrupt.
268 */
269 BEGIN_LP_RING(32);
270 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
271 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
272 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
273 OUT_RING(seqno);
274 OUT_RING(0);
275 PIPE_CONTROL_FLUSH(scratch_addr);
276 scratch_addr += 128; /* write to separate cachelines */
277 PIPE_CONTROL_FLUSH(scratch_addr);
278 scratch_addr += 128;
279 PIPE_CONTROL_FLUSH(scratch_addr);
280 scratch_addr += 128;
281 PIPE_CONTROL_FLUSH(scratch_addr);
282 scratch_addr += 128;
283 PIPE_CONTROL_FLUSH(scratch_addr);
284 scratch_addr += 128;
285 PIPE_CONTROL_FLUSH(scratch_addr);
286 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
287 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
288 PIPE_CONTROL_NOTIFY);
289 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
290 OUT_RING(seqno);
291 OUT_RING(0);
292 ADVANCE_LP_RING();
293 } else {
294 BEGIN_LP_RING(4);
295 OUT_RING(MI_STORE_DWORD_INDEX);
296 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
297 OUT_RING(seqno);
298
299 OUT_RING(MI_USER_INTERRUPT);
300 ADVANCE_LP_RING();
301 }
302 return seqno;
303 }
304
305 static u32
306 render_ring_get_gem_seqno(struct drm_device *dev,
307 struct intel_ring_buffer *ring)
308 {
309 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
310 if (HAS_PIPE_CONTROL(dev))
311 return ((volatile u32 *)(dev_priv->seqno_page))[0];
312 else
313 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
314 }
315
316 static void
317 render_ring_get_user_irq(struct drm_device *dev,
318 struct intel_ring_buffer *ring)
319 {
320 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
321 unsigned long irqflags;
322
323 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
324 if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
325 if (HAS_PCH_SPLIT(dev))
326 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
327 else
328 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
329 }
330 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
331 }
332
333 static void
334 render_ring_put_user_irq(struct drm_device *dev,
335 struct intel_ring_buffer *ring)
336 {
337 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
338 unsigned long irqflags;
339
340 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
341 BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
342 if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
343 if (HAS_PCH_SPLIT(dev))
344 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
345 else
346 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
347 }
348 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
349 }
350
351 static void render_setup_status_page(struct drm_device *dev,
352 struct intel_ring_buffer *ring)
353 {
354 drm_i915_private_t *dev_priv = dev->dev_private;
355 if (IS_GEN6(dev)) {
356 I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr);
357 I915_READ(HWS_PGA_GEN6); /* posting read */
358 } else {
359 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
360 I915_READ(HWS_PGA); /* posting read */
361 }
362
363 }
364
365 void
366 bsd_ring_flush(struct drm_device *dev,
367 struct intel_ring_buffer *ring,
368 u32 invalidate_domains,
369 u32 flush_domains)
370 {
371 intel_ring_begin(dev, ring, 2);
372 intel_ring_emit(dev, ring, MI_FLUSH);
373 intel_ring_emit(dev, ring, MI_NOOP);
374 intel_ring_advance(dev, ring);
375 }
376
377 static inline unsigned int bsd_ring_get_active_head(struct drm_device *dev,
378 struct intel_ring_buffer *ring)
379 {
380 drm_i915_private_t *dev_priv = dev->dev_private;
381 return I915_READ(BSD_RING_ACTHD);
382 }
383
384 static int init_bsd_ring(struct drm_device *dev,
385 struct intel_ring_buffer *ring)
386 {
387 return init_ring_common(dev, ring);
388 }
389
390 static u32
391 bsd_ring_add_request(struct drm_device *dev,
392 struct intel_ring_buffer *ring,
393 struct drm_file *file_priv,
394 u32 flush_domains)
395 {
396 u32 seqno;
397
398 seqno = i915_gem_get_seqno(dev);
399
400 intel_ring_begin(dev, ring, 4);
401 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
402 intel_ring_emit(dev, ring,
403 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
404 intel_ring_emit(dev, ring, seqno);
405 intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
406 intel_ring_advance(dev, ring);
407
408 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
409
410 return seqno;
411 }
412
413 static void bsd_setup_status_page(struct drm_device *dev,
414 struct intel_ring_buffer *ring)
415 {
416 drm_i915_private_t *dev_priv = dev->dev_private;
417 I915_WRITE(BSD_HWS_PGA, ring->status_page.gfx_addr);
418 I915_READ(BSD_HWS_PGA);
419 }
420
421 static void
422 bsd_ring_get_user_irq(struct drm_device *dev,
423 struct intel_ring_buffer *ring)
424 {
425 /* do nothing */
426 }
427 static void
428 bsd_ring_put_user_irq(struct drm_device *dev,
429 struct intel_ring_buffer *ring)
430 {
431 /* do nothing */
432 }
433
434 static u32
435 bsd_ring_get_gem_seqno(struct drm_device *dev,
436 struct intel_ring_buffer *ring)
437 {
438 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
439 }
440
441 static int
442 bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
443 struct intel_ring_buffer *ring,
444 struct drm_i915_gem_execbuffer2 *exec,
445 struct drm_clip_rect *cliprects,
446 uint64_t exec_offset)
447 {
448 uint32_t exec_start;
449 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
450 intel_ring_begin(dev, ring, 2);
451 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
452 (2 << 6) | MI_BATCH_NON_SECURE_I965);
453 intel_ring_emit(dev, ring, exec_start);
454 intel_ring_advance(dev, ring);
455 return 0;
456 }
457
458
459 static int
460 render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
461 struct intel_ring_buffer *ring,
462 struct drm_i915_gem_execbuffer2 *exec,
463 struct drm_clip_rect *cliprects,
464 uint64_t exec_offset)
465 {
466 drm_i915_private_t *dev_priv = dev->dev_private;
467 int nbox = exec->num_cliprects;
468 int i = 0, count;
469 uint32_t exec_start, exec_len;
470 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
471 exec_len = (uint32_t) exec->batch_len;
472
473 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
474
475 count = nbox ? nbox : 1;
476
477 for (i = 0; i < count; i++) {
478 if (i < nbox) {
479 int ret = i915_emit_box(dev, cliprects, i,
480 exec->DR1, exec->DR4);
481 if (ret)
482 return ret;
483 }
484
485 if (IS_I830(dev) || IS_845G(dev)) {
486 intel_ring_begin(dev, ring, 4);
487 intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
488 intel_ring_emit(dev, ring,
489 exec_start | MI_BATCH_NON_SECURE);
490 intel_ring_emit(dev, ring, exec_start + exec_len - 4);
491 intel_ring_emit(dev, ring, 0);
492 } else {
493 intel_ring_begin(dev, ring, 4);
494 if (INTEL_INFO(dev)->gen >= 4) {
495 intel_ring_emit(dev, ring,
496 MI_BATCH_BUFFER_START | (2 << 6)
497 | MI_BATCH_NON_SECURE_I965);
498 intel_ring_emit(dev, ring, exec_start);
499 } else {
500 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
501 | (2 << 6));
502 intel_ring_emit(dev, ring, exec_start |
503 MI_BATCH_NON_SECURE);
504 }
505 }
506 intel_ring_advance(dev, ring);
507 }
508
509 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
510 intel_ring_begin(dev, ring, 2);
511 intel_ring_emit(dev, ring, MI_FLUSH |
512 MI_NO_WRITE_FLUSH |
513 MI_INVALIDATE_ISP );
514 intel_ring_emit(dev, ring, MI_NOOP);
515 intel_ring_advance(dev, ring);
516 }
517 /* XXX breadcrumb */
518
519 return 0;
520 }
521
522 static void cleanup_status_page(struct drm_device *dev,
523 struct intel_ring_buffer *ring)
524 {
525 drm_i915_private_t *dev_priv = dev->dev_private;
526 struct drm_gem_object *obj;
527 struct drm_i915_gem_object *obj_priv;
528
529 obj = ring->status_page.obj;
530 if (obj == NULL)
531 return;
532 obj_priv = to_intel_bo(obj);
533
534 kunmap(obj_priv->pages[0]);
535 i915_gem_object_unpin(obj);
536 drm_gem_object_unreference(obj);
537 ring->status_page.obj = NULL;
538
539 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
540 }
541
542 static int init_status_page(struct drm_device *dev,
543 struct intel_ring_buffer *ring)
544 {
545 drm_i915_private_t *dev_priv = dev->dev_private;
546 struct drm_gem_object *obj;
547 struct drm_i915_gem_object *obj_priv;
548 int ret;
549
550 obj = i915_gem_alloc_object(dev, 4096);
551 if (obj == NULL) {
552 DRM_ERROR("Failed to allocate status page\n");
553 ret = -ENOMEM;
554 goto err;
555 }
556 obj_priv = to_intel_bo(obj);
557 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
558
559 ret = i915_gem_object_pin(obj, 4096);
560 if (ret != 0) {
561 goto err_unref;
562 }
563
564 ring->status_page.gfx_addr = obj_priv->gtt_offset;
565 ring->status_page.page_addr = kmap(obj_priv->pages[0]);
566 if (ring->status_page.page_addr == NULL) {
567 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
568 goto err_unpin;
569 }
570 ring->status_page.obj = obj;
571 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
572
573 ring->setup_status_page(dev, ring);
574 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
575 ring->name, ring->status_page.gfx_addr);
576
577 return 0;
578
579 err_unpin:
580 i915_gem_object_unpin(obj);
581 err_unref:
582 drm_gem_object_unreference(obj);
583 err:
584 return ret;
585 }
586
587
588 int intel_init_ring_buffer(struct drm_device *dev,
589 struct intel_ring_buffer *ring)
590 {
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 struct drm_i915_gem_object *obj_priv;
593 struct drm_gem_object *obj;
594 int ret;
595
596 ring->dev = dev;
597
598 if (I915_NEED_GFX_HWS(dev)) {
599 ret = init_status_page(dev, ring);
600 if (ret)
601 return ret;
602 }
603
604 obj = i915_gem_alloc_object(dev, ring->size);
605 if (obj == NULL) {
606 DRM_ERROR("Failed to allocate ringbuffer\n");
607 ret = -ENOMEM;
608 goto err_hws;
609 }
610
611 ring->gem_object = obj;
612
613 ret = i915_gem_object_pin(obj, PAGE_SIZE);
614 if (ret)
615 goto err_unref;
616
617 obj_priv = to_intel_bo(obj);
618 ring->map.size = ring->size;
619 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
620 ring->map.type = 0;
621 ring->map.flags = 0;
622 ring->map.mtrr = 0;
623
624 drm_core_ioremap_wc(&ring->map, dev);
625 if (ring->map.handle == NULL) {
626 DRM_ERROR("Failed to map ringbuffer.\n");
627 ret = -EINVAL;
628 goto err_unpin;
629 }
630
631 ring->virtual_start = ring->map.handle;
632 ret = ring->init(dev, ring);
633 if (ret)
634 goto err_unmap;
635
636 if (!drm_core_check_feature(dev, DRIVER_MODESET))
637 i915_kernel_lost_context(dev);
638 else {
639 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
640 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
641 ring->space = ring->head - (ring->tail + 8);
642 if (ring->space < 0)
643 ring->space += ring->size;
644 }
645 INIT_LIST_HEAD(&ring->active_list);
646 INIT_LIST_HEAD(&ring->request_list);
647 return ret;
648
649 err_unmap:
650 drm_core_ioremapfree(&ring->map, dev);
651 err_unpin:
652 i915_gem_object_unpin(obj);
653 err_unref:
654 drm_gem_object_unreference(obj);
655 ring->gem_object = NULL;
656 err_hws:
657 cleanup_status_page(dev, ring);
658 return ret;
659 }
660
661 void intel_cleanup_ring_buffer(struct drm_device *dev,
662 struct intel_ring_buffer *ring)
663 {
664 if (ring->gem_object == NULL)
665 return;
666
667 drm_core_ioremapfree(&ring->map, dev);
668
669 i915_gem_object_unpin(ring->gem_object);
670 drm_gem_object_unreference(ring->gem_object);
671 ring->gem_object = NULL;
672 cleanup_status_page(dev, ring);
673 }
674
675 int intel_wrap_ring_buffer(struct drm_device *dev,
676 struct intel_ring_buffer *ring)
677 {
678 unsigned int *virt;
679 int rem;
680 rem = ring->size - ring->tail;
681
682 if (ring->space < rem) {
683 int ret = intel_wait_ring_buffer(dev, ring, rem);
684 if (ret)
685 return ret;
686 }
687
688 virt = (unsigned int *)(ring->virtual_start + ring->tail);
689 rem /= 8;
690 while (rem--) {
691 *virt++ = MI_NOOP;
692 *virt++ = MI_NOOP;
693 }
694
695 ring->tail = 0;
696 ring->space = ring->head - 8;
697
698 return 0;
699 }
700
701 int intel_wait_ring_buffer(struct drm_device *dev,
702 struct intel_ring_buffer *ring, int n)
703 {
704 unsigned long end;
705 drm_i915_private_t *dev_priv = dev->dev_private;
706
707 trace_i915_ring_wait_begin (dev);
708 end = jiffies + 3 * HZ;
709 do {
710 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
711 ring->space = ring->head - (ring->tail + 8);
712 if (ring->space < 0)
713 ring->space += ring->size;
714 if (ring->space >= n) {
715 trace_i915_ring_wait_end (dev);
716 return 0;
717 }
718
719 if (dev->primary->master) {
720 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
721 if (master_priv->sarea_priv)
722 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
723 }
724
725 yield();
726 } while (!time_after(jiffies, end));
727 trace_i915_ring_wait_end (dev);
728 return -EBUSY;
729 }
730
731 void intel_ring_begin(struct drm_device *dev,
732 struct intel_ring_buffer *ring, int num_dwords)
733 {
734 int n = 4*num_dwords;
735 if (unlikely(ring->tail + n > ring->size))
736 intel_wrap_ring_buffer(dev, ring);
737 if (unlikely(ring->space < n))
738 intel_wait_ring_buffer(dev, ring, n);
739
740 ring->space -= n;
741 }
742
743 void intel_ring_advance(struct drm_device *dev,
744 struct intel_ring_buffer *ring)
745 {
746 ring->tail &= ring->size - 1;
747 ring->set_tail(dev, ring, ring->tail);
748 }
749
750 void intel_fill_struct(struct drm_device *dev,
751 struct intel_ring_buffer *ring,
752 void *data,
753 unsigned int len)
754 {
755 unsigned int *virt = ring->virtual_start + ring->tail;
756 BUG_ON((len&~(4-1)) != 0);
757 intel_ring_begin(dev, ring, len/4);
758 memcpy(virt, data, len);
759 ring->tail += len;
760 ring->tail &= ring->size - 1;
761 ring->space -= len;
762 intel_ring_advance(dev, ring);
763 }
764
765 static const struct intel_ring_buffer render_ring = {
766 .name = "render ring",
767 .id = RING_RENDER,
768 .mmio_base = RENDER_RING_BASE,
769 .size = 32 * PAGE_SIZE,
770 .setup_status_page = render_setup_status_page,
771 .init = init_render_ring,
772 .set_tail = ring_set_tail,
773 .get_active_head = render_ring_get_active_head,
774 .flush = render_ring_flush,
775 .add_request = render_ring_add_request,
776 .get_gem_seqno = render_ring_get_gem_seqno,
777 .user_irq_get = render_ring_get_user_irq,
778 .user_irq_put = render_ring_put_user_irq,
779 .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
780 };
781
782 /* ring buffer for bit-stream decoder */
783
784 static const struct intel_ring_buffer bsd_ring = {
785 .name = "bsd ring",
786 .id = RING_BSD,
787 .mmio_base = BSD_RING_BASE,
788 .size = 32 * PAGE_SIZE,
789 .setup_status_page = bsd_setup_status_page,
790 .init = init_bsd_ring,
791 .set_tail = ring_set_tail,
792 .get_active_head = bsd_ring_get_active_head,
793 .flush = bsd_ring_flush,
794 .add_request = bsd_ring_add_request,
795 .get_gem_seqno = bsd_ring_get_gem_seqno,
796 .user_irq_get = bsd_ring_get_user_irq,
797 .user_irq_put = bsd_ring_put_user_irq,
798 .dispatch_gem_execbuffer = bsd_ring_dispatch_gem_execbuffer,
799 };
800
801
802 static void gen6_bsd_setup_status_page(struct drm_device *dev,
803 struct intel_ring_buffer *ring)
804 {
805 drm_i915_private_t *dev_priv = dev->dev_private;
806 I915_WRITE(GEN6_BSD_HWS_PGA, ring->status_page.gfx_addr);
807 I915_READ(GEN6_BSD_HWS_PGA);
808 }
809
810 static inline void gen6_bsd_ring_set_tail(struct drm_device *dev,
811 struct intel_ring_buffer *ring,
812 u32 value)
813 {
814 drm_i915_private_t *dev_priv = dev->dev_private;
815
816 /* Every tail move must follow the sequence below */
817 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
818 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
819 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
820 I915_WRITE(GEN6_BSD_RNCID, 0x0);
821
822 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
823 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
824 50))
825 DRM_ERROR("timed out waiting for IDLE Indicator\n");
826
827 I915_WRITE_TAIL(ring, value);
828 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
829 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
830 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
831 }
832
833 static inline unsigned int gen6_bsd_ring_get_active_head(struct drm_device *dev,
834 struct intel_ring_buffer *ring)
835 {
836 drm_i915_private_t *dev_priv = dev->dev_private;
837 return I915_READ(GEN6_BSD_RING_ACTHD);
838 }
839
840 static void gen6_bsd_ring_flush(struct drm_device *dev,
841 struct intel_ring_buffer *ring,
842 u32 invalidate_domains,
843 u32 flush_domains)
844 {
845 intel_ring_begin(dev, ring, 4);
846 intel_ring_emit(dev, ring, MI_FLUSH_DW);
847 intel_ring_emit(dev, ring, 0);
848 intel_ring_emit(dev, ring, 0);
849 intel_ring_emit(dev, ring, 0);
850 intel_ring_advance(dev, ring);
851 }
852
853 static int
854 gen6_bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
855 struct intel_ring_buffer *ring,
856 struct drm_i915_gem_execbuffer2 *exec,
857 struct drm_clip_rect *cliprects,
858 uint64_t exec_offset)
859 {
860 uint32_t exec_start;
861 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
862 intel_ring_begin(dev, ring, 2);
863 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); /* bit0-7 is the length on GEN6+ */
864 intel_ring_emit(dev, ring, exec_start);
865 intel_ring_advance(dev, ring);
866 return 0;
867 }
868
869 /* ring buffer for Video Codec for Gen6+ */
870 static const struct intel_ring_buffer gen6_bsd_ring = {
871 .name = "gen6 bsd ring",
872 .id = RING_BSD,
873 .mmio_base = GEN6_BSD_RING_BASE,
874 .size = 32 * PAGE_SIZE,
875 .setup_status_page = gen6_bsd_setup_status_page,
876 .init = init_bsd_ring,
877 .set_tail = gen6_bsd_ring_set_tail,
878 .get_active_head = gen6_bsd_ring_get_active_head,
879 .flush = gen6_bsd_ring_flush,
880 .add_request = bsd_ring_add_request,
881 .get_gem_seqno = bsd_ring_get_gem_seqno,
882 .user_irq_get = bsd_ring_get_user_irq,
883 .user_irq_put = bsd_ring_put_user_irq,
884 .dispatch_gem_execbuffer = gen6_bsd_ring_dispatch_gem_execbuffer,
885 };
886
887 int intel_init_render_ring_buffer(struct drm_device *dev)
888 {
889 drm_i915_private_t *dev_priv = dev->dev_private;
890
891 dev_priv->render_ring = render_ring;
892
893 if (!I915_NEED_GFX_HWS(dev)) {
894 dev_priv->render_ring.status_page.page_addr
895 = dev_priv->status_page_dmah->vaddr;
896 memset(dev_priv->render_ring.status_page.page_addr,
897 0, PAGE_SIZE);
898 }
899
900 return intel_init_ring_buffer(dev, &dev_priv->render_ring);
901 }
902
903 int intel_init_bsd_ring_buffer(struct drm_device *dev)
904 {
905 drm_i915_private_t *dev_priv = dev->dev_private;
906
907 if (IS_GEN6(dev))
908 dev_priv->bsd_ring = gen6_bsd_ring;
909 else
910 dev_priv->bsd_ring = bsd_ring;
911
912 return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
913 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree