2 * Atmel MultiMedia Card Interface driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef __DRIVERS_MMC_ATMEL_MCI_H__
11 #define __DRIVERS_MMC_ATMEL_MCI_H__
13 /* MCI Register Definitions */
14 #define MCI_CR 0x0000 /* Control */
15 # define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
16 # define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
17 # define MCI_CR_SWRST ( 1 << 7) /* Software Reset */
18 #define MCI_MR 0x0004 /* Mode */
19 # define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
20 # define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
21 # define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
22 #define MCI_DTOR 0x0008 /* Data Timeout */
23 # define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
24 # define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
25 #define MCI_SDCR 0x000c /* SD Card / SDIO */
26 # define MCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */
27 # define MCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */
28 # define MCI_SDCSEL_MASK ( 3 << 0)
29 # define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
30 # define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
31 # define MCI_SDCBUS_MASK ( 3 << 6)
32 #define MCI_ARGR 0x0010 /* Command Argument */
33 #define MCI_CMDR 0x0014 /* Command */
34 # define MCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
35 # define MCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */
36 # define MCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */
37 # define MCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */
38 # define MCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */
39 # define MCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */
40 # define MCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */
41 # define MCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */
42 # define MCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */
43 # define MCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */
44 # define MCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */
45 # define MCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
46 # define MCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
47 # define MCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */
48 # define MCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */
49 # define MCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
50 # define MCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
51 # define MCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
52 # define MCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
53 # define MCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
54 # define MCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */
55 # define MCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */
56 #define MCI_BLKR 0x0018 /* Block */
57 # define MCI_BCNT(x) ((x) << 0) /* Data Block Count */
58 # define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
59 #define MCI_RSPR 0x0020 /* Response 0 */
60 #define MCI_RSPR1 0x0024 /* Response 1 */
61 #define MCI_RSPR2 0x0028 /* Response 2 */
62 #define MCI_RSPR3 0x002c /* Response 3 */
63 #define MCI_RDR 0x0030 /* Receive Data */
64 #define MCI_TDR 0x0034 /* Transmit Data */
65 #define MCI_SR 0x0040 /* Status */
66 #define MCI_IER 0x0044 /* Interrupt Enable */
67 #define MCI_IDR 0x0048 /* Interrupt Disable */
68 #define MCI_IMR 0x004c /* Interrupt Mask */
69 # define MCI_CMDRDY ( 1 << 0) /* Command Ready */
70 # define MCI_RXRDY ( 1 << 1) /* Receiver Ready */
71 # define MCI_TXRDY ( 1 << 2) /* Transmitter Ready */
72 # define MCI_BLKE ( 1 << 3) /* Data Block Ended */
73 # define MCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
74 # define MCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
75 # define MCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
76 # define MCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
77 # define MCI_RINDE ( 1 << 16) /* Response Index Error */
78 # define MCI_RDIRE ( 1 << 17) /* Response Direction Error */
79 # define MCI_RCRCE ( 1 << 18) /* Response CRC Error */
80 # define MCI_RENDE ( 1 << 19) /* Response End Bit Error */
81 # define MCI_RTOE ( 1 << 20) /* Response Time-Out Error */
82 # define MCI_DCRCE ( 1 << 21) /* Data CRC Error */
83 # define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */
84 # define MCI_OVRE ( 1 << 30) /* RX Overrun Error */
85 # define MCI_UNRE ( 1 << 31) /* TX Underrun Error */
87 #define MCI_REGS_SIZE 0x100
89 /* Register access macros */
90 #define mci_readl(port,reg) \
91 __raw_readl((port)->regs + MCI_##reg)
92 #define mci_writel(port,reg,value) \
93 __raw_writel((value), (port)->regs + MCI_##reg)
95 #endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
