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ath9k: Check for NULL sta in ath_tx_start
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobbce313e85cff158161d66e0ae56c58864db307bc
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34
35 #define OFDM_SIFS_TIME 16
36
37 static u16 bits_per_symbol[][2] = {
38 /* 20MHz 40MHz */
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
47 };
48
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50
51 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
61 int nframes, int nbad, int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64
65 enum {
66 MCS_HT20,
67 MCS_HT20_SGI,
68 MCS_HT40,
69 MCS_HT40_SGI,
70 };
71
72 static int ath_max_4ms_framelen[4][32] = {
73 [MCS_HT20] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
78 },
79 [MCS_HT20_SGI] = {
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
84 },
85 [MCS_HT40] = {
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
90 },
91 [MCS_HT40_SGI] = {
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
96 }
97 };
98
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
102
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
104 {
105 struct ath_atx_ac *ac = tid->ac;
106
107 if (tid->paused)
108 return;
109
110 if (tid->sched)
111 return;
112
113 tid->sched = true;
114 list_add_tail(&tid->list, &ac->tid_q);
115
116 if (ac->sched)
117 return;
118
119 ac->sched = true;
120 list_add_tail(&ac->list, &txq->axq_acq);
121 }
122
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
124 {
125 struct ath_txq *txq = tid->ac->txq;
126
127 WARN_ON(!tid->paused);
128
129 spin_lock_bh(&txq->axq_lock);
130 tid->paused = false;
131
132 if (list_empty(&tid->buf_q))
133 goto unlock;
134
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
137 unlock:
138 spin_unlock_bh(&txq->axq_lock);
139 }
140
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 {
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
147 }
148
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 {
151 struct ath_txq *txq = tid->ac->txq;
152 struct ath_buf *bf;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
156
157 INIT_LIST_HEAD(&bf_head);
158
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
161
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
165
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
168 if (fi->retries) {
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
171 } else {
172 ath_tx_send_normal(sc, txq, tid, &bf_head);
173 }
174 spin_lock_bh(&txq->axq_lock);
175 }
176
177 spin_unlock_bh(&txq->axq_lock);
178 }
179
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 int seqno)
182 {
183 int index, cindex;
184
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187
188 __clear_bit(cindex, tid->tx_buf);
189
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
193 }
194 }
195
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 u16 seqno)
198 {
199 int index, cindex;
200
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
204
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
209 }
210 }
211
212 /*
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
216 * forward.
217 */
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
220
221 {
222 struct ath_buf *bf;
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
226
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
229
230 for (;;) {
231 if (list_empty(&tid->buf_q))
232 break;
233
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
236
237 fi = get_frame_info(bf->bf_mpdu);
238 if (fi->retries)
239 ath_tx_update_baw(sc, tid, fi->seqno);
240
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
244 }
245
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
248 }
249
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
251 struct sk_buff *skb)
252 {
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
255
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
258 return;
259
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
262 }
263
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
265 {
266 struct ath_buf *bf = NULL;
267
268 spin_lock_bh(&sc->tx.txbuflock);
269
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
272 return NULL;
273 }
274
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
276 list_del(&bf->list);
277
278 spin_unlock_bh(&sc->tx.txbuflock);
279
280 return bf;
281 }
282
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
284 {
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
288 }
289
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
291 {
292 struct ath_buf *tbf;
293
294 tbf = ath_tx_get_buffer(sc);
295 if (WARN_ON(!tbf))
296 return NULL;
297
298 ATH_TXBUF_RESET(tbf);
299
300 tbf->aphy = bf->aphy;
301 tbf->bf_mpdu = bf->bf_mpdu;
302 tbf->bf_buf_addr = bf->bf_buf_addr;
303 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
304 tbf->bf_state = bf->bf_state;
305
306 return tbf;
307 }
308
309 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
310 struct ath_tx_status *ts, int txok,
311 int *nframes, int *nbad)
312 {
313 struct ath_frame_info *fi;
314 u16 seq_st = 0;
315 u32 ba[WME_BA_BMP_SIZE >> 5];
316 int ba_index;
317 int isaggr = 0;
318
319 *nbad = 0;
320 *nframes = 0;
321
322 isaggr = bf_isaggr(bf);
323 if (isaggr) {
324 seq_st = ts->ts_seqnum;
325 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
326 }
327
328 while (bf) {
329 fi = get_frame_info(bf->bf_mpdu);
330 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
331
332 (*nframes)++;
333 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
334 (*nbad)++;
335
336 bf = bf->bf_next;
337 }
338 }
339
340
341 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
342 struct ath_buf *bf, struct list_head *bf_q,
343 struct ath_tx_status *ts, int txok, bool retry)
344 {
345 struct ath_node *an = NULL;
346 struct sk_buff *skb;
347 struct ieee80211_sta *sta;
348 struct ieee80211_hw *hw;
349 struct ieee80211_hdr *hdr;
350 struct ieee80211_tx_info *tx_info;
351 struct ath_atx_tid *tid = NULL;
352 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
353 struct list_head bf_head, bf_pending;
354 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
355 u32 ba[WME_BA_BMP_SIZE >> 5];
356 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
357 bool rc_update = true;
358 struct ieee80211_tx_rate rates[4];
359 struct ath_frame_info *fi;
360 int nframes;
361 u8 tidno;
362
363 skb = bf->bf_mpdu;
364 hdr = (struct ieee80211_hdr *)skb->data;
365
366 tx_info = IEEE80211_SKB_CB(skb);
367 hw = bf->aphy->hw;
368
369 memcpy(rates, tx_info->control.rates, sizeof(rates));
370
371 rcu_read_lock();
372
373 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
374 if (!sta) {
375 rcu_read_unlock();
376
377 INIT_LIST_HEAD(&bf_head);
378 while (bf) {
379 bf_next = bf->bf_next;
380
381 bf->bf_state.bf_type |= BUF_XRETRY;
382 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
383 !bf->bf_stale || bf_next != NULL)
384 list_move_tail(&bf->list, &bf_head);
385
386 ath_tx_rc_status(bf, ts, 1, 1, 0, false);
387 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
388 0, 0);
389
390 bf = bf_next;
391 }
392 return;
393 }
394
395 an = (struct ath_node *)sta->drv_priv;
396 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
397 tid = ATH_AN_2_TID(an, tidno);
398
399 /*
400 * The hardware occasionally sends a tx status for the wrong TID.
401 * In this case, the BA status cannot be considered valid and all
402 * subframes need to be retransmitted
403 */
404 if (tidno != ts->tid)
405 txok = false;
406
407 isaggr = bf_isaggr(bf);
408 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
409
410 if (isaggr && txok) {
411 if (ts->ts_flags & ATH9K_TX_BA) {
412 seq_st = ts->ts_seqnum;
413 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
414 } else {
415 /*
416 * AR5416 can become deaf/mute when BA
417 * issue happens. Chip needs to be reset.
418 * But AP code may have sychronization issues
419 * when perform internal reset in this routine.
420 * Only enable reset in STA mode for now.
421 */
422 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
423 needreset = 1;
424 }
425 }
426
427 INIT_LIST_HEAD(&bf_pending);
428 INIT_LIST_HEAD(&bf_head);
429
430 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
431 while (bf) {
432 txfail = txpending = 0;
433 bf_next = bf->bf_next;
434
435 skb = bf->bf_mpdu;
436 tx_info = IEEE80211_SKB_CB(skb);
437 fi = get_frame_info(skb);
438
439 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
440 /* transmit completion, subframe is
441 * acked by block ack */
442 acked_cnt++;
443 } else if (!isaggr && txok) {
444 /* transmit completion */
445 acked_cnt++;
446 } else {
447 if (!(tid->state & AGGR_CLEANUP) && retry) {
448 if (fi->retries < ATH_MAX_SW_RETRIES) {
449 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
450 txpending = 1;
451 } else {
452 bf->bf_state.bf_type |= BUF_XRETRY;
453 txfail = 1;
454 sendbar = 1;
455 txfail_cnt++;
456 }
457 } else {
458 /*
459 * cleanup in progress, just fail
460 * the un-acked sub-frames
461 */
462 txfail = 1;
463 }
464 }
465
466 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
467 bf_next == NULL) {
468 /*
469 * Make sure the last desc is reclaimed if it
470 * not a holding desc.
471 */
472 if (!bf_last->bf_stale)
473 list_move_tail(&bf->list, &bf_head);
474 else
475 INIT_LIST_HEAD(&bf_head);
476 } else {
477 BUG_ON(list_empty(bf_q));
478 list_move_tail(&bf->list, &bf_head);
479 }
480
481 if (!txpending || (tid->state & AGGR_CLEANUP)) {
482 /*
483 * complete the acked-ones/xretried ones; update
484 * block-ack window
485 */
486 spin_lock_bh(&txq->axq_lock);
487 ath_tx_update_baw(sc, tid, fi->seqno);
488 spin_unlock_bh(&txq->axq_lock);
489
490 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
491 memcpy(tx_info->control.rates, rates, sizeof(rates));
492 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
493 rc_update = false;
494 } else {
495 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
496 }
497
498 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
499 !txfail, sendbar);
500 } else {
501 /* retry the un-acked ones */
502 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
503 if (bf->bf_next == NULL && bf_last->bf_stale) {
504 struct ath_buf *tbf;
505
506 tbf = ath_clone_txbuf(sc, bf_last);
507 /*
508 * Update tx baw and complete the
509 * frame with failed status if we
510 * run out of tx buf.
511 */
512 if (!tbf) {
513 spin_lock_bh(&txq->axq_lock);
514 ath_tx_update_baw(sc, tid, fi->seqno);
515 spin_unlock_bh(&txq->axq_lock);
516
517 bf->bf_state.bf_type |=
518 BUF_XRETRY;
519 ath_tx_rc_status(bf, ts, nframes,
520 nbad, 0, false);
521 ath_tx_complete_buf(sc, bf, txq,
522 &bf_head,
523 ts, 0, 0);
524 break;
525 }
526
527 ath9k_hw_cleartxdesc(sc->sc_ah,
528 tbf->bf_desc);
529 list_add_tail(&tbf->list, &bf_head);
530 } else {
531 /*
532 * Clear descriptor status words for
533 * software retry
534 */
535 ath9k_hw_cleartxdesc(sc->sc_ah,
536 bf->bf_desc);
537 }
538 }
539
540 /*
541 * Put this buffer to the temporary pending
542 * queue to retain ordering
543 */
544 list_splice_tail_init(&bf_head, &bf_pending);
545 }
546
547 bf = bf_next;
548 }
549
550 /* prepend un-acked frames to the beginning of the pending frame queue */
551 if (!list_empty(&bf_pending)) {
552 spin_lock_bh(&txq->axq_lock);
553 list_splice(&bf_pending, &tid->buf_q);
554 ath_tx_queue_tid(txq, tid);
555 spin_unlock_bh(&txq->axq_lock);
556 }
557
558 if (tid->state & AGGR_CLEANUP) {
559 ath_tx_flush_tid(sc, tid);
560
561 if (tid->baw_head == tid->baw_tail) {
562 tid->state &= ~AGGR_ADDBA_COMPLETE;
563 tid->state &= ~AGGR_CLEANUP;
564 }
565 }
566
567 rcu_read_unlock();
568
569 if (needreset)
570 ath_reset(sc, false);
571 }
572
573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
574 struct ath_atx_tid *tid)
575 {
576 struct sk_buff *skb;
577 struct ieee80211_tx_info *tx_info;
578 struct ieee80211_tx_rate *rates;
579 u32 max_4ms_framelen, frmlen;
580 u16 aggr_limit, legacy = 0;
581 int i;
582
583 skb = bf->bf_mpdu;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
586
587 /*
588 * Find the lowest frame length among the rate series that will have a
589 * 4ms transmit duration.
590 * TODO - TXOP limit needs to be considered.
591 */
592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
593
594 for (i = 0; i < 4; i++) {
595 if (rates[i].count) {
596 int modeidx;
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
598 legacy = 1;
599 break;
600 }
601
602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
603 modeidx = MCS_HT40;
604 else
605 modeidx = MCS_HT20;
606
607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
608 modeidx++;
609
610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
611 max_4ms_framelen = min(max_4ms_framelen, frmlen);
612 }
613 }
614
615 /*
616 * limit aggregate size by the minimum rate if rate selected is
617 * not a probe rate, if rate selected is a probe rate then
618 * avoid aggregation of this packet.
619 */
620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
621 return 0;
622
623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
624 aggr_limit = min((max_4ms_framelen * 3) / 8,
625 (u32)ATH_AMPDU_LIMIT_MAX);
626 else
627 aggr_limit = min(max_4ms_framelen,
628 (u32)ATH_AMPDU_LIMIT_MAX);
629
630 /*
631 * h/w can accept aggregates upto 16 bit lengths (65535).
632 * The IE, however can hold upto 65536, which shows up here
633 * as zero. Ignore 65536 since we are constrained by hw.
634 */
635 if (tid->an->maxampdu)
636 aggr_limit = min(aggr_limit, tid->an->maxampdu);
637
638 return aggr_limit;
639 }
640
641 /*
642 * Returns the number of delimiters to be added to
643 * meet the minimum required mpdudensity.
644 */
645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
646 struct ath_buf *bf, u16 frmlen)
647 {
648 struct sk_buff *skb = bf->bf_mpdu;
649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
650 u32 nsymbits, nsymbols;
651 u16 minlen;
652 u8 flags, rix;
653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
655
656 /* Select standard number of delimiters based on frame length alone */
657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
658
659 /*
660 * If encryption enabled, hardware requires some more padding between
661 * subframes.
662 * TODO - this could be improved to be dependent on the rate.
663 * The hardware can keep up at lower rates, but not higher rates
664 */
665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
666 ndelim += ATH_AGGR_ENCRYPTDELIM;
667
668 /*
669 * Convert desired mpdu density from microeconds to bytes based
670 * on highest rate in rate series (i.e. first rate) to determine
671 * required minimum length for subframe. Take into account
672 * whether high rate is 20 or 40Mhz and half or full GI.
673 *
674 * If there is no mpdu density restriction, no further calculation
675 * is needed.
676 */
677
678 if (tid->an->mpdudensity == 0)
679 return ndelim;
680
681 rix = tx_info->control.rates[0].idx;
682 flags = tx_info->control.rates[0].flags;
683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
685
686 if (half_gi)
687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
688 else
689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
690
691 if (nsymbols == 0)
692 nsymbols = 1;
693
694 streams = HT_RC_2_STREAMS(rix);
695 nsymbits = bits_per_symbol[rix % 8][width] * streams;
696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
697
698 if (frmlen < minlen) {
699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
700 ndelim = max(mindelim, ndelim);
701 }
702
703 return ndelim;
704 }
705
706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
707 struct ath_txq *txq,
708 struct ath_atx_tid *tid,
709 struct list_head *bf_q,
710 int *aggr_len)
711 {
712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
714 int rl = 0, nframes = 0, ndelim, prev_al = 0;
715 u16 aggr_limit = 0, al = 0, bpad = 0,
716 al_delta, h_baw = tid->baw_size / 2;
717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
720
721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
722
723 do {
724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
726
727 /* do not step over block-ack window */
728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
729 status = ATH_AGGR_BAW_CLOSED;
730 break;
731 }
732
733 if (!rl) {
734 aggr_limit = ath_lookup_rate(sc, bf, tid);
735 rl = 1;
736 }
737
738 /* do not exceed aggregation limit */
739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
740
741 if (nframes &&
742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
743 status = ATH_AGGR_LIMITED;
744 break;
745 }
746
747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
750 break;
751
752 /* do not exceed subframe limit */
753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
754 status = ATH_AGGR_LIMITED;
755 break;
756 }
757 nframes++;
758
759 /* add padding for previous frame to aggregation length */
760 al += bpad + al_delta;
761
762 /*
763 * Get the delimiters needed to meet the MPDU
764 * density for this node.
765 */
766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
767 bpad = PADBYTES(al_delta) + (ndelim << 2);
768
769 bf->bf_next = NULL;
770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
771
772 /* link buffers of this frame to the aggregate */
773 if (!fi->retries)
774 ath_tx_addto_baw(sc, tid, fi->seqno);
775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
776 list_move_tail(&bf->list, bf_q);
777 if (bf_prev) {
778 bf_prev->bf_next = bf;
779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
780 bf->bf_daddr);
781 }
782 bf_prev = bf;
783
784 } while (!list_empty(&tid->buf_q));
785
786 *aggr_len = al;
787
788 return status;
789 #undef PADBYTES
790 }
791
792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
793 struct ath_atx_tid *tid)
794 {
795 struct ath_buf *bf;
796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
798 struct list_head bf_q;
799 int aggr_len;
800
801 do {
802 if (list_empty(&tid->buf_q))
803 return;
804
805 INIT_LIST_HEAD(&bf_q);
806
807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
808
809 /*
810 * no frames picked up to be aggregated;
811 * block-ack window is not open.
812 */
813 if (list_empty(&bf_q))
814 break;
815
816 bf = list_first_entry(&bf_q, struct ath_buf, list);
817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
818
819 /* if only one frame, send as non-aggregate */
820 if (bf == bf->bf_lastbf) {
821 fi = get_frame_info(bf->bf_mpdu);
822
823 bf->bf_state.bf_type &= ~BUF_AGGR;
824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
825 ath_buf_set_rate(sc, bf, fi->framelen);
826 ath_tx_txqaddbuf(sc, txq, &bf_q);
827 continue;
828 }
829
830 /* setup first desc of aggregate */
831 bf->bf_state.bf_type |= BUF_AGGR;
832 ath_buf_set_rate(sc, bf, aggr_len);
833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
834
835 /* anchor last desc of aggregate */
836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
837
838 ath_tx_txqaddbuf(sc, txq, &bf_q);
839 TX_STAT_INC(txq->axq_qnum, a_aggr);
840
841 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
842 status != ATH_AGGR_BAW_CLOSED);
843 }
844
845 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
846 u16 tid, u16 *ssn)
847 {
848 struct ath_atx_tid *txtid;
849 struct ath_node *an;
850
851 an = (struct ath_node *)sta->drv_priv;
852 txtid = ATH_AN_2_TID(an, tid);
853
854 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
855 return -EAGAIN;
856
857 txtid->state |= AGGR_ADDBA_PROGRESS;
858 txtid->paused = true;
859 *ssn = txtid->seq_start;
860
861 return 0;
862 }
863
864 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
865 {
866 struct ath_node *an = (struct ath_node *)sta->drv_priv;
867 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
868 struct ath_txq *txq = txtid->ac->txq;
869
870 if (txtid->state & AGGR_CLEANUP)
871 return;
872
873 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
874 txtid->state &= ~AGGR_ADDBA_PROGRESS;
875 return;
876 }
877
878 spin_lock_bh(&txq->axq_lock);
879 txtid->paused = true;
880
881 /*
882 * If frames are still being transmitted for this TID, they will be
883 * cleaned up during tx completion. To prevent race conditions, this
884 * TID can only be reused after all in-progress subframes have been
885 * completed.
886 */
887 if (txtid->baw_head != txtid->baw_tail)
888 txtid->state |= AGGR_CLEANUP;
889 else
890 txtid->state &= ~AGGR_ADDBA_COMPLETE;
891 spin_unlock_bh(&txq->axq_lock);
892
893 ath_tx_flush_tid(sc, txtid);
894 }
895
896 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
897 {
898 struct ath_atx_tid *txtid;
899 struct ath_node *an;
900
901 an = (struct ath_node *)sta->drv_priv;
902
903 if (sc->sc_flags & SC_OP_TXAGGR) {
904 txtid = ATH_AN_2_TID(an, tid);
905 txtid->baw_size =
906 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
907 txtid->state |= AGGR_ADDBA_COMPLETE;
908 txtid->state &= ~AGGR_ADDBA_PROGRESS;
909 ath_tx_resume_tid(sc, txtid);
910 }
911 }
912
913 /********************/
914 /* Queue Management */
915 /********************/
916
917 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
918 struct ath_txq *txq)
919 {
920 struct ath_atx_ac *ac, *ac_tmp;
921 struct ath_atx_tid *tid, *tid_tmp;
922
923 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
924 list_del(&ac->list);
925 ac->sched = false;
926 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
927 list_del(&tid->list);
928 tid->sched = false;
929 ath_tid_drain(sc, txq, tid);
930 }
931 }
932 }
933
934 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
935 {
936 struct ath_hw *ah = sc->sc_ah;
937 struct ath_common *common = ath9k_hw_common(ah);
938 struct ath9k_tx_queue_info qi;
939 static const int subtype_txq_to_hwq[] = {
940 [WME_AC_BE] = ATH_TXQ_AC_BE,
941 [WME_AC_BK] = ATH_TXQ_AC_BK,
942 [WME_AC_VI] = ATH_TXQ_AC_VI,
943 [WME_AC_VO] = ATH_TXQ_AC_VO,
944 };
945 int qnum, i;
946
947 memset(&qi, 0, sizeof(qi));
948 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
949 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
950 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
951 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
952 qi.tqi_physCompBuf = 0;
953
954 /*
955 * Enable interrupts only for EOL and DESC conditions.
956 * We mark tx descriptors to receive a DESC interrupt
957 * when a tx queue gets deep; otherwise waiting for the
958 * EOL to reap descriptors. Note that this is done to
959 * reduce interrupt load and this only defers reaping
960 * descriptors, never transmitting frames. Aside from
961 * reducing interrupts this also permits more concurrency.
962 * The only potential downside is if the tx queue backs
963 * up in which case the top half of the kernel may backup
964 * due to a lack of tx descriptors.
965 *
966 * The UAPSD queue is an exception, since we take a desc-
967 * based intr on the EOSP frames.
968 */
969 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
970 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
971 TXQ_FLAG_TXERRINT_ENABLE;
972 } else {
973 if (qtype == ATH9K_TX_QUEUE_UAPSD)
974 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
975 else
976 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
977 TXQ_FLAG_TXDESCINT_ENABLE;
978 }
979 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
980 if (qnum == -1) {
981 /*
982 * NB: don't print a message, this happens
983 * normally on parts with too few tx queues
984 */
985 return NULL;
986 }
987 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
988 ath_err(common, "qnum %u out of range, max %zu!\n",
989 qnum, ARRAY_SIZE(sc->tx.txq));
990 ath9k_hw_releasetxqueue(ah, qnum);
991 return NULL;
992 }
993 if (!ATH_TXQ_SETUP(sc, qnum)) {
994 struct ath_txq *txq = &sc->tx.txq[qnum];
995
996 txq->axq_qnum = qnum;
997 txq->axq_link = NULL;
998 INIT_LIST_HEAD(&txq->axq_q);
999 INIT_LIST_HEAD(&txq->axq_acq);
1000 spin_lock_init(&txq->axq_lock);
1001 txq->axq_depth = 0;
1002 txq->axq_tx_inprogress = false;
1003 sc->tx.txqsetup |= 1<<qnum;
1004
1005 txq->txq_headidx = txq->txq_tailidx = 0;
1006 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1007 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1008 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1009 }
1010 return &sc->tx.txq[qnum];
1011 }
1012
1013 int ath_txq_update(struct ath_softc *sc, int qnum,
1014 struct ath9k_tx_queue_info *qinfo)
1015 {
1016 struct ath_hw *ah = sc->sc_ah;
1017 int error = 0;
1018 struct ath9k_tx_queue_info qi;
1019
1020 if (qnum == sc->beacon.beaconq) {
1021 /*
1022 * XXX: for beacon queue, we just save the parameter.
1023 * It will be picked up by ath_beaconq_config when
1024 * it's necessary.
1025 */
1026 sc->beacon.beacon_qi = *qinfo;
1027 return 0;
1028 }
1029
1030 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1031
1032 ath9k_hw_get_txq_props(ah, qnum, &qi);
1033 qi.tqi_aifs = qinfo->tqi_aifs;
1034 qi.tqi_cwmin = qinfo->tqi_cwmin;
1035 qi.tqi_cwmax = qinfo->tqi_cwmax;
1036 qi.tqi_burstTime = qinfo->tqi_burstTime;
1037 qi.tqi_readyTime = qinfo->tqi_readyTime;
1038
1039 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1040 ath_err(ath9k_hw_common(sc->sc_ah),
1041 "Unable to update hardware queue %u!\n", qnum);
1042 error = -EIO;
1043 } else {
1044 ath9k_hw_resettxqueue(ah, qnum);
1045 }
1046
1047 return error;
1048 }
1049
1050 int ath_cabq_update(struct ath_softc *sc)
1051 {
1052 struct ath9k_tx_queue_info qi;
1053 int qnum = sc->beacon.cabq->axq_qnum;
1054
1055 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1056 /*
1057 * Ensure the readytime % is within the bounds.
1058 */
1059 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1060 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1061 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1062 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1063
1064 qi.tqi_readyTime = (sc->beacon_interval *
1065 sc->config.cabqReadytime) / 100;
1066 ath_txq_update(sc, qnum, &qi);
1067
1068 return 0;
1069 }
1070
1071 /*
1072 * Drain a given TX queue (could be Beacon or Data)
1073 *
1074 * This assumes output has been stopped and
1075 * we do not need to block ath_tx_tasklet.
1076 */
1077 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1078 {
1079 struct ath_buf *bf, *lastbf;
1080 struct list_head bf_head;
1081 struct ath_tx_status ts;
1082
1083 memset(&ts, 0, sizeof(ts));
1084 INIT_LIST_HEAD(&bf_head);
1085
1086 for (;;) {
1087 spin_lock_bh(&txq->axq_lock);
1088
1089 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1090 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1091 txq->txq_headidx = txq->txq_tailidx = 0;
1092 spin_unlock_bh(&txq->axq_lock);
1093 break;
1094 } else {
1095 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1096 struct ath_buf, list);
1097 }
1098 } else {
1099 if (list_empty(&txq->axq_q)) {
1100 txq->axq_link = NULL;
1101 spin_unlock_bh(&txq->axq_lock);
1102 break;
1103 }
1104 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1105 list);
1106
1107 if (bf->bf_stale) {
1108 list_del(&bf->list);
1109 spin_unlock_bh(&txq->axq_lock);
1110
1111 ath_tx_return_buffer(sc, bf);
1112 continue;
1113 }
1114 }
1115
1116 lastbf = bf->bf_lastbf;
1117
1118 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1119 list_cut_position(&bf_head,
1120 &txq->txq_fifo[txq->txq_tailidx],
1121 &lastbf->list);
1122 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1123 } else {
1124 /* remove ath_buf's of the same mpdu from txq */
1125 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1126 }
1127
1128 txq->axq_depth--;
1129
1130 spin_unlock_bh(&txq->axq_lock);
1131
1132 if (bf_isampdu(bf))
1133 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1134 retry_tx);
1135 else
1136 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1137 }
1138
1139 spin_lock_bh(&txq->axq_lock);
1140 txq->axq_tx_inprogress = false;
1141 spin_unlock_bh(&txq->axq_lock);
1142
1143 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1144 spin_lock_bh(&txq->axq_lock);
1145 while (!list_empty(&txq->txq_fifo_pending)) {
1146 bf = list_first_entry(&txq->txq_fifo_pending,
1147 struct ath_buf, list);
1148 list_cut_position(&bf_head,
1149 &txq->txq_fifo_pending,
1150 &bf->bf_lastbf->list);
1151 spin_unlock_bh(&txq->axq_lock);
1152
1153 if (bf_isampdu(bf))
1154 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1155 &ts, 0, retry_tx);
1156 else
1157 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1158 &ts, 0, 0);
1159 spin_lock_bh(&txq->axq_lock);
1160 }
1161 spin_unlock_bh(&txq->axq_lock);
1162 }
1163
1164 /* flush any pending frames if aggregation is enabled */
1165 if (sc->sc_flags & SC_OP_TXAGGR) {
1166 if (!retry_tx) {
1167 spin_lock_bh(&txq->axq_lock);
1168 ath_txq_drain_pending_buffers(sc, txq);
1169 spin_unlock_bh(&txq->axq_lock);
1170 }
1171 }
1172 }
1173
1174 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1175 {
1176 struct ath_hw *ah = sc->sc_ah;
1177 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1178 struct ath_txq *txq;
1179 int i, npend = 0;
1180
1181 if (sc->sc_flags & SC_OP_INVALID)
1182 return;
1183
1184 /* Stop beacon queue */
1185 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1186
1187 /* Stop data queues */
1188 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1189 if (ATH_TXQ_SETUP(sc, i)) {
1190 txq = &sc->tx.txq[i];
1191 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1192 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1193 }
1194 }
1195
1196 if (npend) {
1197 int r;
1198
1199 ath_err(common, "Failed to stop TX DMA. Resetting hardware!\n");
1200
1201 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1202 if (r)
1203 ath_err(common,
1204 "Unable to reset hardware; reset status %d\n",
1205 r);
1206 }
1207
1208 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1209 if (ATH_TXQ_SETUP(sc, i))
1210 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1211 }
1212 }
1213
1214 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1215 {
1216 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1217 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1218 }
1219
1220 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1221 {
1222 struct ath_atx_ac *ac;
1223 struct ath_atx_tid *tid;
1224
1225 if (list_empty(&txq->axq_acq))
1226 return;
1227
1228 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1229 list_del(&ac->list);
1230 ac->sched = false;
1231
1232 do {
1233 if (list_empty(&ac->tid_q))
1234 return;
1235
1236 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1237 list_del(&tid->list);
1238 tid->sched = false;
1239
1240 if (tid->paused)
1241 continue;
1242
1243 ath_tx_sched_aggr(sc, txq, tid);
1244
1245 /*
1246 * add tid to round-robin queue if more frames
1247 * are pending for the tid
1248 */
1249 if (!list_empty(&tid->buf_q))
1250 ath_tx_queue_tid(txq, tid);
1251
1252 break;
1253 } while (!list_empty(&ac->tid_q));
1254
1255 if (!list_empty(&ac->tid_q)) {
1256 if (!ac->sched) {
1257 ac->sched = true;
1258 list_add_tail(&ac->list, &txq->axq_acq);
1259 }
1260 }
1261 }
1262
1263 /***********/
1264 /* TX, DMA */
1265 /***********/
1266
1267 /*
1268 * Insert a chain of ath_buf (descriptors) on a txq and
1269 * assume the descriptors are already chained together by caller.
1270 */
1271 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1272 struct list_head *head)
1273 {
1274 struct ath_hw *ah = sc->sc_ah;
1275 struct ath_common *common = ath9k_hw_common(ah);
1276 struct ath_buf *bf;
1277
1278 /*
1279 * Insert the frame on the outbound list and
1280 * pass it on to the hardware.
1281 */
1282
1283 if (list_empty(head))
1284 return;
1285
1286 bf = list_first_entry(head, struct ath_buf, list);
1287
1288 ath_dbg(common, ATH_DBG_QUEUE,
1289 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1290
1291 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1292 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1293 list_splice_tail_init(head, &txq->txq_fifo_pending);
1294 return;
1295 }
1296 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1297 ath_dbg(common, ATH_DBG_XMIT,
1298 "Initializing tx fifo %d which is non-empty\n",
1299 txq->txq_headidx);
1300 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1301 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1302 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1303 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1304 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1305 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1306 } else {
1307 list_splice_tail_init(head, &txq->axq_q);
1308
1309 if (txq->axq_link == NULL) {
1310 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1311 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1312 txq->axq_qnum, ito64(bf->bf_daddr),
1313 bf->bf_desc);
1314 } else {
1315 *txq->axq_link = bf->bf_daddr;
1316 ath_dbg(common, ATH_DBG_XMIT,
1317 "link[%u] (%p)=%llx (%p)\n",
1318 txq->axq_qnum, txq->axq_link,
1319 ito64(bf->bf_daddr), bf->bf_desc);
1320 }
1321 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1322 &txq->axq_link);
1323 ath9k_hw_txstart(ah, txq->axq_qnum);
1324 }
1325 txq->axq_depth++;
1326 }
1327
1328 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1329 struct ath_buf *bf, struct ath_tx_control *txctl)
1330 {
1331 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1332 struct list_head bf_head;
1333
1334 bf->bf_state.bf_type |= BUF_AMPDU;
1335 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1336
1337 /*
1338 * Do not queue to h/w when any of the following conditions is true:
1339 * - there are pending frames in software queue
1340 * - the TID is currently paused for ADDBA/BAR request
1341 * - seqno is not within block-ack window
1342 * - h/w queue depth exceeds low water mark
1343 */
1344 if (!list_empty(&tid->buf_q) || tid->paused ||
1345 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1346 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1347 /*
1348 * Add this frame to software queue for scheduling later
1349 * for aggregation.
1350 */
1351 list_add_tail(&bf->list, &tid->buf_q);
1352 ath_tx_queue_tid(txctl->txq, tid);
1353 return;
1354 }
1355
1356 INIT_LIST_HEAD(&bf_head);
1357 list_add(&bf->list, &bf_head);
1358
1359 /* Add sub-frame to BAW */
1360 if (!fi->retries)
1361 ath_tx_addto_baw(sc, tid, fi->seqno);
1362
1363 /* Queue to h/w without aggregation */
1364 bf->bf_lastbf = bf;
1365 ath_buf_set_rate(sc, bf, fi->framelen);
1366 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1367 }
1368
1369 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1370 struct ath_atx_tid *tid,
1371 struct list_head *bf_head)
1372 {
1373 struct ath_frame_info *fi;
1374 struct ath_buf *bf;
1375
1376 bf = list_first_entry(bf_head, struct ath_buf, list);
1377 bf->bf_state.bf_type &= ~BUF_AMPDU;
1378
1379 /* update starting sequence number for subsequent ADDBA request */
1380 if (tid)
1381 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1382
1383 bf->bf_lastbf = bf;
1384 fi = get_frame_info(bf->bf_mpdu);
1385 ath_buf_set_rate(sc, bf, fi->framelen);
1386 ath_tx_txqaddbuf(sc, txq, bf_head);
1387 TX_STAT_INC(txq->axq_qnum, queued);
1388 }
1389
1390 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1391 {
1392 struct ieee80211_hdr *hdr;
1393 enum ath9k_pkt_type htype;
1394 __le16 fc;
1395
1396 hdr = (struct ieee80211_hdr *)skb->data;
1397 fc = hdr->frame_control;
1398
1399 if (ieee80211_is_beacon(fc))
1400 htype = ATH9K_PKT_TYPE_BEACON;
1401 else if (ieee80211_is_probe_resp(fc))
1402 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1403 else if (ieee80211_is_atim(fc))
1404 htype = ATH9K_PKT_TYPE_ATIM;
1405 else if (ieee80211_is_pspoll(fc))
1406 htype = ATH9K_PKT_TYPE_PSPOLL;
1407 else
1408 htype = ATH9K_PKT_TYPE_NORMAL;
1409
1410 return htype;
1411 }
1412
1413 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1414 int framelen)
1415 {
1416 struct ath_wiphy *aphy = hw->priv;
1417 struct ath_softc *sc = aphy->sc;
1418 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1419 struct ieee80211_sta *sta = tx_info->control.sta;
1420 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1421 struct ieee80211_hdr *hdr;
1422 struct ath_frame_info *fi = get_frame_info(skb);
1423 struct ath_node *an;
1424 struct ath_atx_tid *tid;
1425 enum ath9k_key_type keytype;
1426 u16 seqno = 0;
1427 u8 tidno;
1428
1429 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1430
1431 hdr = (struct ieee80211_hdr *)skb->data;
1432 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1433 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1434
1435 an = (struct ath_node *) sta->drv_priv;
1436 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1437
1438 /*
1439 * Override seqno set by upper layer with the one
1440 * in tx aggregation state.
1441 */
1442 tid = ATH_AN_2_TID(an, tidno);
1443 seqno = tid->seq_next;
1444 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1445 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1446 }
1447
1448 memset(fi, 0, sizeof(*fi));
1449 if (hw_key)
1450 fi->keyix = hw_key->hw_key_idx;
1451 else
1452 fi->keyix = ATH9K_TXKEYIX_INVALID;
1453 fi->keytype = keytype;
1454 fi->framelen = framelen;
1455 fi->seqno = seqno;
1456 }
1457
1458 static int setup_tx_flags(struct sk_buff *skb)
1459 {
1460 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1461 int flags = 0;
1462
1463 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1464 flags |= ATH9K_TXDESC_INTREQ;
1465
1466 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1467 flags |= ATH9K_TXDESC_NOACK;
1468
1469 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1470 flags |= ATH9K_TXDESC_LDPC;
1471
1472 return flags;
1473 }
1474
1475 /*
1476 * rix - rate index
1477 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1478 * width - 0 for 20 MHz, 1 for 40 MHz
1479 * half_gi - to use 4us v/s 3.6 us for symbol time
1480 */
1481 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1482 int width, int half_gi, bool shortPreamble)
1483 {
1484 u32 nbits, nsymbits, duration, nsymbols;
1485 int streams;
1486
1487 /* find number of symbols: PLCP + data */
1488 streams = HT_RC_2_STREAMS(rix);
1489 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1490 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1491 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1492
1493 if (!half_gi)
1494 duration = SYMBOL_TIME(nsymbols);
1495 else
1496 duration = SYMBOL_TIME_HALFGI(nsymbols);
1497
1498 /* addup duration for legacy/ht training and signal fields */
1499 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1500
1501 return duration;
1502 }
1503
1504 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1505 {
1506 struct ath_hw *ah = sc->sc_ah;
1507 struct ath9k_channel *curchan = ah->curchan;
1508 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1509 (curchan->channelFlags & CHANNEL_5GHZ) &&
1510 (chainmask == 0x7) && (rate < 0x90))
1511 return 0x3;
1512 else
1513 return chainmask;
1514 }
1515
1516 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1517 {
1518 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1519 struct ath9k_11n_rate_series series[4];
1520 struct sk_buff *skb;
1521 struct ieee80211_tx_info *tx_info;
1522 struct ieee80211_tx_rate *rates;
1523 const struct ieee80211_rate *rate;
1524 struct ieee80211_hdr *hdr;
1525 int i, flags = 0;
1526 u8 rix = 0, ctsrate = 0;
1527 bool is_pspoll;
1528
1529 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1530
1531 skb = bf->bf_mpdu;
1532 tx_info = IEEE80211_SKB_CB(skb);
1533 rates = tx_info->control.rates;
1534 hdr = (struct ieee80211_hdr *)skb->data;
1535 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1536
1537 /*
1538 * We check if Short Preamble is needed for the CTS rate by
1539 * checking the BSS's global flag.
1540 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1541 */
1542 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1543 ctsrate = rate->hw_value;
1544 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1545 ctsrate |= rate->hw_value_short;
1546
1547 for (i = 0; i < 4; i++) {
1548 bool is_40, is_sgi, is_sp;
1549 int phy;
1550
1551 if (!rates[i].count || (rates[i].idx < 0))
1552 continue;
1553
1554 rix = rates[i].idx;
1555 series[i].Tries = rates[i].count;
1556
1557 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1558 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1559 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1560 flags |= ATH9K_TXDESC_RTSENA;
1561 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1562 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1563 flags |= ATH9K_TXDESC_CTSENA;
1564 }
1565
1566 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1567 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1568 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1569 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1570
1571 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1572 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1573 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1574
1575 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1576 /* MCS rates */
1577 series[i].Rate = rix | 0x80;
1578 series[i].ChSel = ath_txchainmask_reduction(sc,
1579 common->tx_chainmask, series[i].Rate);
1580 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1581 is_40, is_sgi, is_sp);
1582 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1583 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1584 continue;
1585 }
1586
1587 /* legacy rates */
1588 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1589 !(rate->flags & IEEE80211_RATE_ERP_G))
1590 phy = WLAN_RC_PHY_CCK;
1591 else
1592 phy = WLAN_RC_PHY_OFDM;
1593
1594 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1595 series[i].Rate = rate->hw_value;
1596 if (rate->hw_value_short) {
1597 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1598 series[i].Rate |= rate->hw_value_short;
1599 } else {
1600 is_sp = false;
1601 }
1602
1603 if (bf->bf_state.bfs_paprd)
1604 series[i].ChSel = common->tx_chainmask;
1605 else
1606 series[i].ChSel = ath_txchainmask_reduction(sc,
1607 common->tx_chainmask, series[i].Rate);
1608
1609 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1610 phy, rate->bitrate * 100, len, rix, is_sp);
1611 }
1612
1613 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1614 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1615 flags &= ~ATH9K_TXDESC_RTSENA;
1616
1617 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1618 if (flags & ATH9K_TXDESC_RTSENA)
1619 flags &= ~ATH9K_TXDESC_CTSENA;
1620
1621 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1622 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1623 bf->bf_lastbf->bf_desc,
1624 !is_pspoll, ctsrate,
1625 0, series, 4, flags);
1626
1627 if (sc->config.ath_aggr_prot && flags)
1628 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1629 }
1630
1631 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1632 struct ath_txq *txq,
1633 struct sk_buff *skb)
1634 {
1635 struct ath_wiphy *aphy = hw->priv;
1636 struct ath_softc *sc = aphy->sc;
1637 struct ath_hw *ah = sc->sc_ah;
1638 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1639 struct ath_frame_info *fi = get_frame_info(skb);
1640 struct ath_buf *bf;
1641 struct ath_desc *ds;
1642 int frm_type;
1643
1644 bf = ath_tx_get_buffer(sc);
1645 if (!bf) {
1646 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1647 return NULL;
1648 }
1649
1650 ATH_TXBUF_RESET(bf);
1651
1652 bf->aphy = aphy;
1653 bf->bf_flags = setup_tx_flags(skb);
1654 bf->bf_mpdu = skb;
1655
1656 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1657 skb->len, DMA_TO_DEVICE);
1658 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1659 bf->bf_mpdu = NULL;
1660 bf->bf_buf_addr = 0;
1661 ath_err(ath9k_hw_common(sc->sc_ah),
1662 "dma_mapping_error() on TX\n");
1663 ath_tx_return_buffer(sc, bf);
1664 return NULL;
1665 }
1666
1667 frm_type = get_hw_packet_type(skb);
1668
1669 ds = bf->bf_desc;
1670 ath9k_hw_set_desc_link(ah, ds, 0);
1671
1672 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1673 fi->keyix, fi->keytype, bf->bf_flags);
1674
1675 ath9k_hw_filltxdesc(ah, ds,
1676 skb->len, /* segment length */
1677 true, /* first segment */
1678 true, /* last segment */
1679 ds, /* first descriptor */
1680 bf->bf_buf_addr,
1681 txq->axq_qnum);
1682
1683
1684 return bf;
1685 }
1686
1687 /* FIXME: tx power */
1688 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1689 struct ath_tx_control *txctl)
1690 {
1691 struct sk_buff *skb = bf->bf_mpdu;
1692 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1693 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1694 struct list_head bf_head;
1695 struct ath_atx_tid *tid;
1696 u8 tidno;
1697
1698 spin_lock_bh(&txctl->txq->axq_lock);
1699
1700 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && txctl->an) {
1701 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1702 IEEE80211_QOS_CTL_TID_MASK;
1703 tid = ATH_AN_2_TID(txctl->an, tidno);
1704
1705 WARN_ON(tid->ac->txq != txctl->txq);
1706 /*
1707 * Try aggregation if it's a unicast data frame
1708 * and the destination is HT capable.
1709 */
1710 ath_tx_send_ampdu(sc, tid, bf, txctl);
1711 } else {
1712 INIT_LIST_HEAD(&bf_head);
1713 list_add_tail(&bf->list, &bf_head);
1714
1715 bf->bf_state.bfs_ftype = txctl->frame_type;
1716 bf->bf_state.bfs_paprd = txctl->paprd;
1717
1718 if (bf->bf_state.bfs_paprd)
1719 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1720 bf->bf_state.bfs_paprd);
1721
1722 ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
1723 }
1724
1725 spin_unlock_bh(&txctl->txq->axq_lock);
1726 }
1727
1728 /* Upon failure caller should free skb */
1729 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1730 struct ath_tx_control *txctl)
1731 {
1732 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1733 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1734 struct ieee80211_sta *sta = info->control.sta;
1735 struct ath_wiphy *aphy = hw->priv;
1736 struct ath_softc *sc = aphy->sc;
1737 struct ath_txq *txq = txctl->txq;
1738 struct ath_buf *bf;
1739 int padpos, padsize;
1740 int frmlen = skb->len + FCS_LEN;
1741 int q;
1742
1743 /* NOTE: sta can be NULL according to net/mac80211.h */
1744 if (sta)
1745 txctl->an = (struct ath_node *)sta->drv_priv;
1746
1747 if (info->control.hw_key)
1748 frmlen += info->control.hw_key->icv_len;
1749
1750 /*
1751 * As a temporary workaround, assign seq# here; this will likely need
1752 * to be cleaned up to work better with Beacon transmission and virtual
1753 * BSSes.
1754 */
1755 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1756 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1757 sc->tx.seq_no += 0x10;
1758 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1759 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1760 }
1761
1762 /* Add the padding after the header if this is not already done */
1763 padpos = ath9k_cmn_padpos(hdr->frame_control);
1764 padsize = padpos & 3;
1765 if (padsize && skb->len > padpos) {
1766 if (skb_headroom(skb) < padsize)
1767 return -ENOMEM;
1768
1769 skb_push(skb, padsize);
1770 memmove(skb->data, skb->data + padsize, padpos);
1771 }
1772
1773 setup_frame_info(hw, skb, frmlen);
1774
1775 /*
1776 * At this point, the vif, hw_key and sta pointers in the tx control
1777 * info are no longer valid (overwritten by the ath_frame_info data.
1778 */
1779
1780 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1781 if (unlikely(!bf))
1782 return -ENOMEM;
1783
1784 q = skb_get_queue_mapping(skb);
1785 spin_lock_bh(&txq->axq_lock);
1786 if (txq == sc->tx.txq_map[q] &&
1787 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1788 ath_mac80211_stop_queue(sc, q);
1789 txq->stopped = 1;
1790 }
1791 spin_unlock_bh(&txq->axq_lock);
1792
1793 ath_tx_start_dma(sc, bf, txctl);
1794
1795 return 0;
1796 }
1797
1798 /*****************/
1799 /* TX Completion */
1800 /*****************/
1801
1802 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1803 struct ath_wiphy *aphy, int tx_flags, int ftype,
1804 struct ath_txq *txq)
1805 {
1806 struct ieee80211_hw *hw = sc->hw;
1807 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1808 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1809 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1810 int q, padpos, padsize;
1811
1812 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1813
1814 if (aphy)
1815 hw = aphy->hw;
1816
1817 if (tx_flags & ATH_TX_BAR)
1818 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1819
1820 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1821 /* Frame was ACKed */
1822 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1823 }
1824
1825 padpos = ath9k_cmn_padpos(hdr->frame_control);
1826 padsize = padpos & 3;
1827 if (padsize && skb->len>padpos+padsize) {
1828 /*
1829 * Remove MAC header padding before giving the frame back to
1830 * mac80211.
1831 */
1832 memmove(skb->data + padsize, skb->data, padpos);
1833 skb_pull(skb, padsize);
1834 }
1835
1836 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1837 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1838 ath_dbg(common, ATH_DBG_PS,
1839 "Going back to sleep after having received TX status (0x%lx)\n",
1840 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1841 PS_WAIT_FOR_CAB |
1842 PS_WAIT_FOR_PSPOLL_DATA |
1843 PS_WAIT_FOR_TX_ACK));
1844 }
1845
1846 if (unlikely(ftype))
1847 ath9k_tx_status(hw, skb, ftype);
1848 else {
1849 q = skb_get_queue_mapping(skb);
1850 if (txq == sc->tx.txq_map[q]) {
1851 spin_lock_bh(&txq->axq_lock);
1852 if (WARN_ON(--txq->pending_frames < 0))
1853 txq->pending_frames = 0;
1854 spin_unlock_bh(&txq->axq_lock);
1855 }
1856
1857 ieee80211_tx_status(hw, skb);
1858 }
1859 }
1860
1861 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1862 struct ath_txq *txq, struct list_head *bf_q,
1863 struct ath_tx_status *ts, int txok, int sendbar)
1864 {
1865 struct sk_buff *skb = bf->bf_mpdu;
1866 unsigned long flags;
1867 int tx_flags = 0;
1868
1869 if (sendbar)
1870 tx_flags = ATH_TX_BAR;
1871
1872 if (!txok) {
1873 tx_flags |= ATH_TX_ERROR;
1874
1875 if (bf_isxretried(bf))
1876 tx_flags |= ATH_TX_XRETRY;
1877 }
1878
1879 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1880 bf->bf_buf_addr = 0;
1881
1882 if (bf->bf_state.bfs_paprd) {
1883 if (!sc->paprd_pending)
1884 dev_kfree_skb_any(skb);
1885 else
1886 complete(&sc->paprd_complete);
1887 } else {
1888 ath_debug_stat_tx(sc, bf, ts);
1889 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1890 bf->bf_state.bfs_ftype, txq);
1891 }
1892 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1893 * accidentally reference it later.
1894 */
1895 bf->bf_mpdu = NULL;
1896
1897 /*
1898 * Return the list of ath_buf of this mpdu to free queue
1899 */
1900 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1901 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1902 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1903 }
1904
1905 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1906 int nframes, int nbad, int txok, bool update_rc)
1907 {
1908 struct sk_buff *skb = bf->bf_mpdu;
1909 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1910 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1911 struct ieee80211_hw *hw = bf->aphy->hw;
1912 struct ath_softc *sc = bf->aphy->sc;
1913 struct ath_hw *ah = sc->sc_ah;
1914 u8 i, tx_rateindex;
1915
1916 if (txok)
1917 tx_info->status.ack_signal = ts->ts_rssi;
1918
1919 tx_rateindex = ts->ts_rateindex;
1920 WARN_ON(tx_rateindex >= hw->max_rates);
1921
1922 if (ts->ts_status & ATH9K_TXERR_FILT)
1923 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1924 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1925 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1926
1927 BUG_ON(nbad > nframes);
1928
1929 tx_info->status.ampdu_len = nframes;
1930 tx_info->status.ampdu_ack_len = nframes - nbad;
1931 }
1932
1933 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1934 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1935 /*
1936 * If an underrun error is seen assume it as an excessive
1937 * retry only if max frame trigger level has been reached
1938 * (2 KB for single stream, and 4 KB for dual stream).
1939 * Adjust the long retry as if the frame was tried
1940 * hw->max_rate_tries times to affect how rate control updates
1941 * PER for the failed rate.
1942 * In case of congestion on the bus penalizing this type of
1943 * underruns should help hardware actually transmit new frames
1944 * successfully by eventually preferring slower rates.
1945 * This itself should also alleviate congestion on the bus.
1946 */
1947 if (ieee80211_is_data(hdr->frame_control) &&
1948 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1949 ATH9K_TX_DELIM_UNDERRUN)) &&
1950 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1951 tx_info->status.rates[tx_rateindex].count =
1952 hw->max_rate_tries;
1953 }
1954
1955 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1956 tx_info->status.rates[i].count = 0;
1957 tx_info->status.rates[i].idx = -1;
1958 }
1959
1960 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1961 }
1962
1963 static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
1964 {
1965 struct ath_txq *txq;
1966
1967 txq = sc->tx.txq_map[qnum];
1968 spin_lock_bh(&txq->axq_lock);
1969 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1970 if (ath_mac80211_start_queue(sc, qnum))
1971 txq->stopped = 0;
1972 }
1973 spin_unlock_bh(&txq->axq_lock);
1974 }
1975
1976 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1977 {
1978 struct ath_hw *ah = sc->sc_ah;
1979 struct ath_common *common = ath9k_hw_common(ah);
1980 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1981 struct list_head bf_head;
1982 struct ath_desc *ds;
1983 struct ath_tx_status ts;
1984 int txok;
1985 int status;
1986 int qnum;
1987
1988 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1989 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1990 txq->axq_link);
1991
1992 for (;;) {
1993 spin_lock_bh(&txq->axq_lock);
1994 if (list_empty(&txq->axq_q)) {
1995 txq->axq_link = NULL;
1996 spin_unlock_bh(&txq->axq_lock);
1997 break;
1998 }
1999 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2000
2001 /*
2002 * There is a race condition that a BH gets scheduled
2003 * after sw writes TxE and before hw re-load the last
2004 * descriptor to get the newly chained one.
2005 * Software must keep the last DONE descriptor as a
2006 * holding descriptor - software does so by marking
2007 * it with the STALE flag.
2008 */
2009 bf_held = NULL;
2010 if (bf->bf_stale) {
2011 bf_held = bf;
2012 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2013 spin_unlock_bh(&txq->axq_lock);
2014 break;
2015 } else {
2016 bf = list_entry(bf_held->list.next,
2017 struct ath_buf, list);
2018 }
2019 }
2020
2021 lastbf = bf->bf_lastbf;
2022 ds = lastbf->bf_desc;
2023
2024 memset(&ts, 0, sizeof(ts));
2025 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2026 if (status == -EINPROGRESS) {
2027 spin_unlock_bh(&txq->axq_lock);
2028 break;
2029 }
2030
2031 /*
2032 * Remove ath_buf's of the same transmit unit from txq,
2033 * however leave the last descriptor back as the holding
2034 * descriptor for hw.
2035 */
2036 lastbf->bf_stale = true;
2037 INIT_LIST_HEAD(&bf_head);
2038 if (!list_is_singular(&lastbf->list))
2039 list_cut_position(&bf_head,
2040 &txq->axq_q, lastbf->list.prev);
2041
2042 txq->axq_depth--;
2043 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2044 txq->axq_tx_inprogress = false;
2045 if (bf_held)
2046 list_del(&bf_held->list);
2047 spin_unlock_bh(&txq->axq_lock);
2048
2049 if (bf_held)
2050 ath_tx_return_buffer(sc, bf_held);
2051
2052 if (!bf_isampdu(bf)) {
2053 /*
2054 * This frame is sent out as a single frame.
2055 * Use hardware retry status for this frame.
2056 */
2057 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2058 bf->bf_state.bf_type |= BUF_XRETRY;
2059 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
2060 }
2061
2062 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2063
2064 if (bf_isampdu(bf))
2065 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2066 true);
2067 else
2068 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2069
2070 if (txq == sc->tx.txq_map[qnum])
2071 ath_wake_mac80211_queue(sc, qnum);
2072
2073 spin_lock_bh(&txq->axq_lock);
2074 if (sc->sc_flags & SC_OP_TXAGGR)
2075 ath_txq_schedule(sc, txq);
2076 spin_unlock_bh(&txq->axq_lock);
2077 }
2078 }
2079
2080 static void ath_tx_complete_poll_work(struct work_struct *work)
2081 {
2082 struct ath_softc *sc = container_of(work, struct ath_softc,
2083 tx_complete_work.work);
2084 struct ath_txq *txq;
2085 int i;
2086 bool needreset = false;
2087
2088 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2089 if (ATH_TXQ_SETUP(sc, i)) {
2090 txq = &sc->tx.txq[i];
2091 spin_lock_bh(&txq->axq_lock);
2092 if (txq->axq_depth) {
2093 if (txq->axq_tx_inprogress) {
2094 needreset = true;
2095 spin_unlock_bh(&txq->axq_lock);
2096 break;
2097 } else {
2098 txq->axq_tx_inprogress = true;
2099 }
2100 }
2101 spin_unlock_bh(&txq->axq_lock);
2102 }
2103
2104 if (needreset) {
2105 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2106 "tx hung, resetting the chip\n");
2107 ath9k_ps_wakeup(sc);
2108 ath_reset(sc, true);
2109 ath9k_ps_restore(sc);
2110 }
2111
2112 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2113 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2114 }
2115
2116
2117
2118 void ath_tx_tasklet(struct ath_softc *sc)
2119 {
2120 int i;
2121 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2122
2123 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2124
2125 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2126 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2127 ath_tx_processq(sc, &sc->tx.txq[i]);
2128 }
2129 }
2130
2131 void ath_tx_edma_tasklet(struct ath_softc *sc)
2132 {
2133 struct ath_tx_status txs;
2134 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2135 struct ath_hw *ah = sc->sc_ah;
2136 struct ath_txq *txq;
2137 struct ath_buf *bf, *lastbf;
2138 struct list_head bf_head;
2139 int status;
2140 int txok;
2141 int qnum;
2142
2143 for (;;) {
2144 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2145 if (status == -EINPROGRESS)
2146 break;
2147 if (status == -EIO) {
2148 ath_dbg(common, ATH_DBG_XMIT,
2149 "Error processing tx status\n");
2150 break;
2151 }
2152
2153 /* Skip beacon completions */
2154 if (txs.qid == sc->beacon.beaconq)
2155 continue;
2156
2157 txq = &sc->tx.txq[txs.qid];
2158
2159 spin_lock_bh(&txq->axq_lock);
2160 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2161 spin_unlock_bh(&txq->axq_lock);
2162 return;
2163 }
2164
2165 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2166 struct ath_buf, list);
2167 lastbf = bf->bf_lastbf;
2168
2169 INIT_LIST_HEAD(&bf_head);
2170 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2171 &lastbf->list);
2172 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2173 txq->axq_depth--;
2174 txq->axq_tx_inprogress = false;
2175 spin_unlock_bh(&txq->axq_lock);
2176
2177 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2178
2179 if (!bf_isampdu(bf)) {
2180 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2181 bf->bf_state.bf_type |= BUF_XRETRY;
2182 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
2183 }
2184
2185 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2186
2187 if (bf_isampdu(bf))
2188 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2189 txok, true);
2190 else
2191 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2192 &txs, txok, 0);
2193
2194 if (txq == sc->tx.txq_map[qnum])
2195 ath_wake_mac80211_queue(sc, qnum);
2196
2197 spin_lock_bh(&txq->axq_lock);
2198 if (!list_empty(&txq->txq_fifo_pending)) {
2199 INIT_LIST_HEAD(&bf_head);
2200 bf = list_first_entry(&txq->txq_fifo_pending,
2201 struct ath_buf, list);
2202 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2203 &bf->bf_lastbf->list);
2204 ath_tx_txqaddbuf(sc, txq, &bf_head);
2205 } else if (sc->sc_flags & SC_OP_TXAGGR)
2206 ath_txq_schedule(sc, txq);
2207 spin_unlock_bh(&txq->axq_lock);
2208 }
2209 }
2210
2211 /*****************/
2212 /* Init, Cleanup */
2213 /*****************/
2214
2215 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2216 {
2217 struct ath_descdma *dd = &sc->txsdma;
2218 u8 txs_len = sc->sc_ah->caps.txs_len;
2219
2220 dd->dd_desc_len = size * txs_len;
2221 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2222 &dd->dd_desc_paddr, GFP_KERNEL);
2223 if (!dd->dd_desc)
2224 return -ENOMEM;
2225
2226 return 0;
2227 }
2228
2229 static int ath_tx_edma_init(struct ath_softc *sc)
2230 {
2231 int err;
2232
2233 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2234 if (!err)
2235 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2236 sc->txsdma.dd_desc_paddr,
2237 ATH_TXSTATUS_RING_SIZE);
2238
2239 return err;
2240 }
2241
2242 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2243 {
2244 struct ath_descdma *dd = &sc->txsdma;
2245
2246 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2247 dd->dd_desc_paddr);
2248 }
2249
2250 int ath_tx_init(struct ath_softc *sc, int nbufs)
2251 {
2252 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2253 int error = 0;
2254
2255 spin_lock_init(&sc->tx.txbuflock);
2256
2257 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2258 "tx", nbufs, 1, 1);
2259 if (error != 0) {
2260 ath_err(common,
2261 "Failed to allocate tx descriptors: %d\n", error);
2262 goto err;
2263 }
2264
2265 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2266 "beacon", ATH_BCBUF, 1, 1);
2267 if (error != 0) {
2268 ath_err(common,
2269 "Failed to allocate beacon descriptors: %d\n", error);
2270 goto err;
2271 }
2272
2273 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2274
2275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2276 error = ath_tx_edma_init(sc);
2277 if (error)
2278 goto err;
2279 }
2280
2281 err:
2282 if (error != 0)
2283 ath_tx_cleanup(sc);
2284
2285 return error;
2286 }
2287
2288 void ath_tx_cleanup(struct ath_softc *sc)
2289 {
2290 if (sc->beacon.bdma.dd_desc_len != 0)
2291 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2292
2293 if (sc->tx.txdma.dd_desc_len != 0)
2294 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2295
2296 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2297 ath_tx_edma_cleanup(sc);
2298 }
2299
2300 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2301 {
2302 struct ath_atx_tid *tid;
2303 struct ath_atx_ac *ac;
2304 int tidno, acno;
2305
2306 for (tidno = 0, tid = &an->tid[tidno];
2307 tidno < WME_NUM_TID;
2308 tidno++, tid++) {
2309 tid->an = an;
2310 tid->tidno = tidno;
2311 tid->seq_start = tid->seq_next = 0;
2312 tid->baw_size = WME_MAX_BA;
2313 tid->baw_head = tid->baw_tail = 0;
2314 tid->sched = false;
2315 tid->paused = false;
2316 tid->state &= ~AGGR_CLEANUP;
2317 INIT_LIST_HEAD(&tid->buf_q);
2318 acno = TID_TO_WME_AC(tidno);
2319 tid->ac = &an->ac[acno];
2320 tid->state &= ~AGGR_ADDBA_COMPLETE;
2321 tid->state &= ~AGGR_ADDBA_PROGRESS;
2322 }
2323
2324 for (acno = 0, ac = &an->ac[acno];
2325 acno < WME_NUM_AC; acno++, ac++) {
2326 ac->sched = false;
2327 ac->txq = sc->tx.txq_map[acno];
2328 INIT_LIST_HEAD(&ac->tid_q);
2329 }
2330 }
2331
2332 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2333 {
2334 struct ath_atx_ac *ac;
2335 struct ath_atx_tid *tid;
2336 struct ath_txq *txq;
2337 int tidno;
2338
2339 for (tidno = 0, tid = &an->tid[tidno];
2340 tidno < WME_NUM_TID; tidno++, tid++) {
2341
2342 ac = tid->ac;
2343 txq = ac->txq;
2344
2345 spin_lock_bh(&txq->axq_lock);
2346
2347 if (tid->sched) {
2348 list_del(&tid->list);
2349 tid->sched = false;
2350 }
2351
2352 if (ac->sched) {
2353 list_del(&ac->list);
2354 tid->ac->sched = false;
2355 }
2356
2357 ath_tid_drain(sc, txq, tid);
2358 tid->state &= ~AGGR_ADDBA_COMPLETE;
2359 tid->state &= ~AGGR_CLEANUP;
2360
2361 spin_unlock_bh(&txq->axq_lock);
2362 }
2363 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree