drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/version.h>
  24 #include <linux/kref.h>
  25
  26 #include <drm/drmP.h>
  27 #include "drm_global.h"
  28 #include "gem_glue.h"
  29 #include "psb_drm.h"
  30 #include "psb_reg.h"
  31 #include "psb_intel_drv.h"
  32 #include "psb_gtt.h"
  33 #include "psb_powermgmt.h"
  34 #include "mrst.h"
  35
  36 /* Append new drm mode definition here, align with libdrm definition */
  37 #define DRM_MODE_SCALE_NO_SCALE         2
  38 #define DRM_MODE_CONNECTOR_MIPI         15
  39
  40 enum {
  41         CHIP_PSB_8108 = 0,              /* Poulsbo */
  42         CHIP_PSB_8109 = 1,              /* Poulsbo */
  43         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  44         CHIP_MFLD_0130 = 3,             /* Medfield */
  45 };
  46
  47 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  48 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
  49
  50 /*
  51  * Driver definitions
  52  */
  53
  54 #define DRIVER_NAME "gma500"
  55 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  56
  57 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  58 #define PSB_DRM_DRIVER_MAJOR 1
  59 #define PSB_DRM_DRIVER_MINOR 0
  60 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  61
  62 /*
  63  *      Hardware offsets
  64  */
  65 #define PSB_VDC_OFFSET           0x00000000
  66 #define PSB_VDC_SIZE             0x000080000
  67 #define MRST_MMIO_SIZE           0x0000C0000
  68 #define MDFLD_MMIO_SIZE          0x000100000
  69 #define PSB_SGX_SIZE             0x8000
  70 #define PSB_SGX_OFFSET           0x00040000
  71 #define MRST_SGX_OFFSET          0x00080000
  72 /*
  73  *      PCI resource identifiers
  74  */
  75 #define PSB_MMIO_RESOURCE        0
  76 #define PSB_GATT_RESOURCE        2
  77 #define PSB_GTT_RESOURCE         3
  78 /*
  79  *      PCI configuration
  80  */
  81 #define PSB_GMCH_CTRL            0x52
  82 #define PSB_BSM                  0x5C
  83 #define _PSB_GMCH_ENABLED        0x4
  84 #define PSB_PGETBL_CTL           0x2020
  85 #define _PSB_PGETBL_ENABLED      0x00000001
  86 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  87
  88 /* To get rid of */
  89 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  90 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  91
  92 /*
  93  *      SGX side MMU definitions (these can probably go)
  94  */
  95
  96 /*
  97  *      Flags for external memory type field.
  98  */
  99 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
 100 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 101 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 102 /*
 103  *      PTE's and PDE's
 104  */
 105 #define PSB_PDE_MASK              0x003FFFFF
 106 #define PSB_PDE_SHIFT             22
 107 #define PSB_PTE_SHIFT             12
 108 /*
 109  *      Cache control
 110  */
 111 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 112 #define PSB_PTE_WO                0x0002        /* Write only */
 113 #define PSB_PTE_RO                0x0004        /* Read only */
 114 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 115
 116 /*
 117  *      VDC registers and bits
 118  */
 119 #define PSB_MSVDX_CLOCKGATING     0x2064
 120 #define PSB_TOPAZ_CLOCKGATING     0x2068
 121 #define PSB_HWSTAM                0x2098
 122 #define PSB_INSTPM                0x20C0
 123 #define PSB_INT_IDENTITY_R        0x20A4
 124 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 125 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 126 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 127 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 128 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 129 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 130 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 131 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 132 #define _MDFLD_MIPIA_FLAG         (1<<16)
 133 #define _MDFLD_MIPIC_FLAG         (1<<17)
 134 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 135 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 136 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 137
 138 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 139 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 140                                   _MDFLD_PIPEB_EVENT_FLAG | \
 141                                   _PSB_PIPEA_EVENT_FLAG | \
 142                                   _PSB_VSYNC_PIPEA_FLAG | \
 143                                   _MDFLD_MIPIA_FLAG | \
 144                                   _MDFLD_MIPIC_FLAG)
 145 #define PSB_INT_IDENTITY_R        0x20A4
 146 #define PSB_INT_MASK_R            0x20A8
 147 #define PSB_INT_ENABLE_R          0x20A0
 148
 149 #define _PSB_MMU_ER_MASK      0x0001FF00
 150 #define _PSB_MMU_ER_HOST      (1 << 16)
 151 #define GPIOA                   0x5010
 152 #define GPIOB                   0x5014
 153 #define GPIOC                   0x5018
 154 #define GPIOD                   0x501c
 155 #define GPIOE                   0x5020
 156 #define GPIOF                   0x5024
 157 #define GPIOG                   0x5028
 158 #define GPIOH                   0x502c
 159 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 160 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 161 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 162 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 163 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 164 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 165 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 166 #define GPIO_DATA_DIR_MASK              (1 << 8)
 167 #define GPIO_DATA_DIR_IN                (0 << 9)
 168 #define GPIO_DATA_DIR_OUT               (1 << 9)
 169 #define GPIO_DATA_VAL_MASK              (1 << 10)
 170 #define GPIO_DATA_VAL_OUT               (1 << 11)
 171 #define GPIO_DATA_VAL_IN                (1 << 12)
 172 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 173
 174 #define VCLK_DIVISOR_VGA0   0x6000
 175 #define VCLK_DIVISOR_VGA1   0x6004
 176 #define VCLK_POST_DIV       0x6010
 177
 178 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 179 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 180 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 181 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 182 #define PSB_COMM_USER_IRQ (1024 >> 2)
 183 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 184 #define PSB_COMM_FW (2048 >> 2)
 185
 186 #define PSB_UIRQ_VISTEST               1
 187 #define PSB_UIRQ_OOM_REPLY             2
 188 #define PSB_UIRQ_FIRE_TA_REPLY         3
 189 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 190
 191 #define PSB_2D_SIZE (256*1024*1024)
 192 #define PSB_MAX_RELOC_PAGES 1024
 193
 194 #define PSB_LOW_REG_OFFS 0x0204
 195 #define PSB_HIGH_REG_OFFS 0x0600
 196
 197 #define PSB_NUM_VBLANKS 2
 198
 199
 200 #define PSB_2D_SIZE (256*1024*1024)
 201 #define PSB_MAX_RELOC_PAGES 1024
 202
 203 #define PSB_LOW_REG_OFFS 0x0204
 204 #define PSB_HIGH_REG_OFFS 0x0600
 205
 206 #define PSB_NUM_VBLANKS 2
 207 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 208 #define PSB_LID_DELAY (DRM_HZ / 10)
 209
 210 #define MDFLD_PNW_B0 0x04
 211 #define MDFLD_PNW_C0 0x08
 212
 213 #define MDFLD_DSR_2D_3D_0       (1 << 0)
 214 #define MDFLD_DSR_2D_3D_2       (1 << 1)
 215 #define MDFLD_DSR_CURSOR_0      (1 << 2)
 216 #define MDFLD_DSR_CURSOR_2      (1 << 3)
 217 #define MDFLD_DSR_OVERLAY_0     (1 << 4)
 218 #define MDFLD_DSR_OVERLAY_2     (1 << 5)
 219 #define MDFLD_DSR_MIPI_CONTROL  (1 << 6)
 220 #define MDFLD_DSR_DAMAGE_MASK_0 (1 << 0) | (1 << 2) | (1 << 4)
 221 #define MDFLD_DSR_DAMAGE_MASK_2 (1 << 1) | (1 << 3) | (1 << 5)
 222 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 223
 224 #define MDFLD_DSR_RR            45
 225 #define MDFLD_DPU_ENABLE        (1 << 31)
 226 #define MDFLD_DSR_FULLSCREEN    (1 << 30)
 227 #define MDFLD_DSR_DELAY         (DRM_HZ / MDFLD_DSR_RR)
 228
 229 #define PSB_PWR_STATE_ON                1
 230 #define PSB_PWR_STATE_OFF               2
 231
 232 #define PSB_PMPOLICY_NOPM               0
 233 #define PSB_PMPOLICY_CLOCKGATING        1
 234 #define PSB_PMPOLICY_POWERDOWN          2
 235
 236 #define PSB_PMSTATE_POWERUP             0
 237 #define PSB_PMSTATE_CLOCKGATED          1
 238 #define PSB_PMSTATE_POWERDOWN           2
 239 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 240 #define PSB_PCIx_MSI_DATA_LOC           0x98
 241
 242 /* Medfield crystal settings */
 243 #define KSEL_CRYSTAL_19 1
 244 #define KSEL_BYPASS_19 5
 245 #define KSEL_BYPASS_25 6
 246 #define KSEL_BYPASS_83_100 7
 247
 248 struct opregion_header;
 249 struct opregion_acpi;
 250 struct opregion_swsci;
 251 struct opregion_asle;
 252
 253 struct psb_intel_opregion {
 254         struct opregion_header *header;
 255         struct opregion_acpi *acpi;
 256         struct opregion_swsci *swsci;
 257         struct opregion_asle *asle;
 258         int enabled;
 259 };
 260
 261 struct psb_ops;
 262
 263 struct drm_psb_private {
 264         struct drm_device *dev;
 265         const struct psb_ops *ops;
 266
 267         struct psb_gtt *pg;
 268
 269         /* GTT Memory manager */
 270         struct psb_gtt_mm *gtt_mm;
 271         struct page *scratch_page;
 272         u32 *gtt_map;
 273         uint32_t stolen_base;
 274         void *vram_addr;
 275         unsigned long vram_stolen_size;
 276         int gtt_initialized;
 277         u16 gmch_ctrl;          /* Saved GTT setup */
 278         u32 pge_ctl;
 279
 280         struct mutex gtt_mutex;
 281         struct resource *gtt_mem;       /* Our PCI resource */
 282
 283         struct psb_mmu_driver *mmu;
 284         struct psb_mmu_pd *pf_pd;
 285
 286         /*
 287          * Register base
 288          */
 289
 290         uint8_t *sgx_reg;
 291         uint8_t *vdc_reg;
 292         uint32_t gatt_free_offset;
 293
 294         /*
 295          * Fencing / irq.
 296          */
 297
 298         uint32_t vdc_irq_mask;
 299         uint32_t pipestat[PSB_NUM_PIPE];
 300
 301         spinlock_t irqmask_lock;
 302
 303         /*
 304          * Power
 305          */
 306
 307         bool suspended;
 308         bool display_power;
 309         int display_count;
 310
 311         /*
 312          * Modesetting
 313          */
 314         struct psb_intel_mode_device mode_dev;
 315
 316         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 317         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 318         uint32_t num_pipe;
 319
 320         /*
 321          * OSPM info (Power management base) (can go ?)
 322          */
 323         uint32_t ospm_base;
 324
 325         /*
 326          * Sizes info
 327          */
 328
 329         struct drm_psb_sizes_arg sizes;
 330
 331         u32 fuse_reg_value;
 332         u32 video_device_fuse;
 333
 334         /* PCI revision ID for B0:D2:F0 */
 335         uint8_t platform_rev_id;
 336
 337         /*
 338          * LVDS info
 339          */
 340         int backlight_duty_cycle;       /* restore backlight to this value */
 341         bool panel_wants_dither;
 342         struct drm_display_mode *panel_fixed_mode;
 343         struct drm_display_mode *lfp_lvds_vbt_mode;
 344         struct drm_display_mode *sdvo_lvds_vbt_mode;
 345
 346         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 347         struct psb_intel_i2c_chan *lvds_i2c_bus;
 348
 349         /* Feature bits from the VBIOS */
 350         unsigned int int_tv_support:1;
 351         unsigned int lvds_dither:1;
 352         unsigned int lvds_vbt:1;
 353         unsigned int int_crt_support:1;
 354         unsigned int lvds_use_ssc:1;
 355         int lvds_ssc_freq;
 356         bool is_lvds_on;
 357         bool is_mipi_on;
 358         u32 mipi_ctrl_display;
 359
 360         unsigned int core_freq;
 361         uint32_t iLVDS_enable;
 362
 363         /* Runtime PM state */
 364         int rpm_enabled;
 365
 366         /* MID specific */
 367         struct mrst_vbt vbt_data;
 368         struct mrst_gct_data gct_data;
 369
 370         /* MIPI Panel type etc */
 371         int panel_id;
 372         bool dual_mipi;         /* dual display - DPI & DBI */
 373         bool dpi_panel_on;      /* The DPI panel power is on */
 374         bool dpi_panel_on2;     /* The DPI panel power is on */
 375         bool dbi_panel_on;      /* The DBI panel power is on */
 376         bool dbi_panel_on2;     /* The DBI panel power is on */
 377         u32 dsr_fb_update;      /* DSR FB update counter */
 378
 379         /* Moorestown pipe config register value cache */
 380         uint32_t pipeconf;
 381         uint32_t pipeconf1;
 382         uint32_t pipeconf2;
 383
 384         /* Moorestown plane control register value cache */
 385         uint32_t dspcntr;
 386         uint32_t dspcntr1;
 387         uint32_t dspcntr2;
 388
 389         /*
 390          * Register state
 391          */
 392         uint32_t saveDSPACNTR;
 393         uint32_t saveDSPBCNTR;
 394         uint32_t savePIPEACONF;
 395         uint32_t savePIPEBCONF;
 396         uint32_t savePIPEASRC;
 397         uint32_t savePIPEBSRC;
 398         uint32_t saveFPA0;
 399         uint32_t saveFPA1;
 400         uint32_t saveDPLL_A;
 401         uint32_t saveDPLL_A_MD;
 402         uint32_t saveHTOTAL_A;
 403         uint32_t saveHBLANK_A;
 404         uint32_t saveHSYNC_A;
 405         uint32_t saveVTOTAL_A;
 406         uint32_t saveVBLANK_A;
 407         uint32_t saveVSYNC_A;
 408         uint32_t saveDSPASTRIDE;
 409         uint32_t saveDSPASIZE;
 410         uint32_t saveDSPAPOS;
 411         uint32_t saveDSPABASE;
 412         uint32_t saveDSPASURF;
 413         uint32_t saveDSPASTATUS;
 414         uint32_t saveFPB0;
 415         uint32_t saveFPB1;
 416         uint32_t saveDPLL_B;
 417         uint32_t saveDPLL_B_MD;
 418         uint32_t saveHTOTAL_B;
 419         uint32_t saveHBLANK_B;
 420         uint32_t saveHSYNC_B;
 421         uint32_t saveVTOTAL_B;
 422         uint32_t saveVBLANK_B;
 423         uint32_t saveVSYNC_B;
 424         uint32_t saveDSPBSTRIDE;
 425         uint32_t saveDSPBSIZE;
 426         uint32_t saveDSPBPOS;
 427         uint32_t saveDSPBBASE;
 428         uint32_t saveDSPBSURF;
 429         uint32_t saveDSPBSTATUS;
 430         uint32_t saveVCLK_DIVISOR_VGA0;
 431         uint32_t saveVCLK_DIVISOR_VGA1;
 432         uint32_t saveVCLK_POST_DIV;
 433         uint32_t saveVGACNTRL;
 434         uint32_t saveADPA;
 435         uint32_t saveLVDS;
 436         uint32_t saveDVOA;
 437         uint32_t saveDVOB;
 438         uint32_t saveDVOC;
 439         uint32_t savePP_ON;
 440         uint32_t savePP_OFF;
 441         uint32_t savePP_CONTROL;
 442         uint32_t savePP_CYCLE;
 443         uint32_t savePFIT_CONTROL;
 444         uint32_t savePaletteA[256];
 445         uint32_t savePaletteB[256];
 446         uint32_t saveBLC_PWM_CTL2;
 447         uint32_t saveBLC_PWM_CTL;
 448         uint32_t saveCLOCKGATING;
 449         uint32_t saveDSPARB;
 450         uint32_t saveDSPATILEOFF;
 451         uint32_t saveDSPBTILEOFF;
 452         uint32_t saveDSPAADDR;
 453         uint32_t saveDSPBADDR;
 454         uint32_t savePFIT_AUTO_RATIOS;
 455         uint32_t savePFIT_PGM_RATIOS;
 456         uint32_t savePP_ON_DELAYS;
 457         uint32_t savePP_OFF_DELAYS;
 458         uint32_t savePP_DIVISOR;
 459         uint32_t saveBSM;
 460         uint32_t saveVBT;
 461         uint32_t saveBCLRPAT_A;
 462         uint32_t saveBCLRPAT_B;
 463         uint32_t saveDSPALINOFF;
 464         uint32_t saveDSPBLINOFF;
 465         uint32_t savePERF_MODE;
 466         uint32_t saveDSPFW1;
 467         uint32_t saveDSPFW2;
 468         uint32_t saveDSPFW3;
 469         uint32_t saveDSPFW4;
 470         uint32_t saveDSPFW5;
 471         uint32_t saveDSPFW6;
 472         uint32_t saveCHICKENBIT;
 473         uint32_t saveDSPACURSOR_CTRL;
 474         uint32_t saveDSPBCURSOR_CTRL;
 475         uint32_t saveDSPACURSOR_BASE;
 476         uint32_t saveDSPBCURSOR_BASE;
 477         uint32_t saveDSPACURSOR_POS;
 478         uint32_t saveDSPBCURSOR_POS;
 479         uint32_t save_palette_a[256];
 480         uint32_t save_palette_b[256];
 481         uint32_t saveOV_OVADD;
 482         uint32_t saveOV_OGAMC0;
 483         uint32_t saveOV_OGAMC1;
 484         uint32_t saveOV_OGAMC2;
 485         uint32_t saveOV_OGAMC3;
 486         uint32_t saveOV_OGAMC4;
 487         uint32_t saveOV_OGAMC5;
 488         uint32_t saveOVC_OVADD;
 489         uint32_t saveOVC_OGAMC0;
 490         uint32_t saveOVC_OGAMC1;
 491         uint32_t saveOVC_OGAMC2;
 492         uint32_t saveOVC_OGAMC3;
 493         uint32_t saveOVC_OGAMC4;
 494         uint32_t saveOVC_OGAMC5;
 495
 496         /* MSI reg save */
 497         uint32_t msi_addr;
 498         uint32_t msi_data;
 499
 500         /* Medfield specific register save state */
 501         uint32_t saveHDMIPHYMISCCTL;
 502         uint32_t saveHDMIB_CONTROL;
 503         uint32_t saveDSPCCNTR;
 504         uint32_t savePIPECCONF;
 505         uint32_t savePIPECSRC;
 506         uint32_t saveHTOTAL_C;
 507         uint32_t saveHBLANK_C;
 508         uint32_t saveHSYNC_C;
 509         uint32_t saveVTOTAL_C;
 510         uint32_t saveVBLANK_C;
 511         uint32_t saveVSYNC_C;
 512         uint32_t saveDSPCSTRIDE;
 513         uint32_t saveDSPCSIZE;
 514         uint32_t saveDSPCPOS;
 515         uint32_t saveDSPCSURF;
 516         uint32_t saveDSPCSTATUS;
 517         uint32_t saveDSPCLINOFF;
 518         uint32_t saveDSPCTILEOFF;
 519         uint32_t saveDSPCCURSOR_CTRL;
 520         uint32_t saveDSPCCURSOR_BASE;
 521         uint32_t saveDSPCCURSOR_POS;
 522         uint32_t save_palette_c[256];
 523         uint32_t saveOV_OVADD_C;
 524         uint32_t saveOV_OGAMC0_C;
 525         uint32_t saveOV_OGAMC1_C;
 526         uint32_t saveOV_OGAMC2_C;
 527         uint32_t saveOV_OGAMC3_C;
 528         uint32_t saveOV_OGAMC4_C;
 529         uint32_t saveOV_OGAMC5_C;
 530
 531         /* DSI register save */
 532         uint32_t saveDEVICE_READY_REG;
 533         uint32_t saveINTR_EN_REG;
 534         uint32_t saveDSI_FUNC_PRG_REG;
 535         uint32_t saveHS_TX_TIMEOUT_REG;
 536         uint32_t saveLP_RX_TIMEOUT_REG;
 537         uint32_t saveTURN_AROUND_TIMEOUT_REG;
 538         uint32_t saveDEVICE_RESET_REG;
 539         uint32_t saveDPI_RESOLUTION_REG;
 540         uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
 541         uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
 542         uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
 543         uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
 544         uint32_t saveVERT_SYNC_PAD_COUNT_REG;
 545         uint32_t saveVERT_BACK_PORCH_COUNT_REG;
 546         uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
 547         uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
 548         uint32_t saveINIT_COUNT_REG;
 549         uint32_t saveMAX_RET_PAK_REG;
 550         uint32_t saveVIDEO_FMT_REG;
 551         uint32_t saveEOT_DISABLE_REG;
 552         uint32_t saveLP_BYTECLK_REG;
 553         uint32_t saveHS_LS_DBI_ENABLE_REG;
 554         uint32_t saveTXCLKESC_REG;
 555         uint32_t saveDPHY_PARAM_REG;
 556         uint32_t saveMIPI_CONTROL_REG;
 557         uint32_t saveMIPI;
 558         uint32_t saveMIPI_C;
 559
 560         /* DPST register save */
 561         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 562         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 563         uint32_t savePWM_CONTROL_LOGIC;
 564
 565         /*
 566          * DSI info.
 567          */
 568         void * dbi_dsr_info;
 569         void * dbi_dpu_info;
 570         void * dsi_configs[2];
 571         /*
 572          * LID-Switch
 573          */
 574         spinlock_t lid_lock;
 575         struct timer_list lid_timer;
 576         struct psb_intel_opregion opregion;
 577         u32 *lid_state;
 578         u32 lid_last_state;
 579
 580         /*
 581          * Watchdog
 582          */
 583
 584         uint32_t apm_reg;
 585         uint16_t apm_base;
 586
 587         /*
 588          * Used for modifying backlight from
 589          * xrandr -- consider removing and using HAL instead
 590          */
 591         struct backlight_device *backlight_device;
 592         struct drm_property *backlight_property;
 593         uint32_t blc_adj1;
 594         uint32_t blc_adj2;
 595
 596         void *fbdev;
 597         /* DPST state */
 598         uint32_t dsr_idle_count;
 599         bool is_in_idle;
 600         bool dsr_enable;
 601         void (*exit_idle)(struct drm_device *dev, u32 update_src, void *p_surfaceAddr, bool check_hw_on_only);
 602
 603         /* FIXME: Arrays anyone ? */
 604         struct mdfld_dsi_encoder *encoder0;
 605         struct mdfld_dsi_encoder *encoder2;
 606         struct mdfld_dsi_dbi_output * dbi_output;
 607         struct mdfld_dsi_dbi_output * dbi_output2;
 608         u32 bpp;
 609         u32 bpp2;
 610
 611         bool dispstatus;
 612 };
 613
 614
 615 /*
 616  *      Operations for each board type
 617  */
 618
 619 struct psb_ops {
 620         const char *name;
 621         unsigned int accel_2d:1;
 622         int pipes;              /* Number of output pipes */
 623         int sgx_offset;         /* Base offset of SGX device */
 624
 625         /* Sub functions */
 626         struct drm_crtc_helper_funcs const *crtc_helper;
 627         struct drm_crtc_funcs const *crtc_funcs;
 628
 629         /* Setup hooks */
 630         int (*chip_setup)(struct drm_device *dev);
 631
 632         /* Display management hooks */
 633         int (*output_init)(struct drm_device *dev);
 634         /* Power management hooks */
 635         void (*init_pm)(struct drm_device *dev);
 636         int (*save_regs)(struct drm_device *dev);
 637         int (*restore_regs)(struct drm_device *dev);
 638         int (*power_up)(struct drm_device *dev);
 639         int (*power_down)(struct drm_device *dev);
 640 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 641         /* Backlight */
 642         int (*backlight_init)(struct drm_device *dev);
 643 #endif
 644 };
 645
 646
 647
 648 struct psb_mmu_driver;
 649
 650 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 651 extern int drm_pick_crtcs(struct drm_device *dev);
 652
 653 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 654 {
 655         return (struct drm_psb_private *) dev->dev_private;
 656 }
 657
 658 /*
 659  * MMU stuff.
 660  */
 661
 662 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 663                                         int trap_pagefaults,
 664                                         int invalid_type,
 665                                         struct drm_psb_private *dev_priv);
 666 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 667 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 668                                                  *driver);
 669 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 670                                uint32_t gtt_start, uint32_t gtt_pages);
 671 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 672                                            int trap_pagefaults,
 673                                            int invalid_type);
 674 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 675 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 676 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 677                                         unsigned long address,
 678                                         uint32_t num_pages);
 679 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 680                                        uint32_t start_pfn,
 681                                        unsigned long address,
 682                                        uint32_t num_pages, int type);
 683 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 684                                   unsigned long *pfn);
 685
 686 /*
 687  * Enable / disable MMU for different requestors.
 688  */
 689
 690
 691 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 692 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 693                                 unsigned long address, uint32_t num_pages,
 694                                 uint32_t desired_tile_stride,
 695                                 uint32_t hw_tile_stride, int type);
 696 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 697                                  unsigned long address, uint32_t num_pages,
 698                                  uint32_t desired_tile_stride,
 699                                  uint32_t hw_tile_stride);
 700 /*
 701  *psb_irq.c
 702  */
 703
 704 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 705 extern int psb_irq_enable_dpst(struct drm_device *dev);
 706 extern int psb_irq_disable_dpst(struct drm_device *dev);
 707 extern void psb_irq_preinstall(struct drm_device *dev);
 708 extern int psb_irq_postinstall(struct drm_device *dev);
 709 extern void psb_irq_uninstall(struct drm_device *dev);
 710 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 711 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 712
 713 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 714 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 715 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 716 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 717 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 718 void
 719 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 720
 721 void
 722 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 723
 724 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 725
 726 extern int mdfld_enable_te(struct drm_device *dev, int pipe);
 727 extern void mdfld_disable_te(struct drm_device *dev, int pipe);
 728
 729 /*
 730  * psb_opregion.c
 731  */
 732 extern int psb_intel_opregion_init(struct drm_device *dev);
 733
 734 /*
 735  *psb_fb.c
 736  */
 737 extern int psbfb_probed(struct drm_device *dev);
 738 extern int psbfb_remove(struct drm_device *dev,
 739                         struct drm_framebuffer *fb);
 740 /*
 741  * psb_2d.c
 742  */
 743 extern void psbfb_copyarea(struct fb_info *info,
 744                                         const struct fb_copyarea *region);
 745 extern int psbfb_sync(struct fb_info *info);
 746 extern void psb_spank(struct drm_psb_private *dev_priv);
 747 extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
 748                                         unsigned size);
 749
 750 /*
 751  * psb_reset.c
 752  */
 753
 754 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 755 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 756 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 757
 758 /* modesetting */
 759 extern void psb_modeset_init(struct drm_device *dev);
 760 extern void psb_modeset_cleanup(struct drm_device *dev);
 761 extern int psb_fbdev_init(struct drm_device *dev);
 762
 763 /* backlight.c */
 764 int gma_backlight_init(struct drm_device *dev);
 765 void gma_backlight_exit(struct drm_device *dev);
 766
 767 /* mrst_crtc.c */
 768 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 769
 770 /* mrst_lvds.c */
 771 extern void mrst_lvds_init(struct drm_device *dev,
 772                     struct psb_intel_mode_device *mode_dev);
 773
 774 /* psb_intel_display.c */
 775 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
 776 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
 777
 778 /* psb_intel_lvds.c */
 779 extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
 780 extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
 781 extern const struct drm_connector_helper_funcs
 782                                         psb_intel_lvds_connector_helper_funcs;
 783 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 784
 785 /* psb_gem.c */
 786 extern int psb_gem_init_object(struct drm_gem_object *obj);
 787 extern void psb_gem_free_object(struct drm_gem_object *obj);
 788 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 789                                 struct drm_file *file);
 790 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 791                         struct drm_mode_create_dumb *args);
 792 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 793                         uint32_t handle);
 794 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 795                          uint32_t handle, uint64_t *offset);
 796 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 797
 798 /* psb_device.c */
 799 extern const struct psb_ops psb_chip_ops;
 800
 801 /* mrst_device.c */
 802 extern const struct psb_ops mrst_chip_ops;
 803
 804 /* mdfld_device.c */
 805 extern const struct psb_ops mdfld_chip_ops;
 806
 807 /*
 808  * Debug print bits setting
 809  */
 810 #define PSB_D_GENERAL (1 << 0)
 811 #define PSB_D_INIT    (1 << 1)
 812 #define PSB_D_IRQ     (1 << 2)
 813 #define PSB_D_ENTRY   (1 << 3)
 814 /* debug the get H/V BP/FP count */
 815 #define PSB_D_HV      (1 << 4)
 816 #define PSB_D_DBI_BF  (1 << 5)
 817 #define PSB_D_PM      (1 << 6)
 818 #define PSB_D_RENDER  (1 << 7)
 819 #define PSB_D_REG     (1 << 8)
 820 #define PSB_D_MSVDX   (1 << 9)
 821 #define PSB_D_TOPAZ   (1 << 10)
 822
 823 extern int drm_psb_no_fb;
 824 extern int drm_idle_check_interval;
 825
 826 /*
 827  *      Utilities
 828  */
 829
 830 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 831 {
 832         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 833         uint32_t ret_val = 0;
 834         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 835         pci_write_config_dword(pci_root, 0xD0, mcr);
 836         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 837         pci_dev_put(pci_root);
 838         return ret_val;
 839 }
 840 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 841 {
 842         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 843         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 844         pci_write_config_dword(pci_root, 0xD4, value);
 845         pci_write_config_dword(pci_root, 0xD0, mcr);
 846         pci_dev_put(pci_root);
 847 }
 848 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 849 {
 850         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 851         uint32_t ret_val = 0;
 852         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 853         pci_write_config_dword(pci_root, 0xD0, mcr);
 854         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 855         pci_dev_put(pci_root);
 856         return ret_val;
 857 }
 858 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 859 {
 860         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 861         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 862         pci_write_config_dword(pci_root, 0xD4, value);
 863         pci_write_config_dword(pci_root, 0xD0, mcr);
 864         pci_dev_put(pci_root);
 865 }
 866
 867 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 868 {
 869         struct drm_psb_private *dev_priv = dev->dev_private;
 870         return ioread32(dev_priv->vdc_reg + reg);
 871 }
 872
 873 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 874
 875 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 876                                       uint32_t val)
 877 {
 878         struct drm_psb_private *dev_priv = dev->dev_private;
 879         iowrite32((val), dev_priv->vdc_reg + (reg));
 880 }
 881
 882 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 883
 884 static inline void REGISTER_WRITE16(struct drm_device *dev,
 885                                         uint32_t reg, uint32_t val)
 886 {
 887         struct drm_psb_private *dev_priv = dev->dev_private;
 888         iowrite16((val), dev_priv->vdc_reg + (reg));
 889 }
 890
 891 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 892
 893 static inline void REGISTER_WRITE8(struct drm_device *dev,
 894                                        uint32_t reg, uint32_t val)
 895 {
 896         struct drm_psb_private *dev_priv = dev->dev_private;
 897         iowrite8((val), dev_priv->vdc_reg + (reg));
 898 }
 899
 900 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 901
 902 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 903 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 904
 905 /* #define TRAP_SGX_PM_FAULT 1 */
 906 #ifdef TRAP_SGX_PM_FAULT
 907 #define PSB_RSGX32(_offs)                                               \
 908 ({                                                                      \
 909         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 910                 printk(KERN_ERR                                         \
 911                         "access sgx when it's off!! (READ) %s, %d\n",   \
 912                __FILE__, __LINE__);                                     \
 913                 melay(1000);                                            \
 914         }                                                               \
 915         ioread32(dev_priv->sgx_reg + (_offs));                          \
 916 })
 917 #else
 918 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 919 #endif
 920 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
 921
 922 #define MSVDX_REG_DUMP 0
 923
 924 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 925 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
 926
 927 #endif