arch/arm/plat-spear/time.c

   1 /*
   2  * arch/arm/plat-spear/time.c
   3  *
   4  * Copyright (C) 2010 ST Microelectronics
   5  * Shiraz Hashim<shiraz.hashim@st.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clockchips.h>
  14 #include <linux/clocksource.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/time.h>
  21 #include <linux/irq.h>
  22 #include <asm/mach/time.h>
  23 #include <mach/generic.h>
  24 #include <mach/hardware.h>
  25 #include <mach/irqs.h>
  26
  27 /*
  28  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
  29  * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
  30  * they share same functional clock. Any change in one's functional clock will
  31  * also affect other timer.
  32  */
  33
  34 #define CLKEVT  0       /* gpt0, channel0 as clockevent */
  35 #define CLKSRC  1       /* gpt0, channel1 as clocksource */
  36
  37 /* Register offsets, x is channel number */
  38 #define CR(x)           ((x) * 0x80 + 0x80)
  39 #define IR(x)           ((x) * 0x80 + 0x84)
  40 #define LOAD(x)         ((x) * 0x80 + 0x88)
  41 #define COUNT(x)        ((x) * 0x80 + 0x8C)
  42
  43 /* Reg bit definitions */
  44 #define CTRL_INT_ENABLE         0x0100
  45 #define CTRL_ENABLE             0x0020
  46 #define CTRL_ONE_SHOT           0x0010
  47
  48 #define CTRL_PRESCALER1         0x0
  49 #define CTRL_PRESCALER2         0x1
  50 #define CTRL_PRESCALER4         0x2
  51 #define CTRL_PRESCALER8         0x3
  52 #define CTRL_PRESCALER16        0x4
  53 #define CTRL_PRESCALER32        0x5
  54 #define CTRL_PRESCALER64        0x6
  55 #define CTRL_PRESCALER128       0x7
  56 #define CTRL_PRESCALER256       0x8
  57
  58 #define INT_STATUS              0x1
  59
  60 /*
  61  * Minimum clocksource/clockevent timer range in seconds
  62  */
  63 #define SPEAR_MIN_RANGE 4
  64
  65 static __iomem void *gpt_base;
  66 static struct clk *gpt_clk;
  67
  68 static void clockevent_set_mode(enum clock_event_mode mode,
  69                                 struct clock_event_device *clk_event_dev);
  70 static int clockevent_next_event(unsigned long evt,
  71                                  struct clock_event_device *clk_event_dev);
  72
  73 static cycle_t clocksource_read_cycles(struct clocksource *cs)
  74 {
  75         return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
  76 }
  77
  78 static struct clocksource clksrc = {
  79         .name = "tmr1",
  80         .rating = 200,          /* its a pretty decent clock */
  81         .read = clocksource_read_cycles,
  82         .mask = 0xFFFF,         /* 16 bits */
  83         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  84 };
  85
  86 static void spear_clocksource_init(void)
  87 {
  88         u32 tick_rate;
  89         u16 val;
  90
  91         /* program the prescaler (/256)*/
  92         writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
  93
  94         /* find out actual clock driving Timer */
  95         tick_rate = clk_get_rate(gpt_clk);
  96         tick_rate >>= CTRL_PRESCALER256;
  97
  98         writew(0xFFFF, gpt_base + LOAD(CLKSRC));
  99
 100         val = readw(gpt_base + CR(CLKSRC));
 101         val &= ~CTRL_ONE_SHOT;  /* autoreload mode */
 102         val |= CTRL_ENABLE ;
 103         writew(val, gpt_base + CR(CLKSRC));
 104
 105         /* register the clocksource */
 106         clocksource_register_hz(&clksrc, tick_rate);
 107 }
 108
 109 static struct clock_event_device clkevt = {
 110         .name = "tmr0",
 111         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 112         .set_mode = clockevent_set_mode,
 113         .set_next_event = clockevent_next_event,
 114         .shift = 0,     /* to be computed */
 115 };
 116
 117 static void clockevent_set_mode(enum clock_event_mode mode,
 118                                 struct clock_event_device *clk_event_dev)
 119 {
 120         u32 period;
 121         u16 val;
 122
 123         /* stop the timer */
 124         val = readw(gpt_base + CR(CLKEVT));
 125         val &= ~CTRL_ENABLE;
 126         writew(val, gpt_base + CR(CLKEVT));
 127
 128         switch (mode) {
 129         case CLOCK_EVT_MODE_PERIODIC:
 130                 period = clk_get_rate(gpt_clk) / HZ;
 131                 period >>= CTRL_PRESCALER16;
 132                 writew(period, gpt_base + LOAD(CLKEVT));
 133
 134                 val = readw(gpt_base + CR(CLKEVT));
 135                 val &= ~CTRL_ONE_SHOT;
 136                 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
 137                 writew(val, gpt_base + CR(CLKEVT));
 138
 139                 break;
 140         case CLOCK_EVT_MODE_ONESHOT:
 141                 val = readw(gpt_base + CR(CLKEVT));
 142                 val |= CTRL_ONE_SHOT;
 143                 writew(val, gpt_base + CR(CLKEVT));
 144
 145                 break;
 146         case CLOCK_EVT_MODE_UNUSED:
 147         case CLOCK_EVT_MODE_SHUTDOWN:
 148         case CLOCK_EVT_MODE_RESUME:
 149
 150                 break;
 151         default:
 152                 pr_err("Invalid mode requested\n");
 153                 break;
 154         }
 155 }
 156
 157 static int clockevent_next_event(unsigned long cycles,
 158                                  struct clock_event_device *clk_event_dev)
 159 {
 160         u16 val;
 161
 162         writew(cycles, gpt_base + LOAD(CLKEVT));
 163
 164         val = readw(gpt_base + CR(CLKEVT));
 165         val |= CTRL_ENABLE | CTRL_INT_ENABLE;
 166         writew(val, gpt_base + CR(CLKEVT));
 167
 168         return 0;
 169 }
 170
 171 static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
 172 {
 173         struct clock_event_device *evt = &clkevt;
 174
 175         writew(INT_STATUS, gpt_base + IR(CLKEVT));
 176
 177         evt->event_handler(evt);
 178
 179         return IRQ_HANDLED;
 180 }
 181
 182 static struct irqaction spear_timer_irq = {
 183         .name = "timer",
 184         .flags = IRQF_DISABLED | IRQF_TIMER,
 185         .handler = spear_timer_interrupt
 186 };
 187
 188 static void __init spear_clockevent_init(void)
 189 {
 190         u32 tick_rate;
 191
 192         /* program the prescaler */
 193         writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
 194
 195         tick_rate = clk_get_rate(gpt_clk);
 196         tick_rate >>= CTRL_PRESCALER16;
 197
 198         clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
 199
 200         clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
 201                         &clkevt);
 202         clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
 203
 204         clkevt.cpumask = cpumask_of(0);
 205
 206         clockevents_register_device(&clkevt);
 207
 208         setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
 209 }
 210
 211 void __init spear_setup_timer(void)
 212 {
 213         int ret;
 214
 215         if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
 216                 pr_err("%s:cannot get IO addr\n", __func__);
 217                 return;
 218         }
 219
 220         gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
 221         if (!gpt_base) {
 222                 pr_err("%s:ioremap failed for gpt\n", __func__);
 223                 goto err_mem;
 224         }
 225
 226         gpt_clk = clk_get_sys("gpt0", NULL);
 227         if (!gpt_clk) {
 228                 pr_err("%s:couldn't get clk for gpt\n", __func__);
 229                 goto err_iomap;
 230         }
 231
 232         ret = clk_enable(gpt_clk);
 233         if (ret < 0) {
 234                 pr_err("%s:couldn't enable gpt clock\n", __func__);
 235                 goto err_clk;
 236         }
 237
 238         spear_clockevent_init();
 239         spear_clocksource_init();
 240
 241         return;
 242
 243 err_clk:
 244         clk_put(gpt_clk);
 245 err_iomap:
 246         iounmap(gpt_base);
 247 err_mem:
 248         release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
 249 }