drivers/staging/gma500/mdfld_dsi_output.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  * jim liu <jim.liu@intel.com>
  25  * Jackie Li<yaodong.li@intel.com>
  26  */
  27
  28 #ifndef __MDFLD_DSI_OUTPUT_H__
  29 #define __MDFLD_DSI_OUTPUT_H__
  30
  31 #include <linux/backlight.h>
  32 #include <linux/version.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include "psb_drv.h"
  39 #include "psb_intel_drv.h"
  40 #include "psb_intel_reg.h"
  41 #include "psb_powermgmt.h"
  42 #include "mdfld_output.h"
  43
  44 #include <asm/mrst.h>
  45
  46 #define DRM_MODE_ENCODER_MIPI  5
  47
  48 /* Medfield DSI controller registers */
  49
  50 #define MIPIA_DEVICE_READY_REG                          0xb000
  51 #define MIPIA_INTR_STAT_REG                             0xb004
  52 #define MIPIA_INTR_EN_REG                               0xb008
  53 #define MIPIA_DSI_FUNC_PRG_REG                          0xb00c
  54 #define MIPIA_HS_TX_TIMEOUT_REG                         0xb010
  55 #define MIPIA_LP_RX_TIMEOUT_REG                         0xb014
  56 #define MIPIA_TURN_AROUND_TIMEOUT_REG                   0xb018
  57 #define MIPIA_DEVICE_RESET_TIMER_REG                    0xb01c
  58 #define MIPIA_DPI_RESOLUTION_REG                        0xb020
  59 #define MIPIA_DBI_FIFO_THROTTLE_REG                     0xb024
  60 #define MIPIA_HSYNC_COUNT_REG                           0xb028
  61 #define MIPIA_HBP_COUNT_REG                             0xb02c
  62 #define MIPIA_HFP_COUNT_REG                             0xb030
  63 #define MIPIA_HACTIVE_COUNT_REG                         0xb034
  64 #define MIPIA_VSYNC_COUNT_REG                           0xb038
  65 #define MIPIA_VBP_COUNT_REG                             0xb03c
  66 #define MIPIA_VFP_COUNT_REG                             0xb040
  67 #define MIPIA_HIGH_LOW_SWITCH_COUNT_REG                 0xb044
  68 #define MIPIA_DPI_CONTROL_REG                           0xb048
  69 #define MIPIA_DPI_DATA_REG                              0xb04c
  70 #define MIPIA_INIT_COUNT_REG                            0xb050
  71 #define MIPIA_MAX_RETURN_PACK_SIZE_REG                  0xb054
  72 #define MIPIA_VIDEO_MODE_FORMAT_REG                     0xb058
  73 #define MIPIA_EOT_DISABLE_REG                           0xb05c
  74 #define MIPIA_LP_BYTECLK_REG                            0xb060
  75 #define MIPIA_LP_GEN_DATA_REG                           0xb064
  76 #define MIPIA_HS_GEN_DATA_REG                           0xb068
  77 #define MIPIA_LP_GEN_CTRL_REG                           0xb06c
  78 #define MIPIA_HS_GEN_CTRL_REG                           0xb070
  79 #define MIPIA_GEN_FIFO_STAT_REG                         0xb074
  80 #define MIPIA_HS_LS_DBI_ENABLE_REG                      0xb078
  81 #define MIPIA_DPHY_PARAM_REG                            0xb080
  82 #define MIPIA_DBI_BW_CTRL_REG                           0xb084
  83 #define MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG              0xb088
  84
  85 #define DSI_DEVICE_READY                                (0x1)
  86 #define DSI_POWER_STATE_ULPS_ENTER                      (0x2 << 1)
  87 #define DSI_POWER_STATE_ULPS_EXIT                       (0x1 << 1)
  88 #define DSI_POWER_STATE_ULPS_OFFSET                     (0x1)
  89
  90
  91 #define DSI_ONE_DATA_LANE                               (0x1)
  92 #define DSI_TWO_DATA_LANE                               (0x2)
  93 #define DSI_THREE_DATA_LANE                             (0X3)
  94 #define DSI_FOUR_DATA_LANE                              (0x4)
  95 #define DSI_DPI_VIRT_CHANNEL_OFFSET                     (0x3)
  96 #define DSI_DBI_VIRT_CHANNEL_OFFSET                     (0x5)
  97 #define DSI_DPI_COLOR_FORMAT_RGB565                     (0x01 << 7)
  98 #define DSI_DPI_COLOR_FORMAT_RGB666                     (0x02 << 7)
  99 #define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK              (0x03 << 7)
 100 #define DSI_DPI_COLOR_FORMAT_RGB888                     (0x04 << 7)
 101 #define DSI_DBI_COLOR_FORMAT_OPTION2                    (0x05 << 13)
 102
 103 #define DSI_INTR_STATE_RXSOTERROR                       1
 104
 105 #define DSI_INTR_STATE_SPL_PKG_SENT                     (1 << 30)
 106 #define DSI_INTR_STATE_TE                               (1 << 31)
 107
 108 #define DSI_HS_TX_TIMEOUT_MASK                          (0xffffff)
 109
 110 #define DSI_LP_RX_TIMEOUT_MASK                          (0xffffff)
 111
 112 #define DSI_TURN_AROUND_TIMEOUT_MASK                    (0x3f)
 113
 114 #define DSI_RESET_TIMER_MASK                            (0xffff)
 115
 116 #define DSI_DBI_FIFO_WM_HALF                            (0x0)
 117 #define DSI_DBI_FIFO_WM_QUARTER                         (0x1)
 118 #define DSI_DBI_FIFO_WM_LOW                             (0x2)
 119
 120 #define DSI_DPI_TIMING_MASK                             (0xffff)
 121
 122 #define DSI_INIT_TIMER_MASK                             (0xffff)
 123
 124 #define DSI_DBI_RETURN_PACK_SIZE_MASK                   (0x3ff)
 125
 126 #define DSI_LP_BYTECLK_MASK                             (0x0ffff)
 127
 128 #define DSI_HS_CTRL_GEN_SHORT_W0                        (0x03)
 129 #define DSI_HS_CTRL_GEN_SHORT_W1                        (0x13)
 130 #define DSI_HS_CTRL_GEN_SHORT_W2                        (0x23)
 131 #define DSI_HS_CTRL_GEN_R0                              (0x04)
 132 #define DSI_HS_CTRL_GEN_R1                              (0x14)
 133 #define DSI_HS_CTRL_GEN_R2                              (0x24)
 134 #define DSI_HS_CTRL_GEN_LONG_W                          (0x29)
 135 #define DSI_HS_CTRL_MCS_SHORT_W0                        (0x05)
 136 #define DSI_HS_CTRL_MCS_SHORT_W1                        (0x15)
 137 #define DSI_HS_CTRL_MCS_R0                              (0x06)
 138 #define DSI_HS_CTRL_MCS_LONG_W                          (0x39)
 139 #define DSI_HS_CTRL_VC_OFFSET                           (0x06)
 140 #define DSI_HS_CTRL_WC_OFFSET                           (0x08)
 141
 142 #define DSI_FIFO_GEN_HS_DATA_FULL                       (1 << 0)
 143 #define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY                 (1 << 1)
 144 #define DSI_FIFO_GEN_HS_DATA_EMPTY                      (1 << 2)
 145 #define DSI_FIFO_GEN_LP_DATA_FULL                       (1 << 8)
 146 #define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY                 (1 << 9)
 147 #define DSI_FIFO_GEN_LP_DATA_EMPTY                      (1 << 10)
 148 #define DSI_FIFO_GEN_HS_CTRL_FULL                       (1 << 16)
 149 #define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY                 (1 << 17)
 150 #define DSI_FIFO_GEN_HS_CTRL_EMPTY                      (1 << 18)
 151 #define DSI_FIFO_GEN_LP_CTRL_FULL                       (1 << 24)
 152 #define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY                 (1 << 25)
 153 #define DSI_FIFO_GEN_LP_CTRL_EMPTY                      (1 << 26)
 154 #define DSI_FIFO_DBI_EMPTY                              (1 << 27)
 155 #define DSI_FIFO_DPI_EMPTY                              (1 << 28)
 156
 157 #define DSI_DBI_HS_LP_SWITCH_MASK                       (0x1)
 158
 159 #define DSI_HS_LP_SWITCH_COUNTER_OFFSET                 (0x0)
 160 #define DSI_LP_HS_SWITCH_COUNTER_OFFSET                 (0x16)
 161
 162 #define DSI_DPI_CTRL_HS_SHUTDOWN                        (0x00000001)
 163 #define DSI_DPI_CTRL_HS_TURN_ON                         (0x00000002)
 164
 165 /* Medfield DSI adapter registers */
 166 #define MIPIA_CONTROL_REG                               0xb104
 167 #define MIPIA_DATA_ADD_REG                              0xb108
 168 #define MIPIA_DATA_LEN_REG                              0xb10c
 169 #define MIPIA_CMD_ADD_REG                               0xb110
 170 #define MIPIA_CMD_LEN_REG                               0xb114
 171
 172 enum {
 173         MDFLD_DSI_ENCODER_DBI = 0,
 174         MDFLD_DSI_ENCODER_DPI,
 175 };
 176
 177 enum {
 178         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
 179         MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
 180         MDFLD_DSI_VIDEO_BURST_MODE = 3,
 181 };
 182
 183 #define DSI_DPI_COMPLETE_LAST_LINE                      (1 << 2)
 184 #define DSI_DPI_DISABLE_BTA                             (1 << 3)
 185
 186 struct mdfld_dsi_connector_state {
 187         u32 mipi_ctrl_reg;
 188 };
 189
 190 struct mdfld_dsi_encoder_state {
 191
 192 };
 193
 194 struct mdfld_dsi_connector {
 195         /*
 196          * This is ugly, but I have to use connector in it! :-(
 197          * FIXME: use drm_connector instead.
 198          */
 199         struct psb_intel_output base;
 200
 201         int pipe;
 202         void *private;
 203         void *pkg_sender;
 204 };
 205
 206 struct mdfld_dsi_encoder {
 207         struct drm_encoder base;
 208         void *private;
 209 };
 210
 211 /*
 212  * DSI config, consists of one DSI connector, two DSI encoders.
 213  * DRM will pick up on DSI encoder basing on differents configs.
 214  */
 215 struct mdfld_dsi_config {
 216         struct drm_device *dev;
 217         struct drm_display_mode *fixed_mode;
 218         struct drm_display_mode *mode;
 219
 220         struct mdfld_dsi_connector *connector;
 221         struct mdfld_dsi_encoder *encoders[DRM_CONNECTOR_MAX_ENCODER];
 222         struct mdfld_dsi_encoder *encoder;
 223
 224         int changed;
 225
 226         int bpp;
 227         int type;
 228         int lane_count;
 229         /*Virtual channel number for this encoder*/
 230         int channel_num;
 231         /*video mode configure*/
 232         int video_mode;
 233
 234         int dvr_ic_inited;
 235 };
 236
 237 #define MDFLD_DSI_CONNECTOR(psb_output) \
 238                 (container_of(psb_output, struct mdfld_dsi_connector, base))
 239
 240 #define MDFLD_DSI_ENCODER(encoder) \
 241                 (container_of(encoder, struct mdfld_dsi_encoder, base))
 242
 243 static inline struct mdfld_dsi_config *
 244         mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
 245 {
 246         if (!connector)
 247                 return NULL;
 248         return (struct mdfld_dsi_config *)connector->private;
 249 }
 250
 251 static inline void *mdfld_dsi_get_pkg_sender(struct mdfld_dsi_config *config)
 252 {
 253         struct mdfld_dsi_connector *dsi_connector;
 254
 255         if (!config)
 256                 return NULL;
 257
 258         dsi_connector = config->connector;
 259
 260         if (!dsi_connector)
 261                 return NULL;
 262
 263         return dsi_connector->pkg_sender;
 264 }
 265
 266 static inline struct mdfld_dsi_config *
 267         mdfld_dsi_encoder_get_config(struct mdfld_dsi_encoder *encoder)
 268 {
 269         if (!encoder)
 270                 return NULL;
 271         return (struct mdfld_dsi_config *)encoder->private;
 272 }
 273
 274 static inline struct mdfld_dsi_connector *
 275         mdfld_dsi_encoder_get_connector(struct mdfld_dsi_encoder *encoder)
 276 {
 277         struct mdfld_dsi_config *config;
 278
 279         if (!encoder)
 280                 return NULL;
 281
 282         config = mdfld_dsi_encoder_get_config(encoder);
 283         if (!config)
 284                 return NULL;
 285
 286         return config->connector;
 287 }
 288
 289 static inline void *mdfld_dsi_encoder_get_pkg_sender(
 290         struct mdfld_dsi_encoder *encoder)
 291 {
 292         struct mdfld_dsi_config *dsi_config;
 293
 294         dsi_config = mdfld_dsi_encoder_get_config(encoder);
 295         if (!dsi_config)
 296                 return NULL;
 297
 298         return mdfld_dsi_get_pkg_sender(dsi_config);
 299 }
 300
 301 static inline int mdfld_dsi_encoder_get_pipe(struct mdfld_dsi_encoder *encoder)
 302 {
 303         struct mdfld_dsi_connector *connector;
 304
 305         if (!encoder)
 306                 return -1;
 307
 308         connector = mdfld_dsi_encoder_get_connector(encoder);
 309         if (!connector)
 310                 return -1;
 311
 312         return connector->pipe;
 313 }
 314
 315 extern void mdfld_dsi_gen_fifo_ready(struct drm_device *dev,
 316                                 u32 gen_fifo_stat_reg, u32 fifo_stat);
 317 extern void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config,
 318                                 int pipe);
 319 extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
 320                                 int level);
 321 extern void mdfld_dsi_output_init(struct drm_device *dev, int pipe,
 322                                 struct mdfld_dsi_config *config,
 323                                 struct panel_funcs *p_cmd_funcs,
 324                                 struct panel_funcs *p_vid_funcs);
 325 extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
 326                                 int pipe);
 327
 328 #endif /*__MDFLD_DSI_OUTPUT_H__*/