arch/mips/pci/msi-octeon.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2005-2009 Cavium Networks
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/msi.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/interrupt.h>
  13
  14 #include <asm/octeon/octeon.h>
  15 #include <asm/octeon/cvmx-npi-defs.h>
  16 #include <asm/octeon/cvmx-pci-defs.h>
  17 #include <asm/octeon/cvmx-npei-defs.h>
  18 #include <asm/octeon/cvmx-pexp-defs.h>
  19 #include <asm/octeon/pci-octeon.h>
  20
  21 /*
  22  * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
  23  * in use.
  24  */
  25 static uint64_t msi_free_irq_bitmask;
  26
  27 /*
  28  * Each bit in msi_multiple_irq_bitmask tells that the device using
  29  * this bit in msi_free_irq_bitmask is also using the next bit. This
  30  * is used so we can disable all of the MSI interrupts when a device
  31  * uses multiple.
  32  */
  33 static uint64_t msi_multiple_irq_bitmask;
  34
  35 /*
  36  * This lock controls updates to msi_free_irq_bitmask and
  37  * msi_multiple_irq_bitmask.
  38  */
  39 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
  40
  41
  42 /**
  43  * Called when a driver request MSI interrupts instead of the
  44  * legacy INT A-D. This routine will allocate multiple interrupts
  45  * for MSI devices that support them. A device can override this by
  46  * programming the MSI control bits [6:4] before calling
  47  * pci_enable_msi().
  48  *
  49  * @dev:    Device requesting MSI interrupts
  50  * @desc:   MSI descriptor
  51  *
  52  * Returns 0 on success.
  53  */
  54 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
  55 {
  56         struct msi_msg msg;
  57         uint16_t control;
  58         int configured_private_bits;
  59         int request_private_bits;
  60         int irq;
  61         int irq_step;
  62         uint64_t search_mask;
  63
  64         /*
  65          * Read the MSI config to figure out how many IRQs this device
  66          * wants.  Most devices only want 1, which will give
  67          * configured_private_bits and request_private_bits equal 0.
  68          */
  69         pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
  70                              &control);
  71
  72         /*
  73          * If the number of private bits has been configured then use
  74          * that value instead of the requested number. This gives the
  75          * driver the chance to override the number of interrupts
  76          * before calling pci_enable_msi().
  77          */
  78         configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
  79         if (configured_private_bits == 0) {
  80                 /* Nothing is configured, so use the hardware requested size */
  81                 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
  82         } else {
  83                 /*
  84                  * Use the number of configured bits, assuming the
  85                  * driver wanted to override the hardware request
  86                  * value.
  87                  */
  88                 request_private_bits = configured_private_bits;
  89         }
  90
  91         /*
  92          * The PCI 2.3 spec mandates that there are at most 32
  93          * interrupts. If this device asks for more, only give it one.
  94          */
  95         if (request_private_bits > 5)
  96                 request_private_bits = 0;
  97
  98 try_only_one:
  99         /*
 100          * The IRQs have to be aligned on a power of two based on the
 101          * number being requested.
 102          */
 103         irq_step = 1 << request_private_bits;
 104
 105         /* Mask with one bit for each IRQ */
 106         search_mask = (1 << irq_step) - 1;
 107
 108         /*
 109          * We're going to search msi_free_irq_bitmask_lock for zero
 110          * bits. This represents an MSI interrupt number that isn't in
 111          * use.
 112          */
 113         spin_lock(&msi_free_irq_bitmask_lock);
 114         for (irq = 0; irq < 64; irq += irq_step) {
 115                 if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
 116                         msi_free_irq_bitmask |= search_mask << irq;
 117                         msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
 118                         break;
 119                 }
 120         }
 121         spin_unlock(&msi_free_irq_bitmask_lock);
 122
 123         /* Make sure the search for available interrupts didn't fail */
 124         if (irq >= 64) {
 125                 if (request_private_bits) {
 126                         pr_err("arch_setup_msi_irq: Unable to find %d free "
 127                                "interrupts, trying just one",
 128                                1 << request_private_bits);
 129                         request_private_bits = 0;
 130                         goto try_only_one;
 131                 } else
 132                         panic("arch_setup_msi_irq: Unable to find a free MSI "
 133                               "interrupt");
 134         }
 135
 136         /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
 137         irq += OCTEON_IRQ_MSI_BIT0;
 138
 139         switch (octeon_dma_bar_type) {
 140         case OCTEON_DMA_BAR_TYPE_SMALL:
 141                 /* When not using big bar, Bar 0 is based at 128MB */
 142                 msg.address_lo =
 143                         ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
 144                 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
 145         case OCTEON_DMA_BAR_TYPE_BIG:
 146                 /* When using big bar, Bar 0 is based at 0 */
 147                 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
 148                 msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
 149                 break;
 150         case OCTEON_DMA_BAR_TYPE_PCIE:
 151                 /* When using PCIe, Bar 0 is based at 0 */
 152                 /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
 153                 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
 154                 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
 155                 break;
 156         default:
 157                 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
 158         }
 159         msg.data = irq - OCTEON_IRQ_MSI_BIT0;
 160
 161         /* Update the number of IRQs the device has available to it */
 162         control &= ~PCI_MSI_FLAGS_QSIZE;
 163         control |= request_private_bits << 4;
 164         pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
 165                               control);
 166
 167         set_irq_msi(irq, desc);
 168         write_msi_msg(irq, &msg);
 169         return 0;
 170 }
 171
 172
 173 /**
 174  * Called when a device no longer needs its MSI interrupts. All
 175  * MSI interrupts for the device are freed.
 176  *
 177  * @irq:    The devices first irq number. There may be multple in sequence.
 178  */
 179 void arch_teardown_msi_irq(unsigned int irq)
 180 {
 181         int number_irqs;
 182         uint64_t bitmask;
 183
 184         if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
 185                 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
 186                       "MSI interrupt (%d)", irq);
 187         irq -= OCTEON_IRQ_MSI_BIT0;
 188
 189         /*
 190          * Count the number of IRQs we need to free by looking at the
 191          * msi_multiple_irq_bitmask. Each bit set means that the next
 192          * IRQ is also owned by this device.
 193          */
 194         number_irqs = 0;
 195         while ((irq+number_irqs < 64) &&
 196                (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
 197                 number_irqs++;
 198         number_irqs++;
 199         /* Mask with one bit for each IRQ */
 200         bitmask = (1 << number_irqs) - 1;
 201         /* Shift the mask to the correct bit location */
 202         bitmask <<= irq;
 203         if ((msi_free_irq_bitmask & bitmask) != bitmask)
 204                 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
 205                       "interrupt (%d) not in use", irq);
 206
 207         /* Checks are done, update the in use bitmask */
 208         spin_lock(&msi_free_irq_bitmask_lock);
 209         msi_free_irq_bitmask &= ~bitmask;
 210         msi_multiple_irq_bitmask &= ~bitmask;
 211         spin_unlock(&msi_free_irq_bitmask_lock);
 212 }
 213
 214
 215 /*
 216  * Called by the interrupt handling code when an MSI interrupt
 217  * occurs.
 218  */
 219 static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
 220 {
 221         uint64_t msi_bits;
 222         int irq;
 223
 224         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
 225                 msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
 226         else
 227                 msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
 228         irq = fls64(msi_bits);
 229         if (irq) {
 230                 irq += OCTEON_IRQ_MSI_BIT0 - 1;
 231                 if (irq_desc[irq].action) {
 232                         do_IRQ(irq);
 233                         return IRQ_HANDLED;
 234                 } else {
 235                         pr_err("Spurious MSI interrupt %d\n", irq);
 236                         if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
 237                                 /* These chips have PCIe */
 238                                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
 239                                                1ull << (irq -
 240                                                         OCTEON_IRQ_MSI_BIT0));
 241                         } else {
 242                                 /* These chips have PCI */
 243                                 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
 244                                                1ull << (irq -
 245                                                         OCTEON_IRQ_MSI_BIT0));
 246                         }
 247                 }
 248         }
 249         return IRQ_NONE;
 250 }
 251
 252 static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
 253
 254 static void octeon_irq_msi_ack(unsigned int irq)
 255 {
 256         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
 257                 /* These chips have PCI */
 258                 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
 259                                1ull << (irq - OCTEON_IRQ_MSI_BIT0));
 260         } else {
 261                 /*
 262                  * These chips have PCIe. Thankfully the ACK doesn't
 263                  * need any locking.
 264                  */
 265                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
 266                                1ull << (irq - OCTEON_IRQ_MSI_BIT0));
 267         }
 268 }
 269
 270 static void octeon_irq_msi_eoi(unsigned int irq)
 271 {
 272         /* Nothing needed */
 273 }
 274
 275 static void octeon_irq_msi_enable(unsigned int irq)
 276 {
 277         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
 278                 /*
 279                  * Octeon PCI doesn't have the ability to mask/unmask
 280                  * MSI interrupts individually.  Instead of
 281                  * masking/unmasking them in groups of 16, we simple
 282                  * assume MSI devices are well behaved.  MSI
 283                  * interrupts are always enable and the ACK is assumed
 284                  * to be enough.
 285                  */
 286         } else {
 287                 /* These chips have PCIe.  Note that we only support
 288                  * the first 64 MSI interrupts.  Unfortunately all the
 289                  * MSI enables are in the same register.  We use
 290                  * MSI0's lock to control access to them all.
 291                  */
 292                 uint64_t en;
 293                 unsigned long flags;
 294                 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
 295                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
 296                 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
 297                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
 298                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
 299                 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
 300         }
 301 }
 302
 303 static void octeon_irq_msi_disable(unsigned int irq)
 304 {
 305         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
 306                 /* See comment in enable */
 307         } else {
 308                 /*
 309                  * These chips have PCIe.  Note that we only support
 310                  * the first 64 MSI interrupts.  Unfortunately all the
 311                  * MSI enables are in the same register.  We use
 312                  * MSI0's lock to control access to them all.
 313                  */
 314                 uint64_t en;
 315                 unsigned long flags;
 316                 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
 317                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
 318                 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
 319                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
 320                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
 321                 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
 322         }
 323 }
 324
 325 static struct irq_chip octeon_irq_chip_msi = {
 326         .name = "MSI",
 327         .enable = octeon_irq_msi_enable,
 328         .disable = octeon_irq_msi_disable,
 329         .ack = octeon_irq_msi_ack,
 330         .eoi = octeon_irq_msi_eoi,
 331 };
 332
 333 /*
 334  * Initializes the MSI interrupt handling code
 335  */
 336 static int __init octeon_msi_initialize(void)
 337 {
 338         int irq;
 339
 340         for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
 341                 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
 342                                          handle_percpu_irq);
 343         }
 344
 345         if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
 346                 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
 347                                 IRQF_SHARED,
 348                                 "MSI[0:63]", octeon_msi_interrupt))
 349                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
 350         } else if (octeon_is_pci_host()) {
 351                 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
 352                                 IRQF_SHARED,
 353                                 "MSI[0:15]", octeon_msi_interrupt))
 354                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
 355
 356                 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
 357                                 IRQF_SHARED,
 358                                 "MSI[16:31]", octeon_msi_interrupt))
 359                         panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
 360
 361                 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
 362                                 IRQF_SHARED,
 363                                 "MSI[32:47]", octeon_msi_interrupt))
 364                         panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
 365
 366                 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
 367                                 IRQF_SHARED,
 368                                 "MSI[48:63]", octeon_msi_interrupt))
 369                         panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
 370
 371         }
 372         return 0;
 373 }
 374 subsys_initcall(octeon_msi_initialize);