2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: rf function code
29 * IFRFbWriteEmbeded - Embeded write RF register via MAC
35 #if !defined(__MAC_H__)
38 #if !defined(__SROM_H__)
41 #if !defined(__TBIT_H__)
44 #if !defined(__RF_H__)
47 #if !defined(__BASEBAND_H__)
51 /*--------------------- Static Definitions -------------------------*/
53 //static int msglevel =MSG_LEVEL_INFO;
55 #define BY_RF2959_REG_LEN 23 //24bits
56 #define CB_RF2959_INIT_SEQ 15
57 #define SWITCH_CHANNEL_DELAY_RF2959 200 //us
58 #define RF2959_PWR_IDX_LEN 32
60 #define BY_MA2825_REG_LEN 23 //24bit
61 #define CB_MA2825_INIT_SEQ 13
62 #define SWITCH_CHANNEL_DELAY_MA2825 200 //us
63 #define MA2825_PWR_IDX_LEN 31
65 #define BY_AL2230_REG_LEN 23 //24bit
66 #define CB_AL2230_INIT_SEQ 15
67 #define SWITCH_CHANNEL_DELAY_AL2230 200 //us
68 #define AL2230_PWR_IDX_LEN 64
71 #define BY_UW2451_REG_LEN 23
72 #define CB_UW2451_INIT_SEQ 6
73 #define SWITCH_CHANNEL_DELAY_UW2451 200 //us
74 #define UW2451_PWR_IDX_LEN 25
76 //{{ RobertYu: 20041118
77 #define BY_MA2829_REG_LEN 23 //24bit
78 #define CB_MA2829_INIT_SEQ 13
79 #define SWITCH_CHANNEL_DELAY_MA2829 200 //us
80 #define MA2829_PWR_IDX_LEN 64
83 //{{ RobertYu:20050103
84 #define BY_AL7230_REG_LEN 23 //24bit
85 #define CB_AL7230_INIT_SEQ 16
86 #define SWITCH_CHANNEL_DELAY_AL7230 200 //us
87 #define AL7230_PWR_IDX_LEN 64
90 //{{ RobertYu: 20041210
91 #define BY_UW2452_REG_LEN 23
92 #define CB_UW2452_INIT_SEQ 5 //RoberYu:20050113, Rev0.2 Programming Guide(remove R3, so 6-->5)
93 #define SWITCH_CHANNEL_DELAY_UW2452 100 //us
94 #define UW2452_PWR_IDX_LEN 64
97 #define BY_VT3226_REG_LEN 23
98 #define CB_VT3226_INIT_SEQ 12
99 #define SWITCH_CHANNEL_DELAY_VT3226 200 //us
100 #define VT3226_PWR_IDX_LEN 16
102 /*--------------------- Static Classes ----------------------------*/
104 /*--------------------- Static Variables --------------------------*/
108 const DWORD dwAL2230InitTable
[CB_AL2230_INIT_SEQ
] = {
109 0x03F79000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
110 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
111 0x01A00200+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
112 0x00FFF300+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
113 0x0005A400+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
114 0x0F4DC500+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
115 0x0805B600+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
116 0x0146C700+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
117 0x00068800+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
118 0x0403B900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
119 0x00DBBA00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
120 0x00099B00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, //
121 0x0BDFFC00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
122 0x00000D00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
123 0x00580F00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
126 const DWORD dwAL2230ChannelTable0
[CB_MAX_CHANNEL
] = {
127 0x03F79000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 1, Tf = 2412MHz
128 0x03F79000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 2, Tf = 2417MHz
129 0x03E79000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 3, Tf = 2422MHz
130 0x03E79000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 4, Tf = 2427MHz
131 0x03F7A000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 5, Tf = 2432MHz
132 0x03F7A000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 6, Tf = 2437MHz
133 0x03E7A000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 2442MHz
134 0x03E7A000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 2447MHz
135 0x03F7B000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 2452MHz
136 0x03F7B000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 10, Tf = 2457MHz
137 0x03E7B000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 2462MHz
138 0x03E7B000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 2467MHz
139 0x03F7C000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 13, Tf = 2472MHz
140 0x03E7C000+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
// channel = 14, Tf = 2412M
143 const DWORD dwAL2230ChannelTable1
[CB_MAX_CHANNEL
] = {
144 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 1, Tf = 2412MHz
145 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 2, Tf = 2417MHz
146 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 3, Tf = 2422MHz
147 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 4, Tf = 2427MHz
148 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 5, Tf = 2432MHz
149 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 6, Tf = 2437MHz
150 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 2442MHz
151 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 2447MHz
152 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 2452MHz
153 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 10, Tf = 2457MHz
154 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 2462MHz
155 0x0B333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 2467MHz
156 0x03333100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 13, Tf = 2472MHz
157 0x06666100+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
// channel = 14, Tf = 2412M
160 DWORD dwAL2230PowerTable
[AL2230_PWR_IDX_LEN
] = {
161 0x04040900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
162 0x04041900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
163 0x04042900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
164 0x04043900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
165 0x04044900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
166 0x04045900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
167 0x04046900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
168 0x04047900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
169 0x04048900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
170 0x04049900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
171 0x0404A900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
172 0x0404B900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
173 0x0404C900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
174 0x0404D900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
175 0x0404E900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
176 0x0404F900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
177 0x04050900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
178 0x04051900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
179 0x04052900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
180 0x04053900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
181 0x04054900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
182 0x04055900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
183 0x04056900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
184 0x04057900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
185 0x04058900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
186 0x04059900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
187 0x0405A900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
188 0x0405B900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
189 0x0405C900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
190 0x0405D900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
191 0x0405E900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
192 0x0405F900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
193 0x04060900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
194 0x04061900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
195 0x04062900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
196 0x04063900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
197 0x04064900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
198 0x04065900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
199 0x04066900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
200 0x04067900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
201 0x04068900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
202 0x04069900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
203 0x0406A900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
204 0x0406B900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
205 0x0406C900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
206 0x0406D900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
207 0x0406E900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
208 0x0406F900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
209 0x04070900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
210 0x04071900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
211 0x04072900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
212 0x04073900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
213 0x04074900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
214 0x04075900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
215 0x04076900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
216 0x04077900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
217 0x04078900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
218 0x04079900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
219 0x0407A900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
220 0x0407B900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
221 0x0407C900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
222 0x0407D900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
223 0x0407E900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
,
224 0x0407F900+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
227 //{{ RobertYu:20050104
228 // 40MHz reference frequency
229 // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
230 const DWORD dwAL7230InitTable
[CB_AL7230_INIT_SEQ
] = {
231 0x00379000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Channel1 // Need modify for 11a
232 0x13333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Channel1 // Need modify for 11a
233 0x841FF200+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: 451FE2
234 0x3FDFA300+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: 5FDFA3
235 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // 11b/g // Need modify for 11a
236 //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
237 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
238 0x802B5500+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: 8D1B55
239 0x56AF3600+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
240 0xCE020700+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: 860207
241 0x6EBC0800+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
242 0x221BB900+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
243 0xE0000A00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: E0600A
244 0x08031B00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
245 //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
246 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
247 0x000A3C00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11a: 00143C
248 0xFFFFFD00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
249 0x00000E00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
250 0x1ABA8F00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
// Need modify for 11a: 12BACF
253 const DWORD dwAL7230InitTableAMode
[CB_AL7230_INIT_SEQ
] = {
254 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Channel184 // Need modify for 11b/g
255 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Channel184 // Need modify for 11b/g
256 0x451FE200+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g
257 0x5FDFA300+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g
258 0x67F78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // 11a // Need modify for 11b/g
259 0x853F5500+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g, RoberYu:20050113
260 0x56AF3600+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
261 0xCE020700+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g
262 0x6EBC0800+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
263 0x221BB900+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
264 0xE0600A00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g
265 0x08031B00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
266 0x00147C00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // Need modify for 11b/g
267 0xFFFFFD00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
268 0x00000E00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
,
269 0x12BACF00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
// Need modify for 11b/g
273 const DWORD dwAL7230ChannelTable0
[CB_MAX_CHANNEL
] = {
274 0x00379000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 1, Tf = 2412MHz
275 0x00379000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 2, Tf = 2417MHz
276 0x00379000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 3, Tf = 2422MHz
277 0x00379000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 4, Tf = 2427MHz
278 0x0037A000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 5, Tf = 2432MHz
279 0x0037A000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 6, Tf = 2437MHz
280 0x0037A000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 2442MHz
281 0x0037A000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
282 0x0037B000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
283 0x0037B000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
284 0x0037B000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
285 0x0037B000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
286 0x0037C000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
287 0x0037C000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 14, Tf = 2484MHz
289 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
290 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 183, Tf = 4915MHz (15)
291 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 184, Tf = 4920MHz (16)
292 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 185, Tf = 4925MHz (17)
293 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 187, Tf = 4935MHz (18)
294 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 188, Tf = 4940MHz (19)
295 0x0FF52000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 189, Tf = 4945MHz (20)
296 0x0FF53000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 192, Tf = 4960MHz (21)
297 0x0FF53000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 196, Tf = 4980MHz (22)
299 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
300 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
302 0x0FF54000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 5035MHz (23)
303 0x0FF54000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 5040MHz (24)
304 0x0FF54000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 5045MHz (25)
305 0x0FF54000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 5055MHz (26)
306 0x0FF54000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 5060MHz (27)
307 0x0FF55000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 16, Tf = 5080MHz (28)
308 0x0FF56000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 34, Tf = 5170MHz (29)
309 0x0FF56000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 36, Tf = 5180MHz (30)
310 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
311 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 40, Tf = 5200MHz (32)
312 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 42, Tf = 5210MHz (33)
313 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 44, Tf = 5220MHz (34)
314 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 46, Tf = 5230MHz (35)
315 0x0FF57000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 48, Tf = 5240MHz (36)
316 0x0FF58000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 52, Tf = 5260MHz (37)
317 0x0FF58000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 56, Tf = 5280MHz (38)
318 0x0FF58000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 60, Tf = 5300MHz (39)
319 0x0FF59000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 64, Tf = 5320MHz (40)
321 0x0FF5C000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 100, Tf = 5500MHz (41)
322 0x0FF5C000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 104, Tf = 5520MHz (42)
323 0x0FF5C000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 108, Tf = 5540MHz (43)
324 0x0FF5D000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 112, Tf = 5560MHz (44)
325 0x0FF5D000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 116, Tf = 5580MHz (45)
326 0x0FF5D000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 120, Tf = 5600MHz (46)
327 0x0FF5E000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 124, Tf = 5620MHz (47)
328 0x0FF5E000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 128, Tf = 5640MHz (48)
329 0x0FF5E000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 132, Tf = 5660MHz (49)
330 0x0FF5F000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 136, Tf = 5680MHz (50)
331 0x0FF5F000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 140, Tf = 5700MHz (51)
332 0x0FF60000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 149, Tf = 5745MHz (52)
333 0x0FF60000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 153, Tf = 5765MHz (53)
334 0x0FF60000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 157, Tf = 5785MHz (54)
335 0x0FF61000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 161, Tf = 5805MHz (55)
336 0x0FF61000+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
// channel = 165, Tf = 5825MHz (56)
339 const DWORD dwAL7230ChannelTable1
[CB_MAX_CHANNEL
] = {
340 0x13333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 1, Tf = 2412MHz
341 0x1B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 2, Tf = 2417MHz
342 0x03333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 3, Tf = 2422MHz
343 0x0B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 4, Tf = 2427MHz
344 0x13333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 5, Tf = 2432MHz
345 0x1B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 6, Tf = 2437MHz
346 0x03333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 2442MHz
347 0x0B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 2447MHz
348 0x13333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 2452MHz
349 0x1B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 10, Tf = 2457MHz
350 0x03333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 2462MHz
351 0x0B333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 2467MHz
352 0x13333100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 13, Tf = 2472MHz
353 0x06666100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 14, Tf = 2484MHz
355 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
356 0x1D555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 183, Tf = 4915MHz (15)
357 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 184, Tf = 4920MHz (16)
358 0x02AAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 185, Tf = 4925MHz (17)
359 0x08000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 187, Tf = 4935MHz (18)
360 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 188, Tf = 4940MHz (19)
361 0x0D555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 189, Tf = 4945MHz (20)
362 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 192, Tf = 4960MHz (21)
363 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 196, Tf = 4980MHz (22)
365 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
366 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
367 0x1D555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 5035MHz (23)
368 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 5040MHz (24)
369 0x02AAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 5045MHz (25)
370 0x08000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 5055MHz (26)
371 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 5060MHz (27)
372 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 16, Tf = 5080MHz (28)
373 0x05555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 34, Tf = 5170MHz (29)
374 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 36, Tf = 5180MHz (30)
375 0x10000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 38, Tf = 5190MHz (31)
376 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 40, Tf = 5200MHz (32)
377 0x1AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 42, Tf = 5210MHz (33)
378 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 44, Tf = 5220MHz (34)
379 0x05555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 46, Tf = 5230MHz (35)
380 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 48, Tf = 5240MHz (36)
381 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 52, Tf = 5260MHz (37)
382 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 56, Tf = 5280MHz (38)
383 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 60, Tf = 5300MHz (39)
384 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 64, Tf = 5320MHz (40)
385 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 100, Tf = 5500MHz (41)
386 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 104, Tf = 5520MHz (42)
387 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 108, Tf = 5540MHz (43)
388 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 112, Tf = 5560MHz (44)
389 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 116, Tf = 5580MHz (45)
390 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 120, Tf = 5600MHz (46)
391 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 124, Tf = 5620MHz (47)
392 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 128, Tf = 5640MHz (48)
393 0x0AAAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 132, Tf = 5660MHz (49)
394 0x15555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 136, Tf = 5680MHz (50)
395 0x00000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 140, Tf = 5700MHz (51)
396 0x18000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 149, Tf = 5745MHz (52)
397 0x02AAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 153, Tf = 5765MHz (53)
398 0x0D555100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 157, Tf = 5785MHz (54)
399 0x18000100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 161, Tf = 5805MHz (55)
400 0x02AAA100+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
// channel = 165, Tf = 5825MHz (56)
403 const DWORD dwAL7230ChannelTable2
[CB_MAX_CHANNEL
] = {
404 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 1, Tf = 2412MHz
405 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 2, Tf = 2417MHz
406 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 3, Tf = 2422MHz
407 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 4, Tf = 2427MHz
408 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 5, Tf = 2432MHz
409 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 6, Tf = 2437MHz
410 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 2442MHz
411 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 2447MHz
412 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 2452MHz
413 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 10, Tf = 2457MHz
414 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 2462MHz
415 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 2467MHz
416 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 13, Tf = 2472MHz
417 0x7FD78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 14, Tf = 2484MHz
419 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22)
420 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 183, Tf = 4915MHz (15)
421 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 184, Tf = 4920MHz (16)
422 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 185, Tf = 4925MHz (17)
423 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 187, Tf = 4935MHz (18)
424 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 188, Tf = 4940MHz (19)
425 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 189, Tf = 4945MHz (20)
426 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 192, Tf = 4960MHz (21)
427 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 196, Tf = 4980MHz (22)
429 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
430 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
431 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 7, Tf = 5035MHz (23)
432 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 8, Tf = 5040MHz (24)
433 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 9, Tf = 5045MHz (25)
434 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 11, Tf = 5055MHz (26)
435 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 12, Tf = 5060MHz (27)
436 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 16, Tf = 5080MHz (28)
437 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 34, Tf = 5170MHz (29)
438 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 36, Tf = 5180MHz (30)
439 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 38, Tf = 5190MHz (31)
440 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 40, Tf = 5200MHz (32)
441 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 42, Tf = 5210MHz (33)
442 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 44, Tf = 5220MHz (34)
443 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 46, Tf = 5230MHz (35)
444 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 48, Tf = 5240MHz (36)
445 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 52, Tf = 5260MHz (37)
446 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 56, Tf = 5280MHz (38)
447 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 60, Tf = 5300MHz (39)
448 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 64, Tf = 5320MHz (40)
449 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 100, Tf = 5500MHz (41)
450 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 104, Tf = 5520MHz (42)
451 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 108, Tf = 5540MHz (43)
452 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 112, Tf = 5560MHz (44)
453 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 116, Tf = 5580MHz (45)
454 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 120, Tf = 5600MHz (46)
455 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 124, Tf = 5620MHz (47)
456 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 128, Tf = 5640MHz (48)
457 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 132, Tf = 5660MHz (49)
458 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 136, Tf = 5680MHz (50)
459 0x67D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 140, Tf = 5700MHz (51)
460 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 149, Tf = 5745MHz (52)
461 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 153, Tf = 5765MHz (53)
462 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 157, Tf = 5785MHz (54)
463 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
, // channel = 161, Tf = 5805MHz (55)
464 0x77D78400+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
// channel = 165, Tf = 5825MHz (56)
471 /*--------------------- Static Functions --------------------------*/
477 * Description: AIROHA IFRF chip init function
481 * dwIoBase - I/O base address
485 * Return Value: TRUE if succeeded; FALSE if failed.
488 BOOL
s_bAL7230Init (DWORD_PTR dwIoBase
)
495 //3-wire control for normal mode
496 VNSvOutPortB(dwIoBase
+ MAC_REG_SOFTPWRCTL
, 0);
498 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, (SOFTPWRCTL_SWPECTI
|
499 SOFTPWRCTL_TXPEINV
));
500 BBvPowerSaveModeOFF(dwIoBase
); //RobertYu:20050106, have DC value for Calibration
502 for (ii
= 0; ii
< CB_AL7230_INIT_SEQ
; ii
++)
503 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[ii
]);
506 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, SOFTPWRCTL_SWPE3
);
509 MACvTimer0MicroSDelay(dwIoBase
, 150);//150us
510 bResult
&= IFRFbWriteEmbeded(dwIoBase
, (0x9ABA8F00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
)); //TXDCOC:active, RCK:diable
511 MACvTimer0MicroSDelay(dwIoBase
, 30);//30us
512 bResult
&= IFRFbWriteEmbeded(dwIoBase
, (0x3ABA8F00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
)); //TXDCOC:diable, RCK:active
513 MACvTimer0MicroSDelay(dwIoBase
, 30);//30us
514 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[CB_AL7230_INIT_SEQ
-1]); //TXDCOC:diable, RCK:diable
516 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, (SOFTPWRCTL_SWPE3
|
519 SOFTPWRCTL_TXPEINV
));
521 BBvPowerSaveModeON(dwIoBase
); // RobertYu:20050106
523 // PE1: TX_ON, PE2: RX_ON, PE3: PLLON
524 //3-wire control for power saving mode
525 VNSvOutPortB(dwIoBase
+ MAC_REG_PSPWRSIG
, (PSSIG_WPE3
| PSSIG_WPE2
)); //1100 0000
530 // Need to Pull PLLON low when writing channel registers through 3-wire interface
531 BOOL
s_bAL7230SelectChannel (DWORD_PTR dwIoBase
, BYTE byChannel
)
538 MACvWordRegBitsOff(dwIoBase
, MAC_REG_SOFTPWRCTL
, SOFTPWRCTL_SWPE3
);
540 bResult
&= IFRFbWriteEmbeded (dwIoBase
, dwAL7230ChannelTable0
[byChannel
-1]); //Reg0
541 bResult
&= IFRFbWriteEmbeded (dwIoBase
, dwAL7230ChannelTable1
[byChannel
-1]); //Reg1
542 bResult
&= IFRFbWriteEmbeded (dwIoBase
, dwAL7230ChannelTable2
[byChannel
-1]); //Reg4
545 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, SOFTPWRCTL_SWPE3
);
547 // Set Channel[7] = 0 to tell H/W channel is changing now.
548 VNSvOutPortB(dwIoBase
+ MAC_REG_CHANNEL
, (byChannel
& 0x7F));
549 MACvTimer0MicroSDelay(dwIoBase
, SWITCH_CHANNEL_DELAY_AL7230
);
550 // Set Channel[7] = 1 to tell H/W channel change is done.
551 VNSvOutPortB(dwIoBase
+ MAC_REG_CHANNEL
, (byChannel
| 0x80));
557 * Description: Select channel with UW2452 chip
561 * dwIoBase - I/O base address
562 * uChannel - Channel number
566 * Return Value: TRUE if succeeded; FALSE if failed.
571 //{{ RobertYu: 20041210
573 * Description: UW2452 IFRF chip init function
577 * dwIoBase - I/O base address
581 * Return Value: TRUE if succeeded; FALSE if failed.
588 ////////////////////////////////////////////////////////////////////////////////
591 * Description: VT3226 IFRF chip init function
595 * dwIoBase - I/O base address
599 * Return Value: TRUE if succeeded; FALSE if failed.
604 * Description: Select channel with VT3226 chip
608 * dwIoBase - I/O base address
609 * uChannel - Channel number
613 * Return Value: TRUE if succeeded; FALSE if failed.
619 /*--------------------- Export Variables --------------------------*/
621 /*--------------------- Export Functions --------------------------*/
624 * Description: Write to IF/RF, by embeded programming
628 * dwIoBase - I/O base address
629 * dwData - data to write
633 * Return Value: TRUE if succeeded; FALSE if failed.
636 BOOL
IFRFbWriteEmbeded (DWORD_PTR dwIoBase
, DWORD dwData
)
641 VNSvOutPortD(dwIoBase
+ MAC_REG_IFREGCTL
, dwData
);
643 // W_MAX_TIMEOUT is the timeout period
644 for (ww
= 0; ww
< W_MAX_TIMEOUT
; ww
++) {
645 VNSvInPortD(dwIoBase
+ MAC_REG_IFREGCTL
, &dwValue
);
646 if (BITbIsBitOn(dwValue
, IFREGCTL_DONE
))
650 if (ww
== W_MAX_TIMEOUT
) {
651 // DBG_PORT80_ALWAYS(0x32);
660 * Description: RFMD RF2959 IFRF chip init function
664 * dwIoBase - I/O base address
668 * Return Value: TRUE if succeeded; FALSE if failed.
673 * Description: Select channel with RFMD 2959 chip
677 * dwIoBase - I/O base address
678 * uChannel - Channel number
682 * Return Value: TRUE if succeeded; FALSE if failed.
687 * Description: AIROHA IFRF chip init function
691 * dwIoBase - I/O base address
695 * Return Value: TRUE if succeeded; FALSE if failed.
698 BOOL
RFbAL2230Init (DWORD_PTR dwIoBase
)
705 //3-wire control for normal mode
706 VNSvOutPortB(dwIoBase
+ MAC_REG_SOFTPWRCTL
, 0);
708 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, (SOFTPWRCTL_SWPECTI
|
709 SOFTPWRCTL_TXPEINV
));
710 //2008-8-21 chester <add>
713 MACvWordRegBitsOff(dwIoBase
, MAC_REG_SOFTPWRCTL
, SOFTPWRCTL_SWPE3
);
717 //patch abnormal AL2230 frequency output
718 //2008-8-21 chester <add>
719 IFRFbWriteEmbeded(dwIoBase
, (0x07168700+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
));
722 for (ii
= 0; ii
< CB_AL2230_INIT_SEQ
; ii
++)
723 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL2230InitTable
[ii
]);
724 //2008-8-21 chester <add>
725 MACvTimer0MicroSDelay(dwIoBase
, 30); //delay 30 us
728 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, SOFTPWRCTL_SWPE3
);
730 MACvTimer0MicroSDelay(dwIoBase
, 150);//150us
731 bResult
&= IFRFbWriteEmbeded(dwIoBase
, (0x00d80f00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
));
732 MACvTimer0MicroSDelay(dwIoBase
, 30);//30us
733 bResult
&= IFRFbWriteEmbeded(dwIoBase
, (0x00780f00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
));
734 MACvTimer0MicroSDelay(dwIoBase
, 30);//30us
735 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL2230InitTable
[CB_AL2230_INIT_SEQ
-1]);
737 MACvWordRegBitsOn(dwIoBase
, MAC_REG_SOFTPWRCTL
, (SOFTPWRCTL_SWPE3
|
740 SOFTPWRCTL_TXPEINV
));
742 //3-wire control for power saving mode
743 VNSvOutPortB(dwIoBase
+ MAC_REG_PSPWRSIG
, (PSSIG_WPE3
| PSSIG_WPE2
)); //1100 0000
748 BOOL
RFbAL2230SelectChannel (DWORD_PTR dwIoBase
, BYTE byChannel
)
754 bResult
&= IFRFbWriteEmbeded (dwIoBase
, dwAL2230ChannelTable0
[byChannel
-1]);
755 bResult
&= IFRFbWriteEmbeded (dwIoBase
, dwAL2230ChannelTable1
[byChannel
-1]);
757 // Set Channel[7] = 0 to tell H/W channel is changing now.
758 VNSvOutPortB(dwIoBase
+ MAC_REG_CHANNEL
, (byChannel
& 0x7F));
759 MACvTimer0MicroSDelay(dwIoBase
, SWITCH_CHANNEL_DELAY_AL2230
);
760 // Set Channel[7] = 1 to tell H/W channel change is done.
761 VNSvOutPortB(dwIoBase
+ MAC_REG_CHANNEL
, (byChannel
| 0x80));
767 * Description: UW2451 IFRF chip init function
771 * dwIoBase - I/O base address
775 * Return Value: TRUE if succeeded; FALSE if failed.
781 * Description: Select channel with UW2451 chip
785 * dwIoBase - I/O base address
786 * uChannel - Channel number
790 * Return Value: TRUE if succeeded; FALSE if failed.
795 * Description: Set sleep mode to UW2451 chip
799 * dwIoBase - I/O base address
800 * uChannel - Channel number
804 * Return Value: TRUE if succeeded; FALSE if failed.
809 * Description: RF init function
818 * Return Value: TRUE if succeeded; FALSE if failed.
826 switch (pDevice
->byRFType
) {
829 pDevice
->byMaxPwrLevel
= AL2230_PWR_IDX_LEN
;
830 bResult
= RFbAL2230Init(pDevice
->PortOffset
);
833 pDevice
->byMaxPwrLevel
= AL7230_PWR_IDX_LEN
;
834 bResult
= s_bAL7230Init(pDevice
->PortOffset
);
847 * Description: RF ShutDown function
856 * Return Value: TRUE if succeeded; FALSE if failed.
865 switch (pDevice
->byRFType
) {
867 bResult
= IFRFbWriteEmbeded (pDevice
->PortOffset
, 0x1ABAEF00+(BY_AL7230_REG_LEN
<<3)+IFREGCTL_REGW
);
877 * Description: Select channel
882 * byChannel - Channel number
886 * Return Value: TRUE if succeeded; FALSE if failed.
889 BOOL
RFbSelectChannel (DWORD_PTR dwIoBase
, BYTE byRFType
, BYTE byChannel
)
896 bResult
= RFbAL2230SelectChannel(dwIoBase
, byChannel
);
898 //{{ RobertYu: 20050104
900 bResult
= s_bAL7230SelectChannel(dwIoBase
, byChannel
);
914 * Description: Write WakeProgSyn
918 * dwIoBase - I/O base address
919 * uChannel - channel number
920 * bySleepCnt - SleepProgSyn count
922 * Return Value: None.
925 BOOL
RFvWriteWakeProgSyn (DWORD_PTR dwIoBase
, BYTE byRFType
, UINT uChannel
)
928 BYTE byInitCount
= 0;
929 BYTE bySleepCount
= 0;
931 VNSvOutPortW(dwIoBase
+ MAC_REG_MISCFFNDEX
, 0);
936 if (uChannel
> CB_MAX_CHANNEL_24G
)
939 byInitCount
= CB_AL2230_INIT_SEQ
+ 2; // Init Reg + Channel Reg (2)
941 if (byInitCount
> (MISCFIFO_SYNDATASIZE
- bySleepCount
)) {
945 for (ii
= 0; ii
< CB_AL2230_INIT_SEQ
; ii
++ ) {
946 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL2230InitTable
[ii
]);
948 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL2230ChannelTable0
[uChannel
-1]);
950 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL2230ChannelTable1
[uChannel
-1]);
953 //{{ RobertYu: 20050104
954 // Need to check, PLLON need to be low for channel setting
956 byInitCount
= CB_AL7230_INIT_SEQ
+ 3; // Init Reg + Channel Reg (3)
958 if (byInitCount
> (MISCFIFO_SYNDATASIZE
- bySleepCount
)) {
962 if (uChannel
<= CB_MAX_CHANNEL_24G
)
964 for (ii
= 0; ii
< CB_AL7230_INIT_SEQ
; ii
++ ) {
965 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL7230InitTable
[ii
]);
970 for (ii
= 0; ii
< CB_AL7230_INIT_SEQ
; ii
++ ) {
971 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL7230InitTableAMode
[ii
]);
975 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL7230ChannelTable0
[uChannel
-1]);
977 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL7230ChannelTable1
[uChannel
-1]);
979 MACvSetMISCFifo(dwIoBase
, (WORD
)(MISCFIFO_SYNDATA_IDX
+ ii
), dwAL7230ChannelTable2
[uChannel
-1]);
992 MACvSetMISCFifo(dwIoBase
, MISCFIFO_SYNINFO_IDX
, (DWORD
)MAKEWORD(bySleepCount
, byInitCount
));
998 * Description: Set Tx power
1002 * dwIoBase - I/O base address
1003 * dwRFPowerTable - RF Tx Power Setting
1007 * Return Value: TRUE if succeeded; FALSE if failed.
1011 IN PSDevice pDevice
,
1016 BOOL bResult
= TRUE
;
1021 if (pDevice
->dwDiagRefCount
!= 0) {
1024 if ((uCH
< 1) || (uCH
> CB_MAX_CHANNEL
)) {
1033 byPwr
= pDevice
->abyCCKPwrTbl
[uCH
];
1034 byPwrdBm
= pDevice
->abyCCKDefaultPwr
[uCH
];
1039 //printk("Rate <11:byPwr is %d\n",byPwr);
1044 byPwr
= pDevice
->abyOFDMPwrTbl
[uCH
];
1045 if (pDevice
->byRFType
== RF_UW2452
) {
1050 if (byDec
>= pDevice
->byMaxPwrLevel
) {
1051 byDec
= pDevice
->byMaxPwrLevel
-1;
1053 if (pDevice
->byRFType
== RF_UW2452
) {
1054 byPwrdBm
= byDec
- byPwr
;
1057 byPwrdBm
= byDec
- byPwr
;
1060 byPwrdBm
+= pDevice
->abyOFDMDefaultPwr
[uCH
];
1066 //printk("Rate <24:byPwr is %d\n",byPwr);
1072 byPwr
= pDevice
->abyOFDMPwrTbl
[uCH
];
1073 byPwrdBm
= pDevice
->abyOFDMDefaultPwr
[uCH
];
1077 //printk("Rate < 54:byPwr is %d\n",byPwr);
1084 if (pDevice
->bLinkPass
== TRUE
) {
1085 // do not over local constraint
1086 if (byPwrdBm
> pDevice
->abyLocalPwr
[uCH
]) {
1087 pDevice
->byCurPwrdBm
= pDevice
->abyLocalPwr
[uCH
];
1088 byDec
= byPwrdBm
- pDevice
->abyLocalPwr
[uCH
];
1089 if (pDevice
->byRFType
== RF_UW2452
) {
1094 if (byPwr
> byDec
) {
1100 pDevice
->byCurPwrdBm
= byPwrdBm
;
1103 // do not over regulatory constraint
1104 if (byPwrdBm
> pDevice
->abyRegPwr
[uCH
]) {
1105 pDevice
->byCurPwrdBm
= pDevice
->abyRegPwr
[uCH
];
1106 byDec
= byPwrdBm
- pDevice
->abyRegPwr
[uCH
];
1107 if (pDevice
->byRFType
== RF_UW2452
) {
1112 if (byPwr
> byDec
) {
1118 pDevice
->byCurPwrdBm
= byPwrdBm
;
1123 // if (pDevice->byLocalID <= REV_ID_VT3253_B1) {
1124 if (pDevice
->byCurPwr
== byPwr
) {
1127 bResult
= RFbRawSetPower(pDevice
, byPwr
, uRATE
);
1129 if (bResult
== TRUE
) {
1130 pDevice
->byCurPwr
= byPwr
;
1136 * Description: Set Tx power
1140 * dwIoBase - I/O base address
1141 * dwRFPowerTable - RF Tx Power Setting
1145 * Return Value: TRUE if succeeded; FALSE if failed.
1149 BOOL
RFbRawSetPower (
1150 IN PSDevice pDevice
,
1155 BOOL bResult
= TRUE
;
1156 DWORD dwMax7230Pwr
= 0;
1158 if (byPwr
>= pDevice
->byMaxPwrLevel
) {
1161 switch (pDevice
->byRFType
) {
1164 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, dwAL2230PowerTable
[byPwr
]);
1165 if (uRATE
<= RATE_11M
) {
1166 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x0001B400+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1168 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x0005A400+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1174 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, dwAL2230PowerTable
[byPwr
]);
1175 if (uRATE
<= RATE_11M
) {
1176 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x040C1400+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1177 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x00299B00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1179 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x0005A400+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1180 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, 0x00099B00+(BY_AL2230_REG_LEN
<<3)+IFREGCTL_REGW
);
1186 // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
1187 dwMax7230Pwr
= 0x080C0B00 | ( (byPwr
) << 12 ) |
1188 (BY_AL7230_REG_LEN
<< 3 ) | IFREGCTL_REGW
;
1190 bResult
&= IFRFbWriteEmbeded(pDevice
->PortOffset
, dwMax7230Pwr
);
1202 * Routine Description:
1203 * Translate RSSI to dBm
1207 * pDevice - The adapter to be translated
1208 * byCurrRSSI - RSSI to be translated
1210 * pdwdbm - Translated dbm number
1212 * Return Value: none
1217 IN PSDevice pDevice
,
1222 BYTE byIdx
= (((byCurrRSSI
& 0xC0) >> 6) & 0x03);
1223 LONG b
= (byCurrRSSI
& 0x3F);
1225 BYTE abyAIROHARF
[4] = {0, 18, 0, 40};
1227 switch (pDevice
->byRFType
) {
1230 case RF_AIROHA7230
: //RobertYu: 20040104
1231 a
= abyAIROHARF
[byIdx
];
1237 *pldBm
= -1 * (a
+ b
* 2);
1240 ////////////////////////////////////////////////////////////////////////////////
1241 //{{ RobertYu: 20050104
1244 // Post processing for the 11b/g and 11a.
1245 // for save time on changing Reg2,3,5,7,10,12,15
1246 BOOL
RFbAL7230SelectChannelPostProcess (DWORD_PTR dwIoBase
, BYTE byOldChannel
, BYTE byNewChannel
)
1252 // if change between 11 b/g and 11a need to update the following register
1253 // Channel Index 1~14
1255 if( (byOldChannel
<= CB_MAX_CHANNEL_24G
) && (byNewChannel
> CB_MAX_CHANNEL_24G
) )
1257 // Change from 2.4G to 5G
1258 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[2]); //Reg2
1259 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[3]); //Reg3
1260 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[5]); //Reg5
1261 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[7]); //Reg7
1262 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[10]);//Reg10
1263 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[12]);//Reg12
1264 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTableAMode
[15]);//Reg15
1266 else if( (byOldChannel
> CB_MAX_CHANNEL_24G
) && (byNewChannel
<= CB_MAX_CHANNEL_24G
) )
1268 // change from 5G to 2.4G
1269 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[2]); //Reg2
1270 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[3]); //Reg3
1271 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[5]); //Reg5
1272 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[7]); //Reg7
1273 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[10]);//Reg10
1274 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[12]);//Reg12
1275 bResult
&= IFRFbWriteEmbeded(dwIoBase
, dwAL7230InitTable
[15]);//Reg15
1283 ////////////////////////////////////////////////////////////////////////////////