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ACPI: ec: Rename gpe_bit to gpe
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blobf36da488a2c1c1ee9a62e54637bf1d46e7f4c0fd
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_PORTS = 32,
57 AHCI_MAX_SG = 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY = 0xffffffff,
59 AHCI_USE_CLUSTERING = 0,
60 AHCI_MAX_CMDS = 32,
61 AHCI_CMD_SZ = 32,
62 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_RX_FIS_SZ = 256,
64 AHCI_CMD_TBL_CDB = 0x40,
65 AHCI_CMD_TBL_HDR_SZ = 0x80,
66 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
67 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
68 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_RX_FIS_SZ,
70 AHCI_IRQ_ON_SG = (1 << 31),
71 AHCI_CMD_ATAPI = (1 << 5),
72 AHCI_CMD_WRITE = (1 << 6),
73 AHCI_CMD_PREFETCH = (1 << 7),
74 AHCI_CMD_RESET = (1 << 8),
75 AHCI_CMD_CLR_BUSY = (1 << 10),
76
77 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
79
80 board_ahci = 0,
81 board_ahci_pi = 1,
82 board_ahci_vt8251 = 2,
83 board_ahci_ign_iferr = 3,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
144 PORT_IRQ_PHYRDY |
145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152
153 /* PORT_CMD bits */
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
167
168 /* hpriv->flags bits */
169 AHCI_FLAG_MSI = (1 << 0),
170
171 /* ap->flags bits */
172 AHCI_FLAG_NO_NCQ = (1 << 24),
173 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
174 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
175 };
176
177 struct ahci_cmd_hdr {
178 u32 opts;
179 u32 status;
180 u32 tbl_addr;
181 u32 tbl_addr_hi;
182 u32 reserved[4];
183 };
184
185 struct ahci_sg {
186 u32 addr;
187 u32 addr_hi;
188 u32 reserved;
189 u32 flags_size;
190 };
191
192 struct ahci_host_priv {
193 unsigned long flags;
194 u32 cap; /* cache of HOST_CAP register */
195 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
196 };
197
198 struct ahci_port_priv {
199 struct ahci_cmd_hdr *cmd_slot;
200 dma_addr_t cmd_slot_dma;
201 void *cmd_tbl;
202 dma_addr_t cmd_tbl_dma;
203 void *rx_fis;
204 dma_addr_t rx_fis_dma;
205 };
206
207 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
208 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
209 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
210 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
211 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
212 static void ahci_irq_clear(struct ata_port *ap);
213 static int ahci_port_start(struct ata_port *ap);
214 static void ahci_port_stop(struct ata_port *ap);
215 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
216 static void ahci_qc_prep(struct ata_queued_cmd *qc);
217 static u8 ahci_check_status(struct ata_port *ap);
218 static void ahci_freeze(struct ata_port *ap);
219 static void ahci_thaw(struct ata_port *ap);
220 static void ahci_error_handler(struct ata_port *ap);
221 static void ahci_vt8251_error_handler(struct ata_port *ap);
222 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224 static int ahci_port_resume(struct ata_port *ap);
225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226 static int ahci_pci_device_resume(struct pci_dev *pdev);
227 static void ahci_remove_one (struct pci_dev *pdev);
228
229 static struct scsi_host_template ahci_sht = {
230 .module = THIS_MODULE,
231 .name = DRV_NAME,
232 .ioctl = ata_scsi_ioctl,
233 .queuecommand = ata_scsi_queuecmd,
234 .change_queue_depth = ata_scsi_change_queue_depth,
235 .can_queue = AHCI_MAX_CMDS - 1,
236 .this_id = ATA_SHT_THIS_ID,
237 .sg_tablesize = AHCI_MAX_SG,
238 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
239 .emulated = ATA_SHT_EMULATED,
240 .use_clustering = AHCI_USE_CLUSTERING,
241 .proc_name = DRV_NAME,
242 .dma_boundary = AHCI_DMA_BOUNDARY,
243 .slave_configure = ata_scsi_slave_config,
244 .slave_destroy = ata_scsi_slave_destroy,
245 .bios_param = ata_std_bios_param,
246 .suspend = ata_scsi_device_suspend,
247 .resume = ata_scsi_device_resume,
248 };
249
250 static const struct ata_port_operations ahci_ops = {
251 .port_disable = ata_port_disable,
252
253 .check_status = ahci_check_status,
254 .check_altstatus = ahci_check_status,
255 .dev_select = ata_noop_dev_select,
256
257 .tf_read = ahci_tf_read,
258
259 .qc_prep = ahci_qc_prep,
260 .qc_issue = ahci_qc_issue,
261
262 .irq_handler = ahci_interrupt,
263 .irq_clear = ahci_irq_clear,
264
265 .scr_read = ahci_scr_read,
266 .scr_write = ahci_scr_write,
267
268 .freeze = ahci_freeze,
269 .thaw = ahci_thaw,
270
271 .error_handler = ahci_error_handler,
272 .post_internal_cmd = ahci_post_internal_cmd,
273
274 .port_suspend = ahci_port_suspend,
275 .port_resume = ahci_port_resume,
276
277 .port_start = ahci_port_start,
278 .port_stop = ahci_port_stop,
279 };
280
281 static const struct ata_port_operations ahci_vt8251_ops = {
282 .port_disable = ata_port_disable,
283
284 .check_status = ahci_check_status,
285 .check_altstatus = ahci_check_status,
286 .dev_select = ata_noop_dev_select,
287
288 .tf_read = ahci_tf_read,
289
290 .qc_prep = ahci_qc_prep,
291 .qc_issue = ahci_qc_issue,
292
293 .irq_handler = ahci_interrupt,
294 .irq_clear = ahci_irq_clear,
295
296 .scr_read = ahci_scr_read,
297 .scr_write = ahci_scr_write,
298
299 .freeze = ahci_freeze,
300 .thaw = ahci_thaw,
301
302 .error_handler = ahci_vt8251_error_handler,
303 .post_internal_cmd = ahci_post_internal_cmd,
304
305 .port_suspend = ahci_port_suspend,
306 .port_resume = ahci_port_resume,
307
308 .port_start = ahci_port_start,
309 .port_stop = ahci_port_stop,
310 };
311
312 static const struct ata_port_info ahci_port_info[] = {
313 /* board_ahci */
314 {
315 .sht = &ahci_sht,
316 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
317 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
318 ATA_FLAG_SKIP_D2H_BSY,
319 .pio_mask = 0x1f, /* pio0-4 */
320 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
321 .port_ops = &ahci_ops,
322 },
323 /* board_ahci_pi */
324 {
325 .sht = &ahci_sht,
326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
328 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
333 /* board_ahci_vt8251 */
334 {
335 .sht = &ahci_sht,
336 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
338 ATA_FLAG_SKIP_D2H_BSY |
339 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
340 .pio_mask = 0x1f, /* pio0-4 */
341 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
342 .port_ops = &ahci_vt8251_ops,
343 },
344 /* board_ahci_ign_iferr */
345 {
346 .sht = &ahci_sht,
347 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
348 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
349 ATA_FLAG_SKIP_D2H_BSY |
350 AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
354 },
355 };
356
357 static const struct pci_device_id ahci_pci_tbl[] = {
358 /* Intel */
359 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
360 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
361 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
362 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
363 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
364 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
365 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
366 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
367 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
368 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
369 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
370 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
371 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
372 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
373 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
374 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
375 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
376 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
380 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
381 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
385
386 /* JMicron */
387 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
388 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
389 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
390 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
391 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
392
393 /* ATI */
394 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
395 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
396
397 /* VIA */
398 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
399
400 /* NVIDIA */
401 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
406 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
407 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
408 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
413
414 /* SiS */
415 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
416 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
417 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
418
419 /* Generic, PCI class code for AHCI */
420 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 0x010601, 0xffffff, board_ahci },
422
423 { } /* terminate list */
424 };
425
426
427 static struct pci_driver ahci_pci_driver = {
428 .name = DRV_NAME,
429 .id_table = ahci_pci_tbl,
430 .probe = ahci_init_one,
431 .suspend = ahci_pci_device_suspend,
432 .resume = ahci_pci_device_resume,
433 .remove = ahci_remove_one,
434 };
435
436
437 static inline int ahci_nr_ports(u32 cap)
438 {
439 return (cap & 0x1f) + 1;
440 }
441
442 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
443 {
444 return base + 0x100 + (port * 0x80);
445 }
446
447 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
448 {
449 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
450 }
451
452 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
453 {
454 unsigned int sc_reg;
455
456 switch (sc_reg_in) {
457 case SCR_STATUS: sc_reg = 0; break;
458 case SCR_CONTROL: sc_reg = 1; break;
459 case SCR_ERROR: sc_reg = 2; break;
460 case SCR_ACTIVE: sc_reg = 3; break;
461 default:
462 return 0xffffffffU;
463 }
464
465 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
466 }
467
468
469 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
470 u32 val)
471 {
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS: sc_reg = 0; break;
476 case SCR_CONTROL: sc_reg = 1; break;
477 case SCR_ERROR: sc_reg = 2; break;
478 case SCR_ACTIVE: sc_reg = 3; break;
479 default:
480 return;
481 }
482
483 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
484 }
485
486 static void ahci_start_engine(void __iomem *port_mmio)
487 {
488 u32 tmp;
489
490 /* start DMA */
491 tmp = readl(port_mmio + PORT_CMD);
492 tmp |= PORT_CMD_START;
493 writel(tmp, port_mmio + PORT_CMD);
494 readl(port_mmio + PORT_CMD); /* flush */
495 }
496
497 static int ahci_stop_engine(void __iomem *port_mmio)
498 {
499 u32 tmp;
500
501 tmp = readl(port_mmio + PORT_CMD);
502
503 /* check if the HBA is idle */
504 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
505 return 0;
506
507 /* setting HBA to idle */
508 tmp &= ~PORT_CMD_START;
509 writel(tmp, port_mmio + PORT_CMD);
510
511 /* wait for engine to stop. This could be as long as 500 msec */
512 tmp = ata_wait_register(port_mmio + PORT_CMD,
513 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
514 if (tmp & PORT_CMD_LIST_ON)
515 return -EIO;
516
517 return 0;
518 }
519
520 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
521 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
522 {
523 u32 tmp;
524
525 /* set FIS registers */
526 if (cap & HOST_CAP_64)
527 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
528 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
529
530 if (cap & HOST_CAP_64)
531 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
532 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
533
534 /* enable FIS reception */
535 tmp = readl(port_mmio + PORT_CMD);
536 tmp |= PORT_CMD_FIS_RX;
537 writel(tmp, port_mmio + PORT_CMD);
538
539 /* flush */
540 readl(port_mmio + PORT_CMD);
541 }
542
543 static int ahci_stop_fis_rx(void __iomem *port_mmio)
544 {
545 u32 tmp;
546
547 /* disable FIS reception */
548 tmp = readl(port_mmio + PORT_CMD);
549 tmp &= ~PORT_CMD_FIS_RX;
550 writel(tmp, port_mmio + PORT_CMD);
551
552 /* wait for completion, spec says 500ms, give it 1000 */
553 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
554 PORT_CMD_FIS_ON, 10, 1000);
555 if (tmp & PORT_CMD_FIS_ON)
556 return -EBUSY;
557
558 return 0;
559 }
560
561 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
562 {
563 u32 cmd;
564
565 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
566
567 /* spin up device */
568 if (cap & HOST_CAP_SSS) {
569 cmd |= PORT_CMD_SPIN_UP;
570 writel(cmd, port_mmio + PORT_CMD);
571 }
572
573 /* wake up link */
574 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
575 }
576
577 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
578 {
579 u32 cmd, scontrol;
580
581 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
582
583 if (cap & HOST_CAP_SSC) {
584 /* enable transitions to slumber mode */
585 scontrol = readl(port_mmio + PORT_SCR_CTL);
586 if ((scontrol & 0x0f00) > 0x100) {
587 scontrol &= ~0xf00;
588 writel(scontrol, port_mmio + PORT_SCR_CTL);
589 }
590
591 /* put device into slumber mode */
592 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
593
594 /* wait for the transition to complete */
595 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
596 PORT_CMD_ICC_SLUMBER, 1, 50);
597 }
598
599 /* put device into listen mode */
600 if (cap & HOST_CAP_SSS) {
601 /* first set PxSCTL.DET to 0 */
602 scontrol = readl(port_mmio + PORT_SCR_CTL);
603 scontrol &= ~0xf;
604 writel(scontrol, port_mmio + PORT_SCR_CTL);
605
606 /* then set PxCMD.SUD to 0 */
607 cmd &= ~PORT_CMD_SPIN_UP;
608 writel(cmd, port_mmio + PORT_CMD);
609 }
610 }
611
612 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
613 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
614 {
615 /* enable FIS reception */
616 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
617
618 /* enable DMA */
619 ahci_start_engine(port_mmio);
620 }
621
622 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
623 {
624 int rc;
625
626 /* disable DMA */
627 rc = ahci_stop_engine(port_mmio);
628 if (rc) {
629 *emsg = "failed to stop engine";
630 return rc;
631 }
632
633 /* disable FIS reception */
634 rc = ahci_stop_fis_rx(port_mmio);
635 if (rc) {
636 *emsg = "failed stop FIS RX";
637 return rc;
638 }
639
640 return 0;
641 }
642
643 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
644 {
645 u32 cap_save, impl_save, tmp;
646
647 cap_save = readl(mmio + HOST_CAP);
648 cap_save &= ( (1<<28) | (1<<17) );
649 cap_save |= (1 << 27);
650 impl_save = readl(mmio + HOST_PORTS_IMPL);
651
652 /* global controller reset */
653 tmp = readl(mmio + HOST_CTL);
654 if ((tmp & HOST_RESET) == 0) {
655 writel(tmp | HOST_RESET, mmio + HOST_CTL);
656 readl(mmio + HOST_CTL); /* flush */
657 }
658
659 /* reset must complete within 1 second, or
660 * the hardware should be considered fried.
661 */
662 ssleep(1);
663
664 tmp = readl(mmio + HOST_CTL);
665 if (tmp & HOST_RESET) {
666 dev_printk(KERN_ERR, &pdev->dev,
667 "controller reset failed (0x%x)\n", tmp);
668 return -EIO;
669 }
670
671 /* turn on AHCI mode */
672 writel(HOST_AHCI_EN, mmio + HOST_CTL);
673 (void) readl(mmio + HOST_CTL); /* flush */
674
675 /* These write-once registers are normally cleared on reset.
676 * Restore BIOS values... which we HOPE were present before
677 * reset.
678 */
679 if (!impl_save) {
680 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
681 dev_printk(KERN_WARNING, &pdev->dev,
682 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
683 }
684 writel(cap_save, mmio + HOST_CAP);
685 writel(impl_save, mmio + HOST_PORTS_IMPL);
686 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
687
688 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
689 u16 tmp16;
690
691 /* configure PCS */
692 pci_read_config_word(pdev, 0x92, &tmp16);
693 tmp16 |= 0xf;
694 pci_write_config_word(pdev, 0x92, tmp16);
695 }
696
697 return 0;
698 }
699
700 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
701 int n_ports, unsigned int port_flags,
702 struct ahci_host_priv *hpriv)
703 {
704 int i, rc;
705 u32 tmp;
706
707 for (i = 0; i < n_ports; i++) {
708 void __iomem *port_mmio = ahci_port_base(mmio, i);
709 const char *emsg = NULL;
710
711 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
712 !(hpriv->port_map & (1 << i)))
713 continue;
714
715 /* make sure port is not active */
716 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
717 if (rc)
718 dev_printk(KERN_WARNING, &pdev->dev,
719 "%s (%d)\n", emsg, rc);
720
721 /* clear SError */
722 tmp = readl(port_mmio + PORT_SCR_ERR);
723 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
724 writel(tmp, port_mmio + PORT_SCR_ERR);
725
726 /* clear port IRQ */
727 tmp = readl(port_mmio + PORT_IRQ_STAT);
728 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
729 if (tmp)
730 writel(tmp, port_mmio + PORT_IRQ_STAT);
731
732 writel(1 << i, mmio + HOST_IRQ_STAT);
733 }
734
735 tmp = readl(mmio + HOST_CTL);
736 VPRINTK("HOST_CTL 0x%x\n", tmp);
737 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
738 tmp = readl(mmio + HOST_CTL);
739 VPRINTK("HOST_CTL 0x%x\n", tmp);
740 }
741
742 static unsigned int ahci_dev_classify(struct ata_port *ap)
743 {
744 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
745 struct ata_taskfile tf;
746 u32 tmp;
747
748 tmp = readl(port_mmio + PORT_SIG);
749 tf.lbah = (tmp >> 24) & 0xff;
750 tf.lbam = (tmp >> 16) & 0xff;
751 tf.lbal = (tmp >> 8) & 0xff;
752 tf.nsect = (tmp) & 0xff;
753
754 return ata_dev_classify(&tf);
755 }
756
757 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
758 u32 opts)
759 {
760 dma_addr_t cmd_tbl_dma;
761
762 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
763
764 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
765 pp->cmd_slot[tag].status = 0;
766 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
767 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
768 }
769
770 static int ahci_clo(struct ata_port *ap)
771 {
772 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
773 struct ahci_host_priv *hpriv = ap->host->private_data;
774 u32 tmp;
775
776 if (!(hpriv->cap & HOST_CAP_CLO))
777 return -EOPNOTSUPP;
778
779 tmp = readl(port_mmio + PORT_CMD);
780 tmp |= PORT_CMD_CLO;
781 writel(tmp, port_mmio + PORT_CMD);
782
783 tmp = ata_wait_register(port_mmio + PORT_CMD,
784 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
785 if (tmp & PORT_CMD_CLO)
786 return -EIO;
787
788 return 0;
789 }
790
791 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
792 {
793 struct ahci_port_priv *pp = ap->private_data;
794 void __iomem *mmio = ap->host->mmio_base;
795 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
796 const u32 cmd_fis_len = 5; /* five dwords */
797 const char *reason = NULL;
798 struct ata_taskfile tf;
799 u32 tmp;
800 u8 *fis;
801 int rc;
802
803 DPRINTK("ENTER\n");
804
805 if (ata_port_offline(ap)) {
806 DPRINTK("PHY reports no device\n");
807 *class = ATA_DEV_NONE;
808 return 0;
809 }
810
811 /* prepare for SRST (AHCI-1.1 10.4.1) */
812 rc = ahci_stop_engine(port_mmio);
813 if (rc) {
814 reason = "failed to stop engine";
815 goto fail_restart;
816 }
817
818 /* check BUSY/DRQ, perform Command List Override if necessary */
819 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
820 rc = ahci_clo(ap);
821
822 if (rc == -EOPNOTSUPP) {
823 reason = "port busy but CLO unavailable";
824 goto fail_restart;
825 } else if (rc) {
826 reason = "port busy but CLO failed";
827 goto fail_restart;
828 }
829 }
830
831 /* restart engine */
832 ahci_start_engine(port_mmio);
833
834 ata_tf_init(ap->device, &tf);
835 fis = pp->cmd_tbl;
836
837 /* issue the first D2H Register FIS */
838 ahci_fill_cmd_slot(pp, 0,
839 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
840
841 tf.ctl |= ATA_SRST;
842 ata_tf_to_fis(&tf, fis, 0);
843 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
844
845 writel(1, port_mmio + PORT_CMD_ISSUE);
846
847 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
848 if (tmp & 0x1) {
849 rc = -EIO;
850 reason = "1st FIS failed";
851 goto fail;
852 }
853
854 /* spec says at least 5us, but be generous and sleep for 1ms */
855 msleep(1);
856
857 /* issue the second D2H Register FIS */
858 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
859
860 tf.ctl &= ~ATA_SRST;
861 ata_tf_to_fis(&tf, fis, 0);
862 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
863
864 writel(1, port_mmio + PORT_CMD_ISSUE);
865 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
866
867 /* spec mandates ">= 2ms" before checking status.
868 * We wait 150ms, because that was the magic delay used for
869 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
870 * between when the ATA command register is written, and then
871 * status is checked. Because waiting for "a while" before
872 * checking status is fine, post SRST, we perform this magic
873 * delay here as well.
874 */
875 msleep(150);
876
877 *class = ATA_DEV_NONE;
878 if (ata_port_online(ap)) {
879 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
880 rc = -EIO;
881 reason = "device not ready";
882 goto fail;
883 }
884 *class = ahci_dev_classify(ap);
885 }
886
887 DPRINTK("EXIT, class=%u\n", *class);
888 return 0;
889
890 fail_restart:
891 ahci_start_engine(port_mmio);
892 fail:
893 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
894 return rc;
895 }
896
897 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
898 {
899 struct ahci_port_priv *pp = ap->private_data;
900 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
901 struct ata_taskfile tf;
902 void __iomem *mmio = ap->host->mmio_base;
903 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
904 int rc;
905
906 DPRINTK("ENTER\n");
907
908 ahci_stop_engine(port_mmio);
909
910 /* clear D2H reception area to properly wait for D2H FIS */
911 ata_tf_init(ap->device, &tf);
912 tf.command = 0xff;
913 ata_tf_to_fis(&tf, d2h_fis, 0);
914
915 rc = sata_std_hardreset(ap, class);
916
917 ahci_start_engine(port_mmio);
918
919 if (rc == 0 && ata_port_online(ap))
920 *class = ahci_dev_classify(ap);
921 if (*class == ATA_DEV_UNKNOWN)
922 *class = ATA_DEV_NONE;
923
924 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
925 return rc;
926 }
927
928 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
929 {
930 void __iomem *mmio = ap->host->mmio_base;
931 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
932 int rc;
933
934 DPRINTK("ENTER\n");
935
936 ahci_stop_engine(port_mmio);
937
938 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
939
940 /* vt8251 needs SError cleared for the port to operate */
941 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
942
943 ahci_start_engine(port_mmio);
944
945 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
946
947 /* vt8251 doesn't clear BSY on signature FIS reception,
948 * request follow-up softreset.
949 */
950 return rc ?: -EAGAIN;
951 }
952
953 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
954 {
955 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
956 u32 new_tmp, tmp;
957
958 ata_std_postreset(ap, class);
959
960 /* Make sure port's ATAPI bit is set appropriately */
961 new_tmp = tmp = readl(port_mmio + PORT_CMD);
962 if (*class == ATA_DEV_ATAPI)
963 new_tmp |= PORT_CMD_ATAPI;
964 else
965 new_tmp &= ~PORT_CMD_ATAPI;
966 if (new_tmp != tmp) {
967 writel(new_tmp, port_mmio + PORT_CMD);
968 readl(port_mmio + PORT_CMD); /* flush */
969 }
970 }
971
972 static u8 ahci_check_status(struct ata_port *ap)
973 {
974 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
975
976 return readl(mmio + PORT_TFDATA) & 0xFF;
977 }
978
979 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
980 {
981 struct ahci_port_priv *pp = ap->private_data;
982 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
983
984 ata_tf_from_fis(d2h_fis, tf);
985 }
986
987 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
988 {
989 struct scatterlist *sg;
990 struct ahci_sg *ahci_sg;
991 unsigned int n_sg = 0;
992
993 VPRINTK("ENTER\n");
994
995 /*
996 * Next, the S/G list.
997 */
998 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
999 ata_for_each_sg(sg, qc) {
1000 dma_addr_t addr = sg_dma_address(sg);
1001 u32 sg_len = sg_dma_len(sg);
1002
1003 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1004 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1005 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1006
1007 ahci_sg++;
1008 n_sg++;
1009 }
1010
1011 return n_sg;
1012 }
1013
1014 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1015 {
1016 struct ata_port *ap = qc->ap;
1017 struct ahci_port_priv *pp = ap->private_data;
1018 int is_atapi = is_atapi_taskfile(&qc->tf);
1019 void *cmd_tbl;
1020 u32 opts;
1021 const u32 cmd_fis_len = 5; /* five dwords */
1022 unsigned int n_elem;
1023
1024 /*
1025 * Fill in command table information. First, the header,
1026 * a SATA Register - Host to Device command FIS.
1027 */
1028 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1029
1030 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1031 if (is_atapi) {
1032 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1033 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1034 }
1035
1036 n_elem = 0;
1037 if (qc->flags & ATA_QCFLAG_DMAMAP)
1038 n_elem = ahci_fill_sg(qc, cmd_tbl);
1039
1040 /*
1041 * Fill in command slot information.
1042 */
1043 opts = cmd_fis_len | n_elem << 16;
1044 if (qc->tf.flags & ATA_TFLAG_WRITE)
1045 opts |= AHCI_CMD_WRITE;
1046 if (is_atapi)
1047 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1048
1049 ahci_fill_cmd_slot(pp, qc->tag, opts);
1050 }
1051
1052 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1053 {
1054 struct ahci_port_priv *pp = ap->private_data;
1055 struct ata_eh_info *ehi = &ap->eh_info;
1056 unsigned int err_mask = 0, action = 0;
1057 struct ata_queued_cmd *qc;
1058 u32 serror;
1059
1060 ata_ehi_clear_desc(ehi);
1061
1062 /* AHCI needs SError cleared; otherwise, it might lock up */
1063 serror = ahci_scr_read(ap, SCR_ERROR);
1064 ahci_scr_write(ap, SCR_ERROR, serror);
1065
1066 /* analyze @irq_stat */
1067 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1068
1069 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1070 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1071 irq_stat &= ~PORT_IRQ_IF_ERR;
1072
1073 if (irq_stat & PORT_IRQ_TF_ERR)
1074 err_mask |= AC_ERR_DEV;
1075
1076 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1077 err_mask |= AC_ERR_HOST_BUS;
1078 action |= ATA_EH_SOFTRESET;
1079 }
1080
1081 if (irq_stat & PORT_IRQ_IF_ERR) {
1082 err_mask |= AC_ERR_ATA_BUS;
1083 action |= ATA_EH_SOFTRESET;
1084 ata_ehi_push_desc(ehi, ", interface fatal error");
1085 }
1086
1087 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1088 ata_ehi_hotplugged(ehi);
1089 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1090 "connection status changed" : "PHY RDY changed");
1091 }
1092
1093 if (irq_stat & PORT_IRQ_UNK_FIS) {
1094 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1095
1096 err_mask |= AC_ERR_HSM;
1097 action |= ATA_EH_SOFTRESET;
1098 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1099 unk[0], unk[1], unk[2], unk[3]);
1100 }
1101
1102 /* okay, let's hand over to EH */
1103 ehi->serror |= serror;
1104 ehi->action |= action;
1105
1106 qc = ata_qc_from_tag(ap, ap->active_tag);
1107 if (qc)
1108 qc->err_mask |= err_mask;
1109 else
1110 ehi->err_mask |= err_mask;
1111
1112 if (irq_stat & PORT_IRQ_FREEZE)
1113 ata_port_freeze(ap);
1114 else
1115 ata_port_abort(ap);
1116 }
1117
1118 static void ahci_host_intr(struct ata_port *ap)
1119 {
1120 void __iomem *mmio = ap->host->mmio_base;
1121 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1122 struct ata_eh_info *ehi = &ap->eh_info;
1123 u32 status, qc_active;
1124 int rc;
1125
1126 status = readl(port_mmio + PORT_IRQ_STAT);
1127 writel(status, port_mmio + PORT_IRQ_STAT);
1128
1129 if (unlikely(status & PORT_IRQ_ERROR)) {
1130 ahci_error_intr(ap, status);
1131 return;
1132 }
1133
1134 if (ap->sactive)
1135 qc_active = readl(port_mmio + PORT_SCR_ACT);
1136 else
1137 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1138
1139 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1140 if (rc > 0)
1141 return;
1142 if (rc < 0) {
1143 ehi->err_mask |= AC_ERR_HSM;
1144 ehi->action |= ATA_EH_SOFTRESET;
1145 ata_port_freeze(ap);
1146 return;
1147 }
1148
1149 /* hmmm... a spurious interupt */
1150
1151 /* some devices send D2H reg with I bit set during NCQ command phase */
1152 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1153 return;
1154
1155 /* ignore interim PIO setup fis interrupts */
1156 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1157 return;
1158
1159 if (ata_ratelimit())
1160 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1161 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1162 status, ap->active_tag, ap->sactive);
1163 }
1164
1165 static void ahci_irq_clear(struct ata_port *ap)
1166 {
1167 /* TODO */
1168 }
1169
1170 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1171 {
1172 struct ata_host *host = dev_instance;
1173 struct ahci_host_priv *hpriv;
1174 unsigned int i, handled = 0;
1175 void __iomem *mmio;
1176 u32 irq_stat, irq_ack = 0;
1177
1178 VPRINTK("ENTER\n");
1179
1180 hpriv = host->private_data;
1181 mmio = host->mmio_base;
1182
1183 /* sigh. 0xffffffff is a valid return from h/w */
1184 irq_stat = readl(mmio + HOST_IRQ_STAT);
1185 irq_stat &= hpriv->port_map;
1186 if (!irq_stat)
1187 return IRQ_NONE;
1188
1189 spin_lock(&host->lock);
1190
1191 for (i = 0; i < host->n_ports; i++) {
1192 struct ata_port *ap;
1193
1194 if (!(irq_stat & (1 << i)))
1195 continue;
1196
1197 ap = host->ports[i];
1198 if (ap) {
1199 ahci_host_intr(ap);
1200 VPRINTK("port %u\n", i);
1201 } else {
1202 VPRINTK("port %u (no irq)\n", i);
1203 if (ata_ratelimit())
1204 dev_printk(KERN_WARNING, host->dev,
1205 "interrupt on disabled port %u\n", i);
1206 }
1207
1208 irq_ack |= (1 << i);
1209 }
1210
1211 if (irq_ack) {
1212 writel(irq_ack, mmio + HOST_IRQ_STAT);
1213 handled = 1;
1214 }
1215
1216 spin_unlock(&host->lock);
1217
1218 VPRINTK("EXIT\n");
1219
1220 return IRQ_RETVAL(handled);
1221 }
1222
1223 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1224 {
1225 struct ata_port *ap = qc->ap;
1226 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1227
1228 if (qc->tf.protocol == ATA_PROT_NCQ)
1229 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1230 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1231 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1232
1233 return 0;
1234 }
1235
1236 static void ahci_freeze(struct ata_port *ap)
1237 {
1238 void __iomem *mmio = ap->host->mmio_base;
1239 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1240
1241 /* turn IRQ off */
1242 writel(0, port_mmio + PORT_IRQ_MASK);
1243 }
1244
1245 static void ahci_thaw(struct ata_port *ap)
1246 {
1247 void __iomem *mmio = ap->host->mmio_base;
1248 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1249 u32 tmp;
1250
1251 /* clear IRQ */
1252 tmp = readl(port_mmio + PORT_IRQ_STAT);
1253 writel(tmp, port_mmio + PORT_IRQ_STAT);
1254 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1255
1256 /* turn IRQ back on */
1257 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1258 }
1259
1260 static void ahci_error_handler(struct ata_port *ap)
1261 {
1262 void __iomem *mmio = ap->host->mmio_base;
1263 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1264
1265 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1266 /* restart engine */
1267 ahci_stop_engine(port_mmio);
1268 ahci_start_engine(port_mmio);
1269 }
1270
1271 /* perform recovery */
1272 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1273 ahci_postreset);
1274 }
1275
1276 static void ahci_vt8251_error_handler(struct ata_port *ap)
1277 {
1278 void __iomem *mmio = ap->host->mmio_base;
1279 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1280
1281 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1282 /* restart engine */
1283 ahci_stop_engine(port_mmio);
1284 ahci_start_engine(port_mmio);
1285 }
1286
1287 /* perform recovery */
1288 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1289 ahci_postreset);
1290 }
1291
1292 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1293 {
1294 struct ata_port *ap = qc->ap;
1295 void __iomem *mmio = ap->host->mmio_base;
1296 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1297
1298 if (qc->flags & ATA_QCFLAG_FAILED)
1299 qc->err_mask |= AC_ERR_OTHER;
1300
1301 if (qc->err_mask) {
1302 /* make DMA engine forget about the failed command */
1303 ahci_stop_engine(port_mmio);
1304 ahci_start_engine(port_mmio);
1305 }
1306 }
1307
1308 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1309 {
1310 struct ahci_host_priv *hpriv = ap->host->private_data;
1311 struct ahci_port_priv *pp = ap->private_data;
1312 void __iomem *mmio = ap->host->mmio_base;
1313 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1314 const char *emsg = NULL;
1315 int rc;
1316
1317 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1318 if (rc == 0)
1319 ahci_power_down(port_mmio, hpriv->cap);
1320 else {
1321 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1322 ahci_init_port(port_mmio, hpriv->cap,
1323 pp->cmd_slot_dma, pp->rx_fis_dma);
1324 }
1325
1326 return rc;
1327 }
1328
1329 static int ahci_port_resume(struct ata_port *ap)
1330 {
1331 struct ahci_port_priv *pp = ap->private_data;
1332 struct ahci_host_priv *hpriv = ap->host->private_data;
1333 void __iomem *mmio = ap->host->mmio_base;
1334 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1335
1336 ahci_power_up(port_mmio, hpriv->cap);
1337 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1338
1339 return 0;
1340 }
1341
1342 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1343 {
1344 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1345 void __iomem *mmio = host->mmio_base;
1346 u32 ctl;
1347
1348 if (mesg.event == PM_EVENT_SUSPEND) {
1349 /* AHCI spec rev1.1 section 8.3.3:
1350 * Software must disable interrupts prior to requesting a
1351 * transition of the HBA to D3 state.
1352 */
1353 ctl = readl(mmio + HOST_CTL);
1354 ctl &= ~HOST_IRQ_EN;
1355 writel(ctl, mmio + HOST_CTL);
1356 readl(mmio + HOST_CTL); /* flush */
1357 }
1358
1359 return ata_pci_device_suspend(pdev, mesg);
1360 }
1361
1362 static int ahci_pci_device_resume(struct pci_dev *pdev)
1363 {
1364 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1365 struct ahci_host_priv *hpriv = host->private_data;
1366 void __iomem *mmio = host->mmio_base;
1367 int rc;
1368
1369 ata_pci_device_do_resume(pdev);
1370
1371 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1372 rc = ahci_reset_controller(mmio, pdev);
1373 if (rc)
1374 return rc;
1375
1376 ahci_init_controller(mmio, pdev, host->n_ports,
1377 host->ports[0]->flags, hpriv);
1378 }
1379
1380 ata_host_resume(host);
1381
1382 return 0;
1383 }
1384
1385 static int ahci_port_start(struct ata_port *ap)
1386 {
1387 struct device *dev = ap->host->dev;
1388 struct ahci_host_priv *hpriv = ap->host->private_data;
1389 struct ahci_port_priv *pp;
1390 void __iomem *mmio = ap->host->mmio_base;
1391 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1392 void *mem;
1393 dma_addr_t mem_dma;
1394 int rc;
1395
1396 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1397 if (!pp)
1398 return -ENOMEM;
1399 memset(pp, 0, sizeof(*pp));
1400
1401 rc = ata_pad_alloc(ap, dev);
1402 if (rc) {
1403 kfree(pp);
1404 return rc;
1405 }
1406
1407 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1408 if (!mem) {
1409 ata_pad_free(ap, dev);
1410 kfree(pp);
1411 return -ENOMEM;
1412 }
1413 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1414
1415 /*
1416 * First item in chunk of DMA memory: 32-slot command table,
1417 * 32 bytes each in size
1418 */
1419 pp->cmd_slot = mem;
1420 pp->cmd_slot_dma = mem_dma;
1421
1422 mem += AHCI_CMD_SLOT_SZ;
1423 mem_dma += AHCI_CMD_SLOT_SZ;
1424
1425 /*
1426 * Second item: Received-FIS area
1427 */
1428 pp->rx_fis = mem;
1429 pp->rx_fis_dma = mem_dma;
1430
1431 mem += AHCI_RX_FIS_SZ;
1432 mem_dma += AHCI_RX_FIS_SZ;
1433
1434 /*
1435 * Third item: data area for storing a single command
1436 * and its scatter-gather table
1437 */
1438 pp->cmd_tbl = mem;
1439 pp->cmd_tbl_dma = mem_dma;
1440
1441 ap->private_data = pp;
1442
1443 /* power up port */
1444 ahci_power_up(port_mmio, hpriv->cap);
1445
1446 /* initialize port */
1447 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1448
1449 return 0;
1450 }
1451
1452 static void ahci_port_stop(struct ata_port *ap)
1453 {
1454 struct device *dev = ap->host->dev;
1455 struct ahci_host_priv *hpriv = ap->host->private_data;
1456 struct ahci_port_priv *pp = ap->private_data;
1457 void __iomem *mmio = ap->host->mmio_base;
1458 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1459 const char *emsg = NULL;
1460 int rc;
1461
1462 /* de-initialize port */
1463 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1464 if (rc)
1465 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1466
1467 ap->private_data = NULL;
1468 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1469 pp->cmd_slot, pp->cmd_slot_dma);
1470 ata_pad_free(ap, dev);
1471 kfree(pp);
1472 }
1473
1474 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1475 unsigned int port_idx)
1476 {
1477 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1478 base = ahci_port_base_ul(base, port_idx);
1479 VPRINTK("base now==0x%lx\n", base);
1480
1481 port->cmd_addr = base;
1482 port->scr_addr = base + PORT_SCR;
1483
1484 VPRINTK("EXIT\n");
1485 }
1486
1487 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1488 {
1489 struct ahci_host_priv *hpriv = probe_ent->private_data;
1490 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1491 void __iomem *mmio = probe_ent->mmio_base;
1492 unsigned int i, cap_n_ports, using_dac;
1493 int rc;
1494
1495 rc = ahci_reset_controller(mmio, pdev);
1496 if (rc)
1497 return rc;
1498
1499 hpriv->cap = readl(mmio + HOST_CAP);
1500 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1501 cap_n_ports = ahci_nr_ports(hpriv->cap);
1502
1503 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1504 hpriv->cap, hpriv->port_map, cap_n_ports);
1505
1506 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1507 unsigned int n_ports = cap_n_ports;
1508 u32 port_map = hpriv->port_map;
1509 int max_port = 0;
1510
1511 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1512 if (port_map & (1 << i)) {
1513 n_ports--;
1514 port_map &= ~(1 << i);
1515 max_port = i;
1516 } else
1517 probe_ent->dummy_port_mask |= 1 << i;
1518 }
1519
1520 if (n_ports || port_map)
1521 dev_printk(KERN_WARNING, &pdev->dev,
1522 "nr_ports (%u) and implemented port map "
1523 "(0x%x) don't match\n",
1524 cap_n_ports, hpriv->port_map);
1525
1526 probe_ent->n_ports = max_port + 1;
1527 } else
1528 probe_ent->n_ports = cap_n_ports;
1529
1530 using_dac = hpriv->cap & HOST_CAP_64;
1531 if (using_dac &&
1532 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1533 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1534 if (rc) {
1535 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1536 if (rc) {
1537 dev_printk(KERN_ERR, &pdev->dev,
1538 "64-bit DMA enable failed\n");
1539 return rc;
1540 }
1541 }
1542 } else {
1543 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1544 if (rc) {
1545 dev_printk(KERN_ERR, &pdev->dev,
1546 "32-bit DMA enable failed\n");
1547 return rc;
1548 }
1549 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1550 if (rc) {
1551 dev_printk(KERN_ERR, &pdev->dev,
1552 "32-bit consistent DMA enable failed\n");
1553 return rc;
1554 }
1555 }
1556
1557 for (i = 0; i < probe_ent->n_ports; i++)
1558 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1559
1560 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1561 probe_ent->port_flags, hpriv);
1562
1563 pci_set_master(pdev);
1564
1565 return 0;
1566 }
1567
1568 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1569 {
1570 struct ahci_host_priv *hpriv = probe_ent->private_data;
1571 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1572 void __iomem *mmio = probe_ent->mmio_base;
1573 u32 vers, cap, impl, speed;
1574 const char *speed_s;
1575 u16 cc;
1576 const char *scc_s;
1577
1578 vers = readl(mmio + HOST_VERSION);
1579 cap = hpriv->cap;
1580 impl = hpriv->port_map;
1581
1582 speed = (cap >> 20) & 0xf;
1583 if (speed == 1)
1584 speed_s = "1.5";
1585 else if (speed == 2)
1586 speed_s = "3";
1587 else
1588 speed_s = "?";
1589
1590 pci_read_config_word(pdev, 0x0a, &cc);
1591 if (cc == 0x0101)
1592 scc_s = "IDE";
1593 else if (cc == 0x0106)
1594 scc_s = "SATA";
1595 else if (cc == 0x0104)
1596 scc_s = "RAID";
1597 else
1598 scc_s = "unknown";
1599
1600 dev_printk(KERN_INFO, &pdev->dev,
1601 "AHCI %02x%02x.%02x%02x "
1602 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1603 ,
1604
1605 (vers >> 24) & 0xff,
1606 (vers >> 16) & 0xff,
1607 (vers >> 8) & 0xff,
1608 vers & 0xff,
1609
1610 ((cap >> 8) & 0x1f) + 1,
1611 (cap & 0x1f) + 1,
1612 speed_s,
1613 impl,
1614 scc_s);
1615
1616 dev_printk(KERN_INFO, &pdev->dev,
1617 "flags: "
1618 "%s%s%s%s%s%s"
1619 "%s%s%s%s%s%s%s\n"
1620 ,
1621
1622 cap & (1 << 31) ? "64bit " : "",
1623 cap & (1 << 30) ? "ncq " : "",
1624 cap & (1 << 28) ? "ilck " : "",
1625 cap & (1 << 27) ? "stag " : "",
1626 cap & (1 << 26) ? "pm " : "",
1627 cap & (1 << 25) ? "led " : "",
1628
1629 cap & (1 << 24) ? "clo " : "",
1630 cap & (1 << 19) ? "nz " : "",
1631 cap & (1 << 18) ? "only " : "",
1632 cap & (1 << 17) ? "pmp " : "",
1633 cap & (1 << 15) ? "pio " : "",
1634 cap & (1 << 14) ? "slum " : "",
1635 cap & (1 << 13) ? "part " : ""
1636 );
1637 }
1638
1639 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1640 {
1641 static int printed_version;
1642 struct ata_probe_ent *probe_ent = NULL;
1643 struct ahci_host_priv *hpriv;
1644 unsigned long base;
1645 void __iomem *mmio_base;
1646 unsigned int board_idx = (unsigned int) ent->driver_data;
1647 int have_msi, pci_dev_busy = 0;
1648 int rc;
1649
1650 VPRINTK("ENTER\n");
1651
1652 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1653
1654 if (!printed_version++)
1655 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1656
1657 /* JMicron-specific fixup: make sure we're in AHCI mode */
1658 /* This is protected from races with ata_jmicron by the pci probe
1659 locking */
1660 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1661 /* AHCI enable, AHCI on function 0 */
1662 pci_write_config_byte(pdev, 0x41, 0xa1);
1663 /* Function 1 is the PATA controller */
1664 if (PCI_FUNC(pdev->devfn))
1665 return -ENODEV;
1666 }
1667
1668 rc = pci_enable_device(pdev);
1669 if (rc)
1670 return rc;
1671
1672 rc = pci_request_regions(pdev, DRV_NAME);
1673 if (rc) {
1674 pci_dev_busy = 1;
1675 goto err_out;
1676 }
1677
1678 if (pci_enable_msi(pdev) == 0)
1679 have_msi = 1;
1680 else {
1681 pci_intx(pdev, 1);
1682 have_msi = 0;
1683 }
1684
1685 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1686 if (probe_ent == NULL) {
1687 rc = -ENOMEM;
1688 goto err_out_msi;
1689 }
1690
1691 memset(probe_ent, 0, sizeof(*probe_ent));
1692 probe_ent->dev = pci_dev_to_dev(pdev);
1693 INIT_LIST_HEAD(&probe_ent->node);
1694
1695 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1696 if (mmio_base == NULL) {
1697 rc = -ENOMEM;
1698 goto err_out_free_ent;
1699 }
1700 base = (unsigned long) mmio_base;
1701
1702 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1703 if (!hpriv) {
1704 rc = -ENOMEM;
1705 goto err_out_iounmap;
1706 }
1707 memset(hpriv, 0, sizeof(*hpriv));
1708
1709 probe_ent->sht = ahci_port_info[board_idx].sht;
1710 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1711 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1712 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1713 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1714
1715 probe_ent->irq = pdev->irq;
1716 probe_ent->irq_flags = IRQF_SHARED;
1717 probe_ent->mmio_base = mmio_base;
1718 probe_ent->private_data = hpriv;
1719
1720 if (have_msi)
1721 hpriv->flags |= AHCI_FLAG_MSI;
1722
1723 /* initialize adapter */
1724 rc = ahci_host_init(probe_ent);
1725 if (rc)
1726 goto err_out_hpriv;
1727
1728 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1729 (hpriv->cap & HOST_CAP_NCQ))
1730 probe_ent->port_flags |= ATA_FLAG_NCQ;
1731
1732 ahci_print_info(probe_ent);
1733
1734 /* FIXME: check ata_device_add return value */
1735 ata_device_add(probe_ent);
1736 kfree(probe_ent);
1737
1738 return 0;
1739
1740 err_out_hpriv:
1741 kfree(hpriv);
1742 err_out_iounmap:
1743 pci_iounmap(pdev, mmio_base);
1744 err_out_free_ent:
1745 kfree(probe_ent);
1746 err_out_msi:
1747 if (have_msi)
1748 pci_disable_msi(pdev);
1749 else
1750 pci_intx(pdev, 0);
1751 pci_release_regions(pdev);
1752 err_out:
1753 if (!pci_dev_busy)
1754 pci_disable_device(pdev);
1755 return rc;
1756 }
1757
1758 static void ahci_remove_one (struct pci_dev *pdev)
1759 {
1760 struct device *dev = pci_dev_to_dev(pdev);
1761 struct ata_host *host = dev_get_drvdata(dev);
1762 struct ahci_host_priv *hpriv = host->private_data;
1763 unsigned int i;
1764 int have_msi;
1765
1766 for (i = 0; i < host->n_ports; i++)
1767 ata_port_detach(host->ports[i]);
1768
1769 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1770 free_irq(host->irq, host);
1771
1772 for (i = 0; i < host->n_ports; i++) {
1773 struct ata_port *ap = host->ports[i];
1774
1775 ata_scsi_release(ap->scsi_host);
1776 scsi_host_put(ap->scsi_host);
1777 }
1778
1779 kfree(hpriv);
1780 pci_iounmap(pdev, host->mmio_base);
1781 kfree(host);
1782
1783 if (have_msi)
1784 pci_disable_msi(pdev);
1785 else
1786 pci_intx(pdev, 0);
1787 pci_release_regions(pdev);
1788 pci_disable_device(pdev);
1789 dev_set_drvdata(dev, NULL);
1790 }
1791
1792 static int __init ahci_init(void)
1793 {
1794 return pci_register_driver(&ahci_pci_driver);
1795 }
1796
1797 static void __exit ahci_exit(void)
1798 {
1799 pci_unregister_driver(&ahci_pci_driver);
1800 }
1801
1802
1803 MODULE_AUTHOR("Jeff Garzik");
1804 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1805 MODULE_LICENSE("GPL");
1806 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1807 MODULE_VERSION(DRV_VERSION);
1808
1809 module_init(ahci_init);
1810 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree